Integrated circuit copper needle packaging structure and manufacturing method thereof

Abstract

The invention discloses an integrated circuit copper needle packaging structure and a manufacturing method thereof, and belongs to the technical field of semiconductor packaging. 2, arranging a release layer I above the glass carrier plate I; 3, a circuit layer is formed above the first release layer, the circuit layer comprises a plurality of dielectric layers and a plurality of metal wiring layers, and the top metal wiring layer comprises a T-shaped structure; the forming method of the T-shaped structure comprises the following step of: before forming a top metal wiring layer, performing an exposure and development process in a dielectric layer below the top metal wiring layer through a photomask to form an opening structure. A circular structure is additionally arranged on a dielectric layer below a copper needle and corresponding to the lower part of a top metal wiring layer by using a photomask, and a vertical metal layer is additionally arranged on the top metal wiring layer, so that the top metal wiring layer forms a T-shaped structure, and the binding force between the top metal wiring layer and the copper needle is enhanced; and the copper needles are prevented from peeling off along the surface of the dielectric layer below the top metal wiring layer.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor packaging, and particularly relates to a copper needle packaging structure of an integrated circuit and a manufacturing method thereof. BACKGROUND

[0002] In the evolution process of integrated circuit packaging technology towards high density, miniaturization and lightness, fan-out wafer level packaging has unique advantages such as no need for a carrier substrate, realization of multi-chip integration, effective reduction of packaging size and cost. In the packaging architecture of fan-out wafer level packaging, the up-down interconnection structure is a key link for ensuring stable signal transmission, power supply and heat management between the chip and the external circuit, and the copper needle fixing process, as a core technology for realizing this interconnection function, directly determines the service life and performance stability of the entire fan-out wafer level packaging product.

[0003] The copper needle fixing process builds a connection path between the internal circuit of the chip and the external pin by preparing a copper needle in the packaging structure, and the copper redistribution layer and the polyimide dielectric layer are the core components of the interconnection structure. The copper redistribution layer bears the signal and power transmission function, and the dielectric layer is used to realize the insulation isolation and structural support between different wiring layers, and the interface bonding quality of the two is crucial to the reliability of the copper needle fixing process. However, in the actual mass production process of the current fan-out wafer level packaging, the copper needle fixing process generally faces a key technical problem: the interface between the copper redistribution layer and the dielectric layer is prone to delamination, which leads to the peeling of the copper needle from the packaging structure, ultimately causing the chip interconnection to fail, and seriously affecting the yield and long-term reliability of the packaging product. SUMMARY

[0004] In view of the above, in order to overcome the defects of the prior art, the present application provides a copper needle packaging structure of an integrated circuit and a manufacturing method thereof, which effectively solves the problem of peeling of the copper needle caused by delamination of the dielectric layer and the metal wiring layer in the copper needle fixing process in the current market.

[0005] The technical scheme adopted by the present application is as follows: the present application provides a copper needle packaging structure of an integrated circuit and a manufacturing method thereof, step one: preparing a glass carrier plate one; Step two: setting a release layer one above the glass carrier plate one; Step three: forming a wiring layer above the release layer one, the wiring layer comprising a plurality of dielectric layers and a plurality of metal wiring layers, wherein the top layer metal wiring layer comprises a T-shaped structure; The forming method of the T-shaped structure comprises: before forming the top layer metal wiring layer, first performing an exposure and development process on the dielectric layer below the top layer metal wiring layer through a mask to form an opening structure; then when forming the top layer metal wiring layer, filling metal in the opening structure to form the vertical part of the T-shaped structure; Step four: setting solder above the T-shaped structure and mounting copper needle above the solder; Step five: mounting chip above the circuit layer; Step six: forming plastic package by plastic package process, which covers the copper needle, the chip and the circuit layer; Step seven: grinding the plastic package to expose the end of the copper needle.

[0006] Preferably, after step seven, further comprising the following steps: mounting glass carrier two above the copper needle and the chip through release layer two and removing the glass carrier one and the release layer one below the circuit layer; setting metal ball on the surface of the circuit layer; removing the glass carrier two and release layer two and completing the package by reflow soldering.

[0007] Preferably, in step three, circular structure or rectangular structure opposite to the opening structure is set on the mask.

[0008] Preferably, in step three, the circuit layer comprises at least two dielectric layers and one metal wiring layer.

[0009] Preferably, in step five, the chip is mounted on the circuit layer by flip chip process.

[0010] Preferably, the chip is provided with bump, which is connected with corresponding pad on the circuit layer.

[0011] Preferably, after step five, the periphery of the circuit layer and the chip is underfilling.

[0012] Preferably, the circuit layer comprises multiple dielectric layers and multiple metal wiring layers, the dielectric layer below the top metal wiring layer comprises opening structure, the top metal wiring layer comprises T-shaped structure, the vertical part of the T-shaped structure is set in the opening structure; the chip is set above the circuit layer, the chip and the middle of the circuit layer are provided with filling; the copper needle is set above the T-shaped structure through solder; the metal ball is set below the circuit layer.

[0013] Preferably, it further comprises plastic package, which covers the chip, the copper needle and part of the circuit layer.

[0014] The beneficial effects of the present invention using the above structure are as follows: This solution proposes an integrated circuit copper pin packaging structure and its manufacturing method. A circular structure is added to the dielectric layer below the top metal wiring layer using a photomask, and a vertical metal layer is added on the top metal wiring layer to form a T-shaped structure. This method enhances the bonding force between the top metal wiring layer and the copper pin and prevents the copper pin from peeling off along the surface of the dielectric layer below the top metal wiring layer. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of step one of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention. Figure 2 This is a schematic diagram of step two of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention; Figure 3 This is a schematic diagram of step three of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention. Figure 4 This is a schematic diagram of step four of the integrated circuit copper pin packaging structure and its fabrication method proposed in this invention. Figure 5 This is a schematic diagram of step five of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention; Figure 6 This is a schematic diagram of step five of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention; Figure 7 This is a schematic diagram of step six of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention. Figure 8 This is a schematic diagram of step seven of the integrated circuit copper pin packaging structure and its fabrication method proposed in this invention. Figure 9 This is a schematic diagram of step eight of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention. Figure 10 This is a schematic diagram of step eight of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention. Figure 11 This is a schematic diagram of step eight of the integrated circuit copper pin packaging structure and its manufacturing method proposed in this invention. Figure 12 This is a schematic diagram of a photomask illustrating an integrated circuit copper pin packaging structure and its fabrication method proposed in this invention.

[0016] Among them, 1. Glass substrate one; 2. Release layer one; 3. Circuit layer; 31. Dielectric layer; 32. Metal wiring layer; 33. T-structure; 34. Open structure; 4. Solder; 5. Copper pin; 6. Chip; 7. Glass substrate two; 71. Release layer two; 8. Metal ball; 9. Molded body; 10. Filler; 11. Photomask; 12. Bump; 13. Pad.

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0020] like Figures 1-12 As shown, this invention proposes an integrated circuit copper pin packaging structure and its fabrication method, as follows: Figure 1 As shown, the process includes step one: preparing the glass carrier plate 1 to be processed, which serves as a temporary support for the entire encapsulation structure. The glass carrier plate 1 can be circular or square, but is not limited to these.

[0021] like Figure 2 As shown, step two: apply or attach release layer 2 on top of glass carrier plate 1. Release layer 2 can be a heat-sensitive or photosensitive release adhesive, the purpose of which is to facilitate the removal of glass carrier plate 1 after heating or from the product after subsequent processes.

[0022] like Figure 3As shown, step three: A circuit layer 3 is disposed above the glass substrate 1. The circuit layer 3 includes multiple dielectric layers 31 and multiple metal wiring layers 32. The multilayer interconnect structure is formed by alternately depositing dielectric layers 31 and metal wiring layers 32, combined with photolithography, etching and other processes. The dielectric layer 31 includes, but is not limited to, polymer materials such as polyimide (PI), benzocyclobutene (BCB) or polybenzoxazole (PBO), and is formed by spin coating, curing and other processes. The metal wiring layer 32 includes, but is not limited to, a copper metal layer, and is formed by sputtering a seed layer, photolithography, electroplating and etching and other processes, and is used to realize the redistribution layer (RDL) function of the circuit.

[0023] In some implementations, the circuit layer 3 includes at least two dielectric layers 31 and at least one metal wiring layer 32 to enable more complex circuit interconnections.

[0024] Among them, the top metal wiring layer is the uppermost metal wiring layer 32 in the circuit layer 3, which is the top metal wiring layer 32-1. The top metal wiring layer 32-1 includes a T-shaped structure 33. The method for forming the T-shaped structure 33 specifically includes: before forming the top metal wiring layer 32, performing a photolithography process on the dielectric layer 31-1 below it using a photomask 11 to transfer the circuit design pattern corresponding to the T-shaped structure 33 into the dielectric layer 31-1. For example... Figure 12 As shown, the photomask 11 is designed with a specific pattern A, including a circular structure, a rectangular structure, or a rhomboid structure. An opening structure 34 is formed in the dielectric layer 31-1 by exposure and development processes. The pattern A forms the opening structure 34 at the corresponding position in the dielectric layer 31-1. The top metal wiring layer 32-1 is fabricated by electroplating, and the opening structure 34 on the dielectric layer 31-1 is filled to form the vertical part of the T-shaped structure 33. This can improve the bonding force between the top metal wiring layer 32-1 and the copper pins 5 subsequently placed above the T-shaped structure 33, and prevent the copper pins 5 from peeling off along the upper surface of the dielectric layer 31-1 below the top metal wiring layer 32-1.

[0025] In a preferred embodiment, the photomask 11 has a circular structure opposite to the opening structure 34. When the dielectric material used is negative, the circular structure is designed as a solid structure. When the dielectric material is cured by ultraviolet light, the position corresponding to the solid structure is not exposed and is not illuminated. This part of the dielectric material is dissolved and removed in the subsequent developing solution, thereby forming the opening structure 34. The circular structure on the photomask 11 helps to optimize the focusing and developing effects in the photolithography process, reduce edge stress concentration, and thus enhance the reliability of the vertical portion of the T-shaped structure 33.

[0026] like Figure 4As shown, step four: Solder 4 is applied above the formed T-shaped structure 33 by printing or dot coating, and copper pins 5 are mounted on the solder 4. The methods for mounting the copper pins 5 include, but are not limited to, using a pin-planting fixture or positioning fixture to plant the copper pins 5 or transferring the copper pins 5 onto the solder 4. The copper pins 5 establish an electrical connection with the top metal wiring layer 32-1 of the circuit layer 3 through the solder 4, thereby achieving electrical interconnection between the copper pins 5 and the circuit layer 3.

[0027] like Figure 5 As shown, step five: On top of circuit layer 3, chip 6 is mounted using flip-chip bonding or other mounting processes. Bumps 12 are formed on the active surface of chip 6. These bumps 12 include, but are not limited to, copper pillars and solder balls. The bumps 12 on chip 6 are precisely aligned with the pads 13 above circuit layer 3 to achieve electrical connection. Bonding is achieved through thermoforming or reflow soldering, realizing both electrical connection and mechanical fixation between chip 6 and circuit layer 3.

[0028] like Figure 6 As shown, in some embodiments, after step five, an underfill operation is performed on the bonded chip 6, whereby the filler 10 fills the gap between the chip 6 and the circuit layer 3 through capillary action and is then cured to protect the connection points of the bump 12 and improve the reliability of the package.

[0029] like Figure 7 As shown, step six: through the molding process, a molding compound 9 is formed that covers the copper pin 5, the chip 6 and the circuit layer 3; the entire structure is integrated into a robust whole, providing mechanical protection and environmental protection.

[0030] like Figure 8 As shown, step seven: remove excess plastic encapsulation 9 by grinding to expose the surfaces of copper needle 5 and chip 6. Grinding methods include, but are not limited to, mechanical grinding, grinding machine grinding, etc., and the grinding thickness is controlled during the grinding process.

[0031] like Figure 9 As shown, in step eight: after grinding, the exposed end of the copper needle 5 and the back of the chip 6 are attached to the glass carrier plate 7 through the release layer 71 to temporarily fix the copper needle 5 and the chip 6. Then, the release layer 2 loses its adhesiveness by means of laser irradiation or heating, thereby removing the glass carrier plate 1 and the release layer 2 below the circuit layer 3 as a whole, exposing the lower surface of the circuit layer 3.

[0032] like Figure 10 As shown, after flipping the product over, metal balls 8 are placed on the exposed lower surface of the circuit layer 3 using a ball-planting process, serving as the interface for external connection of the package.

[0033] like Figure 11As shown, the glass substrate 2 7 and release layer 2 71 are removed to expose the copper pin 5 and chip 6. The metal ball 8 is reliably connected to the external circuit through reflow soldering, thus completing the entire packaging process.

[0034] like Figure 11 As shown, this invention discloses an integrated circuit copper pin packaging structure, including a circuit layer 3 comprising five dielectric layers 31 and four metal wiring layers 32. Multi-layer three-dimensional interconnect channels are formed by alternately depositing dielectric layers 31 and metal wiring layers 32, combined with photolithography and etching processes. An opening structure 34 is formed in the dielectric layer 31 below the top metal wiring layer 32. The top metal wiring layer 32 includes a T-shaped structure 33, the vertical portion of which is disposed in the opening structure 34. This increases the contact area with the copper pins 5 and enhances the bonding strength during subsequent operations, preventing the copper pins 5 from detaching from the surface of the dielectric layer 31. This ensures the reliability of the copper pins 5 as interconnect pins and achieves stable conduction between the chip 6 and external circuits.

[0035] Chip 6 is the core functional carrier of the integrated circuit. The bumps 12 on the surface of chip 6 are used for interconnection with the outside and are the signal and functional core of the entire package structure. A filler 10 is filled between chip 6 and circuit layer 3. The elastic deformation of the colloid relieves the thermal stress caused by the difference in thermal expansion coefficients between chip 6 and circuit layer 3. The effect is to prevent the chip bumps 12 from cracking or falling off due to thermal cycling, thereby improving the fatigue resistance and long-term reliability of the package structure.

[0036] The copper pins 5 at both ends of the chip 6 are positioned below the circuit layer 3 via solder 4. Reflow soldering melts the solder 4 and fills the gap between the copper pins 5 and the circuit layer 3, forming a strong mechanical connection and electrical conductivity. A metal ball 8 is located below the circuit layer 3, serving as the I / O interface on the other side.

[0037] Metal ball 8 is disposed below the circuit layer 3 to adapt to the soldering requirements of external substrates such as PCB boards, so as to realize convenient and reliable interconnection between the package and external circuits.

[0038] A molding compound 9 is provided outside the copper pin 5, chip 6 and circuit layer 3. The molding compound 9 includes, but is not limited to, epoxy resin material. The epoxy resin is filled into the cavity and cured by high temperature and high pressure molding process to form a dense protective shell, which isolates the internal structure from external environmental factors such as moisture, dust and impurities. At the same time, it provides mechanical support to prevent the copper pin 5 and chip 6 from being damaged by external force collision, and ensures the environmental adaptability and mechanical strength of the packaging structure.

[0039] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0040] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

[0041] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A method for fabricating an integrated circuit copper pin packaging structure, characterized in that: The manufacturing method includes the following steps: Step 1: Prepare glass carrier plate 1 (1); Step 2: Set release layer 1 (2) above the glass carrier plate 1 (1); Step 3: A circuit layer (3) is formed above the release layer (2). The circuit layer (3) includes multiple dielectric layers (31) and multiple metal wiring layers (32). The top metal wiring layer (32) includes a T-shaped structure (33). The method for forming the T-shaped structure (33) includes: before forming the top metal wiring layer (32), an exposure and development process is performed in the dielectric layer (31) below it using a photomask (11) to form an opening structure (34); then, when forming the top metal wiring layer (32), metal is filled into the opening structure (34) to form the vertical part of the T-shaped structure (33); Step 4: Place solder (4) on the T-shaped structure (33) and attach copper pins (5) on the solder (4); Step 5: Mount the chip (6) on top of the circuit layer (3); Step 6: Through the molding process, a molding compound (9) is formed that covers the copper pin (5), the chip (6) and the circuit layer (3). Step 7: Grind the encapsulated body (9) to expose the end of the copper needle (5).

2. The method for fabricating an integrated circuit copper pin packaging structure according to claim 1, characterized in that: Following step seven, the following steps are also included: A glass carrier plate 2 (7) is attached above the copper pin (5) and the chip (6) through a release layer 2 (71), and the glass carrier plate 1 (1) and the release layer 1 (2) below the circuit layer (3) are removed. Metal balls (8) are disposed on the surface of the circuit layer (3); Remove the second glass carrier plate (7) and the second release layer (71), and perform reflow soldering to complete the encapsulation.

3. The method for fabricating an integrated circuit copper pin packaging structure according to claim 1, characterized in that: In step three, a circular or rectangular structure is provided on the photomask (11) opposite to the opening structure (34).

4. The method for fabricating an integrated circuit copper pin packaging structure according to claim 1, characterized in that: In step three, the circuit layer (3) includes at least two dielectric layers (31) and one metal wiring layer (32).

5. The method for fabricating an integrated circuit copper pin packaging structure according to claim 1, characterized in that: In step five, the chip (6) is mounted on the circuit layer (3) by flip-chip bonding.

6. The method for fabricating an integrated circuit copper pin packaging structure according to claim 5, characterized in that: The chip (6) is provided with bumps (12), and the bumps (12) are connected to the corresponding pads on the circuit layer (3).

7. The method for fabricating an integrated circuit copper pin packaging structure according to claim 5, characterized in that: After step five, bottom filling is performed around the circuit layer (3) and the chip (6).

8. An integrated circuit copper pin packaging structure prepared by any one of the manufacturing methods according to claims 1-7, characterized in that: The circuit layer (3) includes multiple dielectric layers (31) and multiple metal wiring layers (32). The dielectric layer (31) below the top metal wiring layer (32) includes an opening structure (34). The top metal wiring layer (32) includes a T-shaped structure (33). The vertical part of the T-shaped structure (33) is disposed in the opening structure (34). A chip (6) is disposed above the circuit layer (3), and a filler (10) is disposed in the middle of the chip (6) and the circuit layer (3). A copper needle (5) is placed above the T-shaped structure (33) by solder (4); Metal ball (8) is disposed below the circuit layer (3).

9. The integrated circuit copper pin packaging structure according to claim 8, characterized in that: It also includes a molding compound (9), which encapsulates the chip (6), copper pins (5), and part of the circuit layer (3).

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