Pixel circuit with memory circuit and image sensor for event detection

Abstract

A pixel circuit includes a capacitive element that receives a pixel voltage (VPR) at a first electrode. The event detection circuit outputs a comparator result signal VC, where the comparator result signal VC changes to an active level when a resettable floating voltage at a floating second electrode of the capacitive element exceeds a predefined threshold voltage VT. The multi-mode memory circuit outputs an event signal EV in which, in a first mode, the event signal EV follows the comparator result signal VC, and in a second mode, the event signal EV changes to an active level in response to receiving an active comparator result signal VC, and changes to a non-active level in response to receiving an active memory reset signal RESL.

Description

[0001] This disclosure relates to pixel circuitry including memory circuitry and image sensors for event detection. More specifically, this disclosure relates to the field of event detection sensors that respond to predefined changes in light intensity, such as dynamic vision sensors (DVS) and event-based vision sensors (EVS). Background Technology

[0002] Event detection image sensors (such as DVS and EVS) deliver information about the location of predefined changes in the imaged scene. Unlike image sensors that transmit large amounts of image information in frames, information about unchanging pixels can be omitted, resulting in intra-pixel data compression. Intra-pixel data compression eliminates data redundancy and combines high temporal resolution with low latency, low power consumption, high dynamic range, and minimal motion blur.

[0003] Pixel circuits used in DVS and EVS detect ON and OFF events. An ON event indicates that the radiant intensity has increased from its initial value by at least a predefined step, and an OFF event indicates that the radiant intensity has decreased from its initial value by at least a predefined step. An EVS pixel circuit with a single comparator sequentially compares a differential voltage derived from the current and previous radiant intensities with a first threshold voltage to check for an ON event, and with a second threshold voltage to check for an OFF event. EVS pixel circuits with capacitor amplifiers typically use two parallel comparators that can simultaneously test for both ON and OFF events.

[0004] The EVS pixel circuit that detects an ON or OFF event stores the event until the pixel circuit is read again. Once the pixel circuit is read, the event is cleared. Clearing the event typically involves a self-zeroing process (“self-zeroing process”, “auto-zeroing”) that resets the differential voltage to its initial value. Summary of the Invention

[0005] In the EVS image sensor, a valid comparator result signal indicating that an event has been detected by the pixel circuit triggers a readout request to the arbitrator circuit. The arbitrator circuit receives and prioritizes the current readout request. The arbitrator circuit outputs an acknowledgment signal to the pixel circuit selected for the next readout. In response to receiving the acknowledgment signal, the pixel circuit outputs an event signal on the data bus indicating the type of event detected and begins a self-zeroing process.

[0006] During the waiting time from the start of event detection to the start of outputting the detected event, the radiation intensity can be changed again in the direction of the initial value, such that the differential voltage no longer exceeds a predefined step increase or drops below a predefined step decrease. The comparator result signal returns to an inactive voltage level. When the pixel circuit outputs the event signal based on the instantaneous comparator result signal, the event data signal does not indicate any event. In this way, short light pulses and short dark periods that end before the pixel circuit outputs event data can be missed. The waiting time for the effect to occur depends on the instantaneous effectiveness of the image sensor's pixel circuitry.

[0007] This technology was developed in view of this situation, and its purpose is to improve event detection in pixel circuits used for event detection.

[0008] In this regard, this disclosure relates to a pixel circuit including a capacitor element configured to receive a pixel voltage VPR at a first electrode. An event detection circuit outputs a comparator result signal, wherein the comparator result signal VC changes to an active level when the resettable floating voltage at the floating second electrode of the capacitor element exceeds a predefined threshold voltage VT. A multi-mode memory circuit outputs an event signal EV, wherein in a first mode, the event signal EV follows the comparator result signal VC, and in a second mode, the event signal EV changes to an active level in response to receiving a valid comparator result signal VC, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

[0009] The first mode is geared towards human visual perception and performs adaptive data compression at the pixel level. The more movement and change in the scene, the more events (especially transient events) are filtered out at the pixel level. The second mode enables reliable detection of typical short-light events during the technical process, such as detecting artificial radiation sources in the imaged scene and / or detecting radiation emitted by radiation sources used for distance measurement, for example, by using structured light and / or time-of-flight methods.

[0010] The described embodiments and other advantages will be best understood by referring to the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a schematic diagram illustrating an example configuration of an imaging device according to an embodiment, the imaging device including a solid-state imaging apparatus having pixel circuitry.

[0012] Figure 2 This is a simplified block diagram illustrating an example configuration of a solid-state imaging device with pixel circuitry according to an embodiment, wherein a multi-mode memory circuitry is integrated into an image sensor for synchronous readout.

[0013] Figure 3 This is a simplified block diagram illustrating an example configuration of a solid-state imaging apparatus having pixel circuitry for continuous detection according to an embodiment, wherein the pixel circuitry is integrated into an image sensor for asynchronous readout.

[0014] Figure 4 This is a schematic diagram illustrating an embodiment in which the solid-state imaging device has a two-layer structure arranged in a stacked CIS configuration.

[0015] Figure 5 This is a simplified circuit diagram illustrating an example configuration of a pixel circuit with a multi-mode memory circuit according to an embodiment.

[0016] Figure 6 This is a simplified circuit diagram illustrating an example configuration of a pixel circuit having a multi-mode memory circuit based on two latch circuits, according to an embodiment.

[0017] Figure 7 This is a simplified circuit diagram illustrating an example configuration of a pixel circuit with a multi-mode memory circuit based on two latch circuits having enable inputs, according to an embodiment.

[0018] Figure 8 It is used to illustrate the operation according to the embodiment, having such Figure 7 The timeline of the image sensor method shown in the pixel circuit is illustrated.

[0019] Figure 9 It is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0020] Figure 10 It is an auxiliary explanation Figure 9 A diagram illustrating an example of the mounting positions of the vehicle external information detection unit and the imaging unit in a vehicle control system. Detailed Implementation

[0021] The embodiments for implementing the technology of this disclosure will now be described in detail using the accompanying drawings. The technology of this disclosure is not limited to the described embodiments, and the various numerical values, etc., in the embodiments are merely illustrative. Identical elements and elements having the same function are indicated by the same reference numerals. Repeated descriptions are omitted.

[0022] Connected electronic components can be electrically connected via direct and permanent low-resistivity connections (e.g., via wires). The terms "connection," "electrical connection," and "signal connection" can also include connections provided by other electronic components and suitable for permanent and / or temporary signal and / or energy transmission. For example, electronic components can be electrically or signal connected via resistors, capacitors, and electronic switches such as transistors or transistor circuits, e.g., MOSFETs, transmission gates, and others.

[0023] The load path of a transistor is the controlled current path of the transistor. For example, the voltage applied to the gate of a field-effect transistor (FET) controls the current flow through the load path (controlled path) between the source and drain of the FET via the field effect.

[0024] Digital signals alternate between at least one active level and at least one inactive level. A digital signal with an active level is valid. A digital signal with an inactive level is invalid. Individually, for each signal, the active level can be a digital high level and the inactive level can be a digital low level, or the active level can be a digital low level and the inactive level can be a digital high level.

[0025] exist Figure 1 In the imaging device 1, there are an optical system 91, a solid-state imaging device 90, a storage unit 92, and a control unit 93. The optical system 91 includes one or more lenses and various mechanisms (such as an autofocus mechanism and an aperture mechanism), and guides light from the object to the light-receiving surface of the solid-state imaging device 90.

[0026] The solid-state imaging device 90 includes an image sensor having multiple pixel circuits. Each pixel circuit includes a photoelectric conversion element that converts incident radiation into an electrical signal through photoelectric conversion and outputs an electrical signal. The solid-state imaging device 90 also includes a signal processing unit that performs predetermined signal processing on the electrical signals output from the pixel circuits and outputs image data based on the electrical signals.

[0027] Storage unit 92 stores image data output from solid-state imaging device 90 in a storage medium. The storage medium may include volatile storage media and / or non-volatile storage media. Non-volatile storage media may be or include flash memory or hard disk drive. Non-volatile storage media may be or include dynamic random access memory (DRAM).

[0028] The control unit 93 controls the solid-state imaging device 90, causing the solid-state imaging device 90 to perform imaging operations. The imaging operations include capturing images of objects or scenes and outputting image data, which includes image information about changes in the appearance of the object or changes in the scene.

[0029] Figure 2 and Figure 3 This is a block diagram illustrating a configuration example of a solid-state imaging apparatus 90 applicable to an embodiment, the solid-state imaging apparatus having an image sensor 80 including pixel circuitry 100. The solid-state imaging apparatus 90 includes the image sensor 80 and a signal processing unit 60. In both figures, the image sensor 80 includes a pixel array 10, a signal buffer circuit 20, a row arbiter 30, and a sensor control circuit 50.

[0030] In pixel array 10, multiple pixel circuits 100 are arranged in a two-dimensional matrix into pixel rows and pixel columns. For simplicity, pixel circuits 100 belonging to the same pixel row are arranged along... Figure 2 and Figure 3 The horizontal lines in the diagram, and the pixel circuits 100 belonging to the same pixel column along... Figure 2 and Figure 3 Vertical lines are arranged in the middle.

[0031] Each pixel circuit 100 includes a radiation-sensitive circuit that outputs a pixel voltage with a voltage level corresponding to the intensity of the received radiation.

[0032] The pixel circuit 100 also includes a capacitor element that receives the pixel voltage at the first electrode. The event detection circuit outputs a comparator result signal, wherein the comparator result signal changes to an active level when the resettable floating voltage at the floating second electrode of the capacitor element exceeds a predefined threshold voltage. The multi-mode memory circuit that outputs the event signal is capable of operating in at least two modes. In a first mode, the event signal follows the comparator result signal. In a second mode, the event signal changes to an active level in response to receiving a valid comparator result signal and changes to an inactive level in response to receiving a valid memory reset signal.

[0033] The event detection circuit detects events based on the magnitude of changes in pixel voltage received from the radiation-sensitive circuit. Each event detection circuit can be reset to its initial state by temporarily turning on a self-zeroing switch, which resets the resettable voltage during self-zeroing. Pixel logic controls the output of event data from pixel circuit 100 and the self-zeroing of the event detection circuit.

[0034] Event data can indicate that the intensity of incident radiation has decreased by more than a step decrease value compared to a previous event readout (“OFF event”). Alternatively, event data can indicate that the intensity of incident radiation has increased by more than a step increase value compared to the amplitude at the time of a previous event readout (“ON” event).

[0035] The signal buffer circuit 20 transmits one or more threshold voltages and memory mode signals to each group of pixel circuits 100 via the control bus 21. Each group of pixel circuits 100 may include some or all of the pixel circuits 100 of a pixel row, more than one pixel row of pixel circuits 100, or all of the pixel circuits 100 of the pixel array 10.

[0036] Figure 2This relates to an image sensor 80 for synchronous readout. A group control bus 31 connects pixel circuits 100 to a row arbiter 30. Each group control bus 31 connects a group of pixel circuits 100 to the row arbiter 30. Each group control bus 31 includes a group request line for transmitting request signals from pixel circuits 100 of a pixel group to the row arbiter 30 and a group response line for transmitting future group response signals from the row arbiter 30 to the selected pixel circuit 100 in the group of pixel circuits 100.

[0037] For each pixel circuit 100 that detects an event, the pixel logic of the involved pixel circuit 100 outputs a valid request to the row arbitrator 30 on the group request line. To transmit the request, the request signal transmitted on the group request line has a valid level.

[0038] The row arbitrator 30 performs arbitration among pending valid requests output from the pixel circuits 100 of the pixel array 10. The row arbitrator 30 selects a request received from a specific group of pixel circuits 100, acknowledges the selected request by outputting an acknowledgment on the group control bus 31, and transmits the corresponding group address (e.g., row number) to the column readout circuit 40. To transmit the acknowledgment, the row arbitrator 30 outputs a valid group acknowledgment signal on the group acknowledgment line. The valid group acknowledgment signal selects a group of pixel circuits 100.

[0039] In response to this confirmation, all selected pixel circuits 100 where an event has been detected apply event data on the corresponding event data bus 41. Each event data bus 41 may be connected to some or all pixel circuits 100 in the same pixel column, or to all pixel circuits 100 in more than one pixel column.

[0040] The event data bus 41 may include a common data line for transmitting ON and OFF events using different signal levels or a time-multiplexed scheme. In the illustrated embodiment, the event data bus 41 includes a first data line 42 for transmitting ON events and a second data line 43 for transmitting OFF events. For transmitting an ON event, the ON event data signal transmitted on the first data line 42 has an active level. For transmitting an OFF event, the OFF event data signal transmitted on the second data line 43 has an active level.

[0041] The column readout circuit 40 receives event data from all pixel circuits 100 of the selected pixel group via the event data bus 41, and receives from the row arbitrator 30 the group address of the selected pixel group from which the received event data originates. Based on the group address and the identifier of the event data bus 41 that transmits the event data, the column readout circuit 40 compiles a Digital Address Event Representation (AER) for each event. The AER includes the group address, the column address derived from the identifier of the event data bus that transmits the event, the event data, and (if applicable) a timestamp. The column readout circuit 40 outputs the AER to the signal processing unit 60.

[0042] Figure 3 The solid-state imaging device 90 is configured for asynchronous, event-triggered readout. Each pixel circuit 100 that detects an event indicates the event by outputting a group request signal to the row arbiter 30 on the group request line of the group control bus 31 and a column request signal to the column arbiter 45 on the column interface bus 46. In the row arbiter 30 and column arbiter 45, the request signal triggers the compilation of event information. The event information includes a pixel address identifying the position of the pixel circuit 100 in the pixel array 10, a symbol for the light intensity change, and a timestamp. The row arbiter 30 and column arbiter 45 output the event information to the signal processing unit 60 and acknowledge receipt of the event to the pixel circuit 100. Upon receiving the acknowledgment, the event in the pixel circuit 100 is cleared and the pixel circuit 100 is reset.

[0043] Figure 2 and Figure 3 The sensor control circuit 50 can control the timing of changing the analog voltage signal in the signal buffer circuit 20, select the voltage level output by the signal buffer circuit 20 according to internal state and / or user settings, store the mode signal, and / or... Figure 2 The column readout circuit 40 and the signal processing unit 60 are located between or between the two. Figure 3 Communication between the row arbitrator 30, column arbitrator 45 and signal processing unit 60 (as indicated by the dashed lines).

[0044] The signal processing unit 60 receives the AER (Average Errata). The signal processing unit 60 can perform signal processing, such as image recognition processing, based on the received AER. The signal processing unit 60 can output the processed image data to... Figure 1 The processed image data is output from the storage unit 92 and / or via a wired or wireless electronic interface.

[0045] For reference Figure 2 and Figure 3The described solid-state imaging device 90 can be provided as, for example, a stacked contact image sensor (CIS) formed by stacking multiple semiconductor chips. As an example, the solid-state imaging device 90 can be formed of a two-layer structure in which semiconductor chips are stacked in two layers.

[0046] Figure 4 It is shown in the diagram. Figure 2 or Figure 3 The solid-state imaging device 90 is illustrated as an example formed by a stacked CIS with a two-layer structure, including a radiation receiving chip 910 and a processing chip 920. The radiation receiving chip 910 includes at least a photoelectric conversion element. For example, the radiation receiving chip 910 may include only the photoelectric conversion element, or a portion of a radiation-sensitive circuit including the photoelectric conversion element and one or more transistors, or the complete radiation-sensitive circuit, or other elements of the complete radiation-sensitive circuit and pixel circuitry. The processing chip 920 includes other elements of the pixel circuitry 100, such as event detection circuitry and pixel logic. Figure 4 The right side shows a solid-state imaging device 90 formed by bonding a radiation receiving chip 910 and a processing chip 920, wherein contact pads on the radiation receiving chip 910 and corresponding contact pads on the processing chip 920 are bonded together to form an electrical contact between the radiation receiving chip 910 and the processing chip 920.

[0047] Figure 5 It shows how to use such Figure 2 The synchronous image sensor 80 shown or such Figure 3 The block diagram of the pixel circuit 100 of the asynchronous image sensor 80 is shown.

[0048] Pixel circuit 100 includes capacitor element 121, which receives pixel voltage VPR at a first electrode. Event detection circuit 140 outputs comparator result signal VC, wherein the comparator result signal VC changes to an active level when the resettable floating voltage VF at the floating second electrode of capacitor element 121 exceeds a predefined threshold voltage VT. Multi-mode memory circuit 200 outputs event signal EV, wherein in a first mode, event signal EV follows comparator result signal VC, and in a second mode, event signal EV changes to an active level in response to receiving a valid comparator result signal VC, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

[0049] The voltage level of the pixel voltage VPR increases as the radiation intensity detected by the pixel circuit 100 increases.

[0050] Capacitor element 121 receives the pixel voltage VPR at the first electrode. The second electrode of capacitor element 121 forms a differential node 122. During the self-zeroing period, differential node 122 is forced to a predefined reference voltage. Immediately after the self-zeroing period, the capacitor voltage VPT across capacitor element 121 is defined by the voltage difference between the pixel voltage VPR immediately after reset and the reference voltage VR.

[0051] During the detection period following the self-zeroing period, differential node 122 is floated. When the first differential node 122 is floated, the capacitor voltage VP remains at least approximately constant and the float voltage VF follows the change in pixel voltage VPR. The change in pixel voltage VPR relative to the end of the reset is converted into a voltage change relative to the reference voltage VR.

[0052] During the detection period, pixel circuit 100 is in detection mode, and the instantaneous value of the floating voltage VF is a function of the difference between the instantaneous voltage level of pixel voltage signal VPR and the voltage level of pixel voltage signal VPR immediately after reset. The floating voltage VF at differential node 122 is a function of the detected change in radiation intensity. The change in radiation intensity involves the difference in radiation intensity between the current time and immediately before the end of reset.

[0053] The event detection circuit 140 outputs a valid comparator result signal VC when the floating voltage VF at the differential node 122 exceeds a predefined threshold voltage VT. For example, the event detection circuit 140 outputs a valid comparator result signal VC as long as the floating voltage VF at the differential node 122 exceeds a predefined upper threshold voltage, or as long as the floating voltage VF at the differential node 122 is lower than a predefined lower threshold voltage.

[0054] The multi-mode memory circuit 200 operates in at least two different modes: In the first mode, the event signal EV output from the multi-mode memory circuit 200 follows the comparator result signal VC, wherein the event signal EV is valid only when the comparator result signal VC is valid, and invalid only when the comparator result signal VC is invalid. The change of the event signal EV between valid and invalid states may be delayed by several nanoseconds relative to the corresponding change in the comparator result signal.

[0055] In the second mode (latch mode), the multi-mode memory circuit 200 latches the comparator result signal VC from invalid to valid transition, and outputs the latched valid comparator result signal VC until the valid memory reset signal RESL resets the multi-mode memory circuit 200.

[0056] In the first mode of the multi-mode memory circuitry, the pixel circuitry performs adaptive data compression at the pixel level by suppressing rapid changes in pixel illumination. The second mode enables reliable detection of short illumination events from artificial radiation sources (such as pulsed radiation sources) and / or the detection of reflected radiation from radiation emitters used for structured light and / or time-of-flight applications in the imaged scene.

[0057] The multi-mode memory circuit 200 is in the first mode when the memory mode signal MODL is not valid, and in the second mode when the memory mode signal MODL is valid.

[0058] The same memory mode signal MODL can be applied to all pixel circuits 100 of the pixel array. Alternatively, a first memory mode signal MODL can be applied to a first group of pixel circuits, and a second memory mode signal MODL can be applied to a second group of pixel circuits 100. The second memory mode signal can be an inverted version of the first memory mode signal. The first group of pixel circuits and the second group of pixel circuits 100 can complement each other in the pixel array. The first group of pixel circuits 100 can include one or more complete pixel columns, one or more complete pixel rows, or a pixel subarray having pixel circuits 100 from neighboring pixel columns and neighboring pixel rows.

[0059] In range-measuring configurations (such as ToF and patterned illumination methods), changes in the memory pattern signal can be synchronized with radiation emitted from the radiation source.

[0060] The concept of Memory Mode Signaling (MODL) prevents oversensitivity to rapidly changing signals or noise coupling and facilitates an adjustable tradeoff between depth mapping performance and 2D imaging performance of image sensors.

[0061] The functions of the event detection circuit 140 and the multi-mode memory circuit 200 can be combined in a latch comparator or in a serial combination of a comparator circuit and a latch, such as an improved RS flip-flop.

[0062] Figure 6 An example of a pixel circuit 100 is shown, which has an event detection circuit 140 including two comparator circuits 131, 132 operating in parallel.

[0063] The pixel circuit 100 shown includes a radiation-sensitive circuit 110 that converts incident radiation into a pixel voltage VPR, wherein the pixel voltage VPR increases with increasing radiation intensity.

[0064] The radiation-sensitive circuit 110 includes a photoelectric conversion element 111 and a photosensor circuit 112. The photoelectric conversion element 111 may include or be composed of a photodiode, which converts electromagnetic radiation incident on the detection surface of the pixel circuit 100 into a photodetector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation, and / or ultraviolet radiation. The amplitude of the photodetector current corresponds to the intensity of the incident electromagnetic radiation, wherein, within the range of interest, the photodetector current can increase approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0065] The photodetector circuit 112 converts the photodetector current into a pixel voltage VPR. The voltage level of the pixel voltage VPR is a function of the photodetector current, wherein, within the voltage range of interest, the voltage amplitude of the pixel voltage VPR increases continuously as the photodetector current increases.

[0066] The photosensitive circuit 112 includes, for example, a logarithmic amplifier and a buffer circuit. The logarithmic amplifier logarithmically converts the photodetector current into a voltage signal, and the buffer circuit outputs the amplified and buffered voltage as the pixel voltage VPR. The pixel voltage VPR increases logarithmically with the photodetector current.

[0067] The first electrode of capacitor element 121 is electrically connected to the output of photosensitive circuit 112 and receives pixel voltage VPR at the first electrode. The second electrode of capacitor element 121 floats during the detection period. The floating voltage VF at the second electrode of capacitor element 121 changes in response to changes in pixel voltage VPR.

[0068] The event detection circuit 140 of the pixel circuit 100 includes a capacitor amplifier circuit 120, which receives a floating voltage VF at the amplifier input and outputs an amplified voltage signal VA at the amplifier output.

[0069] The capacitor amplifier circuit 120 includes a switched capacitor amplifier, which includes an inverting amplifier circuit 123 and a feedback capacitor 125. The input of the inverting amplifier circuit 123 is electrically connected to the second electrode of the capacitor element 121. The inverting amplifier circuit 123 outputs an amplified voltage signal VA at the output of the capacitor amplifier circuit 120, where the amplified voltage signal VA represents the amplified voltage difference between the previously evaluated pixel voltage VPR and the current pixel voltage VPR. The feedback capacitor 125 is connected in parallel between the input and the output of the inverting amplifier circuit 123.

[0070] The event detection circuit 140 includes a first comparator circuit 131 configured to output a first comparator result signal VC1. The first comparator result signal VC1 is valid when the amplified signal exceeds a first threshold voltage VT1.

[0071] The first comparator result signal VC1 is invalid when the amplified signal does not exceed the first threshold voltage VT1. The first comparator circuit 131 receives the amplified voltage signal VA from the output of the capacitor amplifier circuit 120 at the first comparator input and compares the amplified voltage signal VA with the first threshold voltage VT1 applied to the second comparator input. The multi-mode memory circuit 200 receives the first comparator result signal VC1 at the first memory input I / S.

[0072] The multi-mode memory circuit 200 outputs an on event signal EV1 at the first memory output O / Q. In the first mode, the on event signal EV1 follows the first comparator result signal VC1. In the second mode, the on event signal EV1 changes to an active level in response to receiving a valid first comparator result signal VC1, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

[0073] The second comparator circuit 132 is configured to output a second comparator result signal VC2. The second comparator result signal VC2 is valid when the amplified signal is reduced to below the second threshold voltage VT2.

[0074] The second comparator result signal VC2 is invalid if the amplified signal does not drop below the second threshold voltage VT2. The second comparator circuit 132 receives the amplified voltage signal VA from the output of the capacitor amplifier circuit 120 at the second comparator input and compares the amplified voltage signal VA with the second threshold voltage VT2 applied to the second comparator input. The multi-mode memory circuit 200 receives the second comparator result signal VC2 at the second memory input I / S.

[0075] The multi-mode memory circuit 200 outputs a shutdown event signal EV2 at the second memory output O / Q. In the first mode, the shutdown event signal EV2 follows the second comparator result signal VC2. In the second mode, the shutdown event signal EV2 changes to an active level in response to receiving a valid second comparator result signal VC2, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

[0076] The first comparator circuit 131 and the second comparator circuit 132 simultaneously compare the amplified voltage signal VA output from the capacitor amplifier circuit 120 with the first voltage threshold VT1 and the second voltage threshold VT2.

[0077] The multi-mode memory circuit 200 includes a first latch circuit 210 and a second latch circuit 220. The first latch circuit 210 and the second latch circuit 220 have the same electrical functionality. The first latch circuit 210 receives a first comparator result signal VC1 at the first memory input I / S and outputs an on event signal EV1 at the first memory output O / Q. The second latch circuit 220 receives a second comparator result signal VC2 at the second memory input I / S and outputs an off event signal EV2 at the second memory output O / Q.

[0078] The first latch circuit 210 and the second latch circuit 220 receive the same memory mode signal MODL at the mode input MD and the same memory reset signal RESL at the reset input R.

[0079] Pixel logic 150 receives an on event signal EV1 at the first input I1 and an off event signal EV2 at the second input I2.

[0080] The pixel logic 150 of the pixel circuit 100 includes an arbitrator interface circuit 155, which outputs a valid request signal REQ in response to receiving a valid event signal EV from the multi-mode memory circuit 200.

[0081] The valid event signal EV can be a valid on event signal EV1 received at the first input I1 or a valid off event signal EV2 received at the second input I2. The group control bus 31 connects the pixel circuitry 100 of a pixel group to the row arbitrator 30. The group control bus 31 includes a group request line 32, which connects the request output RQ of the arbitrator interface circuit 155 to... Figure 2 or Figure 3 The input electrical connections of the arbitrator 30 are as follows. The request output RQ can be, for example, an open-collector type.

[0082] like Figure 2 or Figure 3 The row arbiter 20 shown receives valid request signals REQ from each pixel group and selects one of the requested pixel groups for readout by selectively transmitting valid acknowledge signals ACK for the selected pixel group. For this purpose, the group control bus 31 includes a group acknowledge line 33 for transmitting the acknowledge signal ACK from the row arbiter 30 to the acknowledge input AK of the pixel circuitry 100 of the selected pixel group.

[0083] The pixel logic 150 of the pixel circuit 100 includes an event output circuit 151, which outputs an event data signal ON / OFF on the event data bus 41 in response to receiving a valid acknowledgment signal ACK.

[0084] More specifically, in response to receiving a valid acknowledgment signal ACK at the acknowledgment input AK, the event output circuit 151 outputs an ON event data signal to the first data line 42 via the first data output DO1 and an OFF event data signal to the second data line 43 via the second data output DO2 for synchronous reading. The ON event data signal is valid only when the ON event signal EV1 is valid, and the OFF event data signal is valid only when the OFF event signal EV2 is valid.

[0085] The pixel logic 150 of the pixel circuit 100 also includes a reset output circuit 154, which outputs a valid memory reset signal RESL in response to receiving a valid acknowledgment signal ACK.

[0086] The reset output circuit 154 outputs a memory reset signal RESL at the reset output ORes. The change of the memory reset signal RESL to an active level is delayed by a few nanoseconds relative to the change of the ACK signal to an active level, or there is no delay. The memory reset signal RESL and one of the ON and OFF event data signals can simultaneously become active, or the change of one of the ON and OFF event data signals to an active level and the change of the memory reset signal RESL to an active level can be slightly delayed relative to each other by at least a few nanoseconds. The change of the memory reset signal RESL to an inactive level can have a fixed timing relationship with the self-zeroing period of the pixel circuit 100.

[0087] Event detection circuit 140 also includes self-zeroing switch circuit m, which resets the resettable floating voltage VF in response to receiving a valid self-zeroing switch signal AZSW during the self-zeroing period.

[0088] The self-zeroing switching circuit 126 includes a switching path between the input and output of the inverting amplifier circuit 123. The self-zeroing switching circuit 126 may include a single enhancement-mode field-effect transistor (FET) or include an n-channel FET and a p-channel FET (where the switching path is electrically connected in parallel).

[0089] During the self-zeroing period, the pixel circuit 100 is in self-zeroing mode, which resets the floating voltage VF at the differential node 122 to a predefined reset voltage. Outside the self-zeroing period, the self-zeroing switch circuit 126 disconnects the second electrode of the capacitor element 121 from the output of the inverting amplifier circuit 123. The self-zeroing switch circuit 126 allows the potential at the differential node 122 to be reset to the reset voltage. During the detection period following the self-zeroing period, the floating voltage VF follows the change in the pixel voltage VPR.

[0090] The pixel logic 150 also includes a self-zeroing control circuit 159, which outputs a valid self-zeroing switch signal AZSW in response to receiving a valid acknowledgment signal ACK.

[0091] The self-zeroing control circuit 159 outputs a self-zeroing switch signal AZSW at the self-zeroing switch output OAz. The self-zeroing switch signal AZSW varies between an active and inactive level. An active self-zeroing switch signal AZSW turns on the self-zeroing switch circuit 126 during the self-zeroing period. An inactive self-zeroing switch signal AZSW turns off the self-zeroing switch circuit 126 at least outside the self-zeroing period (e.g., during the detection period).

[0092] If the self-zeroing switch circuit 126 includes an n-channel FET (nFET), then the effective level of the self-zeroing switch signal AZSW is a digital high level. If the self-zeroing switch circuit 126 includes a p-channel FET (pFET), then the effective level of the self-zeroing switch signal AZSW is a digital low level.

[0093] If the self-zeroing switching circuit 126 includes a pFET and an nFET (where the load paths are electrically connected in parallel), then the self-zeroing switching signal AZSW is applied to the gate of the nFET and the complementary self-zeroing switching signal xAZSW is applied to the gate of the pFET, wherein the self-zeroing switching signal AZSW and the complementary self-zeroing switching signal xAZSW have complementary active signal levels. The self-zeroing switching signal AZSW and the complementary self-zeroing switching signal xAZSW simultaneously change from an inactive level to an active level and simultaneously change from an active level to an inactive level.

[0094] exist Figure 7 In the pixel circuit 100, the multi-mode memory circuit 200 is insensitive to the comparator result signal VC when the input enable signal ENL is not valid, and is sensitive to the valid comparator result signal VC when the input enable signal ENL is valid.

[0095] When the multi-mode memory circuit 200 includes a first latch circuit 210 and a second latch circuit 220 with the same function, the first latch circuit 210 receives an input enable signal ENL at the first enable input EN, and the second latch circuit 220 receives an input enable signal ENL at the second enable input EN.

[0096] When the input enable signal ENL is valid, the first latch circuit 210 and the second latch circuit 220 are sensitive to the first comparator result signal VC1 and the second comparator result signal VC2. When the first latch circuit 210 and the second latch circuit 220 are sensitive to the first comparator result signal VC1 and the second comparator result signal VC2, they operate in the operating mode selected by the memory mode signal MODL. When the input enable signal ENL is invalid, the first latch circuit 210 and the second latch circuit 220 are insensitive to the first comparator result signal VC1 and the second comparator result signal VC2 (opaque), and the logic levels of the ON event signal and the OFF event signal do not change in response to changes in the first comparator result signal VC1 and / or the second comparator result signal VC2.

[0097] The input enable signal ENL can be generated by Figure 2 or Figure 3 The sensor controller 50 controls the input enable signal ENL and transmits it to the pixel circuit via the enable line of the control bus 21. For example, the sensor controller 50 can set the input enable signal ENL to an inactive level for a preset time when the validity of an event on the image sensor exceeds a predefined threshold.

[0098] In the illustrated embodiment, pixel logic 150 includes an enable control circuit 158 ​​configured to change the enable signal ENL from active to inactive and from inactive to active in response to changes in internal conditions of pixel logic 150.

[0099] Figure 8 It shows Figure 7 The following is a timing diagram of some signals from the pixel circuit 100. For each signal shown, the active level is high.

[0100] Initially, the input enable signal ENL and the memory mode signal MODL are valid. Pixel circuit 100 is in the second mode (latch mode). The self-zeroing switch signal AZSW is invalid. Pixel circuit 100 is in the detection period.

[0101] When the intensity of radiation incident on the radiation-sensitive area of ​​the photoelectric conversion element 111 increases to the point that the amplified voltage signal VA exceeds the first threshold voltage VT1, the first comparator result signal VC1 changes to an effective level at t=t0 and sets the first latch circuit 210, wherein the on event signal EV1 changes to an effective level.

[0102] Shortly after, at t=t1, pixel logic 150 outputs a valid request signal REQ to the row arbitrator. When the row arbitrator selects the pixel group including the requesting pixel circuit 100 for the next readout, the row arbitrator sends a valid acknowledge signal ACK to the pixel group including the requesting pixel circuit 100.

[0103] Pixel circuit 100 receives a valid acknowledgment signal ACK at t=t3. In response to receiving the valid acknowledgment signal ACK, pixel circuit 100 can continue to output event data, for example, by outputting an ON event data signal to the data signal line or by outputting a column request signal to the column arbitrator.

[0104] At t=t4, the self-zeroing period begins with pixel logic 150 outputting a valid self-zeroing switch signal AZSW with a valid high level and a valid memory reset signal RESL. The valid self-zeroing switch signal AZSW turns on the self-zeroing switch circuit 126. The valid memory reset signal RESL resets the first latch circuit 210, wherein the on event signal EV1 changes to an inactive level.

[0105] At t=t5, the self-zeroing switch signal AZSW begins to decrease, and the self-zeroing switch circuit 126 is turned off sufficiently slowly. At t=t6, the self-zeroing switch signal AZSW reaches a low level. The slow ramp of the self-zeroing switch signal AZSW prevents the floating voltage VF from changing when the self-zeroing switch circuit 126 is turned off. At t=t7, pixel logic 150 switches the memory reset signal RESL to an inactive level.

[0106] The length of the time interval between t1 and t3 depends on the number of events detected per time unit (event validity). When event validity is high, the time interval can be long enough for the comparator result signal VC1 to return to an invalid level within that time interval, where events will be lost. Latching prevents the loss of such events. For example, when the valid acknowledgment signal ACK is high, the input enable signal ENL can be low: this prevents the latch from storing new events and triggering new requests during readouts and before the current REQ-ACK cycle is complete.

[0107] Figure 9 This is a block diagram illustrating an example configuration of a vehicle control system that is an example of a system to which the technology of embodiments according to this disclosure can be applied.

[0108] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 9In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external vehicle information detection unit 12030, an internal vehicle information detection unit 12040, and an integrated control unit 12050. Additionally, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053 are illustrated as functional configurations of the integrated control unit 12050.

[0109] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 is used as a control device for the following: a drive force generating device (such as an internal combustion engine, drive motor, etc.) for generating the vehicle's driving force, a drive force transmission mechanism for transmitting the driving force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating the vehicle's braking force.

[0110] The body system control unit 12020 controls the operation of various devices supplied to the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for: keyless entry systems, smart key systems, power windows, or various types of lights, such as headlights, reversing lights, brake lights, turn signals, fog lights, etc. In this case, radio waves transmitted from a moving device that serves as a substitute for a key, or signals from various types of switches, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0111] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. The vehicle exterior information detection unit 12030 can be connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting objects (such as people, vehicles, obstacles, signs, characters on the road surface, etc.) or processing for detecting their distance.

[0112] The imaging unit 12031 may be or may include an image sensor or a solid-state imaging device having an image sensor, the image sensor including pixel circuitry according to embodiments of the present disclosure. The light received by the imaging unit 12031 may be visible light or invisible light (such as infrared light).

[0113] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle and may be, or may include, an image sensor or a solid-state imaging device having an image sensor according to embodiments of the present disclosure. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's state. For example, the driver state detection unit 12041 includes a camera that includes a solid-state imaging device and focuses on the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0114] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior (obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040), and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize functions of advanced driver assistance systems (ADAS), including collision avoidance or damping for the vehicle, distance-based following, speed-maintaining driving, collision warning, lane departure warning, etc.

[0115] In addition, the microcomputer 12051 can perform cooperative control intended for autonomous driving, which controls the drive force generation device, steering mechanism, braking device, etc. based on information about the vehicle’s exterior or interior (which is obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040), enabling the vehicle to drive autonomously without relying on driver operation.

[0116] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior, which is obtained by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicles detected by the vehicle exterior information detection unit 12030, thereby performing coordinated control aimed at preventing glare.

[0117] The sound / image output unit 12052 transmits an output signal of at least one of sound or image to an output device capable of visually or audibly notifying passengers of the vehicle or the exterior of the vehicle. Figure 9In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are illustrated as output devices. For example, display unit 12062 may include at least one of an in-vehicle display or a head-up display.

[0118] Figure 10 This is an illustration of an example of the mounting position of the imaging unit 12031, wherein the imaging unit 12031 may include imaging units 12101, 12102, 12103, 12104 and 12105.

[0119] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are located on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, and on the upper portion of the windshield inside the vehicle. Imaging unit 12101 located on the front nose and imaging unit 12105 located on the upper portion of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 located on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 located on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 located on the upper portion of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0120] Incidentally, Figure 10 An example of the imaging range of imaging units 12101 to 12104 is depicted. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above is obtained.

[0121] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, an imaging element having pixels for phase difference detection, or may include a ToF module, which includes an image sensor or a solid-state imaging device having an image sensor, the image sensor including pixel circuitry according to embodiments of the present disclosure.

[0122] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle in front, which specifically exists on the driving path of the vehicle 12100 and is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can pre-set a following distance to remain ahead of the vehicle in front and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, cooperative control intended for autonomous driving can be executed, enabling the vehicle to drive autonomously without relying on driver operation, etc.

[0123] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large-sized vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that are difficult for the driver of vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is therefore a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0124] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed by a procedure that extracts feature points in the image captured by the imaging units 12101 to 12104, which are infrared cameras, and a procedure that determines whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square outline for emphasis, so as to overlay it on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0125] Examples of vehicle control systems applicable to embodiments of the present disclosure have been described above. By applying an image sensor or a solid-state imaging device having an image sensor (which includes pixel circuitry according to embodiments of the present disclosure), high temporal resolution can be combined with low contrast sensitivity inhomogeneity.

[0126] Furthermore, the implementation of this technology is not limited to the above-described implementation, but various changes can be made within the scope of this technology without departing from its essential points.

[0127] An image sensor having pixel circuitry according to this disclosure can be any device for analyzing and / or processing radiation (such as visible light, infrared light, ultraviolet light, and X-rays). For example, a solid-state imaging device including an image sensor having pixel circuitry according to an embodiment can be any electronic device in the fields of transportation, home appliances, medicine and healthcare, security, beauty, sports, agriculture, image reproduction, etc.

[0128] Specifically, in the field of image reproduction, a solid-state imaging device including an image sensor with pixel circuitry according to an embodiment can be a device for capturing images to be provided for viewing, such as a digital camera, a smartphone, or a mobile phone device with camera functionality. In the transportation field, for example, a solid-state imaging device including an image sensor with pixel circuitry according to an embodiment can be integrated into a vehicle in-vehicle sensor (which captures the front, rear, perimeter, and interior of the vehicle for safe driving, such as automatic parking, driver status recognition, etc.), into a surveillance camera that monitors moving vehicles and roads, or into a distance measurement sensor that measures distances between vehicles, etc.

[0129] In the field of home appliances, an image sensor having pixel circuitry according to the embodiments can be integrated into any type of sensor that can be used in devices provided for home appliances (such as television receivers, refrigerators, and air conditioners) to capture user gestures and perform device operations based on those gestures. Accordingly, an image sensor having pixel circuitry according to the embodiments can be integrated into home appliances such as television receivers, refrigerators, and air conditioners, and / or devices that control home appliances. Furthermore, in the medical and healthcare fields, an image sensor having pixel circuitry according to the embodiments can be integrated into any type of sensor, such as solid-state imaging devices used in medical and healthcare applications, such as endoscopes or devices that perform angiography by receiving infrared light.

[0130] In the security field, image sensors with pixel circuits according to embodiments can be integrated into devices provided for use in security, such as surveillance cameras for crime prevention or cameras for personnel authentication. Furthermore, in the beauty field, image sensors with pixel circuits according to embodiments can be used in devices provided for use in beauty, such as skin measuring instruments or microscopes that capture probes. In the sports field, image sensors with pixel circuits according to embodiments can be integrated into devices provided for use in sports, such as action cameras or wearable cameras for sports purposes. Furthermore, in the agricultural field, image sensors with pixel circuits can be used in devices provided for use in agriculture, such as cameras for monitoring the condition of fields and crops.

[0131] This technology can also be configured as follows: [1] A pixel circuit, comprising: Capacitor element (121) is configured to receive pixel voltage VPR at the first electrode; The event detection circuit (140) is configured to output a comparator result signal VC, wherein the comparator result signal VC changes to an active level when the resettable floating voltage VF at the floating second electrode of the capacitor element (121) exceeds a predefined threshold voltage VT; and A multi-mode memory circuit (200) is configured to output an event signal EV, wherein in a first mode, the event signal EV follows a comparator result signal VC, and in a second mode, the event signal EV changes to an active level in response to receiving a valid comparator result signal VC, and changes to an inactive level in response to receiving a valid memory reset signal ef.

[0132] [2] Based on the pixel circuit of [1], The multi-mode memory circuit (200) is configured to be in a first mode when the memory mode signal MODL is not valid, and in a second mode when the memory mode signal MODL is valid.

[0133] [3] According to the pixel circuit of [1] or [2], it also includes: The radiation-sensitive circuit (110) is configured to convert incident radiation into a pixel voltage VPR, wherein the pixel voltage VPR increases with increasing radiation intensity.

[0134] [4] Pixel circuit based on any one of [1] to [3], The event detection circuit (140) includes a capacitor amplifier circuit (120) configured to receive a floating voltage VF at the amplifier input and output an amplified voltage signal VA at the amplifier output.

[0135] [5] Based on the pixel circuit of [4], The event detection circuit (140) includes a first comparator circuit (131), which is configured to output a first comparator result signal VC1. The first comparator result signal VC2 is valid when the amplified signal exceeds a first threshold voltage VT1. The multi-mode memory circuit (200) is configured to output an on event signal EV1, wherein in a first mode, the on event signal EV1 follows a first comparator result signal VC1, and in a second mode, the on event signal EV1 changes to an active level in response to receiving a valid first comparator result signal VC1, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

[0136] [6] Based on the pixel circuitry of [4] or [5], The event detection circuit (140) includes a second comparator circuit (132) configured to output a second comparator result signal VC2, wherein the second comparator result signal VC2 is valid when the amplified signal is reduced to below a second threshold voltage VT2, and... The multi-mode memory circuit (200) is configured to output a shutdown event signal EV2, wherein in a first mode, the shutdown event signal EV2 follows a second comparator result signal VC2, and in a second mode, the shutdown event signal EV2 changes to an active level in response to receiving a valid second comparator result signal VC2, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

[0137] [7] The pixel circuit according to any one of [1] to [6] further includes: The arbitrator interface circuit (155) is configured to output a valid request signal REQ in response to receiving a valid event signal EV from the multi-mode memory circuit (200).

[0138] [8] The pixel circuit according to any one of [1] to [7] further includes: The event output circuit (151) is configured to output an event data signal ON / OFF on the event data bus (41) in response to receiving a valid acknowledgment signal ACK.

[0139] [9] The pixel circuit according to any one of [1] to [8] further includes: The reset output circuit (154) is configured to output a valid memory reset signal RESL in response to receiving a valid acknowledgment signal ACK.

[0140]

[10] The pixel circuit according to any one of [1] to [9] further includes: The self-zeroing switch circuit (135) is configured to reset the resettable floating voltage VF in response to receiving a valid self-zeroing switch signal AZSW during the self-zeroing period.

[0141]

[11] The pixel circuit according to

[10] further includes: The self-zero control circuit (157) is configured to output a valid self-zero switch signal AZSW in response to receiving a valid acknowledgment signal ACK.

[0142]

[12] The pixel circuit based on any one of [1] to

[11] , The multi-mode memory circuit (200) is configured to be insensitive to the comparator result signal VC when the input enable signal ENL is not valid, and sensitive to the valid comparator result signal VC when the input enable signal ENL is valid.

[0143]

[13] The pixel circuit according to claim

[12] further includes: The enable control circuit (158) is configured to output an effective enable signal ENL in response to changes in internal conditions.

[0144]

[14] An image sensor includes pixel circuitry, wherein each pixel circuitry (100) includes: Capacitor element (121) is configured to receive pixel voltage VPR at the first electrode; The event detection circuit (140) is configured to output a comparator result signal VC, wherein the comparator result signal VC changes to an active level when the resettable floating voltage VF at the floating second electrode of the capacitor element (121) exceeds a predefined threshold voltage VT; and A multi-mode memory circuit (200) is configured to output an event signal EV, wherein in a first mode, the event signal EV follows a comparator result signal VC, and in a second mode, the event signal EV changes to an active level in response to receiving a valid comparator result signal VC, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

Claims

1. A pixel circuit, comprising: A capacitor element is configured to receive the pixel voltage VPR at the first electrode; An event detection circuit is configured to output a comparator result signal VC, wherein the comparator result signal VC changes to an active level when the resettable floating voltage VF at the floating second electrode of the capacitor element exceeds a predefined threshold voltage VT; and A multi-mode memory circuit is configured to output an event signal EV, wherein in a first mode, the event signal EV follows the comparator result signal VC, and in a second mode, the event signal EV changes to an active level in response to receiving a valid comparator result signal VC, and changes to an inactive level in response to receiving a valid memory reset signal ef.

2. The pixel circuit according to claim 1, in, The multi-mode memory circuit is configured to be in the first mode when the memory mode signal MODL is not valid, and in the second mode when the memory mode signal MODL is valid.

3. The pixel circuit according to claim 1, further comprising: A radiation-sensitive circuit is configured to convert incident radiation into a pixel voltage VPR, wherein the pixel voltage VPR increases with increasing radiation intensity.

4. The pixel circuit according to claim 1, in, The event detection circuit includes a capacitor amplifier circuit configured to receive the floating voltage VF at the amplifier input and output an amplified voltage signal VA at the amplifier output.

5. The pixel circuit according to claim 4, in, The event detection circuit includes a first comparator circuit configured to output a first comparator result signal VC1, wherein the first comparator result signal VC2 is valid when the amplified signal exceeds a first threshold voltage VT1, and The multi-mode memory circuit is configured to output an on event signal EV1, wherein in the first mode, the on event signal EV1 follows the first comparator result signal VC1, and in the second mode, the on event signal EV1 changes to an active level in response to receiving a valid first comparator result signal VC1, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

6. The pixel circuit according to claim 4, in, The event detection circuit includes a second comparator circuit configured to output a second comparator result signal VC2, wherein the second comparator result signal VC2 is valid when the amplified signal drops below a second threshold voltage VT2, and The multi-mode memory circuit is configured to output a shutdown event signal EV2. In the first mode, the shutdown event signal EV2 follows the second comparator result signal VC2. In the second mode, the shutdown event signal EV2 changes to an active level in response to receiving a valid second comparator result signal VC2, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

7. The pixel circuit according to claim 1, further comprising: The arbitrator interface circuit is configured to output a valid request signal REQ in response to receiving a valid event signal EV from the multi-mode memory circuit.

8. The pixel circuit according to claim 1, further comprising: The event output circuit is configured to output an event data signal ON / OFF on the event data bus in response to receiving a valid ACK signal.

9. The pixel circuit according to claim 1, further comprising: The reset output circuit is configured to output the valid memory reset signal RESL in response to receiving a valid acknowledgment signal ACK.

10. The pixel circuit according to claim 1, further comprising: The self-zeroing switch circuit is configured to reset the resettable floating voltage VF in response to receiving a valid self-zeroing switch signal AZSW during the self-zeroing period.

11. The pixel circuit according to claim 10, further comprising: The self-zero control circuit is configured to output the valid self-zero switch signal AZSW in response to receiving a valid acknowledgment signal ACK.

12. The pixel circuit according to claim 1, in, The multi-mode memory circuit is configured to be insensitive to the comparator result signal VC when the input enable signal ENL is invalid, and sensitive to the valid comparator result signal VC when the input enable signal ENL is valid.

13. The pixel circuit according to claim 12, further comprising: The enable control circuit is configured to output a valid enable signal ENL in response to changes in internal conditions.

14. An image sensor including pixel circuitry, wherein, Each pixel circuitry includes: A capacitor element is configured to receive the pixel voltage VPR at the first electrode; An event detection circuit is configured to output a comparator result signal VC, wherein the comparator result signal VC changes to an active level when the resettable floating voltage VF at the floating second electrode of the capacitor element exceeds a predefined threshold voltage VT; and A multi-mode memory circuit is configured to output an event signal EV, wherein in a first mode, the event signal EV follows the comparator result signal VC, and in a second mode, the event signal EV changes to an active level in response to receiving a valid comparator result signal VC, and changes to an inactive level in response to receiving a valid memory reset signal RESL.

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