Detection circuit, detection method and electronic equipment

Abstract

The invention provides a detection circuit, a detection method and electronic equipment. The power consumption detection efficiency of a device can be improved. The detection circuit comprises a first multiplexing module, a first operational amplifier, a second operational amplifier, an analog-to-digital converter and a controller, the controller is used for controlling the first multiplexing module to output a first sampling signal from a first output end, the first operational amplifier obtains a first differential signal based on the first sampling signal, and the first differential signal is in a stable state at a second moment; controlling the analog-to-digital converter to obtain a first digital sampling signal at a fourth moment; at a fifth moment, the first multiplexing module is controlled to output a second sampling signal from a second output end, the second operational amplifier obtains a second differential signal based on the second sampling signal, and the second differential signal is in a stable state at a sixth moment; the analog-to-digital converter is controlled to obtain a second digital sampling signal at the eighth moment, the fifth moment is earlier than the fourth moment, and the seventh moment is later than or equal to the fourth moment.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and in particular to a detection circuit, detection method and electronic equipment. Background Technology

[0002] In the development of electronic devices, the power consumption of each component affects the device's security, battery life, heat dissipation, and other issues. Therefore, it is crucial to detect the power consumption of each component in electronic devices.

[0003] However, existing power consumption detection methods are often inefficient. Therefore, improving the power consumption detection efficiency of various components in electronic devices has become an urgent technical problem to be solved. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a detection circuit, a detection method, and an electronic device, which can improve the power consumption detection efficiency of electronic devices.

[0005] In a first aspect, this application provides a detection circuit applied to an electronic device, the electronic device including: a first multiplexing module including M input terminals, a first output terminal and a second output terminal, each input terminal corresponding to a device under test of the electronic device, each input terminal being used to acquire the sampling signal of the corresponding device under test, wherein M is an integer greater than or equal to 2;

[0006] A first operational amplifier, with its input terminal connected to a first output terminal; a second operational amplifier, with its input terminal connected to a second output terminal; an analog-to-digital converter, used to acquire the output signal of either the first or second operational amplifier; a controller, used to control a first multiplexing module to output a first sampled signal from its first output terminal at a first moment, wherein the first operational amplifier obtains a first differential signal based on the first sampled signal, wherein the first sampled signal is the sampled signal acquired by the first target input terminal among the M input terminals, and the first differential signal is in a stable state at a second moment; and further used for... At time three, the analog-to-digital converter is controlled to convert the first differential signal, and at time four, a first digital sampled signal is obtained, wherein time three is equal to or later than time two; and, at time five, the first multiplexing module is controlled to output a second sampled signal from the second output terminal, and the second operational amplifier obtains a second differential signal based on the second sampled signal, wherein the second differential signal is in a stable state at time six; and, at time seven, the analog-to-digital converter is controlled to convert the second differential signal, and a second digital sampled signal is obtained at time eight; wherein time five is earlier than time four, and time seven is later than or equal to time four.

[0007] In this embodiment, starting from the fifth moment, the second sampling signal is output from the second output terminal to the second operational amplifier, and the second operational amplifier begins establishing its output signal from the fifth moment. The fourth moment refers to the moment when the analog-to-digital converter completes the analog-to-digital conversion of the first sampling signal. That is, the second operational amplifier establishes its output signal in advance during the processing of the first sampling signal (during the establishment of the output signal of the first operational amplifier and the operation of the analog-to-digital converter). Since the seventh moment is later than or equal to the fourth moment, the analog-to-digital converter performs analog-to-digital conversion on the first sampling signal before performing analog-to-digital conversion on the second sampling signal. Accordingly, by using two operational amplifiers, before one sampling data (e.g., the first sampling data) is processed using one operational amplifier and analog-to-digital converter, another sampling data (e.g., the second sampling data) can be established in advance using the other operational amplifier. This shortens the waiting time for the other sampling signal to stabilize after one sampling data is processed, allowing for analog-to-digital conversion after the other sampling signal stabilizes. This overall reduces the processing time of the sampling signal and improves the efficiency of power consumption detection.

[0008] For example, the first multiplexing module may be a first multiplexing module 1110.

[0009] For example, M can be 8. The M input terminals may include 8 pairs of input ports of the first multiplexing module 1110, namely input port IN1+, input port IN1-, input port IN2+, input port IN2-, ..., input port IN8+, input port IN8-.

[0010] For example, the first output terminal may include a first pair of output ports (first output port OUTa+, second output port OUTa-). The second output terminal may include a second pair of output ports (first output port OUTb+, second output port OUTb-).

[0011] For example, the sampling signal can be the voltage signal across the device under test, namely the first voltage signal at one end of the device under test and the second voltage signal at the other end of the device under test.

[0012] For example, the first operational amplifier may be a first operational amplifier PGA1. The second operational amplifier may be a second operational amplifier PGA2.

[0013] For example, the analog-to-digital converter may be a first analog-to-digital converter ADC1.

[0014] For example, the controller can connect the first target input terminal and the first output terminal of the first multiplexing module. For instance, it can connect the switch pair corresponding to the first target input terminal.

[0015] For example, the detection circuit may further include a first filter LPF1 and a second filter LPF2. Alternatively, the detection circuit may further include a first driving module 1120 and a second driving module 1130.

[0016] For example, the first sampling signal may refer to current sampling data processed by the first operational amplifier, such as first current sampling data, third current sampling data, fifth current sampling data, or seventh current sampling data. Similarly, the second sampling signal may refer to current sampling data processed by the second operational amplifier, such as second current sampling data, fourth current sampling data, sixth current sampling data, or eighth current sampling data.

[0017] For example, the first digital sampling signal can refer to current sampling data in digital signal format obtained by analog-to-digital conversion of the differential signal output from the first operational amplifier. Examples include first current sampling data, third current sampling data, fifth current sampling data, and seventh current sampling data in digital signal format. Similarly, the second digital sampling signal can refer to current sampling data in digital signal format obtained by analog-to-digital conversion of the differential signal output from the second operational amplifier. Examples include second current sampling data, fourth current sampling data, sixth current sampling data, and eighth current sampling data in digital signal format.

[0018] For example, a differential signal can refer to a differential voltage obtained based on current sampling data.

[0019] For example, the first moment can refer to the moment when the first target input terminal and the first output terminal start to conduct, such as moment 0.

[0020] For example, the second moment can refer to the moment when the first differential signal output by the first operational amplifier reaches a stable state or a steady state. The second moment is later than the first moment; for example, the time between the second moment and the first moment can be a preset setup time t1.

[0021] For example, the third time point can refer to the moment when the analog-to-digital converter (ADC) begins operation. The third time point is equal to or later than the second time point. For instance, the third time point can be equal to the second time point, that is, after the first differential signal output by the first operational amplifier has stabilized, the ADC begins to perform analog-to-digital conversion on it.

[0022] For example, the fourth moment can refer to the moment when the analog-to-digital converter completes its conversion. The fourth moment is later than the third moment. For instance, the time difference between the fourth moment and the third moment can be equal to the ADC1 operating time t2.

[0023] For example, the fifth moment can refer to the moment when the second target input terminal and the second output terminal begin to conduct, such as moment 0. The fifth moment is earlier than the fourth moment; for example, the fifth moment can be equal to the first moment, meaning that the first operational amplifier and the second operational amplifier can be established simultaneously. Alternatively, the fifth moment can be equal to the third moment, meaning that the second operational amplifier can establish the signal while the analog-to-digital converter is performing analog-to-digital conversion on the first differential signal.

[0024] For example, the sixth moment can refer to the moment when the second differential signal output by the second operational amplifier reaches a steady state or a stable state. The sixth moment is later than the fifth moment.

[0025] For example, the third moment can refer to the moment when the analog-to-digital converter starts operating. The seventh moment is later than or equal to the sixth moment.

[0026] For example, the eighth moment can refer to the moment when the analog-to-digital converter completes its conversion. The eighth moment is later than the seventh moment.

[0027] In one example, where the first sampled signal is a first sampled voltage signal and the second sampled signal is a second sampled voltage, see [link to example]. Figure 15A The first moment can be equal to the fifth moment, and the second moment can be equal to the sixth moment.

[0028] In another example, where the first sampled signal is the third sampled voltage signal and the second sampled signal is the fourth sampled voltage, see [reference needed]. Figure 15A The third moment can be equal to the fifth moment.

[0029] In one example, the signal establishment of the second sampled data by the second operational amplifier can be completed before the first sampled data is processed by the first operational amplifier and analog-to-digital converter. Alternatively, signal establishment for a portion of the duration can be performed before the first sampled data is processed, and signal establishment for the remaining duration can continue after processing is completed; there are no specific restrictions on this.

[0030] According to the first aspect, the controller is further configured to: at the ninth time, control the first multiplexing module to output a third sampled signal from the first output terminal, and the first operational amplifier to obtain a third differential signal based on the third sampled signal, wherein the third differential signal is in a stable state at the tenth time, and the tenth time is later than the ninth time; and further configured to: at the eleventh time, control the analog-to-digital converter to convert the third differential signal, and obtain a third digital sampled signal at the twelfth time, wherein the eleventh time is equal to or later than the tenth time, and the twelfth time is later than the eleventh time; wherein the ninth time is earlier than the eighth time, and the ninth time is later than or equal to the fourth time.

[0031] In this way, the operational amplifier can establish the signal of the third sampled signal in advance before the processing of the second sampled signal is completed, which shortens the processing time of the third sampled signal, thereby further shortening the processing time of the sampled signal and thus improving the overall efficiency of power consumption detection.

[0032] For example, based on the same approach, during the processing of the third sampled signal (the establishment of the operational amplifier and the operation of the analog-to-digital converter), the fourth sampled signal can be established in advance through the second operational amplifier, and so on, until the analog-to-digital conversion of the last sampled signal is completed. This allows for polling processing of each device under test. For example, the third sampled signal can refer to the next sampled data that needs analog-to-digital processing after the second sampled signal.

[0033] According to the first aspect, or any implementation of the first aspect above, the sixth time point is earlier than or equal to the fourth time point.

[0034] In this way, the second operational amplifier can establish the second sampled data before the first sampled data is processed, outputting stable second sampled data. Therefore, after the first sampled data completes analog-to-digital conversion, there is no need to spend time establishing the second sampled data; the stable second sampled data can be provided to the analog-to-digital converter for analog-to-digital conversion, further shortening the processing time of the sampled signal and thus improving the overall efficiency of power consumption detection.

[0035] According to the first aspect, or any implementation of the first aspect above, the detection circuit further includes: a second multiplexing module, including a first input terminal, a second input terminal, and a third output terminal, wherein the first input terminal is connected to the output terminal of the first operational amplifier, and the second input terminal is connected to the output terminal of the second operational amplifier; the controller is further configured to: control the second multiplexing module to turn on the first input terminal and the third output terminal at or before the third time; and control the second multiplexing module to turn on the second input terminal and the third output terminal at or before the seventh time.

[0036] In this way, the second multiplexing module can flexibly provide either the first differential signal or the second differential signal to the analog-to-digital converter for processing. When the first differential signal needs to be converted to digital, the second multiplexing module selects to provide the first differential signal to the input terminal of the analog-to-digital converter, and when the second differential signal needs to be converted to digital, the second multiplexing module selects to provide the second differential signal to the input terminal of the analog-to-digital converter. This shortens the processing time of the sampled signal and improves the overall efficiency of power consumption detection.

[0037] For example, the second multiplexing module may be the second multiplexing module 1140 in the embodiments of this application.

[0038] According to the first aspect, or any implementation of the first aspect above, M equals 2N, the M input terminals include N third input terminals and N fourth input terminals, N is any positive integer, the first multiplexing module includes: a first multiplexer, including N third input terminals and a first output terminal, wherein the i-th third input terminal is used to acquire the sampling signal of the 2i-1th device under test, i is an integer greater than or equal to 1 and less than or equal to N; a second multiplexer, including N fourth input terminals and a second output terminal, wherein the i-th fourth input terminal is used to acquire the sampling signal of the 2i-th device under test, i is an integer greater than or equal to 1 and less than or equal to N; the controller is specifically used to: at a first moment, control the first multiplexer to connect the k-th third input terminal and the first output terminal, the k-th third input terminal being the first target input terminal; and at a fifth moment, control the second multiplexer to connect the k-th fourth input terminal and the second output terminal, the k-th fourth input terminal being the second target input terminal, k is an integer greater than or equal to 1 and less than or equal to N.

[0039] For example, the first multiplexer may refer to the first multiplexer 1111 in the embodiments of this application. The N third input terminals include a first pair of input ports (including input port IN1+ and input port IN1-) for connecting the first device under test, a third pair of input ports (including input port IN3+ and input port IN3-) for connecting the third device under test, a fifth pair of input ports (including input port IN5+ and input port IN5-) for connecting the fifth device under test, and a seventh pair of input ports (including input port IN7+ and input port IN7-) for connecting the seventh device under test.

[0040] For example, the second multiplexer may be the second multiplexer 1112 in the embodiments of this application. The N fourth input terminals include a second pair of input ports (including input port IN2+ and input port IN2-) for connecting a second device under test, a fourth pair of input ports (including input port IN4+ and input port IN4-) for connecting a fourth device under test, a sixth pair of input ports (including input port IN6+ and input port IN6-) for connecting a sixth device under test, and an eighth pair of input ports (including input port IN8+ and input port IN8-) for connecting an eighth device under test.

[0041] In this way, by using the first and second multiplexers, one port can be selected from the N ports to be turned on, and another port can be selected from the other N ports to be turned on. This allows the operational amplifier's output signal to be established in advance by turning on another port while the sampled data of one port is being processed, thereby shortening the processing time of the sampled signal.

[0042] According to the first aspect, or any implementation of the first aspect above, M equals 2N, N is any positive integer, and the first multiplexing module includes: a third multiplexer, including M fifth input terminals and a first output terminal, wherein the j-th fifth input terminal is used to acquire the sampling signal of the j-th device under test, and j is an integer greater than or equal to 1 and less than or equal to M; a fourth multiplexer, including M sixth input terminals and a second output terminal, wherein the j-th sixth input terminal is used to acquire the sampling signal of the j-th device under test; the controller is specifically used to: at a first moment, control the third multiplexer to connect the 2k-1 fifth input terminal to the first output terminal, and the 2k-1 fifth input terminal is the first target input terminal; and at a fifth moment, control the fourth multiplexer to connect the 2k-th sixth input terminal to the second output terminal, and the 2k-th sixth input terminal is the second target input terminal, where k is an integer greater than or equal to 1 and less than or equal to N.

[0043] In this way, by using the third and fourth multiplexers, one port can be selected to be turned on from among the 2N ports, and another port can be selected to be turned on from among the 2N ports. This allows the operational amplifier's output signal to be established in advance by turning on another port while the sampled data of one port is being processed, thereby shortening the processing time of the sampled signal.

[0044] For example, the third multiplexer may refer to the third multiplexer 1113 in the embodiments of this application.

[0045] For example, the fourth multiplexer may refer to the fourth multiplexer 1114 in the embodiments of this application.

[0046] According to the first aspect, or any implementation of the first aspect above, when k equals 1, the fifth moment is later than or equal to the first moment; when k is greater than 1, the fifth moment is later than or equal to the second moment.

[0047] In this way, the sampling signal of the second device under test (DUT) can be established in advance via the second operational amplifier, starting from the establishment of the sampling signal of the first DUT by the first operational amplifier. Similarly, after the differential signal of the third DUT begins analog-to-digital conversion, the sampling signal of the fourth DUT is established in advance via the second operational amplifier. And after the differential signal of the fifth DUT begins analog-to-digital conversion, the sampling signal of the sixth DUT is established in advance via the second operational amplifier. And after the differential signal of the seventh DUT begins analog-to-digital conversion, the sampling signal of the eighth DUT is established in advance via the second operational amplifier.

[0048] Similarly, after the differential signal of the second device under test (DUT) begins analog-to-digital conversion, the sampling signal of the third DUT is established in advance through the first operational amplifier; ...; after the differential signal of the sixth DUT begins analog-to-digital conversion, the sampling signal of the seventh DUT is established in advance through the first operational amplifier.

[0049] According to the first aspect, or any implementation of the first aspect above, the controller is further configured to: determine the first input terminal as the first target input terminal after controlling the analog-to-digital converter to generate a sampling signal of the Mth device under test in the form of a digital signal.

[0050] In this way, after completing one round of power consumption detection for M devices under test, the power consumption of the first device under test can be detected again, thus realizing the polling detection of M devices under test by the detection circuit.

[0051] Secondly, embodiments of this application provide a detection method, which is applied to the detection circuit in the first aspect and any implementation thereof, the method comprising:

[0052] The controller controls the first multiplexing module to output the first sampling signal from the first output terminal at the first moment;

[0053] The first operational amplifier obtains a first differential signal based on the first sampled signal, wherein the first sampled signal is the sampled signal obtained by the first target input terminal among the M input terminals, and the first differential signal is in a stable state at the second time.

[0054] At the third moment, the controller controls the analog-to-digital converter to convert the first differential signal, and at the fourth moment, it obtains the first digital sampled signal. The third moment is equal to or later than the second moment.

[0055] At the fifth moment, the controller controls the first multiplexing module to output the second sampling signal from the second output terminal;

[0056] The second operational amplifier obtains the second differential signal based on the second sampled signal, wherein the second differential signal is in a stable state at the sixth time.

[0057] At the seventh moment, the controller controls the analog-to-digital converter to convert the second differential signal, and obtains the second digital sampled signal at the eighth moment;

[0058] Among them, the fifth moment is earlier than the fourth moment, and the seventh moment is later than or equal to the fourth moment.

[0059] According to the second aspect, the method also includes:

[0060] At the ninth moment, the controller controls the first multiplexing module to output the third sampling signal from the first output terminal;

[0061] The first operational amplifier obtains the third differential signal based on the third sampled signal, wherein the third differential signal is in a stable state at the tenth time, which is later than the ninth time.

[0062] At time eleven, the controller controls the analog-to-digital converter to convert the third differential signal and obtains the third digital sampled signal at time twelfth, wherein time eleven is equal to or later than time ten, and time twelfth is later than time eleven.

[0063] Among them, the ninth moment is earlier than the eighth moment, and the ninth moment is later than or equal to the fourth moment.

[0064] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects corresponding to the second aspect and any implementation thereof are similar to those corresponding to the first aspect and any implementation thereof, and will not be repeated here.

[0065] Thirdly, this application provides an electronic device, comprising: M devices under test (DUTs) and M resistors, wherein the M DUTs correspond one-to-one with the M resistors, and each resistor is connected to the power supply circuit of the corresponding DUT; a first multiplexing module, including M input terminals, a first output terminal, and a second output terminal, each input terminal corresponding to one DUT and each input terminal connected to the resistor of the corresponding DUT, for acquiring a sampling signal from the resistor of the corresponding DUT, wherein M is an integer greater than or equal to 2; a first operational amplifier, the input terminal of the first operational amplifier being connected to the first output terminal; a second operational amplifier, the input terminal of the second operational amplifier being connected to the second output terminal; an analog-to-digital converter, for acquiring the output signal of the first operational amplifier or the output signal of the second operational amplifier; and a controller, for controlling the first multiplexing module to output a first sampling signal from the first output terminal at a first moment. The system is configured to: 1) obtain a first differential signal based on a first sampled signal, wherein the first sampled signal is a sampled signal acquired by a first target input terminal among M input terminals, and the first differential signal is in a stable state at a second time; 2) control an analog-to-digital converter to convert the first differential signal at a third time, and obtain a first digital sampled signal at a fourth time, wherein the third time is equal to or later than the second time; 3) control a first multiplexing module to output a second sampled signal from a second output terminal at a fifth time, and a second operational amplifier to obtain a second differential signal based on the second sampled signal, wherein the second differential signal is in a stable state at a sixth time; 4) control an analog-to-digital converter to convert the second differential signal at a seventh time, and obtain a second digital sampled signal at an eighth time, wherein the fifth time is earlier than the fourth time, and the seventh time is later than or equal to the fourth time.

[0066] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects corresponding to the third aspect and any implementation thereof are similar to those corresponding to the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0067] Figure 1 A schematic diagram of an exemplary power consumption detection circuit provided in an embodiment of this application is shown;

[0068] Figure 2 A schematic diagram of a detection circuit in a related technology is shown;

[0069] Figure 3 A schematic diagram of an exemplary detection circuit in the related art is shown;

[0070] Figure 4 A schematic diagram of an exemplary voltage conversion circuit provided in an embodiment of this application is illustrated.

[0071] Figure 5 A schematic diagram of another exemplary power consumption detection circuit provided in an embodiment of this application is shown;

[0072] Figure 6 An exemplary polling diagram provided in an embodiment of this application is shown;

[0073] Figure 7 This paper illustrates a schematic diagram of the output voltage variation of an operational amplifier according to an embodiment of this application.

[0074] Figure 8 This illustration shows a schematic diagram illustrating the relationship between closed-loop gain and settling time according to an embodiment of this application.

[0075] Figure 9 This illustration shows an exemplary power consumption detection process provided in an embodiment of this application;

[0076] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0077] Figure 11 A schematic diagram of a detection circuit provided in an embodiment of this application is shown;

[0078] Figure 12 A circuit diagram of an exemplary first multiplexing module provided in an embodiment of this application is shown;

[0079] Figure 13A circuit diagram of another exemplary first multiplexing module provided in an embodiment of this application is shown;

[0080] Figure 14 This illustration shows a schematic diagram of an exemplary second multiplexing module provided in an embodiment of this application;

[0081] Figures 15A-15C A schematic diagram illustrating a set of exemplary polling power consumption tests provided in an embodiment of this application is shown;

[0082] Figures 16A-16B This illustration shows a schematic diagram of the transmission process of a set of exemplary current sampling data provided in an embodiment of this application;

[0083] Figures 17A-17C This illustration shows another set of exemplary polling power consumption tests provided in an embodiment of this application;

[0084] Figure 18 A schematic diagram of another detection circuit provided in an embodiment of this application is shown;

[0085] Figure 19 This paper shows a schematic diagram of another detection circuit provided in an embodiment of the present application;

[0086] Figure 20 A schematic diagram of another detection circuit provided in an embodiment of this application is shown;

[0087] Figure 21 A schematic diagram of a detection method provided in an embodiment of this application is shown;

[0088] Figure 22 A schematic block diagram of an apparatus according to an embodiment of this application is shown. Detailed Implementation

[0089] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0090] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0091] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0092] In the embodiments of this application, directional terms such as "up," "down," "left," and "right" may include, but are not limited to, the orientation relative to the schematic placement of the components in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0093] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or a connection through an intermediate medium. Furthermore, the term "coupled" can refer to an electrical connection method for achieving signal transmission.

[0094] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0095] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0096] Furthermore, in the embodiments of this application, the control terminal of each transistor is the gate of the transistor, the first connection terminal is one of the source and drain of the transistor, and the second connection terminal is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, their source and drain can be structurally indistinguishable.

[0097] To facilitate understanding, the technical terms involved in the embodiments of this application will be explained before introducing the technical solutions of the embodiments of this application.

[0098] (1) A multiplexer (MUX) may include multiple input pins and one output pin. A multiplexer can receive multiple input signals through multiple input pins and select one signal from the received input signals for output.

[0099] (2) Programmable Gain Amplifier (PGA) is a flexible, programmable electronic operational amplifier whose gain can be programmed to meet different application requirements. By adjusting the configuration of internal resistors or electronic switches, the PGA can switch between different gain settings to meet different signal processing needs. It is commonly used in applications such as data acquisition and automatic control systems. In addition, because the gain of the PGA is digitally controlled, the amplification factor can be precisely controlled, avoiding the errors and drift problems that may occur in analog operational amplifiers.

[0100] (3) Low-pass filter (LPF): It allows low-frequency signals to pass through while allowing high-frequency signals to pass through. It can filter high-frequency noise signals in the circuit. For example, an LPF can be implemented as a passive low-frequency filter such as an RC filter or an active low-frequency filter, etc., without specific limitations.

[0101] (4) Analog-to-Digital Converter (ADC), also known as analog-to-digital converter, etc. ADC can convert analog signals into digital signals. It can include successive approximation ADC, Sigma-Delta (Σ-Δ) ADC, indirect ADC, parallel comparator ADC, etc., without specific limitations.

[0102] Among them, the successive approximation ADC is a direct ADC that uses comparators and counting logic to complete the conversion. It belongs to the medium-speed ADC devices and is widely used. It generates a series of comparison voltages VR, which are successively compared with the input voltage to perform analog-to-digital conversion in a progressively approximate manner. Specifically, in the first step of the conversion, the successive approximation ADC checks whether the input voltage is higher than half of the reference voltage. If it is, it sets the most significant bit (MSB) of the output to 1. Then, it subtracts half of the reference voltage from the input value and checks whether the result is greater than 1 / 4 of the reference voltage, and so on until all output bits are set to 1 or cleared to zero.

[0103] The Sigma-Delta ADC employs a 1-bit DAC, filtering, and additional sampling to achieve accurate conversion; its conversion accuracy depends on the reference input and the input clock frequency. Sigma-Delta ADCs offer high resolution.

[0104] After introducing the above technical terms, the technical solutions of the embodiments of this application will be described next.

[0105] In the development of electronic devices such as mobile phones, the power consumption of various components in these devices affects their security, battery life, heat dissipation, and other issues. Therefore, it is crucial to detect the power consumption of these components.

[0106] For example, by detecting the power consumption of each device, it can be determined whether the power consumption of each device meets the requirements. For instance, when the power consumption of a device is too high, the device may have problems such as low efficiency or failure, and the device can be repaired or improved. As another example, device power consumption detection can support the thermal design of electronic devices. For instance, when a device's power consumption is detected to be too high, thermal design can be implemented for that device or the load on that device can be reduced.

[0107] Therefore, in electronic devices, there is a need for a device to detect the power consumption of the electronic devices. Figure 1 A schematic diagram of an exemplary power consumption detection circuit provided in an embodiment of this application is shown.

[0108] like Figure 1 As shown, the power consumption detection circuit may include a power supply VIN0, a power consumption detection resistor R0, a detection circuit 100, a voltage conversion circuit 200, and a device under test M0.

[0109] The power supply VIN0 can be connected to the device under test M0 via the voltage conversion circuit 200. For example, Figure 1 As shown, the positive terminal of the power supply VIN can be connected to the first input terminal IN01 of the voltage conversion circuit 200, and the negative terminal of the power supply VIN can be connected to the second input terminal IN02 of the voltage conversion circuit 200. The first output terminal OUT1 of the voltage conversion circuit 200 can be connected to the first terminal of the device under test M0, and the second output terminal OUT2 of the voltage conversion circuit 200 can be connected to the other terminal of the device under test M0. The power supply voltage provided by the power supply voltage VIN0 can be converted by the voltage conversion circuit 200, and the converted voltage can be used to power the device under test M0.

[0110] Furthermore, the power consumption detection resistor R0 can be placed between the power supply VIN0 and the voltage conversion circuit 200, for example, on the line between the power supply VIN0 and the voltage conversion circuit 200. That is, the positive terminal of the power supply VIN0 can be connected to the voltage conversion circuit through the power consumption detection resistor R0. For example, the resistance value of the power consumption detection resistor R0 can be very small, such as 5mΩ, so that its impact on the supply voltage and supply current provided by the power supply VIN0 is very small and can be ignored, thus ensuring the accuracy of power sampling.

[0111] Furthermore, the detection circuit 100 can be connected in parallel across the two ends of the power consumption detection circuit R0. For example, the first end of the detection circuit 100 can be connected to one end N01 of the power consumption detection resistor R0, and the other end of the detection circuit 100 can be connected to the other end N02 of the power consumption detection circuit R0. In this way, the detection circuit 100 can acquire the voltage (referred to as the first voltage signal) at one end N01 of the power consumption detection resistor R0, and use the acquired first voltage signal as the supply voltage U1 of the power supply VIN0. Additionally, the detection circuit 100 can obtain the voltage difference across the power consumption detection resistor R0, i.e., the voltage difference between one end N01 and the other end N02 of the power consumption detection resistor R0, and calculate the ratio between this voltage difference and the resistance value of the power consumption detection resistor R0 to obtain the supply current I1 of the power supply VIN0. Furthermore, the detection circuit can also calculate the product of the supply voltage U1 and the supply current I1 of the power supply VIN0 to obtain the power consumption of the device under test M0.

[0112] The power supply VIN0 can be a battery in an electronic device. The battery can include one or more individual battery cells, without specific limitation. The multiple battery cells can be connected in series, parallel, or a combination thereof, without specific limitation. In the embodiments of this application, different devices under test M0 can be connected to the same power supply or different power supplies, without specific limitation.

[0113] For the detection circuit 100, it can acquire analog voltage signals corresponding to the supply voltage U1 and supply current I1 of the power supply VIN0 from both ends of the power consumption detection circuit R0, and perform analog-to-digital conversion on the acquired analog voltage signals to obtain digital signals. Exemplarily, in this embodiment, the voltage sampling data can be the voltage at one end of the power consumption detection circuit R0. Furthermore, since the supply current I1 can be calculated based on the voltage difference across the power consumption detection resistor R0 (i.e., the ratio of the voltage difference to the resistance), the current sampling data can be the differential voltage across the voltage values ​​of the power consumption detection circuit R0.

[0114] In one embodiment, Figure 2 A schematic diagram of a detection circuit in a related technology is shown. For example... Figure 2As shown, the detection circuit 100 may include a current signal acquisition circuit 110 and a voltage signal acquisition circuit 120. The detection circuit 100 can sample the power of n devices under test (DUTs) using n power consumption detection resistors, where n is an integer greater than or equal to 2, such as 4, 8, or 16, etc., without specific limitations. Specifically, the first power consumption detection resistor R0 is located in the power supply circuit of the first DUT M0, the second power consumption detection resistor is located in the power supply circuit of the second DUT, ..., and the nth power consumption detection resistor is located in the power supply circuit of the nth DUT. It should be noted that the specific arrangement of the n power consumption detection resistors can be found in the description of the first power consumption detection resistor R0 in the embodiments of this application, without specific limitations.

[0115] Specifically, the current signal acquisition circuit 110 is used to acquire current sampling data (such as the differential voltage of the power consumption detection resistor). Specifically, the current signal acquisition circuit 110 includes a current multiplexer MUX01 (i.e., a multiplexer for current sampling data), a preset operational amplifier PGA0, a preset low-pass filter LPF0, and a current analog-to-digital converter ADC01 (i.e., an analog-to-digital converter for current sampling data).

[0116] The current multiplexer MUX01 includes n pairs of input pins. The first pair of input pins includes input pin AIN0 and input pin AIN1, the second pair of input pins includes input pin AIN2 and input pin AIN3, ..., and the nth pair of input pins includes input pin AIN2n-2 and input pin AIN2n-1. Specifically, input pin AIN0 of the first pair of input pins is connected to one end of the first power detection resistor R0 to obtain the first voltage signal of the first power detection resistor R0; input pin AIN1 of the first pair of input pins is connected to the other end of the first power detection resistor R0 to obtain the second voltage signal of the first power detection resistor R0; input pin AIN2 of the second pair of input pins is connected to one end of the second power detection resistor to obtain the first voltage signal of the second power detection resistor; input pin AIN3 of the second pair of input pins is connected to the other end of the second power detection resistor to obtain the second voltage signal of the second power detection resistor; ...; input pin AIN2n-2 of the nth pair of input pins is connected to one end of the nth power detection resistor to obtain the first voltage signal of the nth power detection resistor; input pin AIN2n-1 of the nth pair of input pins is connected to the other end of the nth power detection resistor to obtain the second voltage signal of the nth power detection resistor.

[0117] In addition, the current multiplexer MUX01 includes two output pins, namely the first output pin B1 and the second output pin B2.

[0118] During the current sampling process of the i-th device under test (i can be any positive integer greater than or equal to 1 and less than or equal to n), the current multiplexer MUX01 selects the i-th pair of input pins to be turned on from the n pairs of input pins. At this time, the first output pin B1 outputs the first voltage signal of the i-th power consumption detection resistor to the non-inverting input terminal of the preset operational amplifier PGA0. Figure 2 The port marked with "+" in the middle), the second output pin B2 outputs the second voltage signal of the i-th power consumption detection resistor to the negative input terminal of the preset operational amplifier PGA0 (the port marked with "+" in the middle). Figure 2 (Ports marked with "-" in Chinese). The preset operational amplifier PGA0 generates a differential voltage for the i-th power consumption detection resistor based on the first and second voltage signals of the i-th power consumption detection resistor. This differential voltage is then filtered at high frequency by LPF0 and output to the current analog-to-digital converter ADC01. The current analog-to-digital converter ADC01 samples the differential voltage in analog signal format and performs analog-to-digital conversion to obtain the differential voltage in digital signal format, thus acquiring the current sampling data in digital signal format.

[0119] In one example Figure 3 A schematic diagram of an exemplary detection circuit in the related art is shown. If the current multiplexer MUX01 includes 16 input pins, then the current multiplexer MUX01 can connect to 8 power consumption sensing resistors. For example... Figure 3 As shown, the current multiplexer MUX01 may include 16 first control switches. The first input pin AIN0 is connected to the first output pin B1 via the first first control switch K0; the third input pin AIN2 is connected to the first output pin B1 via the third first control switch K2, ..., the 15th input pin AIN14 is connected to the first output pin B1 via the 15th first control switch K14. The second input pin AIN1 is connected to the second output pin B2 via the second first control switch K1; the fourth input pin AIN3 is connected to the second output pin B2 via the fourth first control switch K3, ..., the 16th input pin AIN15 is connected to the second output pin B2 via the 16th first control switch K15.

[0120] In addition, the voltage signal sampling circuit 120 is used to acquire voltage sampling data. Specifically, the voltage signal acquisition circuit 120 includes a voltage multiplexer MUX02 (i.e., a multiplexer for voltage sampling data) and a voltage analog-to-digital converter ADC02 (i.e., an analog-to-digital converter for voltage).

[0121] The voltage multiplexer MUX02 includes n input pins. The first input pin is connected to input pin AIN0 to acquire the voltage at one end of the first power detection resistor R0 (for ease of description, this can be referred to as the first voltage signal of the power detection resistor R0). The second input pin is connected to input pin AIN2 to acquire the first voltage signal of the second power detection resistor; ...; the nth input pin is connected to input pin AIN2n-2 to acquire the first voltage signal of the nth power detection resistor. For example, the voltage multiplexer MUX02 may include n second control switches. The j-th input pin of the voltage multiplexer MUX02 is connected to the output pin B3 of the voltage multiplexer MUX02 through the j-th second control switch. Here, j is any positive integer greater than or equal to 1 and less than or equal to n.

[0122] During the voltage sampling process of the i-th device under test, the voltage multiplexer MUX02 selects the i-th input pin from the n input pins to conduct, so as to output the first voltage signal of the i-th power consumption sensing resistor to the voltage analog-to-digital converter ADC01. The voltage analog-to-digital converter ADC02 samples the first voltage signal in analog signal format and performs analog-to-digital conversion to obtain the first voltage signal in digital signal format, that is, to acquire the voltage sampling data in digital signal format.

[0123] After introducing the detection circuit 100, the voltage conversion circuit 200 will be described next.

[0124] The voltage conversion circuit 200 can be a circuit that converts the supply voltage of the power supply VIN0 into the operating voltage of the device under test. For example, the voltage conversion circuit 200 can be a buck converter, a boost converter, or a buck-boost converter, etc., using an inductor as the energy storage element. Alternatively, the voltage conversion circuit 200 can also be implemented as a switch capacitor converter (SC) circuit, etc., using a capacitor as the energy storage element. This application embodiment does not impose specific limitations on this. It should be noted that the specific selection of the voltage conversion circuit 200 can be based on the power requirements of the device under test, and there are no specific limitations on this.

[0125] For example, if the voltage of the device under test is lower than the supply voltage of the power supply VIN0, the voltage conversion circuit 200 can be implemented as a BUCK. For example, Figure 4 A schematic diagram of an exemplary voltage conversion circuit provided in an embodiment of this application is illustrated. For example... Figure 4As shown, the voltage conversion circuit 200 may include a switch S0, a freewheeling diode X0, an energy storage inductor L0, and a filter capacitor C0. The first terminal of switch S0 serves as the first input terminal IN01 of the voltage conversion circuit 200. The second terminal of switch S0 is connected to one end of the energy storage inductor L0 and one end of the freewheeling diode X0. The other end of the freewheeling diode X0 serves as the second input terminal IN02 of the voltage conversion circuit 200, and is also connected to the other end of the filter capacitor C0. The other end of the energy storage inductor L0 serves as the first output terminal OUT1 of the voltage conversion circuit 200, and is connected to one end of the filter capacitor C0. The other end of the filter capacitor C0 serves as the second output terminal OUT2 of the voltage conversion circuit 200.

[0126] Additionally, it should be noted that since different components in electronic devices may have different operating voltages, the output voltage of the voltage conversion circuit of different devices under test may also be different, and no specific restrictions are imposed on this.

[0127] The device under test (DUT) can be an electrical component or structure in an electronic device. For example, the DUT M0 could be a cooling fan, CPU core, screen, speaker, camera module, etc., in a mobile phone, without specific limitations.

[0128] In other embodiments, this application also provides another power consumption detection circuit. Figure 5 A schematic diagram of another exemplary power consumption detection circuit provided in an embodiment of this application is shown. Figure 5 and Figure 1 The difference lies in the fact that the power consumption detection resistor R0 can also be placed between the voltage conversion circuit 200 and the device under test (DUT) M0. In this case, the voltage across one end N01 of the power consumption detection resistor R0 is the voltage consumed by the DUT M0. The ratio between the voltage difference across the power consumption detection resistor R0 and the resistance value of the power consumption detection resistor R0 is the current consumed by the DUT M0. Then, the power consumption of the DUT M0 can be obtained by multiplying the voltage consumed by the DUT M0 by the current consumed by the DUT M0.

[0129] It should be noted that, Figure 5 Further details regarding the power consumption detection circuit shown can be found in [link to relevant documentation]. Figure 1 The description of the power consumption detection circuit shown is not specifically limited.

[0130] In this embodiment, the power consumption detection circuit can also be configured in other forms according to actual needs and specific requirements, and no specific limitations are imposed. Furthermore, it should be noted that the aforementioned power consumption detection circuit can be implemented as a detection chip, or a portion of the circuitry within a chip, and no specific limitations are imposed.

[0131] To facilitate power detection of each device under test, this embodiment of the application may employ a multiplexer polling method for power consumption detection. For example, Figure 6 This illustration shows an exemplary polling diagram provided by an embodiment of this application. For example... Figure 6 As shown, taking the power consumption detection of 8 devices under test (i.e., n=8) as an example, if 8 rounds of power consumption detection can be performed within 1 ms, the power consumption of channels CH0-CH7 can be tested in a preset order in each round of power consumption detection (the test order between channels CH0-CH7 is not specifically limited). Among them, channel 0 is used to detect the power consumption of the first device under test, channel 1 is used to detect the power consumption of the second device under test, ..., channel 7 is used to detect the power consumption of the eighth device under test.

[0132] For example, if power consumption tests are performed sequentially on channels CH0-CH7 in each round of power consumption detection, in the first detection of any round of power consumption detection, for channel CH0, the first control switch K0 and the first control switch K1 can be turned on to detect the current sampling data of the first device under test using the current multiplexer MUX01. The first second control switch in the voltage multiplexer MUX02 can also be turned on to detect the voltage sampling data of the first device under test using the voltage multiplexer MUX02. After the first detection is completed, a second detection can be performed. In the second detection, the voltage and current sampling data of the second device under test can be detected using channel CH1, and the detection method is similar to the first detection, so it will not be described in detail here. Then, the same operation is repeated, and after the detection of other devices under test is completed using CH2-CH7, the next round of power consumption testing can be performed, and the above operation is repeated until the test is completed.

[0133] However, the applicant's research revealed that the PGA's output voltage required a certain period of time to reach a stable state during each test. For example, Figure 7 This paper illustrates a schematic diagram of the output voltage variation of an operational amplifier provided in an embodiment of this application.

[0134] like Figure 7 As shown, starting from the input voltage received at the two input terminals of the PGA, the output voltage of the PGA reaches a steady state after the operational amplifier's settling time. The operational amplifier's settling time refers to the time required for the operational amplifier's output voltage to rise from its initial state and remain within a predetermined voltage threshold range when the input signal changes. The predetermined voltage threshold range describes the positive and negative deviation range of the operational amplifier's steady state; the output voltage reaching and remaining within the predetermined voltage threshold range indicates that a steady state has been achieved.

[0135] Specifically, during the settling time of the operational amplifier, such as Figure 7 As shown, after receiving input voltage at both input terminals of the PGA, the voltage at the output terminal of the PGA increases linearly at a certain rate. After exceeding a predetermined voltage threshold, there will be an overshoot process, followed by a period of damped oscillation, before reaching a steady state (final value), i.e., generating a stable output voltage. Overshoot refers to exceeding the predetermined voltage threshold. For example, overshoot can be... Figure 8 The first peak value of the output voltage exceeding the predetermined voltage threshold can be represented as a spike pulse. Damped oscillation refers to oscillation whose amplitude decreases with time. Among them, such as... Figure 7 As shown, the rate of linear increase of the output voltage in the first segment is related to the slew rate of the PGA. The slew rate describes the performance of the operational amplifier, defining the speed at which the output voltage transitions at the operational amplifier's output.

[0136] Furthermore, the applicant's research found that the settling time of an operational amplifier primarily depends on the characteristics of its internal circuitry (e.g., bandwidth, gain, and noise) and the parameters of its external circuitry (e.g., input signal amplitude and frequency, load capacitance and resistance, supply voltage and current). For the large-signal model of operational amplifier 202, the slew rate is the main factor affecting settling time; for the small-signal model of operational amplifier 202, the closed-loop gain is the main factor affecting settling time.

[0137] For the relationship between slew rate and settling time, please refer to the above. Figure 7 Because the higher the slew rate, the faster the output voltage of the operational amplifier increases, and correspondingly, the shorter the settling time of the operational amplifier.

[0138] Regarding the relationship between closed-loop gain and settling time, Figure 8 This diagram illustrates the relationship between closed-loop gain and settling time according to an embodiment of this application. Figure 8 As shown, increasing the closed-loop gain of an operational amplifier leads to an increase in settling time. This is because as the closed-loop gain increases, the system stability decreases, resulting in increased oscillation or error in the output signal. At high gain, the closed-loop bandwidth of the operational amplifier decreases; therefore, the loop gain (AolB) for adjusting the output error also decreases, ultimately causing an increase in the operational amplifier's settling time.

[0139] Since the current sampling data is related to the output voltage of the operational amplifier, in order to prevent abnormal situations such as sampling data errors or loss, after the first control switch of the current multiplexer MUX01 is switched, it is necessary to wait for the operational amplifier to set up, that is, after the output voltage of the operational amplifier is stable, before controlling the current analog-to-digital converter ADC01 to perform data acquisition and analog-to-digital conversion.

[0140] Therefore, during the polling process of the current multiplexer, Figure 9 This illustration shows an exemplary power consumption detection process according to an embodiment of this application. Figure 9 As shown, the electronic device can detect channel CH0 within the time period from 0 to T. During this detection process, the PGA0 setup time t1 is consumed to establish the PGA0 output voltage and ensure it reaches a stable state. Then, the ADC01 operating time t2 is consumed to execute the current-to-digital converter (ADC01) workflow, allowing it to complete data acquisition and conversion. Next, the detection process for channel CH1 begins within the time period from T to 2T, consuming the PGA0 setup time t1 and the ADC01 operating time t2 before completion. This process is repeated sequentially, using CH2-CH7 to detect other devices under test, before proceeding to the next round of power consumption testing until the test is complete. Using this polling method, the electronic device can complete one round of detection for channels CH0 to CH7 within a time period of 8T.

[0141] Furthermore, since the switching frequency of the current multiplexer does not exceed 66kHz, if the switching frequency of the current multiplexer is 64kHz, then the detection time for each test is 15.625µs. If the settling time of the operational amplifier is 15µs, then the operating time of the current analog-to-digital converter is 0.625µs, which requires the ADC sampling rate to reach 1.6Msps, placing high demands on the ADC sampling rate.

[0142] To further improve power consumption detection efficiency, this application provides a new detection circuit and detection method that can shorten the polling detection time and further improve the polling detection efficiency.

[0143] The detection circuit and detection method provided in this application can be applied to electronic devices with power consumption detection functions. For ease of understanding, the electronic device will be described first before introducing the detection scheme provided in this application.

[0144] Figure 10This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device provided in this embodiment may include, but is not limited to, mobile phones, tablets, laptops, Ultra-Mobile Personal Computers (UMPCs), Personal Digital Assistants (PDAs), Point-of-Sale (POS) machines, walkie-talkies, in-vehicle computers, televisions, smart wearable devices (such as smartwatches or smart bracelets), smart home devices (such as Bluetooth speakers), dashcams, security equipment, and other electronic devices with power consumption detection functions. This embodiment does not specifically limit the specific type of the aforementioned electronic device. For ease of explanation, a mobile phone is used as an example for the following description.

[0145] in, Figure 10 (1) is a schematic diagram of the front structure of the electronic device. Figure 10 (2) A schematic diagram of the rear structure of the electronic device. For example... Figure 10 As shown, the electronic device 100 includes a display module 10, a back cover (also known as a battery cover) 20, and a mid-frame 30.

[0146] The display module 10 includes a cover plate and a display screen stacked together. The cover plate, for example, protects the display screen. The display screen includes, for example, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display screen, and an LED display screen, wherein the LED display screen includes, for example, a micro-LED display screen and a mini-LED display screen. This application embodiment does not limit the type of display screen.

[0147] The material of the back cover 20 may include, for example, opaque materials such as plastic, vegan leather, and fiberglass; or it may include translucent materials such as glass. This application does not limit the material of the back cover 20.

[0148] The middle frame 30 includes an annular outer part 31 and a support (not shown) located within the annular outer part 31 and between the display module 10 and the back cover 20.

[0149] The display module 10, the back cover (also known as the battery cover) 20, and the annular outer part 31 surround a housing cavity, within which are housed a battery, a printed circuit board (PCB) 40, and functional components 50, among other structures. Figure 10(Not shown in the image), the functional device 50 includes a first functional component and a second functional component. The first functional component can be disposed on PCB 40 and electrically connected to PCB 40; the second functional component is not disposed on the PCB, but is electrically connected to PCB 40. The first functional component may include devices such as a processor, a power supply module (such as a power management chip and / or a charging management module), a display driving circuit, and a measurement circuit, etc., and the second functional component may include devices such as a flash, a camera 55, etc. The devices are electrically connected through PCB 40, thereby realizing signal transmission and interaction. The support member can support part of the structure inside the cavity. In the embodiments of this application, the power supply VIN0, the detection circuit 100, the power consumption detection resistor, and the voltage conversion circuit 200 can be disposed on PCB 40. The device under test may be disposed on PCB 40 or not, and its position is not specifically limited.

[0150] The processor may include one or more processing units, such as a baseband processor, application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, memory, video codec, digital signal processor (DSP), and / or neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0151] The processor may include a memory for storing instructions and data. In some embodiments, the memory in the processor is a cache memory. This memory can store instructions or data that the processor has just used or that are used repeatedly. If the processor needs to use the instruction or data again, it can directly retrieve it from the memory. This avoids repeated accesses, reduces processor waiting time, and thus improves system efficiency. In this embodiment, the memory may store compressed data that needs to be stored and sent by the measurement circuit.

[0152] In some embodiments, the processor may include one or more interfaces. Interfaces may include inter-integrated circuit (I2C) interfaces, serial peripheral interfaces (SPI), inter-integrated circuit sound (I2S) interfaces, pulse code modulation (PCM) interfaces, universal asynchronous receiver / transmitter (UART) interfaces, mobile industry processor interfaces (MIPI), general-purpose input / output (GPIO) interfaces, subscriber identity module (SIM) interfaces, and / or universal serial bus (USB) interfaces, etc.

[0153] The I2C interface is a bidirectional synchronous serial bus, including a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor may include multiple I2C buses. The processor can couple to a flash, camera 55, etc., through different I2C bus interfaces. In this embodiment, the processor can couple to a measurement circuit through the I2C interface, enabling the processor and the measurement circuit to communicate through the I2C bus interface, thereby realizing the detection function of the electronic device 100.

[0154] The charging management module receives charging input from the charger, which can be either a wireless or wired charger. While charging the battery, the charging management module can also supply power to the electronic device via the power management module.

[0155] The power management module connects the battery, the charging management module, and the processor. It receives input from the battery and / or the charging management module to power the processor, display screen, camera 55, etc. In some other embodiments, the power management module may be located within the processor. In still other embodiments, the power management module and the charging management module may be located in the same device. The display driver circuit drives the display screen to display images or videos, etc.

[0156] Camera 55 is used to capture still images or videos. An object is projected onto a photosensitive element by an optical image generated through a lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device may include one or more cameras. A flash is used to provide supplemental lighting for camera 55.

[0157] It is understood that the above description only schematically illustrates some of the components included in a mobile phone. An actual mobile phone may have more or fewer components than those described above, or combine or separate certain components, or have different component arrangements. The components illustrated can be implemented in hardware, software, or a combination of both.

[0158] It should be noted that, Figure 10 In this embodiment, the mobile phone is shaped like a rectangular tablet. In other alternative embodiments, the electronic device can also be shaped like a square tablet, a circular tablet, an elliptical tablet, etc. Of course, the electronic device can also be a foldable electronic device, etc.

[0159] After introducing the structure of the electronic device, several feasible implementations of the detection circuit of the present application will be described next.

[0160] In the first feasible implementation, Figure 11 A schematic diagram of a detection circuit provided in an embodiment of this application is shown.

[0161] like Figure 11 As shown, the detection circuit may include a first multiplexing module 1110 (which may also be referred to as the first multiplexing module in this embodiment), a first operational amplifier PGA1, a second operational amplifier PGA2, a first filter LPF1, a second filter LPF2, a first driving module 1120, a second driving module 1130, a second multiplexing module 1140, a first analog-to-digital converter ADC1, and a control module 1150.

[0162] Taking the first multiplexing module 1110, which can poll 8 devices under test (DUTs), as an example, the first multiplexing module 1110 includes 8 pairs of input ports (i.e., M input terminals). Specifically, the first input port IN1+ of the first pair of input ports is connected to one end of the first DUT, and the second input port IN1- of the first pair of input ports is connected to the other end of the first DUT; the first input port IN2+ of the second pair of input ports is connected to one end of the second DUT, and the second input port IN2- of the second pair of input ports is connected to the other end of the second DUT; ...; the first input port IN7+ of the seventh pair of input ports is connected to one end of the seventh DUT, and the second input port IN7- of the seventh pair of input ports is connected to the other end of the seventh DUT; the first input port IN8+ of the eighth pair of input ports is connected to one end of the eighth DUT, and the second input port IN7- of the eighth pair of input ports is connected to the other end of the eighth DUT.

[0163] Furthermore, the first multiplexing module 1110 may include two pairs of output ports (i.e., the first output port and the second output port of this application). Specifically, the first output port OUTa+ of the first pair of output ports is connected to the non-inverting input of the first operational amplifier PGA1, and the second output port OUTa- of the first pair of output ports is connected to the inverting input of the first operational amplifier PGA1. Similarly, the first output port OUTb+ of the second pair of output ports is connected to the non-inverting input of the second operational amplifier PGA2, and the second output port OUTb- of the second pair of output ports is connected to the inverting input of the second operational amplifier PGA2.

[0164] The first multiplexing module 1110 can select two devices under test (DUTs) to output current sampling data from two pairs of output ports respectively. Specifically, the first multiplexing module 1110 can select one pair of input ports from eight pairs of input ports to be connected to the first pair of output ports, and select one pair of input ports from the remaining seven pairs of input ports to be connected to the second pair of output ports. When a pair of input ports is connected to a pair of output ports, the current sampling data transmitted through that pair of input ports can be output from that pair of output ports. For example, if the first pair of input ports is connected to the first pair of output ports, the current sampling data of the first DUT can be output from the first pair of output ports, that is, the first voltage signal of the first DUT is output from the first output port OUTa+ of the first pair of output ports, and the second voltage signal of the first DUT is output from the second output port OUTa- of the first pair of output ports. Similarly, if the first pair of input ports is connected to the second pair of output ports, the current sampling data of the first DUT can be output from the second pair of output ports. In the embodiments of this application, when the first pair of input ports is connected to any pair of output ports, it constitutes the first channel CH0 (i.e., the channel used to transmit the current sampling data of the first device under test), when the second pair of input ports is connected to any pair of output ports, it constitutes the second channel CH1 (i.e., the channel used to transmit the current sampling data of the second device under test), ..., when the eighth pair of input ports is connected to any pair of output ports, it constitutes the eighth channel CH7 (i.e., the channel used to transmit the current sampling data of the eighth device under test).

[0165] In some embodiments, Figure 12 A circuit diagram of an exemplary first multiplexing module provided in an embodiment of this application is shown. Figure 12 As shown, the first multiplexing module 1110 may include a first multiplexer 1111 and a second multiplexer 1112. The first multiplexer 1111 may include the aforementioned first pair of output ports, namely the first output port OUTa+ and the second output port OUTa-. The second multiplexer 1112 may include the aforementioned second pair of output ports, namely the first output port OUTb+ and the second output port OUTb-.

[0166] The first multiplexer 1111 may include four pairs of input ports, such as a first pair of input ports (including input port IN1+ and input port IN1-) for connecting a first device under test (DUT), a third pair of input ports (including input port IN3+ and input port IN3-) for connecting a third DUT, a fifth pair of input ports (including input port IN5+ and input port IN5-) for connecting a fifth DUT, and a seventh pair of input ports (including input port IN7+ and input port IN7-) for connecting a seventh DUT. The first multiplexer 1111 can select one pair of input ports from the four pairs and connect the selected input port to the aforementioned first pair of output ports. The second multiplexer 1112 can select one pair of input ports from the other four channels and connect the selected input port to the aforementioned first pair of output ports. For example, the first multiplexer 1111 can select a pair of input ports from the first pair of input ports (including input port IN1+ and input port IN1-), the third pair of input ports (including input port IN3+ and input port IN3-), the fifth pair of input ports (including input port IN5+ and input port IN5-) and the seventh pair of input ports (including input port IN7+ and input port IN7-).

[0167] Similarly, the second multiplexer 1112 may include four pairs of input ports, such as a second pair of input ports (including input port IN2+ and input port IN2-) for connecting a second device under test (DUT), a fourth pair of input ports (including input port IN4+ and input port IN4-) for connecting a fourth DUT, a sixth pair of input ports (including input port IN6+ and input port IN6-) for connecting a sixth DUT, and an eighth pair of input ports (including input port IN8+ and input port IN8-) for connecting an eighth DUT. The second multiplexer 1112 may select one pair of input ports from the second pair of input ports (including input port IN2+ and input port IN2-), the fourth pair of input ports (including input port IN4+ and input port IN4-), the sixth pair of input ports (including input port IN6+ and input port IN6-), and the eighth pair of input ports (including input port IN8+ and input port IN8-).

[0168] Specifically, see [link to relevant documentation] Figure 12The first multiplexer 1111 may include a first switch pair, a third switch pair, a fifth switch pair, and a seventh switch pair. The first switch pair is located between the first pair of input ports and the first pair of output ports, and is used to control the on / off state (i.e., conduction or disconnection) between the first pair of input ports and the first pair of output ports. When the first switch pair is on, the current sampling data of the first device under test (hereinafter referred to as the first current sampling data) can be output from the first pair of output ports. The third switch pair is located between the third pair of input ports and the first pair of output ports, and is used to control the on / off state between the third pair of input ports and the first pair of output ports. When the third switch pair is on, the current sampling data of the third device under test (hereinafter referred to as the third current sampling data) can be output from the first pair of output ports. Output ports; the fifth switch pair is located between the fifth pair of input ports and the first pair of output ports, and is used to control the on / off state between the fifth pair of input ports and the first pair of output ports. When the fifth switch pair is on, the current sampling data of the fifth device under test (hereinafter referred to as the fifth current sampling data) can be output from the first pair of output ports; the seventh switch pair is located between the seventh pair of input ports and the first pair of output ports, and is used to control the on / off state between the seventh pair of input ports and the first pair of output ports. When the seventh switch pair is on, the current sampling data of the seventh device under test (hereinafter referred to as the seventh current sampling data) can be output from the first pair of output ports.

[0169] Each switch pair includes a first switch and a second switch. For each first switch, the first connection terminal of the first switch S11 in the first switch pair is connected to the first input port IN1+ in the first pair of input ports; the first connection terminal of the first switch S31 in the third switch pair is connected to the first input port IN3+ in the third pair of input ports; the first connection terminal of the first switch S51 in the fifth switch pair is connected to the first input port IN5+ in the fifth pair of input ports; and the first connection terminal of the first switch S71 in the seventh switch pair is connected to the first input port IN7+ in the seventh pair of input ports. The second connection terminals of the first switches S11, S31, S51, and S71 are all connected to a first node P1. This first node P1 can be connected to the first output port OUTa+ in the first pair of output ports, or it can directly serve as the first output port OUTa+. Correspondingly, the non-inverting input terminal of the first operational amplifier PGA1 can be connected to this first node P1.

[0170] For each second switch, the first connection terminal of the second switch S12 in the first switch pair is connected to the second input port IN1- in the first pair of input ports; the first connection terminal of the second switch S32 in the third switch pair is connected to the second input port IN3- in the third pair of input ports; the first connection terminal of the second switch S52 in the fifth switch pair is connected to the second input port IN5- in the fifth pair of input ports; and the first connection terminal of the second switch S72 in the seventh switch pair is connected to the second input port IN7- in the seventh pair of input ports. Furthermore, the second connection terminals of the second switches S12, S32, S52, and S72 are all connected to the second node P2. This second node P2 can be connected to the second output port OUTa- in the first pair of output ports, or it can directly serve as the second output port OUTa-. Correspondingly, the negative phase input terminal of the first operational amplifier PGA1 can be connected to this second node P2.

[0171] And, see also Figure 12 The second multiplexer 1112 may include a second switch pair, a fourth switch pair, a sixth switch pair, and an eighth switch pair. The second switch pair is located between the second pair of input ports and controls the connection between the second pair of input ports and the second pair of output ports. When the second switch pair is on, the current sampling data of the second device under test (hereinafter referred to as the second current sampling data) can be output from the second pair of output ports. The fourth switch pair is located between the fourth pair of input ports and the second pair of output ports and controls the connection between the fourth pair of input ports and the second pair of output ports. When the fourth switch pair is on, the current sampling data of the fourth device under test (hereinafter referred to as the fourth current sampling data) can be output from the second pair of output ports. The sixth switch pair is located between the sixth pair of input ports and the second pair of output ports. It is used to control the connection and disconnection between the sixth pair of input ports and the second pair of output ports. When the sixth switch pair is on, the current sampling data of the sixth device under test (hereinafter referred to as the sixth current sampling data) can be output from the second pair of output ports. The eighth switch pair is located between the eighth pair of input ports and the second pair of output ports. It is used to control the connection and disconnection between the eighth pair of input ports and the second pair of output ports. When the eighth switch pair is on, the current sampling data of the eighth device under test (hereinafter referred to as the eighth current sampling data) can be output from the second pair of output ports.

[0172] Each switch pair includes a first switch and a second switch. For each first switch, the first connection terminal of the first switch S21 in the second switch pair is connected to the first input port IN2+ in the second pair of input ports; the first connection terminal of the first switch S41 in the fourth switch pair is connected to the first input port IN4+ in the fourth pair of input ports; the first connection terminal of the first switch S61 in the sixth switch pair is connected to the first input port IN6+ in the sixth pair of input ports; and the first connection terminal of the first switch S81 in the eighth switch pair is connected to the first input port IN8+ in the eighth pair of input ports. Furthermore, the second connection terminals of the first switches S21, S41, S61, and S81 are all connected to a third node P3. This third node P3 can be connected to the first output port OUTb+ in the second pair of output ports, or it can directly serve as the first output port OUTb+. Correspondingly, the non-inverting input terminal of the second operational amplifier PGA2 can be connected to this third node P3.

[0173] For each second switch, the first connection terminal of the second switch S12 in the second switch pair is connected to the second input port IN2- in the second pair of input ports; the first connection terminal of the second switch S32 in the fourth switch pair is connected to the second input port IN4- in the fourth pair of input ports; the first connection terminal of the second switch S52 in the sixth switch pair is connected to the second input port IN6- in the sixth pair of input ports; and the first connection terminal of the second switch S72 in the eighth switch pair is connected to the second input port IN8- in the eighth pair of input ports. Furthermore, the second connection terminals of the second switches S22, S42, S62, and S82 are all connected to the fourth node P4. The fourth node P4 can be connected to the second output port OUTb- in the second pair of output ports, or the fourth node P4 can directly serve as the second output port OUTb-. Correspondingly, the negative phase input terminal of the second operational amplifier PGA2 can be connected to the fourth node P4.

[0174] In this embodiment, the first multiplexer 1111 can select one of the first, third, fifth, and seventh switch pairs to conduct, so as to output the first, third, fifth, or seventh current sampling data from the first pair of output ports. Similarly, the second multiplexer 1112 can select one of the second, fourth, sixth, and eighth switch pairs to conduct, so as to output the second, fourth, sixth, or eighth current sampling data from the second pair of output ports.

[0175] It should be noted that, in the embodiments of this application, the first multiplexer 1111 can also connect to four other devices under test through four pairs of input ports, such as connecting the first device under test to the fourth device under test through the first pair of input ports to the fourth pair of input ports; correspondingly, the second multiplexer 1112 can also connect to four other devices under test through four pairs of input ports, such as connecting the fifth device under test to the eighth device under test through the fifth pair of input ports to the eighth pair of input ports, and there are no specific limitations on this.

[0176] In other embodiments, Figure 13 A circuit diagram of another exemplary first multiplexing module provided in an embodiment of this application is shown.

[0177] like Figure 13 As shown, the first multiplexing module 1110 may include a third multiplexer 1113 and a fourth multiplexer 1114. The third multiplexer 1113 may include the aforementioned first pair of output ports, namely the first output port OUTa+ and the second output port OUTa-. The second multiplexer 1112 may include the aforementioned second pair of output ports, namely the first output port OUTb+ and the second output port OUTb-.

[0178] The third multiplexer 1113 may include eight pairs of input ports, for example, the first pair of input ports (including input ports IN1+ and IN1-) to the eighth pair of input ports (including input ports IN8+ and IN8-).

[0179] Furthermore, the third multiplexer 1113 may include eight switch pairs, and the ninth to sixteenth switch pairs. Each of the ninth to sixteenth switch pairs may include a third switch and a fourth switch; for example, the ninth switch pair includes the third switch S13 and the fourth switch S14, the tenth switch pair includes the third switch S23 and the fourth switch S24, ..., the fifteenth switch pair includes the third switch S73 and the fourth switch S74, and the sixteenth switch pair includes the third switch S83 and the fourth switch S84.

[0180] Specifically, for any switch pair from the ninth to the sixteenth switch pair, such as the i-th switch pair (i is any integer greater than or equal to nine and less than or equal to sixteen), the first connection terminal of the third switch in the i-th switch pair is connected to the input port INi+ of the i-th input port pair, and the second connection terminal of the third switch in the i-th switch pair is connected to the fifth node P5. This fifth node P5 can be connected to the first output port OUTa+ of the first output port pair, or it can be directly used as the first output port OUTa+. Correspondingly, the non-inverting input terminal of the first operational amplifier PGA1 can be connected to this fifth node P5.

[0181] In this configuration, the first connection terminal of the fourth switch in the i-th switch pair is connected to the input port INi- in the i-th input port pair, and the second connection terminal of the fourth switch in the i-th switch pair is connected to the sixth node P6. The sixth node P6 can be connected to the second output port OUTa- in the first output port pair, or the sixth node P6 can be directly used as the second output port OUTa-. Correspondingly, the negative inverting input terminal of the first operational amplifier PGA1 can be connected to the sixth node P6.

[0182] The fourth multiplexer 1114 may include eight pairs of input ports, wherein each pair of input ports of the fourth multiplexer 1114 can be connected one-to-one with each pair of input ports of the third multiplexer 1113. For example, the first input port in the k-th pair of input ports of the fourth multiplexer 1114 can be connected to the first input port INk+ in the k-th pair of input ports of the third multiplexer 1113, and the second input port in the k-th pair of input ports of the fourth multiplexer 1114 can be connected to the second input port INk- in the k-th pair of input ports of the third multiplexer 1113. Here, k can be any integer greater than or equal to 1 and less than or equal to 8.

[0183] Furthermore, the fourth multiplexer 1114 may include eight switch pairs, namely the seventeenth to the twenty-fourth switch pairs. Each of the seventeenth to the twenty-fourth switch pairs may include a fifth switch and a sixth switch. For example, the seventeenth switch pair includes the fifth switch S15 and the sixth switch S16, the eighteenth switch pair includes the fifth switch S25 and the sixth switch S26, ..., the twenty-third switch pair includes the fifth switch S75 and the sixth switch S76, and the twenty-fourth switch pair includes the fifth switch S85 and the sixth switch S86.

[0184] Specifically, for any switch pair from the seventeenth to the twenty-fourth switch pairs, such as the m-th switch pair (m is any integer greater than or equal to seventeen and less than or equal to twenty-four), the first connection terminal of the fifth switch in the m-th switch pair is connected to the input port INi+ of the i-th input port pair, and the second connection terminal of the fifth switch in the i-th switch pair is connected to the seventh node P7. This seventh node P7 can be connected to the first output port OUTb+ of the second output port pair, or it can be directly used as the first output port OUTb+. Correspondingly, the non-inverting input terminal of the second operational amplifier PGA2 can be connected to this seventh node P7.

[0185] In this configuration, the first connection terminal of the sixth switch in the m-th switch pair is connected to input port INi- in the i-th input port pair, and the second connection terminal of the sixth switch in the m-th switch pair is connected to the eighth node P8. The eighth node P8 can be connected to the second output port OUTb- in the second output port pair, or the eighth node P8 can directly serve as the second output port OUTb-. Correspondingly, the negative inverting input terminal of the second operational amplifier PGA2 can be connected to the eighth node P8.

[0186] In this embodiment, the third multiplexer 1113 can select one switch pair from the ninth to the sixteenth switch pairs to conduct, so as to output one sampled data from the first current sampling data to the eighth current sampling data from the first pair of output ports; the fourth multiplexer 1114 can select one switch pair from the seventeenth to the twenty-fourth switch pairs to conduct, so as to output the other sampled data from the first to the eighth current sampling data from the second pair of output ports. Specifically, when the i-th switch pair in the third multiplexer 1113 is conducted, the fourth multiplexer 1114 can select one switch pair from the remaining seven switch pairs excluding the (i+8)-th switch pair to conduct. For example, if the ninth switch pair (third switch S13 and fourth switch S14) in the third multiplexer 1113 is conducted, then one switch pair can be selected from the remaining seven switch pairs (i.e., the eighteenth to the twenty-fourth switch pairs) excluding the seventeenth switch pair (fifth switch S15 and sixth switch S16) to conduct.

[0187] It should be noted that, in the embodiments of this application, the first multiplexing module 1110 can also be implemented as other circuit structures that can select the conduction between two pairs of input ports and two pairs of output ports, that is, circuit structures that can select two current sampling data outputs, and there are no specific limitations on this.

[0188] For the first operational amplifier PGA1, its non-inverting input is connected to the first output port OUTa+ of the first pair of output ports, and its negative-inverting input is connected to the second output port OUTa- of the first pair of output ports. Specifically, when the current sampling data of the s1th device under test (the first voltage signal and the second voltage signal of the s1th device under test) is output from the first pair of output ports OUTa+ and OUTa- (the s1th pair of input ports is connected to the first pair of output ports), the first operational amplifier PGA1 generates a differential voltage of the s1th device under test based on the first voltage signal of the s1th device under test received at its non-inverting input and the second voltage signal of the s1th device under test received at its negative-inverting input. Here, s1 is any integer greater than or equal to 1 and less than or equal to 8.

[0189] For the second operational amplifier PGA2, its non-inverting input is connected to the first output port OUTb+ of the second pair of output ports, and its negative-inverting input is connected to the second output port OUTb- of the second pair of output ports. Specifically, when the current sampling data of the s2th device under test (the first and second voltage signals of the s2th device under test) is output from the second pair of output ports OUTb+ and OUTb- (the s2th pair of input ports is connected to the first pair of output ports), the second operational amplifier PGA2 generates a differential voltage of the s2th device under test based on the first voltage signal of the s2th device under test received at its non-inverting input and the second voltage signal of the s2th device under test received at its negative-inverting input. Here, s2 is any integer greater than or equal to 1 and less than or equal to 8, and s2 is not equal to s1.

[0190] The second multiplexing module 1140 includes two pairs of input ports and one pair of output ports. The first pair of input ports of the second multiplexing module 1140 is connected to the output port of the first operational amplifier PGA1, and is used to receive the differential signal output by the first operational amplifier PGA1. The second pair of input ports of the second multiplexing module 1140 is connected to the output port of the second operational amplifier PGA2, and is used to receive the differential signal output by the second operational amplifier PGA2. Specifically, the second multiplexing module 1140 selects one of the differential signals output by the first operational amplifier PGA1 and the second operational amplifier PGA2 for output.

[0191] For example, Figure 14 A schematic diagram of an exemplary second multiplexing module provided in an embodiment of this application is shown. Figure 14 As shown, the second multiplexing module 1140 may include a first pair of input ports (input port INa+ and input port INa-), a second pair of input ports (input port INb+ and input port INb-) and a pair of output ports (output port OUTe+ and output port OUTe-).

[0192] For the first pair of input ports of the second multiplexing module 1140, it is connected to the output port of the first operational amplifier PGA1. For example, the first input port INa+ of the first pair of input ports of the second multiplexing module 1140 is connected to the first output port OUTc+ of the first operational amplifier PGA1, and the second input port INa- of the first pair of input ports of the second multiplexing module 1140 is connected to the second output port OUTc- of the first operational amplifier PGA1.

[0193] The second pair of input ports of the second multiplexing module 1140 is connected to the output port of the second operational amplifier PGA2. For example, the first input port INb+ of the second pair of input ports of the second multiplexing module 1140 is connected to the first output port OUTd+ of the second operational amplifier PGA2, and the second input port INb- of the second pair of input ports of the second multiplexing module 1140 is connected to the second output port OUTd- of the second operational amplifier PGA2.

[0194] Specifically, the second multiplexing module 1140 may include a first pair of switches and a second pair of switches, wherein each pair of switches includes a seventh switch and an eighth switch. The first connection terminal of the seventh switch S17 in the first pair of switches is connected to the first output port OUTc+ of the first operational amplifier PGA1, and the second connection terminal of the seventh switch S17 in the first pair of switches is connected to the ninth node P9. The first connection terminal of the eighth switch S18 in the first pair of switches is connected to the second output port OUTc- of the first operational amplifier PGA1, and the second connection terminal of the eighth switch S18 in the first pair of switches is connected to the tenth node P10. Similarly, the first connection terminal of the seventh switch S27 in the second pair of switches is connected to the first output port OUTd+ of the second operational amplifier PGA2, and the second connection terminal of the seventh switch S27 in the second pair of switches is connected to the ninth node P9. The first connection terminal of the eighth switch S28 in the second pair of switches is connected to the second output port OUTd- of the second operational amplifier PGA2, and the second connection terminal of the eighth switch S28 in the second pair of switches is connected to the tenth node P10. Among them, the ninth node P9 and the tenth node P10 can be connected to the input terminal of the first analog-to-digital converter ADC1.

[0195] In this embodiment, when the first pair of switches of the second multiplexing module 1140 is turned on with the output terminal of the second multiplexing module 1140, the differential signal output by the first operational amplifier PGA1 can be output to the first analog-to-digital converter ADC1. And, when the second pair of switches of the second multiplexing module 1140 is turned on with the output terminal of the second multiplexing module 1140, the differential signal output by the second operational amplifier PGA1 can be output to the first analog-to-digital converter ADC1.

[0196] The first analog-to-digital converter (ADC1) can be a converter with analog-to-digital conversion functionality. For example, the first ADC1 can be implemented as a Sigma-Delta type ADC. Alternatively, the first ADC1 can also be implemented as a successive approximation ADC, etc., without specific limitations. The operating time of the first ADC1 is the time required for the first ADC1 to perform one analog-to-digital conversion. For example, the operating time of the first ADC1 includes the sampling time and the data conversion time. In the embodiments of this application, the first ADC1 can begin data sampling and analog-to-digital conversion after receiving a start sampling signal (e.g., a start signal) sent by the controller.

[0197] The control module 1150 is capable of controlling the on / off states of the switch pairs in the first multiplexing module 1110 and the switch pairs in the second multiplexing module 1140. Furthermore, the control module 1150 can control the first analog-to-digital converter ADC1 to perform analog-to-digital conversion.

[0198] In this embodiment, the control module 1150 can perform polling power consumption tests on multiple devices under test (eight devices are used as an example in this embodiment). These multiple devices under test can be devices detected by multiple power consumption detection resistors connected to the first multiplexing module 1110, such as the first to eighth devices under test mentioned above.

[0199] In some embodiments, Figures 15A-15C A schematic diagram of a set of exemplary polling power consumption tests provided in an embodiment of this application is shown.

[0200] In one example, if the PGA setup time is equal to the ADC operating time, such as Figure 15A As shown, at time 0 (which can be called the first time), the first operational amplifier PGA1 (used for power consumption testing of channel CH0) and the second operational amplifier PGA2 (used for power consumption testing of channel CH1) can be established simultaneously. After the establishment of the first operational amplifier PGA1 and the second operational amplifier PGA2 is completed at the PGA0 establishment time t1 (or the second time), the differential voltage of the first device under test can be output to the first analog-to-digital converter ADC1. The first analog-to-digital converter ADC1 completes sampling and data conversion during the time period from the PGA0 establishment time t1 to T, and obtains the first current sampling data (i.e., the current sampling data of the first device under test) in digital signal format. It should be noted that during the time period from the PGA0 establishment time t1 to T, the second operational amplifier PGA2 needs to wait after its establishment until the first analog-to-digital converter ADC1 completes the processing of the first current sampling data. For example, Figures 16A-16BThis diagram illustrates a set of exemplary current sampling data transmission processes provided in an embodiment of this application. During the time period from time 0 to T, such as... Figure 16A As shown, the first pair of input ports (including input port IN1+ and input port IN1-) and the first pair of output ports (first output port OUTa+ and second output port OUTa-) are connected, and the first pair of input ports of the second multiplexing module 1140 and the output ports of the second multiplexing module 1140 are connected. At this time, the first current sampling data collected through the first pair of input ports (including input port IN1+ and input port IN1-) can be transmitted along the transmission path ① to the first analog-to-digital converter ADC1, so that the first analog-to-digital converter ADC1 can perform analog-to-digital conversion on the first current sampling data. Also, during the time period from time 0 to T, such as... Figure 16A As shown in ②, the second pair of input ports (including input port IN2+ and input port IN2-) and the second pair of output ports (first output port OUTb+ and second output port OUTb-) are turned on to enable the second operational amplifier PGA2 to establish a channel, so that the differential voltage (differential voltage of the second current sampling data) at the output of the second operational amplifier PGA2 reaches a stable value.

[0201] Furthermore, after the first analog-to-digital converter (ADC1) completes the data conversion of the first current data at the second time T, the differential voltage of the second device under test (DUT) can be output to the first ADC1 to obtain the second current sampling data in digital signal format. Simultaneously, during the processing of the second current sampling data by the first ADC1, the first operational amplifier (PGA1) can receive the current sampling data of the third DUT (corresponding to channel CH2) and perform amplifier setup, so that after the first ADC1 finishes processing the second current sampling data, the differential voltage of the third DUT can be output to the first ADC1 for data processing. For example, as... Figure 16B As shown, during the time period from T to T+t1, the second pair of input ports (including input port IN2+ and input port IN2-) and the second pair of output ports (first output port OUTb+ and second output port OUTb-) are turned on. The second pair of input ports of the second multiplexing module 1140 is also turned on with the output port of the first operational amplifier PGA1. At this time, the second current sampling data acquired through the second pair of input ports (including input port IN2+ and input port IN2-) can be transmitted along transmission path ③ to the first analog-to-digital converter ADC1, so that the first analog-to-digital converter ADC1 performs analog-to-digital conversion on the second current sampling data. Furthermore, during the time period from T to T+t1, as... Figure 16BAs shown in ④, the third pair of input ports (including input port IN3+ and input port IN3-) are connected to the first pair of output ports (first output port OUTa+ and second output port OUTa-) so that the first operational amplifier PGA1 establishes a channel, and the differential voltage at the output of the first operational amplifier PGA1 (the differential voltage of the third current sampling data) reaches a stable value, thereby preparing in advance for the analog-to-digital conversion of the third current sampling data in the subsequent process.

[0202] Similarly, while the first analog-to-digital converter ADC1 is processing the differential data of one operational amplifier, the other operational amplifier can establish the channel in advance, thereby completing a round of detection for 8 channels within 4T+t1 time, which improves the power consumption detection efficiency.

[0203] In a specific example, with Figure 12 Taking the circuit diagram shown as an example, at time 0, the controller can control the first switch pair (first switch S11 and second switch S12) in the first multiplexer 1111 to turn on, at which time the first channel CH0 is turned on; and control the second switch pair (first switch S21 and second switch S22) in the second multiplexer 1112 to turn on, at which time the second channel CH1 is turned on. Also, at the first time t1 (or before the first time t1), the controller can control the seventh switch S17 and the eighth switch S18 in the first switch pair in the second multiplexing module 1140 to turn on, so as to output the first current sampling data transmitted by the first channel CH0 to the first analog-to-digital converter ADC1. Also, at the first time t1, the controller can send a start sampling signal (e.g., a start signal) to the first analog-to-digital converter ADC1, and the first operational amplifier PGA1 responds to the start sampling signal by sampling and converting the first current sampling data.

[0204] Furthermore, at the second time T, the controller can turn on the seventh switch S27 and the eighth switch S28 in the second pair of switches in the second multiplexing module 1140 to output the second current sampling data transmitted through the second channel CH1 to the first operational amplifier PGA1. The controller can also send a start sampling signal to the first operational amplifier PGA1, which, in response, samples and converts the second current sampling data. At the second time T, the controller can turn on the third pair of switches (first switch S31 and second switch S32) in the first multiplexer 1111, switching to the third channel CH2. The first operational amplifier PGA1 then begins establishing the third channel CH2 (receiving the current sampling data of the third device under test (corresponding to channel CH2) and establishing the amplifier).

[0205] Using a similar control method, the electronic device can complete a round of power consumption detection for eight devices under test.

[0206] In another specific example, with Figure 13 Taking the circuit diagram shown as an example, the control method differs from the previous example in that, at time 0, the controller can turn on the ninth switch pair (third switch S13 and fourth switch S14) in the third multiplexer 1113, and turn on the eighteenth switch pair (fifth switch S25 and sixth switch S26) in the fourth multiplexer 1114. And, at the second time T, the controller can turn on the eleventh switch pair (third switch S33 and fourth switch S34) in the third multiplexer 1113, ..., until one round of power consumption detection for the eight devices under test is completed.

[0207] It should be noted that, in the embodiments of this application, when performing power consumption testing on channel CH1, the second operational amplifier PGA2 can be established simultaneously with the first operational amplifier PGA2, or the second operational amplifier PGA2 can be established later than the first operational amplifier PGA2, that is, it can be established before the second time T.

[0208] In another example, if the PGA settling time is shorter than the ADC operating time, then the polling power consumption test can be performed as follows: Figure 15B As shown. With Figure 15A The difference is that after each PGA is established, it is necessary to wait for the first analog-to-digital converter ADC1 to complete the data processing of another PGA before controlling the first analog-to-digital converter ADC1 to process the data of that PGA.

[0209] In yet another example, if the PGA setup time is longer than the ADC operating time, then the polling power consumption test can be performed as follows: Figure 15C As shown. With Figure 15B The difference is that after each PGA is established, the first analog-to-digital converter ADC1 can be controlled to process the data of that PGA.

[0210] In other embodiments, Figures 17A-17C This illustration shows another set of exemplary polling power consumption tests provided in an embodiment of this application. In this set of power consumption tests,

[0211] In one example, if the PGA setup time is equal to the ADC operating time, Figure 17A and Figure 15AThe difference lies in the fact that the second operational amplifier PGA2 starts to build up when the first analog-to-digital converter ADC1 begins processing the first current sampling data; the first operational amplifier PGA1 starts to build up when the first analog-to-digital converter ADC2 begins processing the second current sampling data; and so on; the second operational amplifier PGA2 starts to build up when the first analog-to-digital converter ADC2 begins processing the seventh current sampling data. The specific control method can be found in the relevant descriptions above, and will not be repeated here.

[0212] In another example, if the PGA setup time is shorter than the ADC runtime, Figure 17B and Figure 15B The difference lies in the fact that the second operational amplifier PGA2 starts to build up when the first analog-to-digital converter ADC1 begins processing the first current sampling data; the first operational amplifier PGA1 starts to build up when the first analog-to-digital converter ADC2 begins processing the second current sampling data; and so on; the second operational amplifier PGA2 starts to build up when the first analog-to-digital converter ADC2 begins processing the seventh current sampling data. The specific control method can be found in the relevant descriptions above, and will not be repeated here.

[0213] In yet another example, if the PGA setup time is longer than the ADC operating time, Figure 17C and Figure 15C The difference lies in the following: after the first analog-to-digital converter (ADC1) completes processing the first current sampling data, it can wait for the second operational amplifier (PGA2) to complete its setup before processing the second current sampling data; and after the first ADC2 completes processing the second current sampling data, it can wait for the first operational amplifier (PGA1) to complete its setup before processing the third current sampling data; and so on; after the first ADC2 completes processing the seventh current sampling data, it can wait for the second operational amplifier (PGA2) to complete its setup before processing the eighth current sampling data. The specific control methods can be found in the relevant descriptions above, and will not be repeated here.

[0214] It should be noted that, in the embodiments of this application, other power consumption testing methods that can complete the operational amplifier setup for the next current sampling data during the processing of the previous current sampling data (during the operational amplifier setup and the operation of the analog-to-digital converter) can also be used, and no specific limitations are imposed on them.

[0215] In some embodiments, the embodiments of this application may omit the first filter LPF1 and the second filter LPF2, or the first driving module 1120 and the second driving module 1130, depending on testing requirements or circuit simplification requirements. No specific restrictions are imposed on this.

[0216] The detection circuit provided in this application embodiment can pre-build the operational amplifier for the next current sampling data during the processing of the previous current sampling data (during the operational amplifier setup and the operation of the analog-to-digital converter). Therefore, after the analog-to-digital conversion of the previous current sampling data is completed, the analog-to-digital conversion of the next current sampling data can be performed without waiting for the operational amplifier to build up, thereby improving power consumption detection efficiency. In other words, this application embodiment can reduce the operational amplifier setup time during power consumption detection and improve detection efficiency by using two operational amplifiers in phase-out processing.

[0217] Furthermore, it should be noted that, in the embodiments of this application, the operational amplifier can establish the next current sampling data during the operation of the analog-to-digital converter. Whether it is an analog-to-digital converter such as a Sigma-Delta ADC that cannot independently control the ADC sampling and conversion processes, or an analog-to-digital converter such as a successive approximation ADC (where the sampled signal is first stored in a location and then retrieved after conversion), which can independently control the ADC sampling and conversion processes, the technical solution provided in the embodiments of this application can be used for power consumption detection.

[0218] Furthermore, it should be noted that since the technical solution provided in this application embodiment can shorten the power consumption detection time, the requirement for the ADC sampling rate can be reduced when the switching frequency of the multiplexer is constant, thus reducing the sampling pressure on the ADC.

[0219] Furthermore, it should be noted that by reusing the first analog-to-digital converter ADC1 in this embodiment, the power consumption of the detection circuit can be reduced.

[0220] In a second feasible implementation, the present application also provides another detection circuit. Figure 18 This paper shows a schematic diagram of another detection circuit provided in an embodiment of the present application. Figure 18 and Figure 11 The difference in the detection circuit shown is that the detection circuit 1800 may not include the second multiplexing module 1140.

[0221] The detection circuit 1800 can be used Figures 17A-17C The power consumption polling test logic shown is used to perform power consumption testing.

[0222] It should be noted that other aspects and beneficial effects of the detection circuit 1800 can be found in the above description of the detection circuit 1100 in the embodiments of this application, and will not be repeated here.

[0223] In this embodiment, there is no need to set up a second multiplexing module 1140, which further simplifies the structure of the detection circuit and reduces the size of the detection circuit.

[0224] In a third feasible implementation, this application also provides yet another detection circuit. Figure 19 This paper shows a schematic diagram of another detection circuit provided in an embodiment of the present application. Figure 19 and Figure 11 The difference in the detection circuit shown is that the detection circuit 1900 may also include a second analog-to-digital converter ADC2, and the detection circuit 1900 may not include a second multiplexing module 1140.

[0225] Furthermore, in the detection circuit 1900, the first analog-to-digital converter (ADC1) can be connected to the output terminal of the first driving module 1120, and the second analog-to-digital converter (ADC2) can be connected to the output terminal of the second driving module 1130. The first ADC1 can perform analog-to-digital conversion on the current sampling data output by the first driving module 1120. Similarly, the second ADC2 can perform analog-to-digital conversion on the current sampling data output by the second driving module 1130.

[0226] The detection circuit 1800 can be used Figures 15A-15C The power consumption polling test logic shown can be used for power consumption testing, or alternatively... Figures 17A-17C The power consumption polling test logic shown is used to perform power consumption testing. This application embodiment does not limit the specific power consumption test logic.

[0227] It should be noted that other contents and beneficial effects of the detection circuit 1900 can be found in the above description of the detection circuit 1100 in the embodiments of this application, and the specific structure and control method of the second analog-to-digital converter ADC2 can be found in the above description of the first analog-to-digital converter ADC1 in the embodiments of this application, and will not be repeated here.

[0228] In a fourth feasible implementation, this application also provides yet another detection circuit. Figure 20 This paper shows a schematic diagram of another detection circuit provided in an embodiment of the present application. Figure 20 and Figure 11 The difference in the detection circuit shown is that the detection circuit 2000 may further include a third multiplexing module 1160. The first multiplexing module 1110 may include a pair of output ports, which can be connected to the input of the first operational amplifier PGA1. The third multiplexing module 1160 may also include a pair of output ports, which can be connected to the input of the second operational amplifier PGA2.

[0229] Furthermore, the third multiplexing module 1160 includes eight pairs of input ports. Specifically, the first input port IN9+ of the first pair of input ports is connected to one end of the ninth device under test (DUT), and the second input port IN9- of the first pair of input ports is connected to the other end of the ninth DUT; the first input port IN10+ of the second pair of input ports is connected to one end of the tenth DUT, and the second input port IN10- of the second pair of input ports is connected to the other end of the tenth DUT; ...; the first input port IN7+ of the seventh pair of input ports is connected to one end of the seventh DUT, and the second input port IN15- of the seventh pair of input ports is connected to the other end of the fifteenth DUT; the first input port IN16+ of the eighth pair of input ports is connected to one end of the sixteenth DUT, and the second input port IN16- of the eighth pair of input ports is connected to the other end of the sixteenth DUT.

[0230] The detection circuit provided in this embodiment can perform power consumption tests on more devices under test, and can save the number of detection circuits when the number of devices under test is large, thus reducing the detection cost.

[0231] It should be noted that other aspects and beneficial effects of the detection circuit 2000 can be found in the above description of the detection circuit 1100 in the embodiments of this application, and will not be repeated here.

[0232] Furthermore, it should be noted that the embodiments of this application provide a detection scheme based on two operational amplifiers. More operational amplifiers can be set for detection according to actual needs and specific requirements, and no specific limitation is made in this regard.

[0233] After introducing the detection circuit above, the detection method involved in the embodiments of this application will be described next.

[0234] Figure 21 A schematic diagram of a detection method provided in an embodiment of this application is shown. Figure 21 As shown, the detection method may include S2101 to S2109.

[0235] S2101, the controller controls the output of the first sampling signal to the first operational amplifier PGA1. Exemplarily, the first sampling signal can be the aforementioned first current sampling data. Alternatively, it can be other sampling signals processed by operational amplifiers; there are no specific limitations on this.

[0236] In this embodiment of the application, after the first operational amplifier PGA1 receives the first sampling signal, it establishes an output signal for the first sampling signal. After a preset establishment time t1, the first operational amplifier PGA1 is successfully established and outputs a stable first differential voltage.

[0237] The preset setup time t1 can be a preset value, which can be the time value that allows the differential voltage output by the first operational amplifier PGA1 to reach a stable state after the first sampling signal is output to the first operational amplifier PGA1. In this embodiment, for multiple devices under test (DUTs) performing power consumption detection in the detection circuit, each DUT can correspond to a setup time, and the preset setup time t1 can be greater than or equal to the maximum value among the setup times corresponding to the multiple DUTs.

[0238] In some embodiments, the controller can control the first pair of input ports (including input port IN1+ and input port IN1-) and the first pair of output ports (first output port OUTa+ and second output port OUTa-) in the first multiplexing module 1110 to conduct, so as to transmit the first sampling signal to the first operational amplifier PGA1.

[0239] For example, with Figure 12 Taking the circuit diagram shown as an example, the controller can control the first switch pair (first switch S11 and second switch S12) in the first multiplexer 1111 to be turned on.

[0240] Another example is, with Figure 13 Taking the circuit diagram shown as an example, the controller can control the ninth switch pair (third switch S13 and fourth switch S14) in the third multiplexer 1113 to be turned on.

[0241] S2102, the controller controls the output of the second sampling signal to the second operational amplifier PGA2. For example, the second sampling signal can be the aforementioned second current sampling data. Alternatively, it can be other sampling signals processed by operational amplifiers; there are no specific limitations on this.

[0242] In this embodiment of the application, after the second operational amplifier PGA2 receives the second sampling signal, it establishes an output signal for the second sampling signal. After a preset establishment time t1, the second operational amplifier PGA2 is successfully established and outputs a stable second differential voltage.

[0243] In some embodiments, the controller can control the second pair of input ports (including input port IN1+ and input port IN1-) and the second pair of output ports (first output port OUTb+ and second output port OUTb-) in the first multiplexing module 1110 to conduct, so as to transmit the second sampling signal to the second operational amplifier PGA2.

[0244] For example, with Figure 12 Taking the circuit diagram shown as an example, the controller can control the second switch pair (first switch S21 and second switch S22) in the first multiplexer 1111 to be turned on.

[0245] Another example is, with Figure 13 Taking the circuit diagram shown as an example, the controller can control the eighteenth switch pair (the fifth switch S25 and the sixth switch S26) in the fourth multiplexer 1113 to be turned on.

[0246] And, it should be noted that, Figure 21 The following explanation uses the simultaneous execution of S2101 and S2102 as an example. It is understood that before the controller controls the first analog-to-digital converter module ADC1 to begin data conversion, the second operational amplifier PGA2 can complete the establishment of the second sampled data. For example, S2102 can be executed when S2103 begins. Alternatively, in this embodiment, S2102 can be executed before S2101; no specific limitation is made in this regard.

[0247] S2103, after the first operational amplifier PGA1 is established, the controller controls the first analog-to-digital converter module ADC1 to perform analog-to-digital conversion on the first sampled data to obtain the first sampled data in digital signal form.

[0248] For example, the controller can send a start sampling signal to the first analog-to-digital converter module ADC1 to drive the first analog-to-digital converter module ADC1 to perform analog-to-digital conversion.

[0249] In some embodiments, prior to S2103, the controller may also control the first pair of input ports of the second multiplexing module 1140 to be connected to the output port of the second multiplexing module 1140, so that the first analog-to-digital converter module ADC1 can receive the first differential signal.

[0250] S2104, after the first analog-to-digital converter module ADC1 completes the conversion of the first sampled data and the second operational amplifier PGA2 is established, the controller controls the first analog-to-digital converter module ADC1 to perform analog-to-digital conversion on the second sampled data to obtain the second sampled data in digital signal form.

[0251] In some embodiments, the controller can determine that the first analog-to-digital conversion module ADC1 has completed the conversion of the first sampled data after the ADC1 operating time t2 has elapsed from the time the start sampling signal is sent.

[0252] In some embodiments, after the first analog-to-digital converter (ADC1) completes the conversion of the first sampled data, the controller can control the second pair of input ports of the second multiplexing module 1140 to be connected to the output port of the second multiplexing module 1140, so that the first analog-to-digital converter (ADC1) can receive the second differential signal.

[0253] It should be noted that the implementation of S2104 is similar to that of S2103. Other contents of S2104 can be found in the relevant descriptions in the above-mentioned parts of the embodiments of this application, and will not be repeated here.

[0254] S2105, after the first analog-to-digital converter module ADC1 completes the conversion of the first sampled data, the controller controls the third sampled signal to be output to the first operational amplifier PGA1.

[0255] The specific implementation of S2105 is similar to that of S2101, and can be found in the relevant description of S2101, so it will not be repeated here. The difference from S2101 is that the controller needs to control the third pair of input ports (including input port IN3+ and input port IN3-) in the first multiplexing module 1110 to be connected to the first pair of output ports (first output port OUTa+ and second output port OUTa-).

[0256] S2106, after the first analog-to-digital converter (ADC1) completes the conversion of the second sampled data, the controller controls the fourth sampled signal to be output to the second operational amplifier (PGA2).

[0257] In S2106, after the fourth sampled signal is output to the second operational amplifier PGA2, the second operational amplifier PGA2 begins to establish the output signal of the fourth sampled signal.

[0258] It should be noted that the specific implementation of S2106 is similar to that of S2102, and can be found in the relevant description of S2102, which will not be repeated here. The difference from S2102 is that the controller needs to control the fourth pair of input ports (including input port IN4+ and input port IN4-) and the second pair of output ports (first output port OUTb+ and second output port OUTb-) in the first multiplexing module 1110 to be turned on.

[0259] S2107, after the first analog-to-digital converter module ADC1 completes the conversion of the third sampled data and the second operational amplifier PGA2 completes the setup, the controller controls the first analog-to-digital converter module ADC1 to perform analog-to-digital conversion on the fourth sampled data to obtain the fourth sampled data in digital signal form.

[0260] It should be noted that the specific implementation of S2107 is similar to that of S2104. Please refer to the relevant description of S2104 for further details.

[0261] S2108, after the first analog-to-digital converter module ADC1 completes the conversion of the third sampled data, the controller controls the fifth sampled signal to be output to the first operational amplifier PGA1.

[0262] S2109, the controller performs analog-to-digital conversion on the fifth to seventh sampled signals in the same way, and after the first analog-to-digital conversion module ADC1 completes the conversion of the seventh sampled data and the second operational amplifier PGA2 completes the setup, the controller controls the first analog-to-digital conversion module ADC1 to perform analog-to-digital conversion on the eighth sampled data to obtain the fourth sampled data in digital signal form.

[0263] It should be noted that the controller's processing procedures for the fifth and seventh sampled signals can be found in the description of the third sampled signal above. Similarly, the controller's processing procedures for the sixth sampled signal can be found in the description of the fourth sampled signal above, and will not be repeated here.

[0264] It should be noted that other aspects of the detection method in this application's embodiments can be found in the relevant descriptions above, such as... Figures 17A to 17C , Figures 17A to 17C The description section will not be repeated here.

[0265] It is understood that, in order to achieve the above-mentioned functions, electronic devices include hardware and / or software modules that perform the respective functions. Based on the algorithmic steps of the examples described in the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.

[0266] In one example, Figure 22 A schematic block diagram of an apparatus 2200 according to an embodiment of this application is shown. The apparatus 2200 may include a processor 2201 and a transceiver / transceiver pin 2202, and optionally, a memory 2203.

[0267] The various components of device 2200 are coupled together via bus 2204, which includes a data bus, a power bus, a control bus, and a status signal bus. However, for clarity, all buses are referred to as bus 2204 in the figure.

[0268] Optionally, the memory 2203 can be used for the instructions in the foregoing method embodiments. The processor 2201 can be used to execute the instructions in the memory 2203, control the receive pin to receive signals, and control the transmit pin to transmit signals.

[0269] Device 2200 may be an electronic device or a chip of an electronic device in the above method embodiments.

[0270] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0271] The steps performed by the control module 1150 in the detection method provided in the above-described embodiment of this application can also be performed by a chip system included in an electronic device. This chip system may include a processor and a Bluetooth chip. The chip system may be coupled to a memory, enabling it to call a computer program stored in the memory during operation to implement the steps performed by the control module 1150. The processor in the chip system can be an application processor or a non-application processor.

[0272] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A detection circuit, characterized in that, Located in electronic devices, including: The first multiplexing module includes M input terminals, a first output terminal, and a second output terminal. Each input terminal corresponds to a device under test (DUT) of the electronic device. Each input terminal is used to acquire the sampling signal of the corresponding DUT, where M is an integer greater than or equal to 2. A first operational amplifier, wherein the input terminal of the first operational amplifier is connected to the first output terminal; A second operational amplifier, wherein the input terminal of the second operational amplifier is connected to the second output terminal; An analog-to-digital converter is used to acquire the output signal of the first operational amplifier or the output signal of the second operational amplifier. The controller is used to control the first multiplexing module to output a first sampling signal from the first output terminal at a first moment, and the first operational amplifier obtains a first differential signal based on the first sampling signal, wherein the first sampling signal is the sampling signal obtained by the first target input terminal among the M input terminals, and the first differential signal is in a stable state at a second moment; Furthermore, it is also used to control the analog-to-digital converter to convert the first differential signal at a third time, and to obtain the first digital sampling signal at a fourth time, wherein the third time is equal to or later than the second time; Furthermore, it is also used to control the first multiplexing module to output a second sampling signal from the second output terminal at the fifth time, and the second operational amplifier obtains a second differential signal based on the second sampling signal, wherein the second differential signal is in a stable state at the sixth time; And, it is also used to control the analog-to-digital converter to convert the second differential signal at the seventh time, so as to obtain the second digital sampling signal at the eighth time; Wherein, the fifth time point is earlier than the fourth time point, and the seventh time point is later than or equal to the fourth time point.

2. The detection circuit according to claim 1, characterized in that, The controller is also used for: At the ninth moment, the first multiplexing module is controlled to output a third sampling signal from the first output terminal, and the first operational amplifier obtains a third differential signal based on the third sampling signal. The third differential signal is in a stable state at the tenth moment, which is later than the ninth moment. Furthermore, it is also used to control the analog-to-digital converter to convert the third differential signal at the eleventh time, and to obtain the third digital sampled signal at the twelfth time, wherein the eleventh time is equal to or later than the tenth time, and the twelfth time is later than the eleventh time; The ninth time is earlier than the eighth time, and the ninth time is later than or equal to the fourth time.

3. The detection circuit according to claim 1, characterized in that, The sixth time point is earlier than or equal to the fourth time point.

4. The detection circuit according to claim 1, characterized in that, The detection circuit further includes: The second multiplexing module includes a first input terminal, a second input terminal, and a third output terminal. The first input terminal is connected to the output terminal of the first operational amplifier, and the second input terminal is connected to the output terminal of the second operational amplifier. The controller is further configured to: control the second multiplexing module to connect the first input terminal to the third output terminal at or before the third time; In addition, at or before the seventh time, the second multiplexing module is controlled to connect the second input terminal to the third output terminal.

5. The detection circuit according to claim 1, characterized in that, M equals 2N, where the M input terminals include N third input terminals and N fourth input terminals, and N is any positive integer. The first multiplexing module includes: The first multiplexer includes the N third input terminals and the first output terminal, wherein the i-th third input terminal is used to acquire the sampling signal of the (2i-1)-th device under test, and i is an integer greater than or equal to 1 and less than or equal to N; The second multiplexer includes the N fourth input terminals and the second output terminal, wherein the i-th fourth input terminal is used to acquire the sampling signal of the 2i-th device under test, and i is an integer greater than or equal to 1 and less than or equal to N; The controller is specifically used for: At the first moment, the first multiplexer is controlled to connect the kth third input terminal to the first output terminal, wherein the kth third input terminal is the first target input terminal; Furthermore, at the fifth moment, the control of the second multiplexer is to connect the kth fourth input terminal to the second output terminal, wherein the kth fourth input terminal is the second target input terminal, and k is an integer greater than or equal to 1 and less than or equal to N.

6. The detection circuit according to claim 1, characterized in that, M equals 2N, where N is any positive integer. The first multiplexing module includes: The third multiplexer includes M fifth input terminals and the first output terminal, wherein the j-th fifth input terminal is used to acquire the sampling signal of the j-th device under test, and j is an integer greater than or equal to 1 and less than or equal to M; The fourth multiplexer includes M sixth input terminals and the second output terminal, wherein the j-th sixth input terminal is used to acquire the sampling signal of the j-th device under test; The controller is specifically used for: At the first moment, the third multiplexer is controlled to connect the 2k-1th fifth input terminal to the first output terminal, and the 2k-1th fifth input terminal is the first target input terminal; Furthermore, at the fifth moment, the fourth multiplexer is controlled to connect the 2kth sixth input terminal to the second output terminal, wherein the 2kth sixth input terminal is the second target input terminal, and k is an integer greater than or equal to 1 and less than or equal to N.

7. The detection circuit according to claim 5 or 6, characterized in that, When k equals 1, the fifth moment is later than or equal to the first moment; When k is greater than 1, the fifth time point is later than or equal to the second time point.

8. The detection circuit according to claim 1, characterized in that, The controller is also used for: After controlling the analog-to-digital converter to generate a sampling signal for the Mth device under test in digital signal form, the first input terminal is determined as the first target input terminal.

9. A detection method, characterized in that, The method is applied to the detection circuit as described in any one of claims 1-8, and the method includes: The controller controls the first multiplexing module to output a first sampling signal from the first output terminal at the first moment; The first operational amplifier obtains a first differential signal based on the first sampled signal, wherein the first sampled signal is the sampled signal obtained by the first target input terminal among the M input terminals, and the first differential signal is in a stable state at the second time. At a third time, the controller controls the analog-to-digital converter to convert the first differential signal and obtains the first digital sampled signal at a fourth time, wherein the third time is equal to or later than the second time. At the fifth moment, the controller controls the first multiplexing module to output the second sampling signal from the second output terminal; The second operational amplifier obtains a second differential signal based on the second sampled signal, wherein the second differential signal is in a stable state at the sixth time. At the seventh time, the controller controls the analog-to-digital converter to convert the second differential signal, and obtains the second digital sampling signal at the eighth time; Wherein, the fifth time point is earlier than the fourth time point, and the seventh time point is later than or equal to the fourth time point.

10. The detection method according to claim 9, characterized in that, The method further includes: At the ninth moment, the controller controls the first multiplexing module to output a third sampling signal from the first output terminal; The first operational amplifier obtains a third differential signal based on the third sampled signal, wherein the third differential signal is in a stable state at the tenth time, which is later than the ninth time; At the eleventh moment, the controller controls the analog-to-digital converter to convert the third differential signal and obtains the third digital sampled signal at the twelfth moment, wherein the eleventh moment is equal to or later than the tenth moment, and the twelfth moment is later than the eleventh moment; The ninth time is earlier than the eighth time, and the ninth time is later than or equal to the fourth time.

11. An electronic device, characterized in that, include: M devices under test, M resistors, wherein the M devices under test correspond one-to-one with the M resistors, and each resistor is connected to the power supply circuit of the device under test corresponding to each resistor; The first multiplexing module includes M input terminals, a first output terminal, and a second output terminal. Each input terminal corresponds to one of the devices under test (DUTs). Each input terminal is connected to the resistor of the corresponding DUT and is used to obtain a sampling signal from the resistor of the corresponding DUT. Here, M is an integer greater than or equal to 2. A first operational amplifier, wherein the input terminal of the first operational amplifier is connected to the first output terminal; A second operational amplifier, wherein the input terminal of the second operational amplifier is connected to the second output terminal; An analog-to-digital converter is used to acquire the output signal of the first operational amplifier or the output signal of the second operational amplifier. The controller is used to control the first multiplexing module to output a first sampling signal from the first output terminal at a first moment, and the first operational amplifier obtains a first differential signal based on the first sampling signal, wherein the first sampling signal is the sampling signal obtained by the first target input terminal among the M input terminals, and the first differential signal is in a stable state at a second moment; Furthermore, it is also used to control the analog-to-digital converter to convert the first differential signal at a third time, and to obtain the first digital sampling signal at a fourth time, wherein the third time is equal to or later than the second time; Furthermore, it is also used to control the first multiplexing module to output a second sampling signal from the second output terminal at the fifth time, and the second operational amplifier obtains a second differential signal based on the second sampling signal, wherein the second differential signal is in a stable state at the sixth time; And, it is also used to control the analog-to-digital converter to convert the second differential signal at the seventh time, so as to obtain the second digital sampling signal at the eighth time; Wherein, the fifth time point is earlier than the fourth time point, and the seventh time point is later than or equal to the fourth time point.

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