Non-maximum suppression hardware acceleration circuit

Abstract

The invention discloses a non-maximum suppression hardware acceleration circuit. The circuit comprises a parameter configuration unit, a read addressing unit, an on-chip storage unit, an IoU processing unit and a write addressing unit, the parameter configuration unit is used for performing parameter configuration, and configured parameters comprise a read addressing base address, an addressing size and a write addressing base address; the read addressing unit is used for reading frame data from the external memory according to the read addressing base address and the addressing size, and writing the read frame data into the on-chip memory unit; the IoU processing unit is used for addressing, calculating and screening the frame data cached by the on-chip storage unit and determining frame mask information; and the write addressing unit is used for writing the frame mask information back to the external memory according to the write addressing base address. By means of the scheme, the calculation efficiency of the NMS can be improved, and power consumption can be reduced.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more specifically to a nonmaximum suppression hardware acceleration circuit. Background Technology

[0002] Non-Maximum Suppression (NMS) is a post-processing technique used for object detection and image segmentation. Its main purpose is to select the optimal bounding box from a set of overlapping bounding boxes to avoid multiple boxes detecting the same object. The basic idea of ​​NMS is to first sort all candidate boxes according to their confidence scores and select the box with the highest confidence score as the reference detection box. Then, the overlap between other detection boxes and the reference detection box is calculated, usually measured by the Intersection over Union (IoU). Finally, these overlapping boxes are removed from the candidate list. This process is repeated until all boxes have been processed. In this way, NMS can effectively suppress boxes with high overlap and low confidence, reduce redundant detection, and improve the accuracy of object detection. It is a widely used method in modern computer vision.

[0003] Traditional NMS implementations primarily rely on the CPU (Central Processing Unit), and the process of calculating the IoU of each frame is serial. This approach has the following main drawbacks:

[0004] (1) High computational resource consumption. Traditional NMS implementations typically require traversing and calculating all candidate boxes, which leads to a sharp increase in computational load when the number of boxes is large, thus consuming a large amount of memory and computational resources. The performance bottleneck of NMS is even more obvious when processing high-resolution images.

[0005] (2) Low processing efficiency. NMS mainly relies on serial processing to calculate the IoU of each candidate box. Especially when there is a lot of box overlap, multiple comparisons and filterings are required, resulting in low computational efficiency. This serial calculation method may take a long time when processing a large number of candidate boxes, affecting the overall detection speed. Especially when the number of boxes is large, the time of NMS increases significantly.

[0006] (3) High energy consumption. Especially with GPU (Graphics Processing Unit) acceleration, energy consumption is significantly increased and the demand for video memory is large. Summary of the Invention

[0007] This invention provides a non-maximum suppression hardware acceleration circuit to improve the efficiency of NMS and reduce power consumption.

[0008] The embodiments of the present invention provide the following technical solutions:

[0009] A nonmaximum suppression hardware acceleration circuit, the circuit comprising: a read addressing unit, an on-chip storage unit, a data processing unit, and a write addressing unit;

[0010] The read addressing unit is used to read frame data from external memory and write the read frame data into the on-chip storage unit;

[0011] The data processing unit is used to address, calculate and filter the frame data cached in the on-chip storage unit to determine the frame mask information.

[0012] The write addressing unit is used to write the box mask information back to the external memory.

[0013] Optionally, the frame data in the external memory is stored in descending order of frame confidence.

[0014] Optionally, the data processing unit includes: an IoU addressing unit and an IoU calculation unit;

[0015] The IoU addressing unit is used to perform multiple rounds of addressing traversal on the on-chip storage unit and transmit the frame data read in each addressing to the IoU computing unit; each addressing reads a set of frame data at once, and the frame data includes the confidence score and coordinates of a single frame;

[0016] The IoU calculation unit is used to take the boxes read by the IoU addressing unit each time as the boxes to be compared, perform IoU calculation on the box data of the boxes to be compared and the box data of the boxes to be compared corresponding to the current round of addressing traversal, determine and record the mask value according to the calculated IoU value, and filter the boxes to be compared corresponding to the next round of addressing traversal according to the mask value.

[0017] Optionally, one address in the on-chip storage unit stores a set of frame data.

[0018] Optionally, the IoU addressing unit performs one or more addressing and reading operations in each round of addressing traversal, reading a set of frame data each time; there are multiple IoU calculation units, and multiple IoU calculation units process the set of frame data in parallel.

[0019] Optionally, each addressing read operation starts with the address of the comparison box corresponding to the current addressing traversal and ends with the address of the last box data stored in the on-chip storage unit.

[0020] Optionally, the IoU calculation unit takes the first valid frame after the comparison frame corresponding to the current round of addressing traversal as the comparison frame corresponding to the next round of addressing traversal.

[0021] Optionally, if the calculated IoU value is greater than a set threshold, the IoU calculation unit sets the mask value of the corresponding comparison box to 1; otherwise, it sets the mask value of the corresponding comparison box to 0.

[0022] Optionally, the IoU calculation unit has a six-stage pipeline structure, wherein the first stage pipeline includes four subtractors and four comparators, the second stage pipeline includes two multipliers and two subtractors, the third stage pipeline includes one adder and one multiplier, the fourth stage pipeline includes one subtractor, the fifth stage pipeline includes one multiplier, and the sixth stage pipeline includes one comparator; the input of the IoU calculation unit is the coordinate information of the bounding box being compared and the bounding box to be compared, as well as the set threshold; the output of the IoU calculation unit is the mask value of the bounding box to be compared.

[0023] Optionally, the circuit further includes:

[0024] The parameter configuration unit is used to configure parameters, including: read addressing base address and addressing size, and write addressing base address;

[0025] The read addressing unit reads frame data from the external memory according to the read addressing base address and the addressing size;

[0026] The write addressing unit writes the frame mask information back to the external memory according to the write addressing base address.

[0027] Compared to the traditional method of serially calculating the IoU of frames and then filtering them, the non-maximum suppression (NMS) hardware acceleration circuit provided in this embodiment of the invention can effectively improve the throughput of hardware computing, reduce the time consumption of frame filtering, and improve the computational efficiency of NMS. This circuit can utilize Field Programmable Gate Array (FPGA) resources to easily and conveniently implement various computing functions, and the circuit structure is more concise. By accelerating the main computation, IoU calculation and filtering can be quickly implemented. The frame sorting and subsequent frame selection processes, due to their small computational load, can be completed by the host, simplifying the overall circuit structure. Moreover, using on-chip storage can significantly reduce the interaction between the NMS hardware acceleration circuit and external memory, enabling data reuse. In addition, on-chip storage has shorter access latency and can provide greater data read / write bandwidth compared to external storage.

[0028] Furthermore, the non-maximum suppression hardware acceleration circuit provided in this embodiment of the invention can support a certain degree of parallelism in calculation and filtering, that is, it can support the calculation of IoU between a comparison box and multiple subsequent boxes and the filtering of detection boxes, which greatly improves the calculation efficiency. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a non-maximum suppression hardware acceleration circuit provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the structure of the frame data cached in the on-chip storage unit in an embodiment of the present invention;

[0031] Figure 3 This is a block diagram illustrating the principle of IoU addressing by the IoU addressing unit in this embodiment of the invention;

[0032] Figure 4 This is a schematic diagram showing the relationship between the two boxes in an embodiment of the present invention;

[0033] Figure 5 This is a schematic diagram of a structure of an IoU calculation unit in an embodiment of the present invention;

[0034] Figure 6 This is another schematic diagram of the non-maximum suppression hardware acceleration circuit provided in the embodiment of the present invention. Detailed Implementation

[0035] The principles and spirit of the invention will now be described with reference to exemplary embodiments shown in the accompanying drawings. It should be understood that these embodiments are described merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way.

[0036] To address the issues of high resource consumption and low efficiency inherent in traditional NMS implementations that rely heavily on the CPU, this invention provides a non-maximum suppression acceleration circuit. This circuit writes the read frame data into an on-chip memory unit for caching, addresses, calculates, and filters the frame data cached in the on-chip memory unit to determine the frame mask information, and then writes the frame mask information back to external memory.

[0037] like Figure 1 The diagram shown is a structural schematic of a nonmaximum suppression hardware acceleration circuit provided in an embodiment of the present invention.

[0038] The nonmaximum suppression hardware acceleration circuit includes: a read addressing unit 101, an on-chip memory unit 102, a data processing unit 103, and a write addressing unit 104. Wherein:

[0039] The read addressing unit 101 is used to read frame data from the external memory 200 according to the read addressing base address and addressing size, and write the read frame data into the on-chip storage unit 102;

[0040] The data processing unit 103 is used to address, calculate and filter the frame data cached in the on-chip storage unit 102 to determine the frame mask information. The data processing unit 103 needs to read the addressing unit 101 to write all the frame data in the external memory 200 into the on-chip storage unit 102 before it can address, calculate and filter the frame data cached in the on-chip storage unit 102.

[0041] The write addressing unit 104 is used to write the frame mask information back to the external memory 200 according to the write addressing base address.

[0042] The frame mask information is used to identify valid and invalid frames, so that the host can select valid frames based on the frame mask information. The frame mask information written back to external memory 200 is the mask value corresponding to all frames. For example, a mask value of 1 indicates that the corresponding frame is valid; a mask value of 0 indicates that the corresponding frame is invalid.

[0043] It should be noted that, in a non-limiting embodiment, the frame data in the external memory 200 can be stored in descending order of frame confidence to facilitate subsequent processing. The frame confidence refers to the confidence that the frame is a target frame.

[0044] like Figure 1 As shown, the data processing unit 103 may include: an IoU addressing unit 131 and an IoU calculation unit 132. Wherein:

[0045] IoU addressing unit 131 is used to perform multiple rounds of addressing traversal on on-chip storage unit 102, and transmit the frame data read in each addressing to the IoU calculation unit; each addressing reads a set of frame data at once, the frame data includes the confidence score and coordinates of a single frame; the coordinates of the frame include the coordinates of the four boundary points of the frame: upper left, lower left, upper right, and lower right.

[0046] The IoU calculation unit 132 is used to take the boxes read by the IoU addressing unit 131 in each addressing as the boxes to be compared, calculate the IoU between the box data of the boxes to be compared and the box data of the boxes to be compared corresponding to the current round of addressing traversal, determine and record the mask value based on the calculated IoU value, and filter the boxes to be compared and the valid boxes corresponding to the next round of addressing traversal based on the mask value.

[0047] In this embodiment, the IoU addressing unit 131 is used for IoU calculation addressing in NMS, and together with the IoU calculation unit, it completes the IoU calculation and filtering of all boxes.

[0048] In some embodiments, an address in the on-chip storage unit 102 can store a set of frame data, such as frame data for 16 frames. For a set of frame data, during subsequent data processing, an IoU calculation unit 132 can perform IoU calculation on each frame in the set of frame data sequentially, or a group of IoU calculation units 132 can process the set of frame data in parallel, that is, multiple frames in the set are used as frame data of the frame to be compared and IoU calculation is performed with the frame data of the current frame being compared, so as to improve processing speed and processing efficiency.

[0049] Accordingly, the IoU addressing unit 131 needs to perform one or more addressing read operations during each round of addressing traversal, and can read a set of frame data each time. Each addressing read operation starts with the address of the comparison frame corresponding to the current round of addressing traversal and ends with the address of the last frame data stored in the on-chip storage unit 102. The IoU calculation unit 132 can process each set of frame data in parallel to determine the valid and invalid frames.

[0050] Furthermore, the IoU calculation unit 132 can also use the first valid frame after the frame being compared in the current round of addressing traversal as the frame being compared in the next round of addressing traversal.

[0051] It should be noted that the calculation of IoU can be performed using some existing calculation methods, and this embodiment of the invention does not limit the calculation of IoU.

[0052] The following example uses 16 boxes per group of data. Figure 2 and Figure 3 The addressing process of IoU addressing unit 131 is described in detail. Among them, Figure 2 This is a schematic diagram of the structure of the frame data cached in the on-chip storage unit in an embodiment of the present invention; Figure 3 This is a block diagram illustrating the principle of IoU addressing in an embodiment of the present invention.

[0053] Reference Figure 2 There are n input boxes, from box0 to box(n-1). These boxes are arranged in descending order of confidence. All boxes are divided into groups of 16, with zeros added to the last group if necessary. Accordingly, one address in the on-chip storage unit 102 needs to store the information of 16 boxes, and the IoU computing unit 132 must also be able to support parallel computing of 16 boxes.

[0054] Simultaneously refer to Figure 3 The IoU addressing unit 131 and the IoU calculation unit 132 complete the addressing calculation process. It should be noted that during the initial IoU addressing, all bounding boxes are considered valid by default. The addressing calculation process is as follows:

[0055] (1) First step of IoU addressing, reading Figure 2 The first set of data is box0 to box15. First, box0 is used as the box to be compared, and boxes1 to box15 are used as boxes to be compared. The IoU calculation unit 132 calculates the IoU of box0 and boxes1 to box15 at the same time, and completes the filtering based on the calculated IoU of the boxes to be compared.

[0056] After filtering, you will get a set of mask information similar to 1010_1000_1111_0000. For example, a 16-bit number corresponds to the mask value of 16 boxes calculated each time. A mask value of 0 indicates that the corresponding box has been filtered as an invalid box, and a mask value of 1 indicates that the corresponding box is a valid box in the current filtering.

[0057] (2) Second step of IoU addressing, reading Figure 2 The second set of data in the middle, namely box16 to box31. At this time, box0 is still the box being compared and will not be refreshed, while box16 to box31 are the boxes to be compared.

[0058] Similar to (1), calculate the IoU between each box to be compared and the box being compared in turn to obtain the mask information of the second set of boxes.

[0059] This process continues until all box data has been traversed once. This yields the IoU calculation results between all valid boxes in this addressing iteration and the comparison box `box0`, allowing us to obtain the mask values ​​for each box and thus determine the valid and invalid boxes after this round of addressing. At this point, the comparison box for the next round of addressing needs to be determined based on the current mask values ​​of each box. Taking the mask information 1010_1000_1111_0000 obtained in the first iteration as an example, the comparison box for the next round of addressing is the first box after `box0` with a mask value of 1, i.e., `box2`.

[0060] (3) Starting from the selected comparison box (i.e., box2), the addressing and reading operation is performed to read the box data from the on-chip memory unit 102. Each time, a group (i.e., 16) of box data is read, and the above steps (1) to (2) are repeated. Each time, the mask value of each box is bitwise ANDed with the mask value of the previous box.

[0061] (4) After all the box data has been compared with the box data of box2, continue the new round of addressing traversal process. Repeat the above operations (1) to (3) until the IoU calculation and filtering of all boxes to be compared with all subsequent boxes is completed.

[0062] Once the last set of box data has been compared, the mask information for all boxes is fixed.

[0063] It should be noted that during the above addressing and calculation process, the mask information can be stored in on-chip memory, for example, Figure 3 The mask memory shown.

[0064] IoU calculation unit 132 needs to calculate the IoU value of the two boxes. When the IoU value of the two boxes is greater than a set threshold, it needs to return false, indicating that the mask value of the box to be compared is 0.

[0065] by Figure 4 Taking the two boxes shown as examples, the white box is the box being compared, and the light gray box is the box to be compared. The coordinates of the top-left corner of the box being compared are (x0, y0), and the coordinates of the bottom-right corner are (x1, y1); the coordinates of the top-left corner of the box to be compared are (x2, y2), and the coordinates of the bottom-right corner are (x3, y3).

[0066] Let sn be the intersection of two bounding boxes, and su be the union of two bounding boxes. The algorithm requires that boxes where sn / su > a set threshold need to be filtered out. That is, boxes where su multiplied by the threshold is less than sn need to be filtered out, and the mask value of the corresponding box to be compared is set to 0; otherwise, it is set to 1.

[0067] In some embodiments, the IoU calculation unit 132 may adopt a multi-stage pipeline structure. The input of the IoU calculation unit 132 is the coordinate information of the comparison box and the box to be compared, as well as the set threshold; its output is the mask value of the box to be compared.

[0068] like Figure 5 The diagram shown is a structural schematic of an IoU calculation unit in an embodiment of the present invention. In this example, the IoU calculation unit is a six-stage pipeline structure.

[0069] The following is combined Figure 4 The two boxes shown illustrate the structure and operation of the IoU calculation unit.

[0070] The first-stage pipeline consists of four subtractors and four comparators. The four subtractors obtain the width *w* and height *h* of the comparison box (white box) and the box to be compared (light gray box). Subtracting *x1* from *x0* yields *w0*, subtracting *y1* from *y0* yields *h0*, and so on. Simultaneously, the four comparators find the intersection of the two boxes, namely the top-left corner (x2, y2) and bottom-right corner (x3, y3) of the dark gray box.

[0071] The second-stage pipeline includes two multipliers and two subtractors. The two multipliers obtain the areas of the comparison box and the box to be compared, respectively, where the area of ​​the comparison box is s0 = w0 * h0; and the area of ​​the box to be compared is s1 = w1 * h1. Simultaneously, the two subtractors obtain the width and height of the intersection of the two boxes, i.e., wn = x1 - x2; hn = y1 - y2.

[0072] The third - stage pipeline includes an adder and a multiplier. The adder is used to obtain the sum of the areas of the compared box and the box to be compared, that is, s0 + s1. At the same time, a multiplier is used to implement wn×hn to obtain the area of the intersection part, sn.

[0073] The fourth - stage pipeline includes a subtractor, which subtracts the area of the intersection part sn of the two boxes from the sum of the areas of the two boxes s0 + s1 to obtain the union area su of the two boxes.

[0074] The fifth - stage pipeline includes a multiplier, which is used to complete the operation su×set threshold.

[0075] The sixth - stage pipeline includes a comparator, which compares the magnitudes of su×set threshold and sn. If su×set threshold < su, it means that the box to be compared should be removed, and the mask value of the box to be compared is output as 0; otherwise, the mask value of the box to be compared is output as 1.

[0076] In an actual circuit, multiple (such as 16) of the above - mentioned IoU calculation units can be instantiated to perform parallel calculations on a set of box data, that is, support parallel calculation of IoU values for multiple boxes and complete screening simultaneously.

[0077] The non - maximum suppression hardware acceleration circuit provided by the embodiment of the present invention can effectively improve the throughput rate of hardware calculation, reduce the time consumption of box screening, and improve the calculation efficiency of NMS.

[0078] Due to the highly flexible, customizable, and low - latency characteristics of FPGA, the embodiment of the present invention provides a non - maximum suppression acceleration circuit, which can utilize FPGA resources to perform parallel IoU calculation and detection box screening for one compared box and multiple boxes to be compared simultaneously when calculating the IoU of boxes, thereby further improving the throughput rate of hardware calculation and the calculation efficiency.

[0079] As Figure 6 shown, in another non - restrictive embodiment, the non - maximum suppression hardware acceleration circuit 100 may further include a parameter configuration unit 10 for parameter configuration. The configured parameters include, but are not limited to: read addressing base address and addressing size, write addressing base address.

[0080] Correspondingly, in this embodiment, the read addressing unit 101 can read box data from the external memory 200 according to the read addressing base address and addressing size; the write addressing unit 104 can write the box mask information back to the external memory 200 according to the write addressing base address.

[0081] By using the above - mentioned parameter configuration unit 10, various parameter configurations can be more flexibly implemented to meet the hardware requirements in different applications.

[0082] In one non-limiting embodiment, Figure 1 The read addressing unit 101 in the circuit can perform read operations on the external memory 200 via register triggering. For example, a startup register (not shown) can be set in the nonmaximum suppression hardware acceleration circuit 100. Accordingly, after the parameter configuration unit 10 completes parameter configuration, a startup indication value (e.g., a startup indication value of 1) can be written into the startup register by an external host to indicate the start of addressing calculation.

[0083] Additionally, an end register (not shown) can be configured in the nonmaximum suppression hardware acceleration circuit 100. After the write addressing unit 104 generates the last write request, an end indicator value (e.g., an end indicator value of 1) is written into the end register by an internal circuit to indicate that the addressing calculation is complete. Accordingly, the external host can read the end register to determine whether the addressing calculation is complete.

[0084] The external host can configure the startup register through a general interface of a Field Programmable Gate Array (FPGA).

[0085] Accordingly, the external host triggers the non-maximum suppression hardware acceleration circuit 100 to start or stop the addressing calculation process by reading the startup register.

[0086] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0087] For example, for various devices and products applied to or integrated into a chip, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A non-maximum suppression hardware acceleration circuit, characterized in that, The circuit includes: a read addressing unit, an on-chip storage unit, a data processing unit, and a write addressing unit; The read addressing unit is used to read frame data from external memory and write the read frame data into the on-chip storage unit; The data processing unit is used to address, calculate and filter the frame data cached in the on-chip storage unit to determine the frame mask information. The write addressing unit is used to write the box mask information back to the external memory.

2. The non-maximum suppression hardware acceleration circuit according to claim 1, characterized in that, The frame data in the external memory is stored in descending order of frame confidence.

3. The non-maximum suppression hardware acceleration circuit according to claim 1, characterized in that, The data processing unit includes: an IoU addressing unit and an IoU calculation unit; The IoU addressing unit is used to perform multiple rounds of addressing traversal on the on-chip storage unit and transmit the frame data read in each addressing to the IoU computing unit; each addressing reads a set of frame data at once, and the frame data includes the confidence score and coordinates of a single frame; The IoU calculation unit is used to take the boxes read by the IoU addressing unit each time as the boxes to be compared, perform IoU calculation on the box data of the boxes to be compared and the box data of the boxes to be compared corresponding to the current round of addressing traversal, determine and record the mask value according to the calculated IoU value, and filter the boxes to be compared corresponding to the next round of addressing traversal according to the mask value.

4. The non-maximum suppression hardware acceleration circuit according to claim 3, characterized in that, One address in the on-chip storage unit stores a set of frame data.

5. The non-maximum suppression hardware acceleration circuit according to claim 4, characterized in that, The IoU addressing unit performs one or more addressing and reading operations in each round of addressing traversal, reading a set of box data each time. There are multiple IoU calculation units, and these multiple IoU calculation units process the set of frame data in parallel.

6. The non-maximum suppression hardware acceleration circuit according to claim 5, characterized in that, Each addressing and reading operation starts at the address of the comparison box corresponding to the current addressing traversal and ends at the address of the last box data stored in the on-chip storage unit.

7. The non-maximum suppression hardware acceleration circuit according to claim 4, characterized in that, The IoU calculation unit uses the first valid frame after the frame being compared in the current round of addressing traversal as the frame being compared in the next round of addressing traversal.

8. The non-maximum suppression hardware acceleration circuit according to claim 7, characterized in that, When the calculated IoU value is greater than a set threshold, the IoU calculation unit sets the mask value of the corresponding comparison box to 1; otherwise, it sets the mask value of the corresponding comparison box to 0.

9. The non-maximum suppression hardware acceleration circuit according to claim 8, characterized in that, The IoU calculation unit has a six-stage pipeline structure. The first stage pipeline includes four subtractors and four comparators; the second stage pipeline includes two multipliers and two subtractors; the third stage pipeline includes one adder and one multiplier; the fourth stage pipeline includes one subtractor; the fifth stage pipeline includes one multiplier; and the sixth stage pipeline includes one comparator. The input of the IoU calculation unit is the coordinate information of the bounding box being compared and the bounding box to be compared, as well as the set threshold. The output of the IoU calculation unit is the mask value of the bounding box to be compared.

10. The non-maximum suppression hardware acceleration circuit according to any one of claims 1 to 9, characterized in that, The circuit also includes: The parameter configuration unit is used to configure parameters, including: read addressing base address and addressing size, and write addressing base address; The read addressing unit reads frame data from the external memory according to the read addressing base address and the addressing size; The write addressing unit writes the frame mask information back to the external memory according to the write addressing base address.

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