On-chip variable resistance device structure and electronic equipment

Abstract

The invention provides an on-chip variable resistance device structure and electronic equipment. The on-chip variable resistance device structure comprises a substrate, a nitride epitaxial layer, an electrode structure layer and a gate structure layer, wherein the nitride epitaxial layer is formed on the substrate; the electrode structure layer and the gate structure layer are formed on the nitride epitaxial layer; the electrode structure layer comprises a first electrode and a second electrode, the nitride epitaxial layer comprises a channel layer and a barrier layer which are used for forming a heterojunction interface, and the gate structure layer comprises a first semiconductor layer and a third electrode which are stacked and formed on the barrier layer, and a separation groove formed in the first semiconductor layer. By regulating and controlling the extension path and the structure parameter of the separation groove on the barrier layer and combining the applied voltage of the third electrode, the concentration and the distribution of two-dimensional electron gas at the heterojunction interface and the dynamic control of a conductive channel can be realized, so that the wide-range and high-precision dynamic adjustment of the on-chip resistance device structure on-resistance is realized, and the on-chip resistance device is suitable for large-scale production. The technical requirements of a high-performance integrated system on the on-chip variable resistor are met, and the on-chip variable resistor has important application value.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an on-chip variable resistor device structure and electronic device. Background Technology

[0002] With the continuous development of integrated circuit and radio frequency electronics technologies, on-chip variable resistors, due to their ability to dynamically adjust resistance, have demonstrated key application value in signal conditioning, impedance matching, and power consumption optimization, becoming an important technological direction for improving system integration and performance. In existing circuits, external series discrete resistors are typically used to achieve resistance adjustment; however, this method suffers from significant drawbacks such as large device size, slow response speed, and low integration, making it difficult to meet the demands of modern high-density, high-response integrated systems. Summary of the Invention

[0003] This application aims to at least partially address one of the technical problems in the related art.

[0004] Therefore, the first objective of this invention is to provide an on-chip variable resistor device structure and electronic device.

[0005] To achieve the above objectives, a first aspect of this application provides an on-chip variable resistor device structure, comprising: Substrate; A nitride epitaxial layer is formed on the substrate, including a channel layer and a barrier layer stacked thereon; the channel layer is formed on the substrate, and the barrier layer is formed on the side of the channel layer away from the substrate and contacts the surface of the channel layer to form a heterojunction interface; An electrode structure layer is formed on the nitride epitaxial layer and includes a first electrode and a second electrode that are spaced apart from each other. A gate structure layer is formed between the first electrode and the second electrode, including a first semiconductor layer formed on the barrier layer, a third electrode formed on the first semiconductor layer, and a partition trench extending along a first direction and / or a second direction to connect the first electrode and the second electrode, and to divide the first semiconductor layer into a plurality of portions along the first direction and / or the second direction; wherein the first direction and the second direction are orthogonal, and the orthogonal plane is parallel to the direction of the substrate surface.

[0006] Optionally, the vertical projection of the dividing groove on the barrier layer is one of a strip shape, a ring shape, a serpentine shape, or a broken line shape.

[0007] Optionally, the dividing groove is a serpentine dividing groove extending along the first direction, and the first electrode and the second electrode are electrically connected through the two ends of the serpentine dividing groove extending along the first direction.

[0008] Optionally, the partition groove is a plurality of interconnected annular partition grooves, and the first electrode and the second electrode are electrically connected through the two ends of the annular partition grooves extending along the first direction.

[0009] Optionally, the dividing groove is a plurality of intersecting strip dividing grooves; the first electrode is located at the center of the intersection of the strip dividing grooves, and the second electrode is arranged in a ring around the periphery of the first electrode and is electrically connected to the first electrode through the strip dividing groove.

[0010] Optionally, the first semiconductor layer is formed from P-type doped gallium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, or indium aluminum gallium nitride.

[0011] Optionally, the nitride epitaxial layer further includes a nucleation layer and a buffer layer sequentially stacked between the substrate and the channel layer; wherein, The nucleation layer is formed from aluminum nitride, the buffer layer is formed from aluminum gallium nitride or gallium nitride, the channel layer is formed from undoped gallium nitride, and the barrier layer is formed from aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride.

[0012] The substrate is formed from a heteroepitaxial substrate or a homoepitaxial substrate; wherein the heteroepitaxial substrate includes one of silicon, diamond, sapphire, gallium arsenide or silicon carbide, and the homoepitaxial substrate includes gallium nitride.

[0013] To achieve the above objectives, a second aspect of this application provides an electronic device including the on-chip variable resistor device structure described in the first aspect.

[0014] Optionally, the number of on-chip variable resistor device structures may include multiple structures, and the multiple on-chip variable resistor device structures may be connected in series and / or in parallel to form an adjustable programmable resistor network.

[0015] The on-chip variable resistor device structure and electronic device provided in this application have at least the following beneficial effects: This application provides an on-chip variable resistor device structure and electronic device, including a substrate, a nitride epitaxial layer formed on the substrate, an electrode structure layer and a gate structure layer formed on the nitride epitaxial layer. The electrode structure layer includes a first electrode and a second electrode. The nitride epitaxial layer includes a channel layer and a barrier layer for forming a heterojunction interface. The gate structure layer includes a first semiconductor layer and a third electrode stacked on the barrier layer, and a separator trench formed in the first semiconductor layer. By adjusting the extension path and structural parameters of the separator trench on the barrier layer, combined with the applied voltage of the third electrode, dynamic control of the concentration, distribution and conductive channels of the two-dimensional electron gas at the heterojunction interface can be achieved. This enables wide-range, high-precision dynamic adjustment of the on-resistance of the on-chip resistor device structure, meeting the technical requirements of high-performance integrated systems for on-chip variable resistors, and has significant application value.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a cross-sectional schematic diagram of an on-chip variable resistor device structure according to an embodiment of this application.

[0018] Figure 2 This is a top view schematic diagram of a first type of on-chip variable resistor device structure according to an embodiment of this application.

[0019] Figure 3 This is a top view schematic diagram illustrating a second on-chip variable resistor device structure according to an embodiment of this application.

[0020] Figure 4 This is a top view schematic diagram illustrating a third on-chip variable resistor device structure according to an embodiment of this application.

[0021] Figure 5 This is a schematic diagram showing the change curve of the on-resistance under dynamic voltage according to an embodiment of this application.

[0022] 100 Substrate; 210 Nucleation layer; 220 Buffer layer; 230 Channel layer; 240 Barrier layer; 250 First dielectric layer; 310 First electrode; 320 Second electrode; 410 First semiconductor layer; 420 Third electrode; 430 Separator trench. Detailed Implementation

[0023] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0024] In traditional circuits, resistance adjustment is typically achieved using external series discrete resistors. However, this method has significant drawbacks, such as large size, slow response speed, and low integration density, making it difficult to meet the needs of modern high-density, high-response integrated systems.

[0025] To realize on-chip variable resistor functionality, this application provides an on-chip variable resistor device structure. Based on the two-dimensional electron gas (2DEG) characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs), a first semiconductor layer of P-type nitride is formed on a barrier layer. The extension path of the first semiconductor layer 410 on the barrier layer is used to control the formation path of the conductive channel composed of 2DEG, thereby controlling the on-resistance threshold of the channel layer 230. Furthermore, by linearly controlling the voltage of the third electrode disposed on the first semiconductor layer, the concentration of 2DEG in the conductive channel is controlled, thereby controlling the on-off state of the conductive channel. This achieves wide-range, high-precision, and high-stability dynamic linear control of the on-chip resistor, meeting the technical requirements of high-performance integrated systems for on-chip variable resistors.

[0026] According to a first aspect of this application, an on-chip variable resistor device structure is provided, such as... Figures 1-4 As shown, the structure includes: a substrate 100; a nitride epitaxial layer formed on the substrate 100; an electrode structure layer and a gate structure layer formed on the nitride epitaxial layer.

[0027] A nitride epitaxial layer is formed on the substrate 100, including a nucleation layer 210, a buffer layer 220, a channel layer 230 and a barrier layer 240 stacked sequentially from bottom to top. The barrier layer 240 is formed on the side of the channel layer 230 away from the substrate 100 and is in contact with the surface of the channel layer 230 to form a heterojunction interface.

[0028] The electrode structure layer is formed on the nitride epitaxial layer and includes a first electrode 310 and a second electrode 320 disposed at intervals.

[0029] A gate structure layer is formed between the first electrode 310 and the second electrode 320, including a first semiconductor layer 410 formed on the barrier layer 240, a third electrode 420 formed on the first semiconductor layer 410, and a partition trench 430 extending along a first direction and / or a second direction to connect the first electrode 310 and the second electrode 320, and to divide the first semiconductor layer 410 into multiple portions along the first direction and / or the second direction.

[0030] For ease of description, the X direction in the figure can be designated as the first direction, and the Y direction in the figure can be designated as the second direction. The first direction and the second direction are orthogonal, and the orthogonal plane is parallel to the direction of the substrate 100 surface.

[0031] It is understood that this application, by forming a partition trench 430 on the barrier layer 240, and extending the partition trench 430 along the first direction and / or the second direction, connects the first electrode 310 and the second electrode 320, and divides the first semiconductor layer 410 into multiple portions along the first direction and / or the second direction, the structural changes of the partition trench 430 directly affect the space depletion range of the 2DEG at the heterojunction interface formed between the channel layer 230 and the barrier layer 240 by the first semiconductor layer 410, thereby affecting the formation range of the conductive channel. Furthermore, by adjusting the length, number, or width of the partition trench 430 extending along the first direction and / or the second direction, the coverage area and distribution of each portion of the first semiconductor layer 410 on the barrier layer 240 can be changed, thereby affecting the maximum threshold of the conductive channel's on-resistance, which is also the maximum threshold of the on-resistance of the channel layer 230. For ease of description, this will be referred to as on-resistance below.

[0032] The conductive channel is essentially formed by 2DEGs at the heterojunction interface between the channel layer 230 and the barrier layer 240. The magnitude of the on-resistance is essentially determined by the areal concentration of 2DEGs at the heterojunction interface within the conductive channel, and changes in the 2DEG areal concentration directly affect the on-resistance. Specifically, the lower the 2DEG areal concentration at the heterojunction interface within the conductive channel, the fewer the conductive carriers. When the areal concentration is reduced to its minimum, the conductivity of the conductive channel is weakest, and the on-resistance reaches its maximum threshold. Conversely, an increase in areal concentration enhances the fundamental conductivity of the conductive channel, thus reducing the on-resistance.

[0033] like Figure 5 As shown, when a linearly varying voltage is applied to the third electrode 420, the voltage drop applied to the third electrode 420 can regulate the dynamic distribution of holes in the first semiconductor layer 410, thereby adjusting the surface concentration of 2DEG at the heterojunction interface within the coverage area of ​​the first semiconductor layer 410.

[0034] Therefore, if a positive bias voltage that increases linearly or a negative bias voltage that decreases linearly is applied to the third electrode 420, the holes in the first semiconductor layer 410 will be pushed to the contact interface between the first semiconductor layer 410 and the third electrode 420, and the depletion effect of 2DEG at the heterojunction interface below will be linearly weakened, thereby causing the 2DEG surface concentration to increase linearly and the on-resistance to decrease linearly. This is equivalent to gradually increasing the 2DEG formation surface concentration in the heterojunction interface and making the on-resistance reach the minimum threshold.

[0035] If the voltage applied to the third electrode 420 is a linearly decreasing positive bias voltage or a linearly increasing negative bias voltage, the depletion effect of the first semiconductor layer 410 on the 2DEG at the heterojunction interface below it is linearly enhanced, which in turn leads to a linear decrease in the 2DEG surface concentration and a linear increase in the on-resistance. This is equivalent to gradually reducing the 2DEG concentration and range within the heterojunction interface until the 2DEG formation range is limited to the area covered by the separator trench 430, and the on-resistance reaches the maximum threshold.

[0036] Furthermore, the maximum threshold of the on-resistance can be controlled through the shape design and size optimization of the separator 430. The control method can be to extend the total extension length of the separator 430, or reduce the width of a single segment of the separator 430, or reduce the spacing between adjacent slots, so that the effective conductive path of the 2DEG is forced to be lengthened and the effective width is forced to be compressed, thereby requiring the transmission path of the 2DEG to extend in a detour along the separator 430.

[0037] The effect of variations in the 2DEG propagation path on the maximum on-resistance threshold follows geometric constraints. The longer the meandering propagation path and the narrower the effective width, the greater the geometric loss in 2DEG propagation. In this case, even if the 2DEG surface concentration is minimized, the 2DEG still needs to overcome scattering and propagation resistance over a longer distance, ultimately pushing the maximum on-resistance threshold further up. Conversely, shortening the propagation path length and increasing the effective width can reduce the geometric loss in 2DEG propagation, thus lowering the maximum on-resistance threshold.

[0038] In other words, by adjusting the structural parameters of the separator 430, this application can limit the adjustable range of the maximum threshold of the on-resistance. Combined with the linear voltage applied to the third electrode 420, continuous and fine adjustment of the on-resistance can be achieved, ultimately achieving wide-range, high-precision and excellent linearity on-chip dynamic control of the resistor, meeting the flexible resistance adjustment requirements of high-performance integrated systems.

[0039] In some embodiments, the vertical projection of the partition groove 430 onto the barrier layer 240 is one of a strip, a ring, a snake, or a broken line.

[0040] It is understood that the separator 430 has a width W1 and a length L1. The length L1 of the separator 430 represents the total extension length of the separator 430, and the width W1 of the separator 430 represents the width of a single segment of the separator 430 along its extension length. With the same length L1, the smaller the width W1 of the separator 430, the larger the maximum threshold of the on-resistance; correspondingly, with the same trench width, the longer the length of the separator 430, the larger the maximum threshold of the on-resistance.

[0041] As an example, such as Figure 2 As shown, the partition groove 430 can be a serpentine partition groove 430 extending along the first direction, and the first electrode 310 and the second electrode 320 are spaced apart from each other along the first direction and are electrically connected through the two ends of the serpentine partition groove 430 extending along the first direction.

[0042] Since the first electrode 310 and the second electrode 320 are connected at both ends along the first direction through the serpentine partition groove 430, the structural morphology of the serpentine partition groove 430 extending along the first direction will directly affect the maximum threshold of the conduction resistance between the first electrode 310 and the second electrode 320 when no voltage is applied to the third electrode 420.

[0043] Specifically, the serpentine divider 430, through its meandering path, extends along the first direction while simultaneously expanding its lateral coverage in the second direction. This results in a significantly larger total coverage area of ​​the serpentine divider 430 on the barrier layer 240 compared to a straight divider 430 of the same length. Consequently, the depletion range of the 2DEG within the heterojunction interface below is reduced by the first semiconductor layer. However, the increased total extension length of the serpentine divider 430 forces a longer effective conductive path for the 2DEG, leading to increased geometric losses in 2DEG transmission and ultimately pushing the maximum threshold of the on-resistance to a further increase.

[0044] Meanwhile, since the total extension length of the serpentine partition groove 430 along the meandering path is much greater than the straight-line distance between the first electrode 310 and the second electrode 320, and while the length of the serpentine partition groove 430 increases, the width of the single-segment groove is adjusted, which can not only further adjust the occupied area of ​​the first semiconductor layer 410 on the surface of the barrier layer 240, but also further adjust the effective width of the 2DEG extension path, thereby improving the linearity of the maximum threshold adjustment of the on-resistance.

[0045] Furthermore, the two ends of the serpentine partition groove 430 are connected to the first electrode 310 and the second electrode 320, forming a serpentine conductive path between the electrodes. This can help stabilize the voltage distribution between the electrodes. That is, when a voltage is applied to the third electrode 420, this serpentine partition groove 430 can make the hole distribution in each part of the first semiconductor layer 410 more uniform, thereby making the change of 2DEG concentration more continuous, and ultimately achieving wide-range, high-precision and linearly stable on-chip resistor dynamic control.

[0046] As an example, such as Figure 3 As shown, the partition groove 430 can also be a plurality of interconnected annular partition grooves 430, the first electrode 310 and the second electrode 320 are spaced apart from each other along the first direction, and the two ends of the annular partition groove 430 extending along the first direction are electrically connected.

[0047] Multiple interconnected annular separators 430, with their unique geometry, can significantly expand the coverage area of ​​the separators 430 on the barrier layer 240, significantly reduce the coverage area of ​​the first semiconductor layer 410 on the barrier layer 240, reduce the depletion range of the underlying 2DEG, and enable more stable conductive channels to be formed at the heterojunction interface, thereby reducing the maximum threshold of the on-resistance and laying the foundation for a wide range of resistance adjustment.

[0048] Meanwhile, multiple interconnected annular partitions 430 divide the first semiconductor layer 410 into more dispersed island-like portions. This can increase the number of 2DEG conductive channels between the first electrode 310 and the second electrode 320 without significantly increasing the total extension length of the 2DEG conductive channels. This allows more stable conductive channels to be formed at the heterojunction interface, thereby reducing the maximum threshold of the on-resistance.

[0049] Furthermore, the number, width, and spacing of the annular separators 430 further affect the maximum threshold of the on-resistance. For example, the more annular separators there are, the finer the division of the first semiconductor layer 410, resulting in higher precision in adjusting the maximum threshold of the on-resistance. The variation in the width of the annular separators 430 affects the initial resistance and the stability of the current path; the spacing between multiple annular separators 430 determines the smoothness or stepped feel of the depletion.

[0050] As an example, such as Figure 4 As shown, the partition groove 430 can also be a plurality of intersecting strip partition grooves 430; the first electrode 310 is located at the center of the intersecting strip partition grooves 430, and the second electrode 320 is arranged in a ring around the periphery of the first electrode 310 and is electrically connected to the first electrode 310 through the plurality of strip partition grooves 430.

[0051] Multiple interlocking strip-shaped dividers 430 form a uniformly distributed coverage area between the first electrode 310 and the second electrode 320. This not only significantly expands the coverage area of ​​the dividers 430 on the barrier layer 240, but also precisely compresses the remaining space of the first semiconductor layer 410, dividing it into multiple fragmented parts around the central first electrode 310. This reduces the local over-depletion of the 2DEG by the first semiconductor layer 410, allowing the 2DEG conductive channels to be uniformly distributed along the gaps of the interlocking dividers 430. This enables the formation of more stable conductive channels at the heterojunction interface between the first electrode 310 and the second electrode 320, reducing the maximum on-resistance threshold while ensuring the stability of current transmission.

[0052] Meanwhile, the interlaced strip-shaped partitions 430 also construct multiple parallel and extended connection paths between the first electrode 310 and the second electrode 320. Compared with a single path, this can more evenly distribute the current density between the first electrode 310 and the second electrode 320, making the voltage gradient change from the first electrode 310 to the annular second electrode 320 smoother, avoiding 2DEG concentration fluctuations caused by local voltage concentration, and providing a stable electric field environment for voltage regulation of the third electrode 420.

[0053] Furthermore, adjusting parameters such as the number and width of the separator slots 430 allows for finer adjustment of the maximum threshold of the on-resistance. The greater the number of slots, the wider the slot width, and the finer the division of the first semiconductor layer 410, the higher the resistance adjustment accuracy. This structural design, through multi-dimensional collaboration, achieves wide-range, high-precision, and uniformly stable dynamic control of the on-chip variable resistor, adapting to the flexible application requirements of high-performance integrated systems.

[0054] It should be noted that, Figure 2 Although it is shown that the first electrode 310 and the second electrode 320 can penetrate the barrier layer 240 and contact the channel layer 230, in practical applications, the first electrode 310 and the second electrode 320 may only penetrate the first insulating dielectric layer, but not the barrier layer 240. This application embodiment does not limit this.

[0055] In addition, such as Figure 2 and Figure 3 As shown, in practical applications, due to limitations in process precision, the first electrode 310 and the second electrode 320 may be symmetrically distributed on both sides of the third electrode 420, or they may not be completely symmetrically distributed on both sides of the gate structure layer. That is, the first electrode 310 and the second electrode 320 can be basically symmetrically distributed on both sides of the gate structure layer to achieve the functions of conduction and blocking.

[0056] Furthermore, the first electrode 310 and the second electrode 320 can be either a source electrode or a drain electrode, for example, the first electrode 310 is a source electrode and the second electrode 320 is a drain electrode; or, the first electrode 310 is a drain electrode and the second electrode 320 is a source electrode; this application does not impose any special restrictions on the specific arrangement of the first electrode 310 and the second electrode 320.

[0057] In some embodiments, the substrate 100 may be formed from heteroepitaxial materials such as silicon, diamond, sapphire gallium arsenide (GaAs), or silicon carbide (SiC), or from GaN homoepitaxial substrate material; the nucleation layer 210 may be formed from aluminum nitride (AlN); the buffer layer 220 may be formed from high-resistivity GaN or from aluminum gallium nitride (AlGaN); the channel layer 230 may be formed from unintentionally doped GaN; and the barrier layer 240 may be formed from aluminum gallium nitride (AlGaN) or from aluminum nitride (InAlN) or other aluminum nitrides, so that the barrier layer 240 can form a heterojunction with the channel layer 230.

[0058] And, as Figure 1 As shown, the nitride epitaxial layer composed of nucleation layer 210, buffer layer 220, channel layer 230 and barrier layer 240 can also be the nitride epitaxial layer of HEMT device. The nitride epitaxial layer can be a nitride epitaxial layer formed by group III to V nitrides.

[0059] The first semiconductor layer 410 can be formed from P-type nitrides, such as GaN, AlGaN, indium gallium nitride (InGaN), InAlN, or indium aluminum gallium nitride (InAlGaN). The specific material composition of the first semiconductor layer 410 is not limited in this embodiment. Exemplarily, the first semiconductor layer 410 can be formed from P-type GaN. In another example, the first semiconductor layer 410 can also be formed from P-type Al... x Ga 1-x N is generated, where 0 ≤ x ≤ 1.

[0060] A first dielectric layer 250 is also formed on the barrier layer 240. The first dielectric layer 250 is formed on the surface of the barrier layer 240 away from the substrate 100 and covers the exposed surface of the barrier layer 240 except for the first semiconductor layer 410, i.e., the surface of the barrier layer 240 exposed by the separator trench 430, for passivation of the surface of the barrier layer 240 and for metal separation between the barrier layer 240 and the subsequently formed third electrode 420. Exemplarily, the first dielectric layer 250 can be formed of insulating dielectric materials such as silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon oxide (SiO2).

[0061] The first electrode 310 and the second electrode 320 can both be composed of one or more alloys of conductive metals such as titanium, aluminum, nickel, gold, platinum, iridium, molybdenum, tantalum, niobium, cobalt, zirconium, and tungsten, and the first electrode 310 and the second electrode 320 form an ohmic contact with the nitride epitaxial layer. The third electrode 420 can be composed of one or more alloys of conductive metals such as platinum, iridium, nickel, gold, molybdenum, palladium, selenium, beryllium, and Ti, or polycrystalline silicon, and the third electrode 420 forms an ohmic contact or a Schottky contact with the first semiconductor layer 410.

[0062] Furthermore, an insertion layer can be provided between the barrier layer 240 and the channel layer 230. The insertion layer is made of AlN, GaN / AlN superlattice or low-doped GaN material, and the thickness is designed to be 0.7nm~1nm. Its core function is to optimize the surface concentration and electron mobility of 2DEG by controlling the polarization coupling strength and interface characteristics of the heterojunction.

[0063] It should be noted that the variable resistor device structure provided in this application is fully compatible with GaN monolithic integration technology, including but not limited to adjustable resistor applications in monolithic microwave integrated circuits (MMICs) or power integrated circuits (Power ICs). The embodiments of this application do not impose any special limitations on the specific application of the above-described variable resistor device structure.

[0064] According to a second aspect of this application, an electronic device is provided, which includes the on-chip variable resistor device structure described in the first aspect above.

[0065] In some embodiments, the number of on-chip variable resistor device structures includes multiple structures, and the multiple on-chip variable resistor device structures are connected in series and / or in parallel to form an adjustable programmable resistor network.

[0066] It should be noted that the electronic devices described in this application include, but are not limited to, different types of user equipment or terminal equipment such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices. These electronic devices can also be network equipment such as base stations. This application does not impose any special limitations on the specific form of the aforementioned electronic devices.

[0067] In summary, this application provides an on-chip variable resistor device structure and electronic device, including a substrate 100, a nitride epitaxial layer formed on the substrate 100, an electrode structure layer and a gate structure layer formed on the nitride epitaxial layer. The electrode structure layer includes a first electrode 310 and a second electrode 320. The nitride epitaxial layer includes a channel layer 230 and a barrier layer 240 for forming a heterojunction interface. The gate structure layer includes a first semiconductor layer 410 and a third electrode 420 stacked on the barrier layer 240, and a separator trench 430 formed in the first semiconductor layer 410. By adjusting the extension path and structural parameters of the separator trench 430 on the barrier layer 240, combined with the applied voltage of the third electrode 420, dynamic control of the concentration, distribution and conductive channels of the two-dimensional electron gas at the heterojunction interface can be achieved, thereby achieving wide-range, high-precision dynamic adjustment of the on-chip resistor, meeting the technical requirements of high-performance integrated systems for on-chip variable resistors, and has significant application value.

[0068] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0069] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An on-chip variable resistor device structure, characterized in that, include: Substrate; A nitride epitaxial layer is formed on the substrate, including a channel layer and a barrier layer stacked thereon; the channel layer is formed on the substrate, and the barrier layer is formed on the side of the channel layer away from the substrate and contacts the surface of the channel layer to form a heterojunction interface; An electrode structure layer is formed on the nitride epitaxial layer and includes a first electrode and a second electrode that are spaced apart from each other. A gate structure layer is formed between the first electrode and the second electrode, including a first semiconductor layer formed on the barrier layer, a third electrode formed on the first semiconductor layer, and a partition trench extending along a first direction and / or a second direction to connect the first electrode and the second electrode, and to divide the first semiconductor layer into a plurality of portions along the first direction and / or the second direction; wherein the first direction and the second direction are orthogonal, and the orthogonal plane is parallel to the direction of the substrate surface.

2. The on-chip variable resistor device structure according to claim 1, characterized in that, The vertical projection of the dividing groove on the barrier layer is one of the following: bar shape, ring shape, serpentine shape, or polygonal shape.

3. The on-chip variable resistor device structure according to claim 2, characterized in that, The dividing groove is a serpentine dividing groove extending along the first direction, and the first electrode and the second electrode are electrically connected through the two ends of the serpentine dividing groove extending along the first direction.

4. The on-chip variable resistor device structure according to claim 2, characterized in that, The partition groove is a plurality of interconnected annular partition grooves, and the first electrode and the second electrode are electrically connected through the two ends of the annular partition grooves extending along the first direction.

5. The on-chip variable resistor device structure according to claim 2, characterized in that, The dividing groove consists of multiple intersecting strip-shaped dividing grooves; the first electrode is located at the center of the intersection of the strip-shaped dividing grooves, and the second electrode is arranged in a ring around the periphery of the first electrode and is electrically connected to the first electrode through the strip-shaped dividing grooves.

6. The on-chip variable resistor device structure according to claim 1, characterized in that, The first semiconductor layer is formed from P-type doped gallium nitride, aluminum gallium nitride, indium gallium nitride, indium aluminum nitride, or indium aluminum gallium nitride.

7. The on-chip variable resistor device structure according to claim 1, characterized in that, The nitride epitaxial layer further includes a nucleation layer and a buffer layer sequentially stacked between the substrate and the channel layer; wherein... The nucleation layer is formed from aluminum nitride, the buffer layer is formed from aluminum gallium nitride or gallium nitride, the channel layer is formed from undoped gallium nitride, and the barrier layer is formed from aluminum gallium nitride, aluminum indium nitride, or aluminum indium gallium nitride.

8. The on-chip variable resistor device structure according to claim 1, characterized in that, The substrate is formed from a heteroepitaxial substrate or a homoepitaxial substrate. The heteroepitaxial substrate includes one of silicon, diamond, sapphire, gallium arsenide, or silicon carbide. The homoepitaxial substrate includes gallium nitride.

9. An electronic device, characterized in that, Includes the on-chip variable resistor device structure as described in any one of claims 1 to 8.

10. The electronic device according to claim 9, characterized in that, The number of on-chip variable resistor device structures includes multiple structures, and the multiple on-chip variable resistor device structures are connected in series and / or in parallel to form an adjustable programmable resistor network.

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