Preparation method for improving gate insulation layer and input capacitance of semiconductor device

Abstract

The invention relates to the technical field of semiconductor device manufacturing, and discloses a preparation method for improving a gate insulating layer and an input capacitance of a semiconductor device, which comprises the following steps of: thermally oxidizing a silicon carbide substrate to generate a first silicon oxide film, depositing an undoped polycrystalline silicon layer on the surface of the first silicon oxide film, and photoetching and etching to form a patterned polycrystalline silicon layer; and performing a high-temperature oxidation process, completely converting the patterned polycrystalline silicon layer into silicon dioxide, oxidizing the silicon carbide substrate in an uncovered area, forming a gate insulation layer with a step thickness, preparing a gate structure on the surface of the gate insulation layer, depositing an interlayer dielectric layer, and etching to form a contact hole. Damage of reaction gas to the surface of the silicon carbide substrate in the deposition process is blocked through the first silicon oxide thin film, input capacitance is reduced and low on-resistance is maintained through a step thickness structure formed by oxidation of the non-doped polycrystalline silicon layer, diffusion of doped impurities is avoided, and interface state density and gate leakage current are reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a method for improving the preparation of the gate insulating layer and input capacitance of a semiconductor device. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor (MOS) field-effect transistors (FETs) are characterized by high voltage resistance, high temperature resistance, and low high-frequency loss. FETs are widely used in power electronics. Reducing on-resistance and input capacitance are key objectives for improving FET performance. In conventional planar gate structures, while reducing the gate insulating layer thickness helps lower on-resistance, it also increases the reverse transfer capacitance between the gate and drain. Furthermore, reducing the gate insulating layer thickness lowers its breakdown voltage and reliability. Conversely, increasing the gate insulating layer thickness reduces reverse transfer capacitance and improves gate withstand voltage, but it also increases channel resistance, thereby increasing the conduction loss of the semiconductor device.

[0003] To resolve the conflict between on-resistance and input capacitance, stepped-thickness gate insulating layer (GIL) structures have been applied in semiconductor device design. However, existing methods for fabricating stepped-thickness GILs involve either directly depositing a polysilicon layer on a silicon carbide substrate or etching the substrate surface. During chemical vapor deposition of the polysilicon layer, the direct contact of the reactant gas with the silicon carbide substrate surface causes lattice damage, leading to an increase in the interface state density at the GIL-Si substrate interface. Furthermore, existing processes use doped polysilicon as a sacrificial layer for oxidation to form a thicker oxide layer. During high-temperature oxidation, dopants can easily diffuse into the interior and interface of the GIL, reducing the density of the GIL and increasing gate leakage current. The lattice damage and impurity diffusion problems on the silicon carbide substrate surface limit the threshold voltage stability and long-term reliability of silicon carbide semiconductor devices. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an improved method for fabricating the gate insulating layer and input capacitance of semiconductor devices. This method solves the problems of mutual constraints between reducing on-resistance and input capacitance in existing semiconductor devices, as well as the problems of increased interface state density due to direct contact of reactant gases with the silicon carbide substrate surface and increased leakage current in the gate insulating layer due to the diffusion of doped impurities.

[0005] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a method for improving the fabrication of the gate insulating layer and input capacitance of a semiconductor device, comprising the following steps: S1. Select a silicon carbide substrate and clean it. Perform thermal oxidation treatment on the cleaned silicon carbide substrate to generate a first silicon oxide film on the surface of the silicon carbide substrate. S2. Deposit an undoped polycrystalline silicon layer on the surface of the first silicon oxide thin film; S3. Spin-coat positive photoresist onto the surface of the undoped polysilicon layer, form a preset mask pattern by exposure and development, remove the undoped polysilicon layer in the area that does not need to be retained by etching process, remove the positive photoresist, and retain the undoped polysilicon layer in the preset area to obtain a silicon carbide substrate with a patterned polysilicon layer. S4. A high-temperature oxidation process is performed on the silicon carbide substrate with a patterned polysilicon layer to form a gate insulating layer with stepped thickness. S5. Deposit a doped polysilicon layer on the surface of the gate insulating layer, define the pattern through photolithography, and perform dry etching on the doped polysilicon layer to form the gate structure. S6. A silicon dioxide layer is deposited on the gate structure and the surface of the silicon carbide substrate as an interlayer dielectric layer. The contact hole pattern is defined by photolithography and the contact hole is formed by etching to obtain a semiconductor device.

[0006] By adopting the above technical solution, a first silicon oxide thin film is used as a buffer layer to protect the silicon carbide surface, and a stepped-thickness gate insulating layer is formed by oxidizing a patterned undoped polysilicon layer. This reduces the gate input capacitance while ensuring low on-resistance and high interface quality.

[0007] Preferably, in step S1, the first silicon oxide film acts as a physical barrier layer to isolate the surface of the silicon carbide substrate from the reaction environment in step S2. During the chemical vapor deposition of an undoped polycrystalline silicon layer, the silicon source gas has reducing properties at high temperatures. If the silicon source gas directly contacts the silicon carbide substrate, it will etch the surface of the silicon carbide substrate and introduce lattice damage. The first silicon oxide film avoids direct contact between the silicon source gas and the surface of the silicon carbide substrate, prevents the destruction of the lattice integrity of the silicon carbide substrate surface, reduces the interface state density at the interface between the final gate insulating layer and the silicon carbide substrate, reduces the scattering of charge carriers at the interface, and improves the threshold voltage stability of the semiconductor device.

[0008] Preferably, in step S2, depositing an undoped polysilicon layer avoids the introduction of impurity elements. The undoped polysilicon layer ensures that the silicon dioxide layer generated during the high-temperature oxidation process in step S4 has high purity and high density. If a doped polysilicon layer is used, during the high-temperature oxidation process, the dopant will diffuse and enter the generated silicon dioxide layer and the interface between the silicon dioxide layer and the silicon carbide substrate. The dopant, as an impurity center, will reduce the breakdown field strength of the silicon dioxide layer and provide a leakage path. Using an undoped polysilicon layer as a sacrificial material to be oxidized ensures that the insulation performance of the first thickness region converted from polysilicon is close to that of thermally grown silicon dioxide.

[0009] Preferably, in step S4, the high-temperature oxidation process utilizes the volume expansion characteristics of silicon material during oxidation and the difference in oxidation rate to form a stepped structure. The high-temperature oxidation process completely depletes the undoped polysilicon layer retained in the preset region and converts it into silicon dioxide. At the same time, it oxidizes the surface of the silicon carbide substrate in the region not covered by the undoped polysilicon layer to generate silicon dioxide. Since the volume expands when polysilicon is converted into silicon dioxide, and the oxidation rate of polysilicon is higher than that of silicon carbide, a first thickness region with a larger thickness is formed in the preset region. In the region not covered by the undoped polysilicon layer, a second thickness region with a smaller thickness is formed directly by oxidation of the silicon carbide substrate. The first thickness region is located above the drift region of the semiconductor device. The larger physical thickness reduces the reverse transfer capacitance between the gate and the drain. The second thickness region is located above the channel region of the semiconductor device. The smaller physical thickness enhances the gate voltage's control over the channel current and maintains a lower specific on-resistance. At the same time, the long-term high-temperature process in step S4 thermally annealed the stress generated in steps S1 to S3 to repair it.

[0010] Preferably, in step S1, the cleaning is standard RCA cleaning, and the thermal oxidation treatment is carried out in an oxygen atmosphere at an oxygen flow rate of 8-12 slm at 950-1050 degrees Celsius for 10-20 minutes, and the thickness of the first silicon oxide film is 10-50 angstroms.

[0011] Preferably, in step S2, the deposition of the undoped polycrystalline silicon layer is carried out using silane as the silicon source gas, with the silane flow rate controlled at 150-250 sccm, at a temperature of 600-640 degrees Celsius and a pressure of 150-250 mTorr, and the thickness of the undoped polycrystalline silicon layer is 400-500 angstroms.

[0012] Preferably, in step S3, the specific method for forming the preset mask pattern is as follows: a 1.5-2.5 micrometer thick layer of positive photoresist is spin-coated on the surface of an undoped polysilicon layer at a rotation speed of 2500-3500 rpm, and the preset mask pattern is formed by exposure and development.

[0013] Preferably, in step S3, the etching process is a dry etching process, specifically: sulfur hexafluoride is used as the etching gas, the sulfur hexafluoride flow rate is controlled at 40-60 sccm, and the positive photoresist is removed by using an oxygen plasma process.

[0014] Preferably, in step S4, the high-temperature oxidation process is carried out in an oxygen atmosphere, with the oxygen flow rate controlled at 8-12 slm, and the oxidation treatment is carried out at a temperature of 900-1000 degrees Celsius for 120-180 minutes.

[0015] Preferably, in step S4, the gate insulating layer is divided into a first thickness region and a second thickness region. The thickness of the first thickness region is 900-1100 angstroms, and the thickness of the second thickness region is 350-450 angstroms. The gate insulating layer has a stepped gate structure.

[0016] Preferably, in step S5, the deposition of the doped polysilicon layer is carried out by a low-pressure chemical vapor deposition process, with silane at a flow rate of 150-250 sccm and phosphine at a flow rate of 40-60 sccm, and the thickness of the doped polysilicon layer is 3500-4500 angstroms; chlorine gas is used as the etching gas for dry etching of the doped polysilicon layer.

[0017] Preferably, in step S6, trifluoromethane is used as the etching gas to form the contact hole.

[0018] This invention provides a method for improving the fabrication of the gate insulating layer and input capacitance of a semiconductor device. It has the following beneficial effects: 1. This invention generates a first silicon oxide film on the surface of a silicon carbide substrate before depositing an undoped polysilicon layer, which serves as a buffer layer to protect the silicon carbide surface. High-purity undoped polysilicon is used as a sacrificial layer to be converted into silicon dioxide, avoiding the excessive accumulation and residue of carbon elements at the interface caused by direct long-term thick oxidation of the silicon carbide substrate. This reduces the interface state density and improves the channel mobility and high-temperature gate bias reliability of semiconductor devices.

[0019] 2. This invention achieves complete depletion oxidation of a patterned undoped polysilicon layer, utilizing the volume expansion characteristics of polysilicon when it is converted into silicon dioxide to form a first thickness region with a larger thickness above the drift region of the semiconductor device, and a second thickness region with a smaller thickness above the channel region of the semiconductor device. The first thickness region reduces the input capacitance of the semiconductor device, while the second thickness region maintains the low on-resistance of the semiconductor device.

[0020] 3. By using an undoped polysilicon layer as the silicon source material for forming the first thickness region of the gate insulating layer, the undoped polysilicon layer avoids the diffusion of doped impurities into the gate insulating layer during high-temperature oxidation, prevents doped impurities from forming defect centers or leakage paths in the gate insulating layer, ensures the compactness of the gate insulating layer, and reduces the gate leakage current of the semiconductor device. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to comparative examples and test cases. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. Examples 1-3: Example 1: This embodiment provides a method for improving the fabrication of the gate insulating layer and input capacitance of a semiconductor device, including the following steps: S1. Select silicon carbide substrate as the starting material for semiconductor device fabrication. Perform standard RCA cleaning on the silicon carbide substrate to remove organic matter, oxides and metal ion contaminants from the surface. Place the cleaned silicon carbide substrate in a high-temperature oxidation furnace tube and perform thermal oxidation treatment at 1000 degrees Celsius for 15 minutes under an oxygen atmosphere with an oxygen flow rate of 10 slm. This will generate a first silicon oxide film with a thickness of 30 angstroms on the surface of the silicon carbide substrate, which will serve as a buffer layer for subsequent polycrystalline silicon deposition. S2. Place the silicon carbide substrate with the first silicon oxide film on it in a low-pressure chemical vapor deposition equipment, use silane as the silicon source gas, control the silane flow rate to 200 sccm, and deposit an undoped polycrystalline silicon layer with a thickness of 450 angstroms on the surface of the first silicon oxide film at a temperature of 620 degrees Celsius and a pressure of 200 mTorr. S3. A 2-micron thick photoresist layer is formed by spin-coating positive photoresist on the surface of the undoped polysilicon layer at a speed of 3000 rpm. The layer is then exposed and developed using a photolithography machine to form a preset mask pattern. Sulfur hexafluoride is used as the etching gas, and the flow rate of sulfur hexafluoride is controlled at 50 sccm. The undoped polysilicon layer in the areas that do not need to be retained is selectively removed by a dry etching process, while the undoped polysilicon layer in the preset areas (corresponding to the areas in the device design that require a thicker gate insulating layer) is retained. Subsequently, the positive photoresist is removed by an oxygen plasma process, and the substrate is cleaned with deionized water to obtain a silicon carbide substrate with a patterned polysilicon layer. S4. A silicon carbide substrate with a patterned polysilicon layer is placed in a high-temperature oxidation furnace tube for high-temperature oxidation. Oxygen is introduced and the oxygen flow rate is controlled at 10 slm. The oxidation process is carried out at 950 degrees Celsius for 120 minutes, so that the remaining undoped polysilicon layer is completely exhausted and converted into silicon dioxide. At the same time, the surface of the silicon carbide substrate in the area not covered by the polysilicon layer is also oxidized to form silicon dioxide, and finally a gate insulating layer with stepped thickness is formed. The area formed by the conversion of the undoped polysilicon layer and the oxidation of the underlying silicon carbide layer is the first thickness region with a thickness of 1000 angstroms. The area formed directly by the oxidation of the silicon carbide substrate is the second thickness region with a thickness of 400 angstroms. This forms a SplitGate structure (stepped gate structure). The first thickness region is used to reduce the gate input capacitance of the semiconductor device. S5. A 4000 angstrom-thickness doped polysilicon layer is deposited on the surface of the gate insulating layer by low-pressure chemical vapor deposition, through which silane with a flow rate of 200 sccm and phosphine with a flow rate of 50 sccm are introduced. This layer serves as the gate conductive layer. Subsequently, the pattern is defined by photolithography, and chlorine is used as the etching gas to perform dry etching on the doped polysilicon layer, forming a gate structure that simultaneously covers the first and second thickness regions. S6. A thick silicon dioxide layer is deposited on the gate structure and the surface of the silicon carbide substrate as an interlayer dielectric layer. The contact hole pattern is defined by photolithography. Trifluoromethane is used as an etching gas to form the contact holes, and the gate and source of the silicon carbide MOS device are brought out respectively, thus completing the fabrication of the semiconductor device.

[0022] Example 2: This embodiment provides a method for improving the fabrication of the gate insulating layer and input capacitance of a semiconductor device, including the following steps: S1. Select silicon carbide substrate as the starting material for preparing semiconductor devices. Perform standard RCA cleaning on the silicon carbide substrate to remove organic matter, oxides and metal ion contaminants on the surface. Place the cleaned silicon carbide substrate in a high-temperature oxidation furnace tube. Under an oxygen atmosphere, control the oxygen flow rate to 12 slm and perform thermal oxidation treatment at 1050 degrees Celsius for 20 minutes to generate a first silicon oxide film with a thickness of 50 angstroms on the surface of the silicon carbide substrate, which serves as a buffer layer for subsequent polycrystalline silicon deposition. S2. Place the silicon carbide substrate with the first silicon oxide film on it in a low-pressure chemical vapor deposition equipment, use silane as the silicon source gas, control the silane flow rate to 250 sccm, and deposit a layer of undoped polycrystalline silicon with a thickness of 500 angstroms on the surface of the first silicon oxide film at a temperature of 640 degrees Celsius and a pressure of 250 mTorr. S3. A 1.5-micron thick photoresist layer is formed by spin-coating positive photoresist on the surface of the undoped polysilicon layer at a speed of 3500 rpm. The layer is then exposed and developed using a photolithography machine to form a preset mask pattern. Sulfur hexafluoride is used as the etching gas, and the flow rate of sulfur hexafluoride is controlled at 60 sccm. The undoped polysilicon layer in the areas that do not need to be retained is selectively removed by a dry etching process, while the undoped polysilicon layer in the preset areas (corresponding to the areas in the device design that require a thicker gate insulating layer) is retained. Subsequently, the positive photoresist is removed by an oxygen plasma process, and the substrate is cleaned with deionized water to obtain a silicon carbide substrate with a patterned polysilicon layer. S4. A silicon carbide substrate with a patterned polysilicon layer is placed in a high-temperature oxidation furnace tube for high-temperature oxidation. Oxygen is introduced and the oxygen flow rate is controlled at 12 slm. The oxidation process is carried out at 1000 degrees Celsius for 150 minutes, so that the remaining undoped polysilicon layer is completely exhausted and converted into silicon dioxide. At the same time, the surface of the silicon carbide substrate in the area not covered by the polysilicon layer is also oxidized to form silicon dioxide, and finally a gate insulating layer with stepped thickness is formed. The area formed by the conversion of the undoped polysilicon layer and the oxidation of the underlying silicon carbide layer is the first thickness region with a thickness of 1100 angstroms. The area formed directly by the oxidation of the silicon carbide substrate is the second thickness region with a thickness of 450 angstroms. This forms a SplitGate structure (stepped gate structure). The first thickness region is used to reduce the gate input capacitance of the semiconductor device. S5. A doped polysilicon layer with a thickness of 4500 angstroms is deposited on the surface of the gate insulating layer by introducing silane with a flow rate of 250 sccm and phosphine with a flow rate of 60 sccm through a low-pressure chemical vapor deposition process. This layer serves as the gate conductive layer. Subsequently, the pattern is defined by a photolithography process, and chlorine gas is used as the etching gas to perform dry etching on the doped polysilicon layer to form a gate structure that simultaneously covers the first thickness region and the second thickness region. S6. A thick silicon dioxide layer is deposited on the gate structure and the surface of the silicon carbide substrate as an interlayer dielectric layer. The contact hole pattern is defined by photolithography. Trifluoromethane is used as an etching gas to form the contact holes, and the gate and source of the silicon carbide MOS device are brought out respectively, thus completing the fabrication of the semiconductor device.

[0023] Example 3: This embodiment provides a method for improving the fabrication of the gate insulating layer and input capacitance of a semiconductor device, including the following steps: S1. Select silicon carbide substrate as the starting material for semiconductor device fabrication. Perform standard RCA cleaning on the silicon carbide substrate to remove organic matter, oxides and metal ion contaminants from the surface. Place the cleaned silicon carbide substrate in a high-temperature oxidation furnace tube. Under an oxygen atmosphere, control the oxygen flow rate to 8 slm and perform thermal oxidation treatment at 950 degrees Celsius for 10 minutes to generate a first silicon oxide film with a thickness of 10 angstroms on the surface of the silicon carbide substrate, which serves as a buffer layer for subsequent polycrystalline silicon deposition. S2. Place the silicon carbide substrate with the first silicon oxide film on it in a low-pressure chemical vapor deposition equipment, use silane as the silicon source gas, control the silane flow rate to 150 sccm, and deposit an undoped polycrystalline silicon layer with a thickness of 400 angstroms on the surface of the first silicon oxide film at a temperature of 600 degrees Celsius and a pressure of 150 mTorr. S3. A 2.5-micron-thick photoresist layer is formed by spin-coating positive photoresist on the surface of the undoped polysilicon layer at a speed of 2500 rpm. The layer is then exposed and developed using a photolithography machine to form a preset mask pattern. Sulfur hexafluoride is used as the etching gas, and the flow rate of sulfur hexafluoride is controlled at 40 sccm. The undoped polysilicon layer in the areas that do not need to be retained is selectively removed by a dry etching process, while the undoped polysilicon layer in the preset areas (corresponding to the areas in the device design that require a thicker gate insulating layer) is retained. Subsequently, the positive photoresist is removed by an oxygen plasma process, and the substrate is cleaned with deionized water to obtain a silicon carbide substrate with a patterned polysilicon layer. S4. A silicon carbide substrate with a patterned polysilicon layer is placed in a high-temperature oxidation furnace tube for high-temperature oxidation. Oxygen is introduced and the oxygen flow rate is controlled at 8 slm. The oxidation process is carried out at 900 degrees Celsius for 180 minutes, so that the remaining undoped polysilicon layer is completely exhausted and converted into silicon dioxide. At the same time, the surface of the silicon carbide substrate in the area not covered by the polysilicon layer is also oxidized to form silicon dioxide, and finally a gate insulating layer with stepped thickness is formed. The area formed by the conversion of the undoped polysilicon layer and the oxidation of the underlying silicon carbide layer is the first thickness region with a thickness of 900 angstroms. The area formed directly by the oxidation of the silicon carbide substrate is the second thickness region with a thickness of 350 angstroms. This forms a SplitGate structure (stepped gate structure). The first thickness region is used to reduce the gate input capacitance of the semiconductor device. S5. A doped polysilicon layer with a thickness of 3500 angstroms is deposited on the surface of the gate insulating layer by introducing silane with a flow rate of 150 sccm and phosphine with a flow rate of 40 sccm through a low-pressure chemical vapor deposition process. This layer serves as the gate conductive layer. Subsequently, the pattern is defined by a photolithography process, and chlorine gas is used as the etching gas to perform dry etching on the doped polysilicon layer to form a gate structure that simultaneously covers the first thickness region and the second thickness region. S6. A thick silicon dioxide layer is deposited on the gate structure and the surface of the silicon carbide substrate as an interlayer dielectric layer. The contact hole pattern is defined by photolithography. Trifluoromethane is used as an etching gas to form the contact holes, and the gate and source of the silicon carbide MOS device are brought out respectively, thus completing the fabrication of the semiconductor device.

[0024] Comparative Examples 1-4: Comparative Example 1: Compared with Example 1, the difference is that steps S1, S2 and S3 are omitted. In step S4, the silicon carbide substrate that has been cleaned by RCA is directly placed in a high-temperature oxidation furnace tube and thermally oxidized at 1100 degrees Celsius in an oxygen atmosphere. The time is controlled so that a silicon dioxide layer with a uniform thickness of 400 angstroms is generated on the surface as a gate insulating layer. The remaining steps S5 to S6 are basically the same as those in Example 1, except that the gate structure defined in step S5 covers the surface of the gate insulating layer with a uniform thickness.

[0025] Comparative Example 2: Compared with Example 1, the difference is that step S3 is omitted. After depositing the undoped polysilicon layer in step S2, the high-temperature oxidation process in step S4 is performed directly, so that all the undoped polysilicon layer on the surface is retained and oxidized. Finally, a relatively thick gate insulating layer with a uniform thickness of 1000 angstroms is formed on the surface of the silicon carbide substrate. The remaining steps S5 to S6 are basically the same as in Example 1, except that the gate structure defined in step S5 covers the surface of the gate insulating layer with uniform thickness.

[0026] Comparative Example 3: Compared with Example 1, the difference is that step S1 is omitted, and in step S2, an undoped polysilicon layer is directly deposited on the surface of the silicon carbide substrate after RCA cleaning. The remaining steps are the same.

[0027] Comparative Example 4: Compared with Example 1, the difference is that in step S2, the deposited polysilicon layer is a doped polysilicon layer, while the other steps are the same.

[0028] Test Example 1-2: Test Example 1: Gate Insulator Thickness Uniformity and Interface State Density Test In the preparation process of Examples 1 to 3 and Comparative Examples 1 to 4, the silicon carbide substrates after step S4 was completed and before step S5 was started were selected as test samples.

[0029] An aluminum metal layer was deposited on the surface of the test sample using magnetron sputtering. A circular metal electrode array with a diameter of 500 micrometers was then formed using photolithography and wet etching processes. The circular metal electrode array covered different regions of the silicon carbide substrate surface. For Examples 1 to 3, the circular metal electrode array was located at positions corresponding to the first thickness region and the second thickness region, respectively. For Comparative Examples 1 to 4, the circular metal electrode array was located on the surface of the gate insulating layer.

[0030] The oxide on the back of the test sample was removed, and a large-area aluminum metal layer was deposited on the back of the test sample as the back ohmic contact electrode. Then, an alloying annealing treatment was carried out at 450 degrees Celsius for 30 minutes to prepare the MOS capacitor structure.

[0031] The prepared MOS capacitor structure was placed on the probe stage of the semiconductor parameter analyzer.

[0032] In room temperature and dark room environments, probes are connected to the upper electrode and the back electrode of the MOS capacitor structure, respectively. A high-frequency small signal with a frequency of 1MHz is applied to the MOS capacitor structure, and the DC bias voltage is scanned from -10V to +10V. High-frequency capacitance-voltage characteristic curves are collected.

[0033] Based on the maximum capacitance value of the accumulation region in the high-frequency capacitance-voltage characteristic curve, combined with the area of ​​the circular metal electrode array and the relative permittivity of silicon dioxide, the equivalent oxide layer thickness of the gate insulating layer is calculated using the parallel plate capacitance formula.

[0034] Using the high- and low-frequency capacitance method, the quasi-static capacitance-voltage characteristic curves were tested within the same voltage range. The capacitance difference between the high-frequency capacitance-voltage characteristic curve and the quasi-static capacitance-voltage characteristic curve in the depletion region was compared to extract the interface state density at the interface between the silicon carbide substrate and the gate insulating layer.

[0035] The experimental data are shown in Table 1: Table 1. Test data on gate insulating layer thickness and interface state density of different embodiments and comparative examples Note: Comparative Examples 1 and 2 did not use patterned undoped polysilicon layers during the preparation process, resulting in a uniform thickness of the final gate insulating layer across the entire silicon carbide substrate surface. Physically, there is no distinction between the first and second thickness regions. Therefore, the test data of Comparative Examples 1 and 2 in Table 1 represent the overall characteristics of the uniform gate insulating layer surface and are marked as the overall region.

[0036] Results Analysis and Conclusions: As shown in Table 1, the measured equivalent oxide layer thicknesses in the first and second thickness regions of Examples 1, 2, and 3 are close to the designed target thickness values. The measured equivalent oxide layer thickness data for Examples 1, 2, and 3 indicate that through the high-temperature oxidation process in step S4, the retained undoped polysilicon layer can be completely exhausted and converted into silicon dioxide. Furthermore, the first thickness region formed by the conversion of the undoped polysilicon layer and the second thickness region formed directly from the oxidation of the silicon carbide substrate can form the expected thickness difference, thus realizing the SplitGate structure.

[0037] According to the data in Table 1, the interface state densities of Examples 1, 2, and 3 range from 1.6 to 2.2 x 10^11. The interface state densities of Comparative Examples 1 and 2 range from 4.5 to 4.8 x 10^11. The interface state densities of Examples 1, 2, and 3 are lower than those of Comparative Examples 1 and 2. This is because in Example 1, 2, and 3, a first silicon oxide film was generated as a buffer layer in step S1. The first silicon oxide film avoided direct damage to the surface of the silicon carbide substrate by the subsequent deposition process, and the long-term high-temperature oxidation process in step S4 played a role in annealing and repairing lattice damage.

[0038] The interface state density of Comparative Example 3 is as high as 11.9 to 12.6 x 10^11. Comparative Example 3 omits step S1, directly depositing an undoped polycrystalline silicon layer on the surface of the silicon carbide substrate. The high interface state density data of Comparative Example 3 indicates that, lacking the buffering effect of the first silicon oxide film, the heterogeneous interface formed by the direct contact between the undoped polycrystalline silicon layer and the silicon carbide substrate exhibits significant lattice mismatch and stress. Furthermore, the reaction atmosphere in the chemical vapor deposition process directly damages the surface of the silicon carbide substrate, and the lattice damage is difficult to completely eliminate during subsequent oxidation, leading to deterioration of the interface quality.

[0039] Comparative Example 4 showed a measured equivalent oxide layer thickness of 1085.6 Å in the first thickness region, deviating from the design target of 1000 Å, and the interface state density of Comparative Example 4 was higher than that of Example 1. Comparative Example 4 used a doped polysilicon layer in step S2. The dopant elements (such as phosphorus or boron) in the doped polysilicon layer alter the oxidation rate during the high-temperature oxidation process in step S4, increasing the difficulty of thickness control. Simultaneously, the dopant elements diffuse to the interface between the gate insulating layer and the silicon carbide substrate, forming additional scattering centers and defect levels, thus reducing interface quality.

[0040] The preparation methods used in Examples 1 to 3 utilize the complete depletion oxidation of the undoped polysilicon layer in conjunction with the first silicon oxide thin film buffer layer in step S1, which enables the gate insulating layer with low interface state density to be obtained while controlling the geometry of the SplitGate structure.

[0041] Examples 1 to 3 use undoped polysilicon layer oxidation to form gate insulating layer, reducing the direct thermal oxidation time of silicon carbide substrate and reducing carbon element residue at the interface between gate insulating layer and silicon carbide substrate. Table 1 shows that the interface state density of Examples 1 to 3 is lower than that of Comparative Examples 1 to 4. The low interface state density reduces carrier scattering, confirming that Examples 1 to 3 have higher channel mobility than Comparative Examples 1 to 4.

[0042] Test Example 2: Device Capacitance Characteristics, Conductivity Characteristics, and Gate Reliability Testing The semiconductor devices prepared in Examples 1 to 3 and Comparative Examples 1 to 4 were selected as devices under test.

[0043] Place the device under test on the probe stage, connect the probe stage to the semiconductor parameter analyzer, and set the test environment temperature to 25 degrees Celsius.

[0044] Connect the source measurement unit of the semiconductor parameter analyzer to the gate, source, and drain of the device under test, respectively.

[0045] Perform reverse transfer capacitance test: Set the gate voltage of the device under test to 0 volts, the source voltage to 0 volts, and the drain voltage from 0 volts to 600 volts. Set the frequency to 1 MHz and use a semiconductor parameter analyzer to measure the reverse transfer capacitance (i.e., Miller capacitance) when the drain voltage is 600 volts.

[0046] Perform on-resistance test: Set the gate voltage of the device under test to 20 volts, the source voltage to 0 volts, and the drain current to half of the rated current. Measure the drain-source voltage of the device under test and calculate the specific on-resistance according to Ohm's law.

[0047] Perform gate leakage current test: Ground the source and drain of the device under test, scan the gate voltage from 0 volts to 25 volts, and record the gate leakage current value when the gate voltage is 20 volts.

[0048] Threshold voltage stability test: The test environment temperature is raised to 150 degrees Celsius, a constant bias voltage of +20 volts is applied to the gate of the device under test, and the stress duration is 1000 hours. The threshold voltage of the device under test is measured before and after stress application, and the threshold voltage drift is calculated.

[0049] The experimental data are shown in Table 2: Table 2. Device capacitance, resistance, and reliability test data for different embodiments and comparative examples Results Analysis and Conclusions: From the data in Table 2, the reverse transfer capacitance values ​​of Examples 1, 2, and 3 range from 11.8 to 13.1 picofarads, and the specific on-resistance values ​​range from 3.38 to 3.52 milliohms per square centimeter. Comparative Example 1 has a reverse transfer capacitance as high as 48.6 picofarads. Comparative Example 1 uses a uniform silicon dioxide layer with a thickness of 400 angstroms as the gate insulating layer. The data from Comparative Example 1 show that although a thinner uniform gate insulating layer can achieve a lower specific on-resistance (3.25 milliohms per square centimeter), a thinner uniform gate insulating layer leads to an increase in the reverse transfer capacitance between the gate and drain. The SplitGate structure formed in Example 1 through step S4 has a thicker oxide layer in the first thickness region covering the drift region. This first thickness region reduces the reverse transfer capacitance, making the reverse transfer capacitance of Example 1 close to that of Comparative Example 2, which uses a thick gate design. Since the reverse transfer capacitance is an important component of the input capacitance, its reduction means an improvement in the overall input capacitance characteristics of the device.

[0050] Comparative Example 2 exhibits a high on-resistance of 6.84 milliohms per square centimeter, approximately twice that of Example 1. Comparative Example 2 utilizes a uniformly thick silicon dioxide layer of 1000 angstroms. The data from Comparative Example 2 demonstrates that while increasing the gate insulating layer thickness reduces the reverse transfer capacitance, it also decreases the gate drive capability required for channel reversal, thus increasing the on-resistance. Example 1 retains a thinner second-thickness region in the channel area, ensuring a lower on-resistance. The data from Example 1 proves that the stepped-thickness gate insulating layer structure successfully resolves the constraint between reverse transfer capacitance and on-resistance.

[0051] The gate leakage current of Comparative Example 3 was 58.40 nanoamps, and the threshold voltage drift was 1.85 volts. The gate leakage current of Example 1 was only 0.12 nanoamps, and the threshold voltage drift was only 0.08 volts. Comparative Example 3 omitted the first silicon oxide thin film buffer layer in step S1. The high leakage current and high threshold voltage drift of Comparative Example 3 indicate that the lattice mismatch caused by direct contact between the undoped polycrystalline silicon layer and the silicon carbide substrate, as well as surface damage during the deposition process, leads to easy charge trapping at the interface under high temperature and high field stress, causing reliability issues. The low leakage current data of Example 1 verifies the necessity of introducing a buffer layer in step S1.

[0052] Comparative Example 4 exhibits a gate leakage current as high as 125.70 nanoamps and a threshold voltage drift of 1.24 volts. Comparative Example 4 uses a doped polysilicon layer in step S2. The high leakage current data of Comparative Example 4 indicates that the dopant impurities in the doped polysilicon layer diffuse into the generated silicon dioxide layer during the high-temperature oxidation process in step S4. These impurities reduce the insulating density of the silicon dioxide layer and provide leakage paths. Example 1 uses an undoped polysilicon layer as a sacrificial layer for oxidation, ensuring the purity and density of the final gate insulating layer, thereby achieving excellent gate insulation performance.

[0053] In the high-temperature gate bias reliability test at 150 degrees Celsius and +20 volts, the data in Table 2 show that the threshold voltage drift of Examples 1 to 3 is less than that of Comparative Examples 1 to 4. Examples 1 to 3 improve the input capacitance and enhance the long-term reliability of the gate insulating layer.

Claims

1. A method for improving the fabrication of the gate insulating layer and input capacitance of a semiconductor device, characterized in that, Includes the following steps: S1. Select a silicon carbide substrate and clean it. Perform thermal oxidation treatment on the cleaned silicon carbide substrate to generate a first silicon oxide film on the surface of the silicon carbide substrate. S2. Deposit an undoped polycrystalline silicon layer on the surface of the first silicon oxide film; S3. Spin-coat positive photoresist onto the surface of the undoped polysilicon layer, form a preset mask pattern by exposure and development, remove the undoped polysilicon layer in the area that does not need to be retained by etching process, remove the positive photoresist, and retain the undoped polysilicon layer in the preset area to obtain a silicon carbide substrate with a patterned polysilicon layer. S4. Perform a high-temperature oxidation process on the silicon carbide substrate with the patterned polysilicon layer to form a gate insulating layer with stepped thickness. S5. A doped polysilicon layer is deposited on the surface of the gate insulating layer, a pattern is defined by photolithography, and the doped polysilicon layer is dry etched to form a gate structure. S6. A silicon dioxide layer is deposited on the surface of the gate structure and the silicon carbide substrate as an interlayer dielectric layer. The contact hole pattern is defined by photolithography. The interlayer dielectric layer is etched to form contact holes to obtain a semiconductor device.

2. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S1, the cleaning is standard RCA cleaning, the thermal oxidation treatment is carried out in an oxygen atmosphere at a flow rate of 8-12 slm at 950-1050 degrees Celsius for 10-20 minutes, and the thickness of the first silicon oxide film is 10-50 angstroms.

3. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S2, the deposition of the undoped polycrystalline silicon layer is carried out using silane as the silicon source gas, with the silane flow rate controlled at 150-250 sccm, at a temperature of 600-640 degrees Celsius and a pressure of 150-250 mTorr, and the thickness of the undoped polycrystalline silicon layer is 400-500 angstroms.

4. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S3, the specific method for forming the preset mask pattern is as follows: A 1.5-2.5 micrometer thick photoresist layer is formed by spin-coating the positive photoresist on the surface of the undoped polysilicon layer at a rotation speed of 2500-3500 rpm, and the preset mask pattern is formed by exposure and development.

5. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S3, the etching process is a dry etching process, specifically: Sulfur hexafluoride is used as the etching gas, and the flow rate of sulfur hexafluoride is controlled at 40-60 sccm. The positive photoresist is removed by an oxygen plasma process.

6. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S4, the high-temperature oxidation process is carried out under an oxygen atmosphere, with the oxygen flow rate controlled at 8-12 slm, and the oxidation treatment is carried out at a temperature of 900-1000 degrees Celsius for 120-180 minutes.

7. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S4, the gate insulating layer is divided into a first thickness region and a second thickness region. The thickness of the first thickness region is 900-1100 angstroms, and the thickness of the second thickness region is 350-450 angstroms. The gate insulating layer has a stepped gate structure.

8. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S5, the doped polycrystalline silicon layer is deposited by a low-pressure chemical vapor deposition process, using silane at a flow rate of 150-250 sccm and phosphine at a flow rate of 40-60 sccm, and the thickness of the doped polycrystalline silicon layer is 3500-4500 angstroms.

9. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S5, chlorine gas is used as the etching gas for dry etching of the doped polycrystalline silicon layer.

10. The method for preparing an improved gate insulating layer and input capacitance of a semiconductor device according to claim 1, characterized in that, In step S6, trifluoromethane is used as the etching gas to form the contact hole.

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