Integrated circuit packaging structure

Abstract

The embodiment of the invention discloses an integrated circuit packaging structure, relates to the technical field of integrated circuits, and aims to compensate the voltage drop of a main chip in the integrated circuit packaging structure. The packaging structure comprises: a substrate; a plurality of main chips, wherein the plurality of main chips are stacked on the substrate; the plurality of main chips comprise a first main chip and a second main chip which are arranged adjacently; the power supply compensation chip is arranged between the first main chip and the second main chip; a first deep groove capacitor and a second deep groove capacitor are arranged in the power supply supplement chip, and a first chip connecting part and a second chip connecting part of the first deep groove capacitor are respectively connected with a power supply network in the first main chip; and a third chip connecting part and a fourth chip connecting part of the second deep groove capacitor are respectively connected with a power supply network in the second main chip.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an integrated circuit packaging structure. Background Technology

[0002] In three-dimensional integrated circuit packaging structures, the number of stacked layers and chip size continue to increase. The shrinking size of three-dimensional chip interconnect technologies (such as micro-bumps, hybrid bonding, and through-silicon vias) leads to a significant increase in the resistance of power / ground network metal interconnects. When the chip load current undergoes a sudden change, such as switching from a low-power state to a high-power state, the supply voltage within the chip drops, resulting in a severe voltage drop (IR-Drop, Internal Resistance Drop) problem. Summary of the Invention

[0003] In view of this, embodiments of this application provide an integrated circuit packaging structure that facilitates compensation for the voltage drop of the main chip in the integrated circuit packaging structure.

[0004] This application provides an integrated circuit packaging structure, including: a substrate; a plurality of main chips stacked on the substrate; the plurality of main chips including a first main chip and a second main chip disposed adjacent to each other; a power supply compensation chip, the power supply supplement chip being disposed between the first main chip and the second main chip; the power supply supplement chip having a first deep trench capacitor and a second deep trench capacitor, the first chip connection portion and the second chip connection portion of the first deep trench capacitor being respectively connected to the power supply network in the first main chip, and the third chip connection portion and the fourth chip connection portion of the second deep trench capacitor being respectively connected to the power supply network in the second main chip.

[0005] According to a specific implementation of an embodiment of this application, the power supply supplement chip includes: a substrate; a first deep trench capacitor including a first deep trench capacitor unit array, the first deep trench capacitor unit array being disposed in a region of the substrate near a first surface of the substrate; the first deep trench capacitor unit array including a plurality of first deep trench capacitor units arranged side by side; a plurality of first leads of each first deep trench capacitor unit being connected to a first chip connection portion; a plurality of second leads of each first deep trench capacitor unit being connected to a second chip connection portion; a second deep trench capacitor including a second deep trench capacitor unit array, the second deep trench capacitor unit array being disposed in a region of the substrate near a second surface of the substrate; the second deep trench capacitor unit array including a plurality of second deep trench capacitor units arranged side by side; a plurality of third leads of each second deep trench capacitor unit being connected to a third chip connection portion; a plurality of fourth leads of each second deep trench capacitor unit being connected to a fourth chip connection portion.

[0006] According to one specific implementation of the embodiments of this application, each of the first deep trench capacitor units and each of the second deep trench capacitor units are arranged in a one-to-one correspondence; or, each of the first deep trench capacitor units and each of the second deep trench capacitor units are arranged alternately.

[0007] According to a specific implementation of the present application, when each of the first deep trench capacitor units and each of the second deep trench capacitor units are arranged alternately, the bottom of each of the first deep trench capacitor units extends to the region between two adjacent second deep trench capacitor units in the substrate.

[0008] According to a specific implementation of an embodiment of this application, the first leads of each of the first deep trench capacitor units are connected in series to form a first series electrode; the first chip connection portion is connected to the first series electrode; the second leads of each of the first deep trench capacitor units are connected in series to form a second series electrode; the second chip connection portion is connected to the second series electrode; and / or, the third leads of each of the second deep trench capacitor units are connected in series to form a third series electrode; the third chip connection portion is connected to the third series electrode; the fourth leads of each of the second deep trench capacitor units are connected in series to form a fourth series electrode; the fourth chip connection portion is connected to the fourth series electrode.

[0009] According to a specific implementation of an embodiment of this application, a first trench is provided on the first surface of the substrate; the first deep trench capacitor unit includes: a first dielectric layer disposed in the first trench; a plurality of first capacitor plates disposed side by side in the first dielectric layer; a plurality of second capacitor plates disposed side by side in the first dielectric layer and interleaved with each of the first capacitor plates; a first lead electrode connected to each of the first capacitor plates; and a second lead electrode connected to each of the second capacitor plates.

[0010] According to a specific implementation of an embodiment of this application, the first lead-out electrode and the second lead-out electrode are disposed on the first surface of the substrate.

[0011] According to a specific implementation of an embodiment of this application, the substrate is provided with a power supply via that connects a first surface and a second surface of the substrate; the power supply network of the first main chip is connected to the power supply network of the second main chip through the power supply via.

[0012] According to a specific implementation of this application, the substrate is provided with a signal via connecting a first surface and a second surface of the substrate; the first signal pin of the first main chip is connected to the second signal pin of the second main chip through the signal via.

[0013] According to a specific implementation of an embodiment of this application, a first support portion is provided on a first surface of the substrate; the first support portion abuts against the surface of the first main chip near the power supply supplement chip; and / or, a second support portion is provided on a second surface of the substrate; the second support portion abuts against the surface of the second main chip near the power supply supplement chip.

[0014] In the integrated circuit packaging structure of this embodiment, a power supply compensation chip is disposed between the first main chip 1 and the second main chip. The first chip connection portion and the second chip connection portion of the first deep trench capacitor in the power supply compensation chip are respectively connected to the power supply network in the first main chip. The third chip connection portion and the fourth chip connection portion of the second deep trench capacitor in the power supply compensation chip are connected to the power supply network of the second main chip. In this way, the voltage drop of the first main chip can be slowed down by the first deep trench capacitor, thus providing power supply compensation for the first main chip. The voltage drop of the second main chip can be slowed down by the second deep trench capacitor, thus providing power supply compensation for the second main chip. Furthermore, it can also slow down the voltage drop of other main chips among multiple main chips besides the first and second main chips. Therefore, it is convenient to compensate for the voltage drop of the main chips in the entire integrated circuit packaging structure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of an integrated circuit packaging structure provided in an embodiment of this application; Figure 2 A top view of the surface of a power supply supplement chip provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a power supply compensation chip provided in a specific embodiment of this application; Figure 4 A schematic diagram of the structure of a power supply compensation chip provided in another specific embodiment of this application; Figures 5-12 This is a schematic diagram of the process for manufacturing a power supply compensation chip according to an embodiment of this application. Detailed Implementation

[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0019] Figure 1 This is a schematic diagram of an integrated circuit packaging structure provided in an embodiment of this application. Figure 2 A top view of the surface of a power supply supplement chip provided in an embodiment of this application, as shown below. Figure 1 and Figure 2 As shown, The integrated circuit packaging structure in this embodiment is a three-dimensional packaging structure.

[0020] The integrated circuit packaging structure of this embodiment may include: a substrate and multiple main chips; multiple main chips are stacked on the substrate; the multiple main chips include a first main chip 1 and a second main chip 2 arranged adjacent to each other.

[0021] The integrated circuit packaging structure also includes a power supply compensation chip 3, which is located between the first main chip 1 and the second main chip 2. The power supply supplement chip 3 is provided with a first deep trench capacitor 30 and a second deep trench capacitor 32. The first chip connection portion 30a and the second chip connection portion 30b of the first deep trench capacitor 30 are respectively connected to the power supply network in the first main chip 1, and the third chip connection portion and the fourth chip connection portion of the second deep trench capacitor 32 are respectively connected to the power supply network in the second main chip 2.

[0022] Substrates are typically made of insulating materials, possessing excellent insulation and thermal conductivity. They help dissipate heat and support internal circuitry. In the field of semiconductor packaging, substrates provide physical support for chips, ensuring their stability during packaging and use, enabling electrical connections between chips and other electronic components, and ensuring signal transmission.

[0023] In this embodiment, multiple main chips are stacked on a substrate, and the number of main chips can be two or more. Specifically, the integrated circuit packaging structure in this embodiment is a three-dimensional packaging structure including 8-layer, 12-layer, or 16-layer main chips.

[0024] For a specific example, a power compensation chip can be placed between the 4th and 5th layers from the bottom, or between the 5th and 6th layers. Alternatively, two power compensation chips can be placed, one between the 4th and 5th layers and the other between the 5th and 6th layers.

[0025] When the first main chip 1 is mounted on the substrate, it can be mounted directly or indirectly. For example, the first main chip 1 can be mounted on the substrate via an adapter board. Specifically, the adapter board is mounted on the substrate, and the first main chip 1 is mounted on the adapter board. Furthermore, a redistribution layer can be provided on the adapter board, and the first main chip 1 can be mounted on the redistribution layer. The adapter board and redistribution layer enable horizontal interconnection between chips. In the vertical direction, multiple chips can be mounted, with vertical interconnection between them.

[0026] It is understandable that the first main chip 1 can also be set on other main chips besides the first and second main chips.

[0027] The first main chip 1 can be a data processing chip, an information storage chip, a communication chip, etc. The function of the second main chip 2 can be the same as or different from that of the first main chip 1.

[0028] The power supply compensation chip 3 is located between the first main chip 1 and the second main chip 2. The power supply compensation chip 3 includes a first deep trench capacitor 30 and a second deep trench capacitor 32.

[0029] The first chip connection portion 30a and the second chip connection portion 30b of the first deep trench capacitor 30 are used to connect the first deep trench capacitor 30 to other components. The first chip connection portion 30a and the second chip connection portion 30b are connected to the first main chip 1 through through-silicon vias (TSVs) or bonding structures.

[0030] When the load current of the first main chip 1 experiences a high-frequency jump (di / dt), the parasitic inductance L of the package of the first main chip 1 will introduce a transient voltage drop ΔV. AC = L·di / dt. The first deep trench capacitor 30 can provide transient charge to the first main chip 1, thereby converting ΔV AC High-frequency decoupling is achieved by limiting it to a specified range.

[0031] In some examples, the first deep trench capacitor 30 is located near the chip's power supply network, has a small equivalent series inductance, and can discharge in nanoseconds to provide transient charge.

[0032] In a power delivery network (PDN) of an integrated circuit, when the load current of the first chip changes abruptly (e.g., switching from a low-power state to a high-performance state), the parasitic inductance and resistance on the power path cause a momentary drop in the load voltage (dynamic IR drop). At this time, the first deep trench capacitor 30, located near the load, can discharge quickly, providing transient current and mitigating the voltage drop, thus acting as a "local energy storage buffer." In addition, the first deep trench capacitor 30 can absorb high-frequency noise in the power network, providing a low-impedance loop for high-frequency currents and maintaining power integrity.

[0033] The function of the second deep trench capacitor 32 in mitigating voltage drop in the second main chip 2 is similar to that of the first deep trench capacitor 30 in mitigating voltage drop in the first main chip 1.

[0034] With the power supply compensation chip 3 mounted on the first main chip 1 and the second main chip 2 mounted on the power supply compensation chip 3, the first deep trench capacitor 30 of the power supply compensation chip 3 not only compensates for the dynamic voltage drop of the first main chip 1, but also compensates for the dynamic voltage drop of the chips located between the substrate and the first main chip 1. Similarly, the second deep trench capacitor 32 of the power supply compensation chip 3 not only compensates for the dynamic voltage drop of the second main chip 2, but also compensates for the dynamic voltage drop of other chips located on the second main chip 2. In other words, the power supply compensation chip 3 in this embodiment can solve the voltage drop (IR-drop) problem in the entire 3D integrated circuit packaging structure and improve power integrity and signal integrity.

[0035] In this embodiment, the power supply compensation chip 3 is disposed between the first main chip 1 and the second main chip 2. The first chip connection portion 30a and the second chip connection portion 30b of the first deep trench capacitor 30 in the power supply compensation chip 3 are respectively connected to the power supply network in the first main chip 1. The third chip connection portion and the fourth chip connection portion of the second deep trench capacitor 32 in the power supply compensation chip 3 are connected to the power supply network of the second main chip 2. In this way, the voltage drop of the first main chip 1 can be reduced by the first deep trench capacitor 30, thus providing power supply compensation for the first main chip 1. The voltage drop of the second main chip 2 can be reduced by the second deep trench capacitor 32, thus providing power supply compensation for the second main chip 2. Furthermore, it can also reduce the voltage drop of other main chips among multiple main chips besides the first main chip 1 and the second main chip 2. Therefore, it is convenient to compensate for the voltage drop of the main chips in the entire integrated circuit packaging structure, improve the power integrity and signal integrity of the integrated circuit packaging structure, and does not occupy the area of ​​the main chip.

[0036] In a specific example, power compensation chip 3 is used as an intermediate layer, with processor chips or memory chips stacked on top and bottom respectively. Vertical interconnection between the chips is achieved using hybrid bonding technology, with a bonding pitch of less than 10μm. The upper surface capacitor array of power compensation chip 3 provides decoupling for the processor chip, and the lower surface capacitor array provides decoupling for the memory chip, effectively mitigating voltage drop (IR-Drop). Power compensation chip 3 can simultaneously mitigate voltage drop for the stacked chips, improving package density. For ease of fabrication, see [link to documentation]. Figure 2 and Figure 4 In some examples, the power supply compensation chip 3 may include: a substrate 34; a first deep trench capacitor 30 including a first deep trench capacitor unit array 30c, and a second deep trench capacitor 32 including a second deep trench capacitor unit array 32c; the first deep trench capacitor unit array 30c is disposed in a region of the substrate 34 near the first surface of the substrate 34; the first deep trench capacitor unit array 30c includes a plurality of first deep trench capacitor units 30ca arranged side by side; a plurality of first lead electrodes a1 of each first deep trench capacitor unit 30ca are connected to a first chip connection portion 30a; and a plurality of second lead electrodes a2 of each first deep trench capacitor unit 30ca are connected to a second chip connection portion 30b.

[0037] The second deep trench capacitor cell array 32c is disposed in the region of the substrate 34 near the second surface of the substrate 34; the second deep trench capacitor cell array 32c includes a plurality of second deep trench capacitor cells 32ca arranged side by side; a plurality of third lead electrodes of each second deep trench capacitor cell 32ca are connected to a third chip connection portion; a plurality of fourth lead electrodes of each second deep trench capacitor cell 32ca are connected to a fourth chip connection portion.

[0038] In this embodiment, the first surface of the substrate 34 may be the surface of the substrate 34 close to the first main chip 1, and the second surface may be the surface of the substrate 34 close to the second main chip 2.

[0039] In the substrate 34, the first deep trench capacitor cell array 30c is close to the first surface of the substrate 34, and the second deep trench capacitor cell array 32c is close to the second surface.

[0040] The number of multiple first deep trench capacitor units 30ca can be two or more; the number of multiple second deep trench capacitor units 32ca can be two or more.

[0041] The number of multiple first deep trench capacitor units 30ca may be the same as or different from the number of multiple second deep trench capacitor units 32ca.

[0042] The structures of the first deep trench capacitor unit 30ca and the second deep trench capacitor unit 32ca can be the same or different.

[0043] Each first deep trench capacitor unit 30ca has a first lead electrode a1 and a second lead electrode a2. The first lead electrode a1 of each first deep trench capacitor unit 30ca is connected to the first chip connection part 30a, and the second lead electrode a2 is connected to the second chip connection part 30b. This is equivalent to connecting each first deep trench capacitor unit 30ca in parallel, and the total capacitance obtained after parallel connection is larger.

[0044] The second deep trench capacitor array 32c is similar to the first deep trench capacitor array 30c.

[0045] The first lead-out electrode a1 of each first deep trench capacitor unit 30ca can be directly connected to the first chip connection portion 30a or indirectly connected; the second lead-out electrode a2 of each first deep trench capacitor unit 30ca can be directly connected to the second chip connection portion 30b or indirectly connected. In one embodiment A, the first lead-out electrodes a1 of each first deep trench capacitor unit 30ca are connected in series to form a first series electrode 30d; the first chip connection portion 30a is connected to the first series electrode 30d; the second lead-out electrodes a2 of each first deep trench capacitor unit 30ca are connected in series to form a second series electrode 30e; the second chip connection portion 30b is connected to the second series electrode 30e.

[0046] For example, the positive terminals of each first deep trench capacitor unit 30ca are connected to form a first series electrode 30d, which is then connected to the first chip connection part 30a. The negative terminals of each first deep trench capacitor unit 30ca are connected to form a second series electrode 30e, which is then connected to the second chip connection part 30b. In this way, it is not necessary to connect metal wires to the positive and negative terminals of each first deep trench capacitor unit 30ca. Power is supplied to multiple first deep trench capacitor units 30ca only through the first chip connection part 30a and the second chip connection part 30b to the power supply network (power network), which can reduce the winding resources.

[0047] The third lead-out electrode of each second deep trench capacitor unit 32ca can be directly connected to the third chip connection portion or indirectly connected; the fourth lead-out electrode of each second deep trench capacitor unit 32ca can be directly connected to the fourth chip connection portion or indirectly connected. In one embodiment B, the third lead-out electrodes of each second deep trench capacitor unit 32ca are connected in series to form a third series electrode; the third chip connection portion is connected to the third series electrode; the fourth lead-out electrodes of each second deep trench capacitor unit 32ca are connected in series to form a fourth series electrode; the fourth chip connection portion is connected to the fourth series electrode.

[0048] It is understood that an embodiment C is also provided, which includes the technical solutions of embodiments A and B described above.

[0049] The relative positional relationship between each of the first deep trench capacitor units 30ca near the first surface of the substrate 34 and each of the second deep trench capacitor units 32ca near the second surface of the substrate 34 is arbitrary. In order to make the structure of the power supply compensation chip 3 more compact and reduce the area of ​​the power supply compensation chip 3, in some examples, each of the first deep trench capacitor units 30ca and each of the second deep trench capacitor units 32ca are arranged in a one-to-one correspondence.

[0050] like Figure 3 In the illustrated embodiment, the bottom of the first deep trench capacitor unit 30ca and the bottom of the second deep trench capacitor unit 32ca are at a predetermined distance. The number of first deep trench capacitor units 30ca is equal to the number of second deep trench capacitor units 32ca.

[0051] like Figure 4 In the embodiment shown, each of the first deep trench capacitor units 30ca and each of the second deep trench capacitor units 32ca are arranged alternately.

[0052] Furthermore, when the first deep trench capacitor units 30ca and the second deep trench capacitor units 32ca are arranged in an alternating manner, in order to make the structure of the power supply compensation chip 3 more compact, in some examples, the bottom of each first deep trench capacitor unit 30ca extends into the region between two adjacent second deep trench capacitor units 32ca in the substrate 34.

[0053] The structure of the first deep trench capacitor unit 30ca can be any structure, see [link to relevant documentation]. Figures 5-12 In some examples, the first surface of the substrate 34 is provided with a first trench; the first deep trench capacitor unit 30ca may include: a first dielectric layer a3, a plurality of first capacitor plates a4 and a plurality of second capacitor plates a5; the first dielectric layer a3 is disposed in the first trench; each first capacitor plate a4 is disposed side by side in the first dielectric layer a3; each second capacitor plate a5 is disposed side by side in the first dielectric layer a3 and is staggered with each first capacitor plate a4; a first lead electrode a1 is connected to each first capacitor plate a4; a second lead electrode a2 is connected to each second capacitor plate a5.

[0054] like Figure 3 In the illustrated embodiment, the first capacitor plate a4 and the second capacitor plate a5 are of equal size. The first capacitor plates a4 and the second capacitor plates a5 are alternately arranged.

[0055] In some examples, the first lead electrode a1 and the second lead electrode a2 are disposed on the first surface of the substrate 34, which can significantly improve the flatness of the first surface of the power supply compensation chip 3. In addition, the flat first lead electrode a1 and the second lead electrode a2 facilitate the interconnection between each first deep trench capacitor unit 30ca, reduce the wiring difficulty, and can be directly adapted to micro bump or hybrid bonding technology, providing a basis for efficient interconnection with other 3D stacked chips.

[0056] It is understood that the structure of the second deep trench capacitor unit 32ca is the same as that of the first deep trench capacitor unit 30ca, and the third and fourth lead electrodes of the second deep trench capacitor unit 32ca are disposed on the second surface of the substrate 34.

[0057] In one embodiment, the first deep trench capacitor cell 30ca is fabricated according to the following process: Process flow 1: Etch deep trenches in a predetermined area of ​​substrate 34, such as... Figure 5 As shown.

[0058] Etching deep trenches provides the basic space for subsequent deep trench capacitor fabrication.

[0059] Deep trench structures are formed on silicon substrate 34 using etching processes such as Bosch process and reactive ion etching (RIE). The trench depth is 50-100μm and the trench width is 0.5-20μm.

[0060] Process Flow 2: Deposit an isolation layer a6 inside the deep trench, such as... Figure 6 As shown.

[0061] A deposition of an isolation layer enables electrical isolation between the substrate 34 and the subsequent capacitor structure. In some examples, SiO2 is deposited in a deep trench as the isolation layer, with a thickness of 20-50 nm.

[0062] Process Flow 3: Depositing dielectric materials, such as Figure 7 As shown.

[0063] Dielectric materials are deposited on the isolation layer, such as high-k dielectric materials like HfO2, with a thickness of 10-30 nm. Other dielectric materials include SiO2 and Al2O3.

[0064] Process flow four: Further deposit an isolation layer on the surface of substrate 34 and the surface of the dielectric material, such as... Figure 8 As shown.

[0065] Further deposition of an isolation layer enhances the isolation effect and avoids damage to the capacitor dielectric layer in subsequent processes.

[0066] Process Flow 5: Etching electrode metal grooves into the surface isolation layer, such as... Figure 9 As shown.

[0067] The position and shape of the electrode metal groove are determined on the surface isolation layer.

[0068] Process Flow Six: Immerse the plate material, such as..., in the metal tank. Figure 10 and 11 As shown.

[0069] Commonly used electrode materials include tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), and P-type / N-type silicon (Si).

[0070] After the electrode material deposition is completed, the surface is smoothed by chemical mechanical polishing. The first lead electrode a1 and the second lead electrode a2 of the deep trench capacitor unit are then fabricated for external connection. The electrode plates are connected to the first lead electrode a1 and the second lead electrode a2 to form alternating positive and negative electrode plates, ultimately forming an independently functioning deep trench capacitor unit. Figure 12 As shown.

[0071] The first lead-out electrode a1 and the second lead-out electrode a2 can be metal electrodes such as Au (gold), Al (aluminum), Cu (copper), and Ni (nickel).

[0072] According to the above steps, multiple deep trench capacitor units can be fabricated on one surface of the substrate 34 to form a first deep trench capacitor unit array 30c; or multiple deep trench capacitor units can be fabricated on the other surface of the substrate 34 to form a second deep trench capacitor unit array 32c.

[0073] When fabricating the double-sided capacitor unit array, a double-sided polished silicon substrate 34 is selected and thinned to a thickness of 100-200μm. Then, the substrate 34 is thinned to a predetermined thickness to ensure that the overall thickness of the power supply compensation chip 3 meets the stacking requirements of 3D packaging.

[0074] The deep trench capacitor cell structure of this embodiment provides higher capacitance density and better high-frequency characteristics.

[0075] See Figure 1 In the case where the power supply network of the integrated circuit package structure supplies power to the first main chip 1 through the second main chip 2, the substrate 34 is provided with a power supply via 36 that connects the first surface and the second surface of the substrate 34; the power supply network of the first main chip 1 is connected to the power supply network of the second main chip 2 through the power supply via.

[0076] The power supply network of the first main chip 1 and the power supply network of the second main chip 2 are connected through the power supply via 36 in the substrate 34, which shortens the power supply distance.

[0077] In a scenario where the first main chip 1 and the second main chip 2 communicate with each other, a signal via 38 is provided in the substrate 34 to connect the first surface and the second surface of the substrate 34. The first signal pin of the first main chip 1 is connected to the second signal pin of the second main chip 2 through the signal via 38. In this way, the signal transmission distance between the first main chip 1 and the second main chip 2 can be shortened and the signal quality can be improved.

[0078] In order to reduce uneven distribution of thermal and mechanical stress and increase packaging yield and long-term reliability, in some examples, the first surface of the substrate 34 is provided with a first support portion; the first support portion abuts against the surface of the first main chip 1 near the power supply compensation chip 3.

[0079] The first support portion is abutted against the surface of the first main chip 1 near the power supply compensation chip 3, which facilitates the adjustment of the thermal stress of the first main chip 1.

[0080] In some other examples, the second surface of the substrate 34 is provided with a second support portion; the second support portion abuts against the surface of the second main chip 2 near the power supply compensation chip 3.

[0081] The second support is abutted against the surface of the second main chip 2 near the power supply compensation chip 3, which facilitates the adjustment of the thermal stress of the second main chip 2.

[0082] It is understood that a first support portion may be provided on the first surface of the substrate 34, and a second support portion may be provided on the second surface.

[0083] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0085] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An integrated circuit packaging structure, characterized in that, include: substrate; Multiple main chips are stacked on the substrate; The plurality of main chips includes a first main chip and a second main chip arranged adjacent to each other. A power supply compensation chip is provided, wherein the power supply supplement chip is disposed between the first main chip and the second main chip; the power supply supplement chip is provided with a first deep trench capacitor and a second deep trench capacitor; the first chip connection portion and the second chip connection portion of the first deep trench capacitor are respectively connected to the power supply network in the first main chip, and the third chip connection portion and the fourth chip connection portion of the second deep trench capacitor are respectively connected to the power supply network in the second main chip.

2. The integrated circuit packaging structure according to claim 1, characterized in that, The power supply supplement chip includes: Substrate; The first deep trench capacitor includes a first deep trench capacitor unit array, which is disposed in a region of the substrate near a first surface of the substrate; the first deep trench capacitor unit array includes a plurality of first deep trench capacitor units arranged side by side; a plurality of first lead electrodes of each first deep trench capacitor unit are connected to the first chip connection portion; a plurality of second lead electrodes of each first deep trench capacitor unit are connected to the second chip connection portion. The second deep trench capacitor includes a second deep trench capacitor cell array, which is disposed in a region of the substrate near the second surface of the substrate; the second deep trench capacitor cell array includes a plurality of second deep trench capacitor cells arranged side by side; a plurality of third lead electrodes of each second deep trench capacitor cell are connected to the third chip connection portion; a plurality of fourth lead electrodes of each second deep trench capacitor cell are connected to the fourth chip connection portion.

3. The integrated circuit packaging structure according to claim 2, characterized in that, Each of the first deep trench capacitor units and each of the second deep trench capacitor units are arranged in a one-to-one correspondence; or, each of the first deep trench capacitor units and each of the second deep trench capacitor units are arranged alternately.

4. The integrated circuit packaging structure according to claim 3, characterized in that, When the first deep trench capacitor units and the second deep trench capacitor units are arranged alternately, the bottom of each first deep trench capacitor unit extends into the region between two adjacent second deep trench capacitor units in the substrate.

5. The integrated circuit packaging structure according to claim 2, characterized in that, The first lead-out electrodes of each of the first deep trench capacitor units are connected in series to form a first series electrode; the first chip connection portion is connected to the first series electrode. The second leads of each of the first deep trench capacitor units are connected in series to form a second series electrode; the second chip connection portion is connected to the second series electrode; and / or... The third lead-out electrodes of each of the second deep trench capacitor units are connected in series to form a third series electrode; the third chip connection portion is connected to the third series electrode; The fourth lead-out electrodes of each of the second deep trench capacitor units are connected in series to form a fourth series electrode; the fourth chip connection part is connected to the fourth series electrode.

6. The integrated circuit packaging structure according to claim 2, characterized in that, The first surface of the substrate is provided with a first trench; The first deep trench capacitor unit includes: A first dielectric layer is disposed in the first trench; Multiple first capacitor plates are arranged side by side in the first dielectric layer; Multiple second capacitor plates are arranged side by side in the first dielectric layer and are staggered with each of the first capacitor plates. The first lead-out electrode is connected to each of the first capacitor plates; The second lead electrode is connected to each of the second capacitor plates.

7. The integrated circuit packaging structure according to claim 6, characterized in that, The first lead-out electrode and the second lead-out electrode are disposed on the first surface of the substrate.

8. The integrated circuit packaging structure according to claim 6, characterized in that, The substrate has a power supply via that connects the first surface and the second surface of the substrate; The power supply network of the first main chip is connected to the power supply network of the second main chip through the power supply via.

9. The integrated circuit packaging structure according to claim 10, characterized in that, The substrate is provided with a signal via that connects the first surface and the second surface of the substrate; The first signal pin of the first main chip is connected to the second signal pin of the second main chip through the signal via.

10. The integrated circuit packaging structure according to claim 1, characterized in that, The first surface of the substrate is provided with a first support portion; The first support portion abuts against the surface of the first main chip near the power supply supplement chip; and / or, The second surface of the substrate is provided with a second support portion; The second support portion abuts against the surface of the second main chip near the power supply supplement chip.

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