Silicon carbide stepped trench MOSFET with short channel embedded super barrier rectifier

Abstract

A silicon carbide trench power device includes at least one silicon carbide MOSFET and one silicon carbide super barrier rectifier (SBR) integrated together in each cell having at least a single step gate trench structure for the silicon carbide MOSFET. The at least one single-step gate trench comprises a first top gate trench and at least one first bottom gate trench; the trench width of the first top gate trench is greater than the trench width of the at least one first bottom gate trench; a gate electrode of the silicon carbide MOSFET is located in the first top gate trench, a first insulating film is arranged in the bottom area of the first top gate trench, and a first gate oxide layer is arranged on the side wall of the first top gate trench; the at least one first bottom gate trench is filled with a first insulating film, and the thickness of the first insulating film is larger than that of the first gate oxide layer; and the Y-shaped grounding shielding region surrounds at least one first bottom gate trench and is used for reducing the electric field of the first gate oxide layer and improving the short-circuit capability.

Description

Technical Field

[0001] The present invention generally relates to a cell structure for a semiconductor device having at least two types of gate trenches, and more specifically, to integrating a silicon carbide stepped trench metal-oxide-semiconductor field-effect transistor (MOSFET) or a hybrid-channel silicon carbide stepped trench MOSFET having at least one stepped gate trench with a silicon carbide super barrier rectifier (SBR) as a MOS channel diode (MCD) into a cell to achieve lower on-resistance, lower switching losses and higher short-circuit capability, and further improve the safe operating area. Background Technology

[0002] Silicon carbide MOSFETs (SiC MOSFETs) have the potential to replace silicon superjunction MOSFETs and silicon insulated gate bipolar transistors (IGBTs) due to their faster switching speeds, higher operating temperatures, and lower switching losses. However, due to their wide bandgap characteristics, the parasitic PIN diode turn-on voltage of SiC MOSFETs (approximately 3 V) is higher than that of their silicon MOSFET counterparts (approximately 0.7 V), which degrades their reverse recovery characteristics. Therefore, external Schottky barrier diodes (SBDs) are typically used in power modules to disable the parasitic PIN diode. However, research has found that the parasitic inductance between the MOSFET and the external Schottky barrier diode has a significant negative impact on power loss during operation.

[0003] In response, the industry has proposed and validated various integrated devices to improve the characteristics of parasitic PIN body diodes in silicon carbide MOSFETs. Among them, the solution of integration with Schottky barrier diodes or junction barrier diodes (JBSDs) is widely used. However, the high-temperature reverse leakage current of Schottky barrier diodes is much greater than that of parasitic PIN diodes.

[0004] Therefore, in the design and manufacturing of silicon carbide MOSFETs, a novel cell structure, device configuration, and manufacturing process are still needed to enable SGT MOSFETs to have lower on-resistance and lower switching losses. Summary of the Invention

[0005] This invention provides a silicon carbide stepped trench MOSFET with an integrated super barrier rectifier (SBR). This SBR acts as a short-channel MOS channel diode, reducing switching losses. The integrated SBR provides a low-barrier environment for majority carriers in the MOS channel, and this low barrier can be adjusted by the gate oxide thickness, the doping concentration of the P-type body region, and the channel length. Compared to Schottky barrier rectifiers, this SBR exhibits lower forward voltage Vf and reverse leakage current Ir, and demonstrates superior and more reliable performance at high temperatures compared to Schottky diodes and junction barrier diodes.

[0006] This invention discloses a silicon carbide power device having multiple unit cells, comprising a silicon carbide stepped trench MOSFET (STMOSFET) and a silicon carbide super barrier rectifier disposed in each unit cell as a first silicon carbide MOSFET. The unit cell has at least two types of gate trenches, including: a first type of gate trench for the silicon carbide stepped trench MOSFET and a second type of gate trench for the silicon carbide super barrier rectifier; the first type of gate trench includes a first top gate trench and at least one first bottom gate trench, which are respectively used to form a first gate electrode and a first grounded P-type shielding region (PS) to reduce the electric field of the gate oxide layer. The first gate electrode is located within the first top gate trench, and the bottom region of the first top gate trench is provided with a first thick oxide layer serving as a first insulating film. A first grounded P-type shielding region is formed around the at least one first bottom gate trench filled with the first thick oxide layer, and is connected to the first body region via at least one grounded P-region (GP) adjacent to a portion of the sidewall of the first type of gate trench, and short-circuited to the source metal. The first grounded P-type shielding region is a Y-shaped structure with multiple sub-P-type shielding regions, forming a saturated current cutoff region (PSC) with the second grounded P-type shielding region below the first body region to improve short-circuit capability. The silicon carbide super barrier rectifier includes a second gate electrode, which is disposed in the second type of... Within the gate trench, and at the bottom region of the second type of gate trench, a second thick oxide layer serving as a second insulating film is provided; in the silicon carbide stepped trench MOSFET, a first channel region is formed within the first body region along at least one trench sidewall of the first type of gate trench; in the silicon carbide super barrier rectifier, a second channel region is formed within the second body region along the sidewall of the second type of gate trench; the silicon carbide stepped trench MOSFET has a first gate oxide layer, and the silicon carbide super barrier rectifier has a second gate oxide layer, the thickness of the second gate oxide layer being less than that of the first gate oxide layer; and the channel length of the silicon carbide super barrier rectifier is less than that of the silicon carbide stepped trench MOSFET.

[0007] According to another aspect of the present invention, in some preferred embodiments, the silicon carbide power device further includes: a first gate electrode disposed on the upper part of the first top gate trench, and a shielding gate electrode disposed in the first top gate trench and located below the first gate electrode, wherein the first gate electrode and the shielding gate electrode are isolated from each other by a polysilicon interoxide (IPO) layer.

[0008] According to another aspect of the present invention, in some preferred embodiments, the silicon carbide power device further includes a superjunction structure (SJ), the superjunction structure including a P-type pillar region (PC) of a second conductivity type, at least two opposing sidewall P-type shield regions (SPS) of the second conductivity type, and a junction field-effect transistor region (JFET) of a first conductivity type; the doping concentration of the sidewall P-type shield regions is higher than that of the P-type pillar regions, and they are adjacent to the P-type pillar regions; the junction field-effect transistor region is formed between the at least two sidewall P-type shield regions, and its doping concentration is higher than that of the epitaxial layer.

[0009] According to another aspect of the present invention, in some preferred embodiments, the silicon carbide power device further includes a second silicon carbide MOSFET without a stepped gate trench, wherein the second silicon carbide MOSFET and the first silicon carbide MOSFET form a hybrid channel MOSFET (HCMOSFET) in the unit cell of the silicon carbide power device to reduce the specific on-resistance; wherein the hybrid channel MOSFET forms two different threshold voltages by performing an additional short-channel injection in the channel region of the second silicon carbide MOSFET, thereby further improving the positive temperature coefficient to ensure the reliability of operation at high temperatures.

[0010] The above and other objects and advantages of the present invention will be readily apparent to those skilled in the art upon referring to the following figures and reading the detailed description of preferred embodiments below. Attached Figure Description

[0011] Figure 1A This is a top view of a trench MOSFET with a strip cell layout according to a preferred embodiment of the present invention.

[0012] Figure 1B yes Figure 1A A preferred cross-sectional view of section A1-A1' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, wherein the first type of gate trench of the silicon carbide MOSFET is a single-step gate trench structure.

[0013] Figure 1C yes Figure 1AA preferred cross-sectional view of section B1-B1' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, and a grounded P region is provided along the sidewall of the first type of gate trench.

[0014] Figure 2A This is a top view of a trench MOSFET with a strip cell layout according to another preferred embodiment of the present invention.

[0015] Figure 2B yes Figure 2A A preferred cross-sectional view of section A2-A2' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, and a grounded P region is provided along one sidewall of the first type of gate trench.

[0016] Figure 2C yes Figure 2A Another preferred cross-sectional view of section A2-A2' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, wherein the second type of gate trench of the silicon carbide super barrier rectifier is a single-step gate trench structure.

[0017] Figure 2D yes Figure 2A Another preferred cross-sectional view of section A2-A2' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, and an L-type and P-type shielding region is provided around the sidewalls and part of the bottom region of the second type of gate trench.

[0018] Figure 2E yes Figure 2A Another preferred cross-sectional view of section A2-A2' shows a structure in which silicon carbide MOSFETs and silicon carbide superbarrier rectifiers are integrated in each unit cell, and an N-type buffer source region (nb) is provided below the first source region and the second source region.

[0019] Figure 2F This is a cross-sectional view according to another preferred embodiment of the present invention, which shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, and a saturation current cutoff region (PSC) is provided.

[0020] Figure 3 yes Figure 1A Another preferred cross-sectional view of section A1-A1' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, wherein the first type of gate trench of the silicon carbide MOSFET is a double-step gate trench structure.

[0021] Figure 4AThis is a top view of a trench MOSFET with a strip cell layout according to another preferred embodiment of the present invention, the device integrating a silicon carbide super barrier rectifier and a silicon carbide hybrid channel MOSFET.

[0022] Figure 4B yes Figure 4A A preferred cross-sectional view of section A3-A3' shows that each unit cell includes a second silicon carbide MOSFET, the second silicon carbide MOSFET forming a hybrid channel MOSFET with the first silicon carbide MOSFET.

[0023] Figure 5 yes Figure 1A Another preferred cross-sectional view of section A1-A1' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, wherein a shielding gate electrode is included below the first gate electrode in the first type of gate trench of the silicon carbide MOSFET.

[0024] Figure 6A yes Figure 1A Another preferred cross-sectional view of section A1-A1' shows a structure in which a silicon carbide MOSFET and a silicon carbide super barrier rectifier are integrated in each unit cell, and a P-type pillar region is provided adjacent to the bottom surface of the first body region, the P-type pillar region being located above the N+ substrate.

[0025] Figure 6B yes Figure 1A Another preferred cross-sectional view of section A1-A1' shows a structure in which silicon carbide MOSFETs and silicon carbide superbarrier rectifiers are integrated in each unit cell, and a junction field-effect transistor region is formed between two adjacent sidewall P-type shielding regions.

[0026] Figure 7A yes Figure 1A Another preferred cross-sectional view of section A1-A1' shows an IGBT using a P+ substrate according to the present invention.

[0027] Figure 7B yes Figure 1A Another preferred cross-sectional view of section A1-A1' shows another IGBT according to the invention, wherein the P+ substrate is provided with a plurality of alternating P+ and N+ regions. Detailed Implementation

[0028] The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. The invention may be embodied in various ways, but should not be limited to the embodiments described herein. For example, the description herein refers more to N-channel semiconductor integrated circuits, but it will be apparent that other devices are also possible. The preferred embodiments of the invention are described in detail below with reference to the accompanying drawings. Some directional terms, such as “top,” “bottom,” “front,” “back,” “above,” “below,” etc., are used with reference to the orientation of the accompanying drawings. Since the elements in the embodiments can be placed in many different orientations, the directional terms in this invention are for descriptive purposes only and should not be considered as limiting the invention. It should be understood that various structural or logical substitutions and modifications in the embodiments should be covered within the true spirit and scope of the invention. Therefore, the following detailed description should not be considered as limiting the invention, the scope of which is defined by the appended claims. It should be understood that the inventive features of the various preferred embodiments described herein can be combined with each other, unless otherwise specified.

[0029] Figure 1A The diagram shows a top view of a preferred silicon carbide power device according to the present invention, having a strip-shaped unit cell layout. The unit cell further includes a first type of gate trench 103 located in a silicon carbide MOSFET and a second type of gate trench 105 located in a silicon carbide super-barrier rectifier. The first type of gate trench 103 is surrounded by a first P-type shielding region (PS1, as shown), and a trench-type source contact region 113 is located between the first type of gate trench 103 and the second type of gate trench 105. According to the present invention, the first P-type shielding region is grounded to the source metal through a grounded P-region (GP, as shown) and the trench-type source contact region 113. The grounded P-region surrounds a portion of the sidewall of the first type of gate trench 103, and a first channel region 130 is formed between the two grounded P-regions along the sidewall of the first type of gate trench 103, with the grounded P-region and the first channel region 130 alternating along the sidewall of the first type of gate trench 103.

[0030] Figure 1B The following is shown Figure 1AA cross-sectional view of a preferred embodiment along section A1-A1'. An N-channel silicon carbide stepped trench MOSFET 100' and a silicon carbide super barrier rectifier 160' are integrated in each unit cell. The unit cell has a dual-gate trench (DGT) structure formed on an N+ substrate 101', on which a lightly doped N-type epitaxial layer 102' extends. The back side of the N+ substrate 101' is coated with a back metal as a drain metal 120'. Within the N-type epitaxial layer 102', multiple gate trenches (including a first type of gate trench for the silicon carbide stepped trench MOSFET and a second type of gate trench for the silicon carbide super barrier rectifier) ​​are formed vertically downwards from the upper surface of the N-type epitaxial layer 102', without reaching the common interface between the N-type epitaxial layer 102' and the N+ substrate 101'. The first type of gate trench is a single-step gate trench structure, including a first top gate trench 103' and a first bottom gate trench 104', wherein the first top gate trench 103' is located above the first bottom gate trench 104', and its gate width is greater than that of the first bottom gate trench 104'. The first gate electrode 115' (G1, as shown in the figure) of the silicon carbide MOSFET 100' is located within the first top gate trench 103'. The bottom region of the first top gate trench 103' is provided with a thick bottom oxide layer serving as a first insulating film 116', and the sidewalls of the first top gate trench 103' are provided with a first gate oxide layer 119', wherein the thickness of the first insulating film 116' is greater than that of the first gate oxide layer 119'. The first bottom gate trench 104' is filled with the first insulating film 116'. The second gate electrode 125' (G2, as shown) of the silicon carbide super barrier rectifier 160' is located within each second type gate trench 105'. A second insulating film 126' is provided at the bottom region of the second type gate trench 105', and a second gate oxide layer 129' is provided on the sidewall of the second type gate trench 105'. The thickness of the second gate oxide layer 129' is less than the thickness of the first gate oxide layer 119' and the second insulating film 126', and the thickness of the second insulating film 126' is less than the thickness of the first insulating film 116'. In the silicon carbide MOSFET 100', a first body region 114' (p1, as shown) is located below the first n+ source region 111' and extends to the upper part of the N-type epitaxial layer 102', surrounding the first gate electrode 115' isolated by the first gate oxide layer 119'. The first channel region 130' is located within the first body region 114' and is formed along a portion of the sidewall of the first top gate trench 103'.In the silicon carbide superbarrier rectifier 160', a second body region 124' is located below the second n+ source region 121' and extends above the N-type epitaxial layer 102', surrounding the second gate electrode 125' isolated by the second gate oxide layer 129'. The doping concentration of the second body region 124' is lower than that of the first body region 114'. A second channel region 140' is located within the second body region 124' and is formed along a portion of the sidewall of the second type gate trench 105', with a channel length shorter than that of the first channel region 130'. A short-channel implantation region 122' (Nsci, as shown) is formed by angular implantation of nitrogen or phosphorus, surrounding the second channel region 140' but along the sidewall of the second type gate trench 105', with a doping concentration higher than that of the N-type epitaxial layer 102'. Furthermore, an N-type current extension layer 107' (CSL, as shown) is formed below the first type of gate trench, and its doping concentration is higher than that of the N-type epitaxial layer 102'. A first P-type shielding region 117' (PS1, as shown) of a Y-shaped structure for reducing the electric field of the gate oxide is formed around the first bottom gate trench 104' and includes two sub-P-type shielding regions, namely a first top P-type shielding region 1171' (PS1t, as shown) and a first bottom P-type shielding region 1172' (PS1b, as shown), wherein the first bottom P-type shielding region 1172' is located below the first top P-type shielding region 1171' and its doping concentration is lower than that of the first top P-type shielding region 1171'; a second P-type shielding region 127' (PS2, as shown) is adjacent to the lower surface of the first body region 114' and forms a saturated current cutoff region (SCP, as shown) with the first P-type shielding region 117' to improve short-circuit capability. An interlayer dielectric film 108' is stacked on the epitaxial layer 102', and a source metal 109' is formed on the interlayer dielectric film 108'. The first body region 114', the first body region 124', the first n+ source region 111', the second n+ source region 121', and the second gate electrode 125' are shorted to the source metal 109' through multiple trench-type source contact regions 113' and 123'. The trench-type source contact regions 113' and 123' are filled with contact metal plugs and metal barrier layers, and a heavily doped p+ region 110' is provided around the bottom of the first n+ source region 111' and the second n+ source region 121'.

[0031] Figure 1C As shown Figure 1A A sectional view of a preferred embodiment of section B1-B1'. Figure 1C Structure and Figure 1B Similar, the difference is that, Figure 1CIt also includes a grounded P-region 118'' (GP, as shown) formed along a portion of the sidewall of the first type of gate trench 103'', for grounding the first P-type shielding region 117'' to the source metal 109'' through the first body region 114'' and the source contact region 113''.

[0032] Figure 2A The diagram shows a top view of a preferred silicon carbide power device according to the present invention, having a strip-shaped cell layout. The cell further includes a first type of gate trench 203 located in a silicon carbide MOSFET and a second type of gate trench 205 located in a silicon carbide super-barrier rectifier. The structure of this silicon carbide power device is similar to... Figure 1A Similarly, the difference is that in this embodiment, the strip-shaped channel region is formed along the first sidewall 203-S1 of the first type of gate trench 203, while the ground P region is formed along the second sidewall 203-S2 of the first type of gate trench 203.

[0033] Figure 2B As shown Figure 2A A sectional view of a preferred embodiment of section A2-A2'. Figure 2B Structure and Figure 1B Similarly, but with a difference, this embodiment also includes a grounded P-region 218' formed along the trench sidewall of the first type of gate trench 203', for grounding the first P-type shielding region 217' to the source metal 209' through the first body region 214' and the source contact region 213'.

[0034] Figure 2C As shown Figure 2A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 2B Similarly, the difference lies in that the second type of gate trench of the silicon carbide super barrier rectifier in this embodiment is a single-step gate trench structure, including a second top gate trench 205'' and a second bottom gate trench 206'', wherein the second top gate trench 205' is located above the second bottom gate trench 206'' and the gate width is greater than the second bottom gate trench 206'', and the second bottom gate trench 206'' is filled with the second insulating film 226''.

[0035] Figure 2D As shown Figure 2A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 2BSimilarly, the difference is that this embodiment also includes a third P-type shielding region 237''' (PS3, as shown in the figure) of the second conductivity type, which is an L-shaped structure surrounding the sidewalls and part of the bottom region of the second type of gate trench 205''' and connected to the second body region 224''' to reduce the electric field of the second gate oxide layer.

[0036] Figure 2E As shown Figure 2A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 2D Similarly, the difference is that this embodiment also includes an N-type buffer source region 241'''' (nb, as shown in the figure), which is located below the first n+ source region 211'''' and the second n+ source region 221'''', and its doping concentration is lower than that of the first n+ source region 211'''' and the second n+ source region 221''''.

[0037] Figure 2F This is a cross-sectional view of another preferred embodiment of a silicon carbide power device according to the present invention, featuring a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 2D Similarly, the difference lies in that this embodiment also includes a first N-type buffer source region 241''''' and a second N-type buffer source region 251'''''. The first N-type buffer source region 241''''' is formed on the side of the first n+ source region 211'''' adjacent to the first channel region 230'''', and its doping concentration is lower than that of the first n+ source region 211'''''. The second N-type buffer source region 251''''' is formed on the side of the second n+ source region 221''''' adjacent to the second channel region 240'''', and its doping concentration is lower than that of the first n+ source region 211'''''. Furthermore, the heavily doped P-type region 252''''' (psc, as shown in the figure) is used to form the first saturated current cutoff region (SCP1 region, as shown in the figure) and the second saturated current cutoff region (SCP2 region, as shown in the figure). It is located on top of the first n+ source region 211''''', the second n+ source region 221''''', the first N-type buffer source region 241''''', and the second N-type buffer source region 251''''', and is shorted to the source metal 209''''' through the trench-type source contact 213''''. The first saturated current cutoff region is formed between the heavily doped P-type region 252''''' and the first body region 214''''', and the second saturated current cutoff region is formed between the heavily doped P-type region 252''''' and the second body region 224'''''.

[0038] Figure 3 As shown Figure 1A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 1B Similarly, the difference is that in this embodiment, the first type of gate trench of the silicon carbide MOSFET is a double-step gate trench structure, including a first top gate trench 303 with a width of Wt, a first middle gate trench 304 located below the first top gate trench 303 with a width of Wm, and a first bottom gate trench 306 located below the middle gate trench 304 with a width of Wb, wherein the width relationship is Wt>Wm>Wb. Furthermore, the first intermediate gate trench 304 and the first bottom gate trench 306 are filled with the first insulating film 316 and surrounded by a first P-type shielding region 317 (PS1, as shown in the figure). The first P-type shielding region has a Y-shaped structure and includes three sub-P-type shielding regions: a first top P-type shielding region 3171 (PS1t, as shown in the figure), a first intermediate P-type shielding region 3173 (PS1m, as shown in the figure) located below the first top P-type shielding region 3171, and a first bottom P-type shielding region 3172 (PS1b, as shown in the figure) located below the first intermediate P-type shielding region 3173. The doping concentration of the first bottom P-type shielding region 3172 is lower than that of the intermediate P-type shielding region 3173, and the doping concentration of the intermediate P-type shielding region 3173 is lower than that of the first top P-type shielding region 3171.

[0039] Figure 4A The diagram shows a top view of a preferred silicon carbide power device according to the present invention, which has a strip-shaped unit cell layout. The unit cell further includes a first type of gate trench 403 located in a silicon carbide MOSFET, a second type of gate trench 405 located in a silicon carbide super-barrier rectifier, and a third type of gate trench 443 located in a second silicon carbide MOSFET. The structure of this silicon carbide power device is similar to... Figure 1A Similarly, the difference is that each unit cell in this embodiment is also provided with a third type of gate trench 443.

[0040] Figure 4B As shown Figure 4A A cross-sectional view of a preferred embodiment along section A3-A3'. A first silicon carbide MOSFET 400' (MOSFET1, as shown), a second silicon carbide MOSFET 470' (MOSFET2, as shown), and a silicon carbide super-barrier rectifier 460' are integrated in each unit cell. The structure of this silicon carbide power device is similar to... Figure 1BSimilarly, but with a difference, this embodiment also includes a second silicon carbide MOSFET 470', which, together with the first silicon carbide MOSFET 400', forms a mixed-channel MOSFET in the unit cell of the silicon carbide power device. In this embodiment, the third type gate trench 443' of the second silicon carbide MOSFET 470' is formed vertically downward from the upper surface of the N-type epitaxial layer 402' and does not reach the common interface between the N-type epitaxial layer 402' and the N+ substrate 401'. The third gate electrode 435' (G3, as shown) of the second silicon carbide MOSFET 470' is located within the third type gate trench 443'. The bottom region of the third type gate trench 443' is provided with a thick bottom oxide layer serving as a third insulating film 436', and the sidewalls of the third type gate trench 443' are provided with a third gate oxide layer 439', wherein the thickness of the third insulating film 436' is greater than the thickness of the third gate oxide layer 439'. Furthermore, a third body region 434' (p3, as shown) is located below the third n+ source region 431' and is formed on top of the N-type epitaxial layer 402', surrounding the third gate electrode 435' isolated by the third gate oxide layer 439'. The doping concentration of the third body region 434' is lower than that of the first body region 414', wherein the third body region 434' and the third n+ source region 431' are shorted to the source metal 409' through the trench source contact region 433'. The third channel region 450' of the second silicon carbide MOSFET 470' is located within the third body region 434' and is formed along the trench sidewall of the third type gate trench 443'. A second short channel injection region 432' (Nsci2, as shown) of the first conductivity type surrounds the third channel region 450'.

[0041] Figure 5 As shown Figure 1A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 1BSimilarly, the difference lies in the shielding gate structure in the first top gate trench 503 of the first type of gate trenches. In this embodiment, the shielding gate electrode 545 (SG, as shown in the figure) is located in the lower part of the first top gate trench and below the first gate electrode 515 (G1, as shown in the figure). The first gate electrode 515 is laterally isolated from the adjacent epitaxial layer through the first gate oxide layer 519. The shielding gate electrode 545 is vertically isolated from the epitaxial layer through the insulating layer 516 in the bottom region of the first top gate trench, where the thickness of the insulating layer 516 is greater than the thickness of the first gate oxide layer 519. Meanwhile, the shielding gate electrode 545 and the first gate electrode 515 are insulated from each other through another insulating film 546 serving as an inter-polyoxide (IPO) layer.

[0042] Figure 6A as shown Figure 1A is a cross-sectional view of another preferred embodiment of the A1 - A1' section shown, which has a novel and improved device structure. The structure of this silicon carbide power device is similar to Figure 1B Similarly, the difference lies in that Figure 1B the second P-type shielding region 127' in is absent in Fig. 6A, and this embodiment further includes an N-type buffer layer 612 (NB, as shown in the figure) with a resistivity of Rb, sandwiched between the N+ substrate 601 and the N-type epitaxial layer 602. The N-type epitaxial layer 602 is a single epitaxial layer with a uniform doping concentration and a resistivity of R, where R < Rb. In addition, a P-type column region 647 (PC, as shown in the figure) of the second conduction type is introduced into the N-type epitaxial layer 602 to form a superjunction region, and the superjunction region includes multiple alternating P regions 647 and N regions 602. The P-type column region 647 is adjacent to the bottom surface of the first body region 614 and contacts the bottom surface of the N-type epitaxial layer 602 through multiple epitaxy methods or by opening deep trenches and filling with an epitaxial layer of the second conduction type.

[0043] Figure 6B as shown Figure 1A is a cross-sectional view of another preferred embodiment of the A1 - A1' section shown, which has a novel and improved device structure. The structure of this silicon carbide power device is similar to Figure 6ASimilarly, but with a difference, this embodiment also includes two opposing sidewall P-type shielding regions 657' (SPS, as shown in the figure) of a second conductivity type, which are horizontally adjacent to the P-type pillar region 647' and spaced apart from the first body region 614'. The doping concentration of the sidewall P-type shielding regions 657' is higher than that of the P-type pillar region 647'; a junction field-effect transistor region 658' (JFET, as shown in the figure) of a first conductivity type is formed between the two sidewall P-type shielding regions 657', and its doping concentration is higher than that of the N-type epitaxial layer 602'.

[0044] Figure 7A As shown Figure 1A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 6B Similarly, the difference lies in the substrate. In this embodiment, the silicon carbide power device is formed on a P+ substrate 701, and the resistivity Rb of the N-type buffer layer 712 (NB, as shown) sandwiched between the P+ substrate 701 and the P-type pillar region 747 is lower than the resistivity R of the N-type epitaxial layer 702.

[0045] Figure 7B As shown Figure 1A A cross-sectional view of another preferred embodiment of the silicon carbide power device, showing a novel and improved device structure. The structure of this silicon carbide power device is similar to... Figure 7A Similar, the difference is that, Figure 7B The silicon carbide power device also includes a plurality of heavily doped N+ regions 762' disposed within the P+ substrate 701' to form a plurality of alternating P+ and N+ regions in the substrate.

[0046] Although various embodiments have been described herein, it will be understood that various modifications can be made to the invention by means of the guidance provided in the appended claims without departing from the spirit and scope of the invention. For example, the methods of the invention can be used to form structures of various semiconductor regions having a conductivity type opposite to that described herein.

Claims

1. A silicon carbide power device, characterized in that, The system comprises multiple unit cells with at least two types of gate trenches, each unit cell including a first silicon carbide MOSFET and a silicon carbide super barrier rectifier, and further includes: a first conductivity type epitaxial layer grown on a substrate; the at least two types of gate trenches include a first type of gate trench for the first silicon carbide MOSFET and a second type of gate trench for the silicon carbide super barrier rectifier; the first silicon carbide MOSFET further includes: the first type of gate trench having at least a single-step gate trench structure; the single-step gate trench structure having a first top gate trench and at least one first bottom gate trench, wherein the first top gate trench... A trench is located above at least one of the first bottom gate trenches, and the trench width is greater than the trench width of at least one of the first bottom gate trenches; a first gate electrode is located within the first top gate trench; a first insulating film is provided in the bottom region of the first top gate trench, a first gate oxide layer is provided on the sidewall of the first top gate trench, and the thickness of the first insulating film is greater than the thickness of the first gate oxide layer; a first body region of a second conductivity type is provided on the first body region, and a first source region of a first conductivity type is provided on the first body region; a first channel region is formed in the first body region, extends along at least one sidewall of the first top gate trench and is connected to the first source region; a second conductive... The first shielding region of electrical type surrounds the at least one first bottom gate trench filled with the first insulating film; the first shielding region includes at least two sub-shielding regions, the at least two sub-shielding regions including a first top shielding region and a first bottom shielding region, wherein the first bottom shielding region is located below the first top shielding region and has a lower doping concentration than the first top shielding region; and at least one grounding region of second conductivity type surrounds a portion of the sidewall of the first type of gate trench, connecting the first body region and the first P-type shielding region; the silicon carbide super barrier rectifier further includes: a second gate electrode located within the second type of gate trench. The second type of gate trench has a second insulating film at its bottom region, a second gate oxide layer on its sidewall, and the thickness of the second gate oxide layer is less than the thickness of the second insulating film; a second body region of a second conductivity type, a second source region of a first conductivity type on the second body region, and the doping concentration of the second body region is lower than the doping concentration of the first body region; a second channel region is formed in the second body region, extends along at least one sidewall of the second type of gate trench and is connected to the second source region; the first body region, the second body region, the first source region, the second source region and the second gate electrode are shorted to the source metal through a source contact portion.

2. The silicon carbide power device according to claim 1, characterized in that, The at least one first bottom gate trench includes a single first bottom gate trench, the single first bottom gate trench being surrounded by a first shielding region of a Y-shaped structure.

3. The silicon carbide power device according to claim 1, characterized in that, The at least one first bottom gate trench includes a plurality of first bottom gate trenches, the plurality of first bottom gate trenches being surrounded by the first shielding region of a Y-shaped structure.

4. The silicon carbide power device according to claim 1, characterized in that, Also includes: The first type of gate trench has a double-step gate trench structure; The double-step gate trench structure has a first top gate trench with a width of Wt, a first middle gate trench with a width of Wm, and a first bottom gate trench with a width of Wb. The first top gate trench is located above the middle gate trench, and the middle gate trench is located above the first bottom gate trench, wherein Wt > Wm > Wb; and The first shielding area includes three sub-shielding areas, namely the first top shielding area, the first middle shielding area, and the first bottom shielding area. The first bottom shielding area is located below the first middle shielding area and has a lower doping concentration than the middle shielding area. The first middle shielding area is located below the first top shielding area and has a lower doping concentration than the top shielding area.

5. The silicon carbide power device according to claim 1, characterized in that, Also includes: The second silicon carbide MOSFET, together with the first silicon carbide MOSFET, forms a hybrid channel MOSFET in each cell of the silicon carbide power device; The second silicon carbide MOSFET further includes: A third type of gate trench is formed within the epitaxial layer; The third gate electrode is located within the third type of gate trench; Around the third gate electrode, a third insulating film is provided in the bottom region of the third type of gate trench, and a third gate oxide layer is provided on the sidewall of the third type of gate trench. The thickness of the third insulating film is greater than the thickness of the third gate oxide layer. A third body region of the second conductivity type is provided on the third body region, and the doping concentration of the third body region is lower than that of the first body region. A third channel region is formed within the third body region, extends along at least one sidewall of the third type of gate trench, and connects to the third source region; and The third body region and the third source region are shorted to the source metal.

6. The silicon carbide power device according to claim 1, characterized in that, It also includes a first short-channel implantation region of a first conductivity type surrounding the second channel region, wherein the first short-channel implantation region is formed by angular implantation of nitrogen or phosphorus and the doping concentration is higher than the doping concentration of the epitaxial layer, the channel length of the second channel region is less than the channel length of the first channel region, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

7. The silicon carbide power device according to claim 5, characterized in that, It also includes a second short-channel injection region of a first conductivity type surrounding the third channel region, wherein the channel length of the third channel region is less than the channel length of the first channel region.

8. The silicon carbide power device according to claim 1, characterized in that, It also includes a current spreading layer of a first conductivity type located below the first type of gate trench, wherein the doping concentration of the current spreading layer is higher than that of the epitaxial layer.

9. The silicon carbide power device according to claim 1, characterized in that, It also includes a buffer source region of a first conductivity type located below the first source region and the second source region, wherein the doping concentration of the buffer source region is lower than that of the first source region and the second source region.

10. The silicon carbide power device according to claim 1, characterized in that, Also includes: A first buffer source region of a first conductivity type is formed on the side of the first source region adjacent to the first channel region, and the doping concentration is lower than that of the first source region. A second buffer source region of the first conductivity type is formed on the side of the second source region adjacent to the second channel region, and the doping concentration is lower than that of the second source region. as well as The heavily doped region of the second conductivity type is disposed at the top of the first source region, the second source region, the first buffer source region, and the second buffer source region, forming a first saturated current cutoff region and a second saturated current cutoff region with the first body region and the second body region, respectively; and the heavily doped region is shorted to the source metal through the source contact region.

11. The silicon carbide power device according to claim 1, characterized in that, It also includes a shielded gate electrode, which is located in the lower part of the first top gate trench of the first type of gate trench, below the first gate electrode, and is isolated from the first gate electrode by a polysilicon inter-oxide layer.

12. The silicon carbide power device according to claim 1, characterized in that, The junction area and the first channel area are alternately formed along the sidewall of the first type of gate trench.

13. The silicon carbide power device according to claim 1, characterized in that, The first channel region is formed along the first sidewall of the first type of gate trench, and the junction region is formed along the second sidewall of the first type of gate trench, wherein the first sidewall and the second sidewall are opposite to each other.

14. The silicon carbide power device according to claim 1, characterized in that, It also includes a second shielding region of a second conductivity type, which is adjacent to the lower surface of the first body region and forms a saturated current cutoff region with the first shielding region to improve short-circuit capability.

15. The silicon carbide power device according to claim 1, characterized in that, It also includes a third shielding region of the second conductivity type, which is an L-shaped structure surrounding the sidewalls and part of the bottom region of the second type of gate trench and connected to the second body region to reduce the electric field of the second gate oxide layer.

16. The silicon carbide power device according to claim 1, characterized in that, It also includes a superjunction structure, which includes a pillar region of a second conductivity type located on a buffer layer of a first conductivity type. The buffer layer has a resistivity of Rb, is sandwiched between the substrate and the epitaxial layer, and the pillar region is connected to the first body region and the second body region, forming the superjunction structure with the epitaxial layer.

17. The silicon carbide power device according to claim 16, characterized in that, The substrate is of a first conductivity type, and the epitaxial layer is a single epitaxial layer with a uniform doping concentration, a resistivity of R, and R < Rb.

18. The silicon carbide power device according to claim 16, characterized in that, The substrate is of the second conductivity type, and the epitaxial layer is a single epitaxial layer with a uniform doping concentration, a resistivity of R, and R > Rb.

19. The silicon carbide power device according to claim 18, characterized in that, It also includes multiple heavily doped regions of a first conductivity type located within the substrate to form multiple alternating P+ and N+ regions in the substrate.

20. The silicon carbide power device according to claim 16, characterized in that, Also includes: At least two opposing sidewall shielding regions of a second conductivity type, wherein the doping concentration of the sidewall shielding regions is higher than that of the pillar regions, and the sidewall shielding regions are adjacent to the pillar regions and spaced apart from the first body region; as well as A junction field-effect transistor region of a first conductivity type is formed between the at least two sidewall shielding regions, the doping concentration of the junction field-effect transistor region being higher than the doping concentration of the epitaxial layer.

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