In-situ integration method and monolithic integrated device

Abstract

The invention discloses an in-situ integration method and a monolithic integrated device, and the in-situ integration method comprises the following steps: providing a substrate, and growing an epitaxial structure on the substrate; etching the epitaxial structure; preparing a first electrode on the step; forming a passivation layer on the epitaxial structure, and forming a hole in the first passivation layer; preparing a second electrode in the second through hole, and preparing a third electrode on the passivation layer; forming an active layer on the mesa; forming a dielectric layer at least on the mesa; and preparing a fourth electrode on the dielectric layer on the mesa. According to the in-situ integration method, the bonding step can be eliminated, the photoetching alignment frequency is reduced, the process complexity is reduced, meanwhile, the device performance can be improved, high pixel density is supported, and the cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of display device technology, specifically relating to an in-situ integration method and a monolithic integrated device. Background Technology

[0002] Micro-LEDs (micro-light-emitting diodes) are considered a core technology that will revolutionize the display industry due to their high brightness, high contrast, low power consumption, and long lifespan. However, their commercialization faces bottlenecks: existing technologies mostly adopt a "separate fabrication + bonding integration" approach, such as combining a TFT driving substrate with a Micro-LED epitaxial wafer through mass transfer technology. This approach requires multiple alignment, bonding, and packaging steps, resulting in a complex process and low yield. In particular, there is the problem of bonding misalignment at the micron level, and the difference in thermal expansion coefficients between the epitaxial material and the driving substrate can easily cause interface failures, affecting device reliability.

[0003] Thin-film transistor (TFT) technology has become an ideal driving solution for Micro-LEDs due to its advantages such as high-resolution driving, low power consumption, and compatibility with flexible substrates. However, traditional TFT driving solutions rely on a step-by-step process of "first preparing the TFT driving substrate, then transferring the Micro-LED", which is costly and difficult to break through the pixel density limit.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide an in-situ integration method and a monolithic integrated device. Summary of the Invention

[0005] The purpose of this invention is to provide an in-situ integration method and a monolithic integrated device, which can simplify the integration process and improve device performance.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] An in-situ integration method, the in-situ integration method comprising the following steps:

[0008] A substrate is provided on which an epitaxial structure is grown;

[0009] The epitaxial structure is etched to form steps in the etched area and a platform outside the etched area;

[0010] A first electrode is prepared on the step;

[0011] A passivation layer covering the step, the mesa and the first electrode is formed on the epitaxial structure, and the first passivation layer is perforated to form a first through hole extending to the first electrode and a second through hole extending to the mesa.

[0012] A second electrode is fabricated in the second through-hole, and a third electrode is fabricated on the passivation layer, wherein the third electrode is partially located above the mesa and partially located above the step;

[0013] An active layer covering a passivation layer, a second electrode, and part of a third electrode is formed on the platform.

[0014] A dielectric layer is formed at least on the platform surface;

[0015] A fourth electrode is fabricated on the dielectric layer of the said mesa.

[0016] In one or more embodiments of the present invention, the passivation layer is a SiO2 passivation layer, which is deposited using a PECVD process. In the deposition process, the flow ratio of the reactive gases SiH4 and N2O is 1:(2~4), the deposition temperature is 200℃~400℃, the radio frequency power is 100W~300W, the deposition rate is 20nm / min~40nm / min, and the deposition thickness is 200nm~400nm.

[0017] In one or more embodiments of the present invention, the step of forming an active layer on the mesa includes:

[0018] Carbon nanotubes are formed on the steps and the platform.

[0019] The carbon nanotubes above the steps are removed by oxygen plasma treatment. The power of the oxygen plasma treatment process is 50W~200W, the O2 flow rate is 10sccm~100sccm, and the treatment time is 10s~100s.

[0020] In one or more embodiments of the present invention, the step of forming carbon nanotubes on the step and the platform includes:

[0021] Single-walled carbon nanotubes are ultrasonically dispersed in toluene and xylene solutions, and carbon nanotubes are formed on the steps and the platform by dip-deposition, spin coating or inkjet printing.

[0022] The diameter of the single-walled carbon nanotubes is 1nm~2nm, the concentration of the toluene and xylene solution is 0.01mg / mL~0.1mg / mL, the absorbance of the ink in the immersion deposition process is 0.3~2.0, the rotation speed in the spin coating process is 2000rpm~4000rpm, the thickness is 5nm~20nm, and the droplet volume in the inkjet printing process is 10pL~50pL.

[0023] In one or more embodiments of the present invention, the step of forming a dielectric layer at least on the mesa includes:

[0024] A dielectric layer is formed on the platform and the step, the dielectric layer covering the active layer on the platform and the passivation layer and the third electrode on the step;

[0025] An opening is made in the dielectric layer on the step, a third through hole is formed in the first through hole to the first electrode, and a fourth through hole is formed above the third electrode on the step to the third electrode.

[0026] In one or more embodiments of the present invention, the dielectric layer is an HfO2 dielectric layer. In the formation process of the HfO2 dielectric layer, the precursor includes HfCl4 and H2O, the deposition temperature is 200℃~300℃, the number of cycles is 100~300 times, and the thickness is 10nm~30nm.

[0027] In one or more embodiments of the present invention, the epitaxial structure is a Micro-LED epitaxial structure, comprising an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer and a transparent conductive layer stacked sequentially, wherein the first electrode is in electrical contact with the N-type semiconductor layer on the step and the second electrode is in electrical contact with the transparent conductive layer on the mesa.

[0028] Another specific embodiment of the present invention provides the following technical solution:

[0029] A monolithic integrated device, the monolithic integrated device comprising:

[0030] Substrate;

[0031] An epitaxial structure is located on the substrate, wherein the epitaxial structure forms a step in a first region and a mesa outside the first region;

[0032] A passivation layer is located on the epitaxial structure and covers the steps and the platform;

[0033] An active layer is located on the mesa and covers part of the passivation layer;

[0034] A dielectric layer, at least located on the mesa and covering the active layer;

[0035] The first electrode is located on the step;

[0036] The second electrode penetrates the passivation layer and contacts the epitaxial structure, and is located below the active layer;

[0037] The third electrode is located on the passivation layer, and at least a portion of the third electrode is located on the mesa and below the active layer.

[0038] The fourth electrode is located on the dielectric layer of the mesa.

[0039] In one or more embodiments of the present invention, the epitaxial structure is a Micro-LED epitaxial structure, comprising an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer and a transparent conductive layer stacked sequentially, wherein the first electrode is in electrical contact with the N-type semiconductor layer on the step and the second electrode is in electrical contact with the transparent conductive layer on the mesa.

[0040] In one or more embodiments of the present invention, the passivation layer is a SiO2 passivation layer with a thickness of 200 nm to 400 nm; and / or,

[0041] The active layer is a carbon nanotube; and / or,

[0042] The dielectric layer is an HfO2 dielectric layer with a thickness of 10nm~30nm.

[0043] Compared with existing technologies, the in-situ integration method of the present invention can eliminate bonding steps, reduce the number of photolithography alignments, reduce process complexity, and at the same time improve device performance, support high pixel density, and reduce costs. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of the monolithic integrated device in this invention;

[0046] Figures 2a to 2k This is a process flow diagram of the in-situ integration method in this invention.

[0047] Explanation of key figure labels:

[0048] 11-Substrate, 12-N-type semiconductor layer, 13-Multiple quantum well layer, 14-P-type semiconductor layer, 15-Transparent conductive layer, 20-Passivation layer, 31-Active layer, 32-Dielectric layer, 41-First electrode, 42-Second electrode, 43-Third electrode, 44-Fourth electrode, 311-First via, 312-Second via, 321-Third via, 322-Fourth via. Detailed Implementation

[0049] To enable those skilled in the art to better understand the technical solutions in this disclosure, the following will clearly and completely describe the technical solutions in the embodiments of this disclosure in conjunction with the accompanying drawings in the embodiments of this disclosure. Obviously, the described embodiments are only a part of the embodiments of this disclosure, rather than all of the embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this disclosure.

[0050] In this invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature has a lower horizontal height than the second feature.

[0051] As Figure 1 shown, this invention provides a monolithic integrated device, comprising:

[0052] a substrate 11;

[0053] an epitaxial structure, located on the substrate 11, the epitaxial structure forming a step in a first region and forming a mesa outside the first region;

[0054] a passivation layer 20, located on the epitaxial structure and covering the step and the mesa;

[0055] an active layer 31, located on the mesa and covering a part of the passivation layer 20;

[0056] a dielectric layer 32, at least located on the mesa and covering the active layer 31;

[0057] a first electrode 41, located on the step;

[0058] a second electrode 42, passing through the passivation layer 20 and contacting the epitaxial structure, and located below the active layer 31;

[0059] a third electrode 43, located on the passivation layer 20, at least part of the third electrode 43 is located on the mesa and below the active layer 31;

[0060] a fourth electrode 44, located on the dielectric layer 32 on the mesa.

[0061] In some embodiments, the epitaxial structure is a Micro-LED epitaxial structure, including an N-type semiconductor layer 12, a multiple quantum well layer 13, a P-type semiconductor layer 14 and a transparent conductive layer 15 stacked sequentially. The first electrode 41 is in electrical contact with the N-type semiconductor layer 12 on the step, and the second electrode 42 is in electrical contact with the transparent conductive layer 15 on the mesa.

[0062] For example, substrate 11 can be a sapphire patterned substrate (PSS); N-type semiconductor layer 12 can be Si-doped with a doping concentration of 5E18cm⁻¹. -3 The thickness is 3 μm; the multiple quantum well layer 13 can be an InGaN / GaN multiple quantum well layer, grown in 5 alternating periods, including a 2.5 nm thick In... 0.2 Ga 0.8 An N-well layer and a 12 nm thick GaN barrier layer; the P-type semiconductor layer 14 can be Mg-doped with a doping concentration of 1E20 cm⁻¹. -3 The thickness is 200nm.

[0063] In some embodiments, the passivation layer 20 is a SiO2 passivation layer with a thickness of 200nm~400nm; the active layer 31 is a carbon nanotube; and the dielectric layer 32 is an HfO2 dielectric layer with a thickness of 10nm~30nm.

[0064] The following detailed description of the monolithic integrated device and in-situ integration method of the present invention is provided in conjunction with specific embodiments.

[0065] In a specific embodiment of the present invention, the in-situ integration method of a monolithic integrated device includes the following steps:

[0066] S1, Reference Figure 2a As shown, a substrate 11 is provided, on which an epitaxial structure is grown.

[0067] In this embodiment, the substrate 11 is a sapphire substrate, for example, a 2-inch sapphire patterned substrate (PSS).

[0068] In some embodiments, the substrate 11 may be cleaned before epitaxial growth on the substrate, for example, by ultrasonic cleaning with acetone / isopropanol.

[0069] In some embodiments, the epitaxial structure can be a Micro-LED epitaxial structure, which is GaN-based epitaxial growth performed in an MOCVD reaction chamber and may include an N-type semiconductor layer 12, a multiple quantum well layer 13, a P-type semiconductor layer 14, and a transparent conductive layer 15 stacked sequentially.

[0070] For example, the epitaxial structure in this embodiment is a GaN-based Micro-LED epitaxial structure, and the parameters of each layer are as follows:

[0071] The N-type semiconductor layer 12 is an N-type GaN layer with a thickness of 3 μm, doped with Si at a doping concentration of 5E18cm⁻¹. -3 ;

[0072] The multi-quantum well layer 13 is an InGaN / GaN multi-quantum well layer, grown in 5 alternating periods, including a 2.5nm thick In... 0.2 Ga 0.8 N-well layer and 12nm thick GaN barrier layer;

[0073] The p-type semiconductor layer 14 is Mg-doped with a doping concentration of 1E20cm⁻¹. -3 The thickness is 200nm.

[0074] S2, Reference Figure 2b As shown, the epitaxial structure is etched, forming steps in the etched area and a platform outside the etched area.

[0075] First, AZ5214 photoresist was spin-coated onto the surface of the epitaxial structure at a spin speed of 3000 rpm for 30 seconds. The area was then defined as 20*20 μm using UV lithography. 2 Tabletop array, Figure 2b S1 is the etched area, also known as the step area, and S2 is the platform area outside the etched area.

[0076] Then, an ICP dry etching process was used, with etching gases including Cl2 and BCl3 in a flow ratio of 2:1, a cavity pressure of 5 mTorr, an RF power of 400 W, a bias power of 80 W, and an etching depth of 800 nm, until the N-type semiconductor layer 12 was exposed.

[0077] S3, Reference Figure 2c As shown, the first electrode 41 is fabricated on the step.

[0078] The first electrode 41 is electrically connected to the N-type semiconductor layer 12. The fabrication method of the first electrode 41 specifically includes:

[0079] First, a Ti / Al / Ti / Au composite metal layer was deposited using an electron beam evaporation process, with thicknesses of 50 nm, 100 nm, 50 nm, and 200 nm for each layer.

[0080] Then, the first electrode 41, which is the N electrode of the Micro-LED, is formed by a peeling process (acetone ultrasonication for 10 minutes).

[0081] Finally, the first electrode 41 was subjected to rapid thermal annealing in a nitrogen atmosphere and held at 500°C for 30 seconds.

[0082] S4, Reference Figure 2d As shown, a passivation layer 20 covering the steps, mesas, and the first electrode 41 is formed on the epitaxial structure.

[0083] Specifically, the passivation layer 20 is a SiO2 passivation layer, which is deposited using a PECVD process. In the deposition process, the flow ratio of the reaction gases SiH4 and N2O is 1:(2~4), the deposition temperature is 200℃~400℃, the RF power is 100W~300W, the deposition rate is 20nm / min~40nm / min, and the deposition thickness is 200nm~400nm.

[0084] For example, in this embodiment, the SiO2 passivation layer is deposited using an OXFORD Plasmalab 800+ device. The flow ratio of the reaction gases SiH4 and N2O in the deposition process is 1:3, the deposition temperature is 300℃, the radio frequency power is 200W, the deposition rate is 30nm / min, and the deposition thickness is 300nm.

[0085] S5, Participant Figure 2e As shown, the passivation layer 20 is perforated to form a first through hole 311 extending to the first electrode 41 and a second through hole 312 extending to the mesa.

[0086] For example, in this embodiment, the RIE etching process is used to open the hole. The reaction gas in the etching process is CF4 and O2 with a flow ratio of 4:1, the cavity pressure is 100mTorr, the power is 150W, the etching time is 120s, the diameter of the first through hole 311 is 2μm, and the diameter of the second through hole 312 is 1.5μm.

[0087] S6, Participant Figure 2f As shown, a second electrode 42 is prepared in the second through hole 312, and a third electrode 43 is prepared on the passivation layer 20. The third electrode 43 is partially located above the mesa and partially located above the step.

[0088] The second electrode 42 is electrically connected to the P-type semiconductor layer 14 through the transparent conductive layer 15. The second electrode 42 serves as the P-electrode of the Micro-LED and can also serve as the source of the subsequent TFT driving network. The third electrode 43 serves as the drain of the subsequent TFT driving network. The specific methods for fabricating the second electrode 42 and the third electrode 43 include:

[0089] First, a Cr / Au composite metal layer was deposited using a magnetron sputtering process, with each layer having a thickness of 10 nm and 70 nm, respectively.

[0090] Subsequently, a peeling process is used to form the second electrode 42 and the third electrode 43. The second electrode 42 forms an ohmic contact with the P-type semiconductor layer 14 through the second through-hole 312, with a contact resistance not greater than 1E-4 Ω·cm. 2 .

[0091] S7, Reference Figure 2g ,2h As shown, an active layer 31 is formed on the mesa, covering the passivation layer 20, the second electrode 42, and part of the third electrode 43.

[0092] First of all, participants Figure 2g As shown, carbon nanotubes are formed on the steps and platforms.

[0093] Specifically, single-walled carbon nanotubes (SWCNTs) are ultrasonically dispersed in a toluene and xylene solution, and carbon nanotubes are formed on the steps and the platform by dip-deposition, spin-coating or inkjet printing.

[0094] The diameter of the single-walled carbon nanotubes is 1nm~2nm, the concentration of the toluene and xylene solution is 0.01mg / mL~0.1mg / mL, the absorbance of the ink in the immersion deposition process is 0.3~2.0, the rotation speed in the spin coating process is 2000rpm~4000rpm, the thickness is 5nm~20nm, and the droplet volume in the inkjet printing process is 10pL~50pL.

[0095] Then, participate Figure 2h As shown, an oxygen plasma treatment process is used to remove carbon nanotubes above the steps. The power of the oxygen plasma treatment process is 50W~200W, the O2 flow rate is 10sccm~100sccm, and the treatment time is 10s~100s.

[0096] Ultimately, the aspect ratio (W / L) of the trench dimensions is 10 μm / 5 μm.

[0097] S8, Participant Figure 2i As shown, a dielectric layer 32 is formed on the tabletop and steps.

[0098] Specifically, a dielectric layer 32 is formed on the platform and the step, and the dielectric layer 32 covers the active layer 31 on the platform and the passivation layer 20 and the third electrode 43 on the step.

[0099] The dielectric layer is an HfO2 dielectric layer. In the formation process of the HfO2 dielectric layer, the precursors include HfCl4 and H2O, the deposition temperature is 200℃~300℃, the number of cycles is 100~300 times, and the thickness is 10nm~30nm.

[0100] For example, in this embodiment, the deposition temperature is 250°C, the number of cycles is 200, the thickness is 20nm, and the dielectric constant k of the HfO2 dielectric layer is 22.

[0101] S9, Participant Figure 2j As shown, a fourth electrode 44 is fabricated on the dielectric layer 32 on the mesa.

[0102] The fourth electrode 44 serves as the gate of the TFT driving network, and its fabrication method is as follows:

[0103] First, the fourth electrode 44 was prepared by radio frequency sputtering. The target material composition was In2O3:SnO2=90:10 wt%. The process parameters were Ar flow rate of 20 sccm, power of 150W, deposition rate of 0.3 Å / s, and deposition thickness of 150 nm.

[0104] The fourth electrode 44 was then annealed, specifically at 250°C in a nitrogen atmosphere for 30 minutes. After annealing, the sheet resistance of the fourth electrode 44 was no greater than 20 Ω / square.

[0105] S9, Participant Figure 2k As shown, a hole is made in the dielectric layer 32 on the step, a third through hole 321 is formed in the first through hole 311 to penetrate to the first electrode 41, and a fourth through hole 322 is formed above the third electrode 43 on the step to penetrate to the third electrode 43.

[0106] The opening of dielectric layer 32 can be performed using the RIE etching process in step S5, which will not be described in detail here.

[0107] It should be understood that step S9 can be performed after step S8 or before step S8.

[0108] This invention uses an in-situ integration method to fabricate monolithic integrated devices, which has the following advantages:

[0109] The process is simplified. The TFT driving network adopts a low-temperature process, and in-situ integration eliminates bonding steps, reduces the number of photolithography alignments, and reduces process complexity.

[0110] High pixel density, TFT driving network is directly 3D fabricated on the Micro-LED mesa, saving space, reducing signal delay caused by complex interconnect wires, and supporting micron-level pixel arrays;

[0111] Performance is improved by using carbon nanotubes (CNTs) as the active layer in the TFT driving network. The high mobility of CNTs ensures fast TFT response. The top-gate TFT structure and passivation post-treatment enable the device to exhibit excellent optical, thermal, and electrical bias stability. At the same time, the passivation layer protects the Micro-LED from damage in subsequent processes.

[0112] Transparent display: Active-drive transparent display can be achieved using a single integrated device;

[0113] Cost advantage: Integrated processes reduce material waste and equipment investment.

[0114] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0115] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An in-situ integration method, characterized in that, The in-situ integration method includes the following steps: A substrate is provided on which an epitaxial structure is grown; The epitaxial structure is etched to form steps in the etched area and a platform outside the etched area; A first electrode is prepared on the step; A passivation layer covering the step, the mesa and the first electrode is formed on the epitaxial structure, and the first passivation layer is perforated to form a first through hole extending to the first electrode and a second through hole extending to the mesa. A second electrode is fabricated in the second through-hole, and a third electrode is fabricated on the passivation layer, wherein the third electrode is partially located above the mesa and partially located above the step; An active layer covering a passivation layer, a second electrode, and part of a third electrode is formed on the platform. A dielectric layer is formed at least on the platform surface; A fourth electrode is fabricated on the dielectric layer of the said mesa.

2. The in-situ integration method according to claim 1, characterized in that, The passivation layer is a SiO2 passivation layer, which is deposited using a PECVD process. In the deposition process, the flow ratio of the reactive gases SiH4 and N2O is 1:(2~4), the deposition temperature is 200℃~400℃, the radio frequency power is 100W~300W, the deposition rate is 20nm / min~40nm / min, and the deposition thickness is 200nm~400nm.

3. The in-situ integration method according to claim 1, characterized in that, The step of forming an active layer on the mesa includes: Carbon nanotubes are formed on the steps and the platform. The carbon nanotubes above the steps are removed by oxygen plasma treatment. The power of the oxygen plasma treatment process is 50W~200W, the O2 flow rate is 10sccm~100sccm, and the treatment time is 10s~100s.

4. The in-situ integration method according to claim 3, characterized in that, The steps for forming carbon nanotubes on the steps and the platform include: Single-walled carbon nanotubes are ultrasonically dispersed in a toluene and xylene solution, and carbon nanotubes are formed on the steps and the platform by dip-deposition, spin coating or inkjet printing. The diameter of the single-walled carbon nanotubes is 1nm~2nm, the concentration of the toluene and xylene solution is 0.01mg / mL~0.1mg / mL, the absorbance of the ink in the immersion deposition process is 0.3~2.0, the rotation speed in the spin coating process is 2000rpm~4000rpm, the thickness is 5nm~20nm, and the droplet volume in the inkjet printing process is 10pL~50pL.

5. The in-situ integration method according to claim 1, characterized in that, The step of forming a dielectric layer at least on the mesa includes: A dielectric layer is formed on the platform and the step, the dielectric layer covering the active layer on the platform and the passivation layer and the third electrode on the step; An opening is made in the dielectric layer on the step, a third through hole is formed in the first through hole to the first electrode, and a fourth through hole is formed above the third electrode on the step to the third electrode.

6. The in-situ integration method according to claim 5, characterized in that, The dielectric layer is an HfO2 dielectric layer. In the formation process of the HfO2 dielectric layer, the precursors include HfCl4 and H2O, the deposition temperature is 200℃~300℃, the number of cycles is 100~300 times, and the thickness is 10nm~30nm.

7. The in-situ integration method according to claim 1, characterized in that, The epitaxial structure is a Micro-LED epitaxial structure, comprising an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer, and a transparent conductive layer stacked sequentially. The first electrode is in electrical contact with the N-type semiconductor layer on the step, and the second electrode is in electrical contact with the transparent conductive layer on the mesa.

8. A monolithic integrated device, characterized in that, The monolithic integrated device includes: Substrate; An epitaxial structure is located on the substrate, wherein the epitaxial structure forms a step in a first region and a mesa outside the first region; A passivation layer is located on the epitaxial structure and covers the steps and the platform; An active layer is located on the mesa and covers part of the passivation layer; A dielectric layer, at least located on the mesa and covering the active layer; The first electrode is located on the step; The second electrode penetrates the passivation layer and contacts the epitaxial structure, and is located below the active layer; The third electrode is located on the passivation layer, and at least a portion of the third electrode is located on the mesa and below the active layer. The fourth electrode is located on the dielectric layer of the mesa.

9. The monolithic integrated device according to claim 8, characterized in that, The epitaxial structure is a Micro-LED epitaxial structure, comprising an N-type semiconductor layer, a multiple quantum well layer, a P-type semiconductor layer, and a transparent conductive layer stacked sequentially. The first electrode is in electrical contact with the N-type semiconductor layer on the step, and the second electrode is in electrical contact with the transparent conductive layer on the mesa.

10. The monolithic integrated device according to claim 8, characterized in that, The passivation layer is a SiO2 passivation layer with a thickness of 200nm~400nm; and / or, The active layer is a carbon nanotube; and / or, The dielectric layer is an HfO2 dielectric layer with a thickness of 10nm~30nm.

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