Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising: having a first side and a second side for display, comprising: a substrate; a display area comprising a first display area and a second display area, the first display area comprising a plurality of pixel unit groups, each of the plurality of pixel unit groups comprising a plurality of first pixel units, each of the plurality of first pixel units comprising a pixel area and an opening area; a plurality of first power lines located in the pixel area; a shielding layer comprising a hollow area and a shielding area; for a pixel unit group, the opening area of each first pixel unit at least partially overlaps the shielding area of the shielding layer, the opening area of at least one first pixel unit comprises a first shielding connecting portion, at least partially overlaps the shielding area of the shielding layer, and the shielding layer is connected by the first shielding connecting portion and at least one of the plurality of first power lines. The display substrate can connect a direct current signal to the shielding layer without reducing the pixel density, preventing the shielding layer from being in a floating state.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0002] Under-display camera designs typically include high pixel density (Pixels Per Inch, PPI) areas and low PPI areas. However, the light transmittance of low PPI areas in typical display panels is low, which is not conducive to improving the display effect of the camera in the imaging area. Summary of the Invention

[0003] This disclosure provides at least one embodiment of a display substrate having a first side for display and a second side opposite to the first side, comprising: a substrate; a display area disposed on the substrate, including a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate for sensing, the first display area including a plurality of pixel unit groups arranged at intervals, each of the plurality of pixel unit groups including a plurality of first pixel units, each of the plurality of first pixel units including a pixel area and an opening area; a plurality of first power lines located in the pixel area and configured to be connected to the plurality of pixel unit groups to provide a first power supply voltage to the plurality of pixel unit groups; and a shielding layer disposed on the substrate. On the substrate, and located on the side of the first power line near the substrate, there are a cutout area and a shielding area; for a pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the shielding area of ​​the shielding layer, the opening area of ​​at least one first pixel unit includes a first shielding connection portion, which at least partially overlaps with the shielding area of ​​the shielding layer, and the shielding layer is connected to at least one of the plurality of first power lines through the first shielding connection portion to receive the first power supply voltage; the plurality of first power lines are located on the side of the first shielding connection portion away from the substrate, the shielding layer is located on the side of the first shielding connection portion near the substrate, and the first shielding connection portion is located between the shielding layer and the plurality of first power lines.

[0004] For example, in a display substrate provided in at least one embodiment of this disclosure, the shielding layer is connected to the first shielding connection portion through a first via, and the first shielding connection portion is connected to the at least one first power line through a second via.

[0005] For example, in at least one embodiment of the display substrate provided in this disclosure, the display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is located between the shielding layer and the first shielding connection portion, the second insulating layer is located between the first insulating layer and the first shielding layer connection portion, and the third insulating layer is located between the first shielding connection portion and the plurality of first power lines; or, the second insulating layer is located between the first shielding connection portion and the plurality of first power lines, the third insulating layer is located between the second insulating layer and the plurality of first power lines, the shielding layer is connected to the first shielding connection portion through a first via penetrating the first insulating layer, and the first shielding connection portion is connected to the at least one first power line through a second via penetrating the second and third insulating layers; or, the shielding layer is connected to the first shielding connection portion through a first via penetrating the first and second insulating layers, and the first shielding connection portion is connected to the at least one first power line through a second via penetrating the third insulating layer.

[0006] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projections of the first via and the second via on the substrate do not overlap; the first power line includes a protrusion, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the protrusion on the substrate, and the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first power line on the substrate.

[0007] For example, in a display substrate provided in at least one embodiment of this disclosure, adjacent pixel unit groups are connected by traces, and the orthographic projection of the plurality of pixel unit groups and the traces on the substrate falls within the orthographic projection of the shielding area of ​​the shielding layer on the substrate.

[0008] For example, in a display substrate provided in at least one embodiment of this disclosure, the second display area includes a plurality of second pixel units arranged in an array and a plurality of second power lines. Each of the plurality of second pixel units includes a pixel area and an opening area. The plurality of second power lines are configured to be connected to the plurality of second pixel units to provide a second power supply voltage to the plurality of second pixel units. The second power supply voltage is the same as the first power supply voltage. For a second pixel unit, the opening area of ​​each second pixel unit at least partially overlaps with the blocking area of ​​the blocking layer. The opening area of ​​the at least one second pixel unit includes a second blocking connection portion, and the second blocking connection portion at least partially overlaps with the blocking area of ​​the blocking layer.

[0009] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the second display area on the substrate falls within the orthographic projection of the shielding area of ​​the shielding layer on the substrate.

[0010] For example, in a display substrate provided in at least one embodiment of this disclosure, each of the plurality of first pixel units and the plurality of second pixel units includes a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit is configured to drive the light-emitting device to emit light.

[0011] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, and a storage capacitor; the active layers of the first reset transistor, the compensation transistor, the second light-emitting control transistor, and the second reset transistor are located on a first semiconductor layer extending along a first direction, and the active layers of the data writing transistor and the first light-emitting control transistor are located on a second semiconductor layer extending along a second direction. The first semiconductor layer and the second semiconductor layer are connected and integrally formed through the active layer of the driving transistor. The active layer of the driving transistor is located on an imaginary line of the active layer of the first reset transistor in the first direction. The active layers of the compensation transistor and the data writing transistor are respectively located on both sides of the active layer of the driving transistor, and are located on the side of the active layer of the driving transistor closer to the active layer of the first reset transistor. The active layers of the second light-emitting control transistor and the first light-emitting control transistor are respectively located on both sides of the active layer of the driving transistor, and are located on the side of the active layer of the driving transistor away from the active layer of the first reset transistor. The active layer of the second reset transistor is located on the side of the active layer of the second light-emitting control transistor away from the active layer of the compensation transistor. The compensation transistor includes a first gate extending along the first direction and a second gate extending along the second direction. The second gate, the gate of the second light-emitting control transistor extending along the second direction, and the gate of the second reset transistor are arranged side by side in the first direction. The gate of the data writing transistor and the gate of the first light-emitting control transistor extend along the second direction and are arranged side by side in the first direction. The gate of the first reset transistor and the gate of the driving transistor extend along the second direction and are arranged side by side in the first direction. The gate of the driving transistor is integrally formed with the first plate of the storage capacitor.

[0012] For example, the display substrate provided in at least one embodiment of this disclosure further includes a gate line, a light emission control signal line, a first reset signal line, and a second reset signal line extending along the second direction. The gate of the first reset transistor and the first reset signal line are connected and integrally formed. The second gate of the compensation transistor and the gate of the data writing transistor are connected to the gate line and integrally formed. The gate of the second light emission control transistor and the gate of the first light emission control transistor are connected to the light emission control signal line and integrally formed. The gate of the second reset transistor is connected to the second reset signal line and integrally formed.

[0013] For example, at least one embodiment of the display substrate provided in this disclosure further includes a data line, wherein the data line is connected to the active layer of the data writing transistor and configured to provide a data signal, the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projections of the active layer of the first reset transistor and the active layer of the driving transistor on the substrate, and the orthographic projection of the data line on the substrate is located on the side of the second semiconductor layer on the substrate away from the orthographic projection of the first power line on the substrate.

[0014] For example, in a display substrate provided in at least one embodiment of this disclosure, the pixel driving circuit further includes a first transition electrode. The first transition electrode is connected to the active layer of the second light-emitting control transistor, the active layer of the second reset transistor, and the first electrode of the light-emitting device through a via. The orthographic projection of the first transition electrode on the substrate is located between the orthographic projections of the active layer of the second reset transistor and the active layer of the driving transistor on the substrate.

[0015] For example, in a display substrate provided in at least one embodiment of the present disclosure, for each of the plurality of second pixel units, the orthographic projection of the second shielding connection portion on the substrate is located between the orthographic projection of the active layer of the second reset transistor on the substrate and the orthographic projection of the second power line on the substrate, and at least partially overlaps with the orthographic projection of the second power line on the substrate.

[0016] For example, in a display substrate provided in at least one embodiment of this disclosure, for each pixel unit group, the first blocking connection portion is located between two adjacent first pixel units in the first direction in each pixel unit group.

[0017] For example, in a display substrate provided in at least one embodiment of this disclosure, the orthographic projection of the first shielding connection portion on the substrate is located between the orthographic projection of the active layer of the second reset transistor on the substrate and the orthographic projection of the first power line on the substrate, and at least partially overlaps with the orthographic projection of the first power line on the substrate.

[0018] For example, in a display substrate provided in at least one embodiment of this disclosure, the first shielding connection portion is located at both ends of each pixel unit group, and is connected to at least one of the multiple first power lines corresponding to each pixel unit group.

[0019] For example, in a display substrate provided in at least one embodiment of this disclosure, the first blocking connection portion is located at one end of each pixel unit group and is connected to at least one of the multiple first power lines corresponding to the pixel unit group.

[0020] For example, the display substrate provided in at least one embodiment of this disclosure further includes a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; the first conductive layer includes the gate line, the second conductive layer includes the second electrode of the storage capacitor, and the third conductive layer includes the first power line. In a direction perpendicular to the substrate, the fourth insulating layer is located between the shielding layer and the active layer of the transistor, the first insulating layer is located between the active layer and the first conductive layer, the second insulating layer is located between the gate line and the second conductive layer, and the third insulating layer is located between the second electrode of the storage capacitor and the third conductive layer.

[0021] For example, in a display substrate provided in at least one embodiment of this disclosure, the first shielding connection portion is located in the first conductive layer or the second conductive layer.

[0022] At least one embodiment of this disclosure also provides a display device, including a display substrate and a sensor provided in any embodiment of this disclosure, wherein the sensor is disposed on a second side of the display substrate and the sensor is configured to receive light from a first side of the display substrate; the orthographic projection of the sensor on the substrate at least partially overlaps with the first display area. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0024] Figure 1A A plan view of a display substrate provided for at least one embodiment of this disclosure;

[0025] Figure 1B This is a partially enlarged schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0026] Figure 1C This is a partially enlarged schematic diagram of a display substrate provided for at least another embodiment of this disclosure;

[0027] Figure 1D For along Figure 1A A schematic diagram of the cross-section of line B1-B2 shown in the figure;

[0028] Figure 2 A schematic diagram of the pixel unit arrangement of a second display area provided for at least one embodiment of this disclosure;

[0029] Figure 3 A schematic diagram of the first display area of ​​a display panel provided in at least one embodiment of this disclosure;

[0030] Figure 4 This is a schematic diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0031] Figure 5 A schematic diagram of a pixel driving circuit provided for at least one embodiment of this disclosure;

[0032] Figure 6A for Figure 5 A schematic diagram of a stacked structure of the pixel driving circuit shown;

[0033] Figure 6B for Figure 5 A schematic diagram of another stacked structure of the pixel driving circuit shown;

[0034] Figure 7 A schematic cross-sectional view along line AA' provided in at least one embodiment of this disclosure;

[0035] Figure 8 for Figure 6A A plan view of the semiconductor pattern of the display substrate shown;

[0036] Figure 9 for Figure 6A The diagram shows a plan view of the first conductive layer of the display substrate.

[0037] Figure 10 for Figure 6A The diagram shows a plan view of the second conductive layer of the display substrate.

[0038] Figure 11 for Figure 6A The diagram shows a plan view of the third conductive layer of the display substrate.

[0039] Figure 12AA schematic diagram illustrating an example of a display substrate provided in at least one embodiment of this disclosure;

[0040] Figure 12B for Figure 12A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown.

[0041] Figure 12C for Figure 12A A plan view of the semiconductor pattern of the display substrate shown;

[0042] Figure 12D for Figure 12A The diagram shows a plan view of the first conductive layer of the display substrate.

[0043] Figure 12E for Figure 12A The diagram shows a plan view of the second conductive layer of the display substrate.

[0044] Figure 12F for Figure 12A The diagram shows a plan view of the third conductive layer of the display substrate.

[0045] Figure 13A A schematic diagram illustrating an example of another display substrate provided in at least one embodiment of this disclosure;

[0046] Figure 13B for Figure 13A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown.

[0047] Figure 13C for Figure 13A A plan view of the semiconductor pattern of the display substrate shown;

[0048] Figure 13D for Figure 13A The diagram shows a plan view of the first conductive layer of the display substrate.

[0049] Figure 13E for Figure 13A The diagram shows a plan view of the second conductive layer of the display substrate.

[0050] Figure 13F for Figure 13A The diagram shows a plan view of the third conductive layer of the display substrate.

[0051] Figure 14A A schematic diagram illustrating another example of a display substrate provided in at least one embodiment of this disclosure;

[0052] Figure 14B for Figure 14A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown.

[0053] Figure 14C for Figure 14A A plan view of the semiconductor pattern of the display substrate shown;

[0054] Figure 14D for Figure 14A The diagram shows a plan view of the first conductive layer of the display substrate.

[0055] Figure 14E for Figure 14A The diagram shows a plan view of the second conductive layer of the display substrate.

[0056] Figure 14F for Figure 14A The diagram shows a plan view of the third conductive layer of the display substrate.

[0057] Figure 15A A schematic diagram illustrating another example of a display substrate provided in at least one embodiment of this disclosure;

[0058] Figure 15B for Figure 15A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown.

[0059] Figure 15C for Figure 15A A plan view of the semiconductor pattern of the display substrate shown;

[0060] Figure 15D for Figure 15A The diagram shows a plan view of the first conductive layer of the display substrate.

[0061] Figure 15E for Figure 15A The diagram shows a plan view of the second conductive layer of the display substrate.

[0062] Figure 15F for Figure 15A The diagram shows a plan view of the third conductive layer of the display substrate.

[0063] Figure 16 This is a schematic diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0065] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0066] OLED (Organic Light-Emitting Diode) display technology is highly competitive in the display industry due to its advantages such as wide viewing angles, high contrast, fast response, low power consumption, foldability, and flexibility. With the widespread development and application of OLED technology, the demand for displays with high screen-to-body ratios is becoming increasingly strong. Under-display camera technology, where the front-facing camera is located under the screen, eliminates the notch area for the front-facing camera, increasing the screen-to-body ratio and providing a superior visual experience.

[0067] To allow more light to pass through the display panel and reach the front-facing camera, it is necessary to reduce the PPI of the screen's light-transmitting display area, i.e., reduce the pixel density. However, there are many slits between the pixel circuit traces and between the signal lines connecting the pixels. When light passes through these slits, diffraction and interference occur, resulting in uneven brightness when the light reaches the camera, causing glare (excessive brightness in a certain area of ​​the field of view or excessive brightness changes from front to back), reducing the visibility of objects, reducing the image quality of the camera, and easily causing eye fatigue.

[0068] Currently, one solution is to add a metal layer as a shielding layer to block the pixel circuits and wiring, preventing light from interfering with these slits. However, because these metal layers are in a floating state, they can interfere with the signals of the pixel circuits, affecting the display effect. Therefore, it is necessary to pass a DC signal through these metal layers to stabilize the voltage. However, if a hole is directly drilled in the pixel circuit for connection, space is needed to place the connection hole, which will increase the pixel size and reduce the screen resolution; if the connection is only made from the IC (Integrated Chip) end, it will cause a large voltage drop in the wiring, affecting the display quality.

[0069] At least one embodiment of this disclosure provides a display substrate having a first side for display and a second side opposite to the first side, comprising: a substrate; a display area disposed on the substrate, including a first display area and a second display area at least partially surrounding the first display area, the first display area allowing light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate for sensing, the first display area including a plurality of pixel unit groups arranged at intervals, each of the plurality of pixel unit groups including a plurality of first pixel units, each of the plurality of first pixel units including a pixel area and an opening area; and a plurality of first power lines located in the pixel areas and configured to be connected to the plurality of pixel unit groups to provide first power to the plurality of pixel unit groups. Voltage; a shielding layer, disposed on a substrate and located on the side of the first power line near the substrate, including a cutout area and a shielding area; for a pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the shielding area of ​​the shielding layer, the opening area of ​​at least one first pixel unit includes a first shielding connection portion, which at least partially overlaps with the shielding area of ​​the shielding layer, and the shielding layer is connected to at least one of the multiple first power lines through the first shielding connection portion to receive the first power supply voltage; the multiple first power lines are located on the side of the first shielding connection portion away from the substrate, the shielding layer is located on the side of the first shielding connection portion near the substrate, and the first shielding connection portion is located between the shielding layer and the multiple first power lines.

[0070] The display substrate provided in this embodiment can connect a DC signal to the shielding layer without reducing the pixel density, preventing the shielding layer from being in a floating state, preventing signal jumps in the shielding layer from interfering with the pixel driving circuit, and reducing the voltage drop of the first power line, thereby improving the display quality of the display panel.

[0071] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0072] Figure 1A A plan view of a display substrate provided for at least one embodiment of this disclosure; Figure 1B This is a partially enlarged schematic diagram of a display substrate provided in at least one embodiment of the present disclosure; Figure 1C This is a partially enlarged schematic diagram of a display substrate provided for at least another embodiment of this disclosure; Figure 1D For along Figure 1A A schematic diagram of the cross-section along the centerline B1-B2.

[0073] For example, such as Figure 1AAs shown, at least one embodiment of this disclosure provides a display substrate 1 including a substrate 100 and a display area. The display area is disposed on the substrate 100 and includes a first display area 10 (e.g., a light-transmitting display area) and a second display area 20 (e.g., a normal display area). The display substrate 1 may also include a peripheral area 30 surrounding (e.g., partially surrounding) the display area. The second display area 20 surrounds (e.g., partially surrounding) the first display area 10.

[0074] For example, the display substrate 1 provided in at least one embodiment of this disclosure can be an organic light-emitting diode (OLED) display substrate or a quantum dot light-emitting diode (QLED) display substrate, etc. The embodiments of this disclosure do not limit the specific type of display substrate.

[0075] For example, such as Figure 1D As shown, the first display area 10 is a light-transmitting display area, meaning that light from the first side S1 (e.g., the display side) of the display substrate 1 is at least partially transmitted to the second side S2 (e.g., the non-display side) of the display substrate 1. In other words, incident light from the display side is transmitted through the first display area 10 to reach the non-display side of the display substrate 1. A sensor 192 can also be disposed on the second side S2 of the display substrate 1 to receive the transmitted light, thereby realizing corresponding functions (e.g., imaging, infrared sensing, distance sensing, etc.). For example, the sensor 192 is disposed on the second side S2 of the display substrate 1, and its orthographic projection onto the substrate 100 at least partially overlaps with the first display area 10, and it is configured to receive and process light from the first side S1 of the display substrate 1. The light from the first side S1 of the display substrate 1 can be collimated light along the normal direction of the display substrate 1 (e.g., the Z1 direction) or decollimated light.

[0076] For example, sensor 192 can be an image sensor, an infrared sensor, a distance sensor, etc., and sensor 192 can be implemented in the form of a chip, etc. Sensor 192 is disposed on the second side S2 (the side away from the user) of display substrate 1. Sensor 192 and the first display area 10 overlap at least partially in the normal direction of the display surface of the display substrate.

[0077] For example, sensor 192 can be an image sensor, used to acquire images of the external environment facing the light-collecting surface of sensor 192, such as a CMOS image sensor or a CCD image sensor; sensor 192 can also be an infrared sensor, a distance sensor, etc. Sensor 192 can be used to implement cameras in mobile terminals such as mobile phones and laptops, and may further include optical devices such as lenses, mirrors, or optical waveguides to modulate the light path as needed. The embodiments of this disclosure do not limit the type, function, or arrangement of sensor 192.

[0078] Sensor 192 is mounted on the first side S2 of the display substrate using double-sided adhesive or similar means, and the orthographic projection of sensor 192 on the substrate 100 at least partially overlaps with the first display area 10, configured to receive light from the first side S1. Thus, the first display area 10 not only enables display but also facilitates the mounting of sensor 192.

[0079] For example, such as Figure 1B as well as Figure 1C As shown, the first display area 10 includes a first sub-pixel array (composed of gray boxes in the first display area 10). The first sub-pixel array includes multiple pixel unit groups P1 (gray boxes in the first display area 10) arranged in a first direction Y1 and a second direction X1 intersecting the first direction Y1. Each of the multiple pixel unit groups P1 includes at least one first pixel unit (e.g., multiple first pixel units) (described in detail later). The first pixel unit includes a first light-emitting device and a first pixel driving circuit directly connected to each other. The first pixel driving circuit is configured to drive the first light-emitting device to emit light. The first light-emitting device and the first pixel driving circuit are located in the same pixel region and are not separated from each other in position.

[0080] It should be noted that the first direction Y1 and the second direction X1 may or may not intersect perpendicularly. For example, the acute angle at which the first direction Y1 and the second direction X1 intersect can be less than or equal to 10° and greater than or equal to 45°. The accompanying drawings of this embodiment illustrate an example where the first direction Y1 and the second direction X1 intersect perpendicularly.

[0081] There are gaps between multiple pixel unit groups P1 that allow light to pass through, i.e. blank areas in the first display area 10, so that incident light from the first side S1 can be transmitted through the gaps between adjacent pixel unit groups P1 to ensure the light transmittance of the first display area 10.

[0082] For example, such as Figure 1B As shown, multiple first pixel unit groups P1 are arranged in a staggered manner between adjacent columns. That is, the pixel unit group P1 in the first column of the figure is staggered from the pixel unit group P1 in the second column in the second direction X1 and is distributed in different rows. For example, the pixel unit groups P1 in adjacent columns are not in the same row.

[0083] For example, such as Figure 1C As shown, multiple pixel unit groups P1 are arranged in multiple rows and columns. That is, the pixel unit group P1 in the first column of the figure is adjacent to the pixel unit group P1 in the second column in the second direction X1.

[0084] For example, such as Figure 1B as well as Figure 1CAs shown, the second display area 20 includes a second sub-pixel array (composed of white squares in the second display area 20), and the second sub-pixel array includes a plurality of second pixel units C (white squares in the second display area 20). Each of the plurality of second pixel units C includes a second light-emitting device and a second pixel driving circuit directly connected to each other, the second pixel driving circuit being configured to drive the second light-emitting device to emit light. The second light-emitting device and the second pixel driving circuit are located in the same pixel region and are not separated from each other in position. For example, the arrangement of the second pixel units in the second display area 20 is as follows: Figure 2 As shown,

[0085] For example, the pixel density of the second display area is greater than the pixel density of the first display area, such as... Figure 1B as well as Figure 1C As shown, the pixel density of the pixel unit group P1 in the first display area 10 is less than the pixel density of the second pixel unit C in the second display area 20. That is, the resolution of the first display area 10 is set lower than the resolution of the second display area 20 to allow space for light to pass through, i.e., the pixel density for display in the first display area 10 is less than the pixel density in the second display area 20.

[0086] Figure 2 This is a schematic diagram of the arrangement of pixel units in a second display area provided for at least one embodiment of the present disclosure. Figure 3 This is a schematic diagram of the first display area of ​​a display panel provided in at least one embodiment of the present disclosure. Figure 2 and Figure 3 As shown, the first display area 10 and the second display area 20 of the display substrate each include a plurality of pixel unit groups P1, for example, Figure 2 and Figure 3 The diagram only schematically illustrates that each pixel unit group P1 includes four pixel units P0. For example, the four pixel units P0 are the first sub-pixel unit 101, the second sub-pixel unit 102, the third sub-pixel unit 103, and the fourth sub-pixel unit 104, respectively. The embodiments disclosed herein do not limit this.

[0087] It should be noted that each pixel unit group P1 can also include two pixel units P0 (e.g., ... Figures 14A-14E (as shown) or 3 pixel units P0 (such as Figures 15A-15E As shown in the figure, the embodiments disclosed herein are not limited in this respect.

[0088] For example, in Figure 14A In the example shown, a pixel group may also include two sub-pixels, for example, a first sub-pixel 101 and a second sub-pixel 102, where the first sub-pixel 101 is a red sub-pixel and the second sub-pixel 102 is a green sub-pixel; for example, in Figure 15AIn the illustrated embodiment, a first pixel group P1 may further include three sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel. For example, these three sub-pixels are located in a row; for example, in... Figure 12A In the example shown, a pixel group may also include four sub-pixels, for example, a first sub-pixel 101, a second sub-pixel 102, a third sub-pixel 103, and a fourth sub-pixel 104. For example, the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, the third sub-pixel 103 is a blue sub-pixel, and the fourth sub-pixel 104 is a green sub-pixel. In other embodiments, the pixel group may also use pixel units of other colors. Of course, in other embodiments, the arrangement of multiple sub-pixels P0 in the display panel is not limited to... Figure 2 and Figure 3 As shown. The embodiments disclosed herein are not limited thereto.

[0089] For example, such as Figure 2 As shown, in the second display area 20, each pixel unit P0 is arranged uniformly and regularly, which will not be described in detail here.

[0090] For example, such as Figure 3 As shown, the display substrate also includes gate lines 113 and data lines 313. Gate lines 113 and data lines 313 are insulated from each other. Each gate line 113 connects to a row of sub-pixels, and each data line 313 connects to a column of sub-pixels. For example, the gate line 113 is configured to provide a scan signal to a row of sub-pixels. The data line 313 is configured to provide a data signal to a column of sub-pixels.

[0091] For example, such as Figure 3 As shown, data line 313 includes a first data line DL1. The first data line DL1 is located at least in the first display area 10. For example, the first data line DL1 extends from the first display area 10 to the second display area 20. For example, as... Figure 3 As shown, the gate line 113 includes a first gate line GL1, which extends from the second display area 20 to the first display area 10.

[0092] To be clear and concise, Figure 3 The connection relationship between adjacent pixel groups P1 in the first display area 10 is only schematically shown and does not constitute a limitation of this disclosure. Figure 4 This is a schematic diagram of a display substrate provided for at least one embodiment of the present disclosure. For example, such as... Figure 4 As shown, the display substrate also includes a first power line VDD1, and is configured to be connected to a plurality of pixel unit groups P1 to provide a first power supply voltage to the plurality of pixel unit groups P1.

[0093] For example, such as Figure 4 As shown, the display substrate also includes a shielding layer LS, disposed on the substrate 100 and located on the side of the first power line VDD1 near the substrate 100, including a cutout area LS2 and a shielding area LS1. For example, the cutout area LS2 corresponds to... Figure 3 The light-transmitting area R0 between adjacent first pixel unit groups is shown in the diagram. Figure 3 and 4 As shown, the light-transmitting area R0 is enclosed by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited to this.

[0094] For example, the first display area 10 includes multiple light-transmitting areas R0; the light-transmitting areas R0 are located between adjacent first pixel groups P1. The light-transmitting areas R0 are transparent to ambient light. For example, the light-transmitting areas R0 may include a substrate and a transparent insulating layer located on the substrate. The light-transmitting areas R0 do not have light-blocking structures, for example, they do not have metal traces. For example, the light-transmitting areas R0 are located within the area enclosed by four adjacent pixel unit groups P1 and the traces connecting the pixel unit groups P1, but are not limited thereto.

[0095] For example, such as Figure 4 As shown, adjacent pixel units are connected by traces (e.g., first data line DL1, first power line 311, gate line GL1, first reset signal line 111, second reset signal line 112, light emission control signal line 110, and initialization signal line 210). For example, the orthographic projection of multiple pixel units P0 and traces on the substrate 100 falls within the orthographic projection of the shielding area LS1 of the shielding layer LS on the substrate 100. That is, the shielding area LS1 shields the numerous slits between the traces connecting each first pixel unit group and between the internal connections of each first pixel unit group, thereby avoiding diffraction and interference when light passes through these slits, and preventing glare caused by uneven brightness when light reaches the camera.

[0096] For example, in embodiments of this disclosure, such as Figure 6A As shown, each of the plurality of first pixel units P0 includes a pixel region A11 (i.e., the area containing transistors, capacitors, and wiring in the first pixel unit; for example, the aforementioned plurality of power lines 311 (e.g., for the first pixel unit P0, power line 311 is the first power line VDD1; for the second pixel unit C, power line 311 is the second power line VDD2; the following embodiments are the same and will not be described again) located in the pixel region A11 and the opening region A12. For example, the opening region is for... Figure 6B The area obtained by reducing the size of the first pixel unit P0 shown. For example, by appropriately reducing... Figure 6BThe pixel driving circuit shown includes the line width, aspect ratio of each transistor, capacitor size, hole size, and the centralized placement of the traces, which ensures that the first pixel unit P0 has an open area A12 within the same solid-line rectangle (as shown). Figure 6A This improves the light transmittance of the display panel. For example, in an embodiment of this disclosure, the pixel area A11 is concentrated above the pixel unit group P0 (i.e., the solid-line rectangle) to reduce the space occupied by the driving circuit while maintaining the pixel resolution. Therefore, a portion of space (i.e., the opening area A12) can be freed up for placing the first shielding connection part SP1 and the connection holes V1 / V2 that connect the shielding layer LS to the first power line 311. A comparison diagram of the normal pixel unit and the pixel unit after reduction in size is shown below. Figure 6B and Figure 6A As shown.

[0097] For example, Figure 6A The size of the pixel driving circuit in the image (i.e., the size of the scaled-down pixel driving circuit) is: Figure 6B The pixel driving circuit shown is one-quarter the size of the original pixel driving circuit (i.e., the size of the pixel driving circuit before shrinking). Of course, it can also be one-sixth, one-half, etc., as long as the corresponding function can be achieved. The embodiments disclosed herein do not limit this. For example, in some examples, for an FHD resolution under-display camera screen, the size of the pixel driving circuit can be compressed to the QHD level while maintaining the FHD pixel resolution. Therefore, some space can be freed up to place the shielding connection part LS2 and the connection hole connecting the shielding layer LS.

[0098] In the above embodiments of this disclosure, reducing the size of the pixel driving circuit of the first pixel unit can facilitate light transmission and, at the same time, facilitate the connection between the shielding layer and the first power line or other power lines without changing the pixel resolution. This allows the shielding layer to be connected to a DC signal without reducing the pixel density, preventing signal interference to the pixel driving circuit caused by the shielding layer being in a floating state, reducing the voltage drop of the first power line, and improving the display quality of the display panel.

[0099] To ensure the uniformity of the etching of the masking layer, a masking layer is also placed below the pixel circuits in the normal display area. For example, the orthographic projection of the second display area 20 on the substrate 100 falls within the orthographic projection of the masking area LS2 of the masking layer LS on the substrate 100. For example, since the second display area 20 does not include the light-transmitting area R0, the portion of the masking layer LS corresponding to the second display area 20 can be a whole surface, i.e., without any cutouts, thereby masking the gaps in the individual pixel driving circuits in the second display area 20 and the gaps between the traces connecting the individual pixel driving circuits.

[0100] Because of normal pixel driving circuits (e.g., Figure 6B The pixel driving circuit shown has a compact routing. The size occupied by the driving circuit routing is the same as the pixel density. Therefore, there is no remaining space to place the shielding connection part and connection hole of the shielding layer LS.

[0101] To ensure that the pixel density remains constant, the pixel driving circuit in the second display area 20 adopts the same structure as the pixel driving circuit in the first display area 10, that is, it also adopts... Figure 6A The structure and dimensions are shown.

[0102] For example, for the second display area 20, such as Figure 1B and Figure 1C As shown, the second display area 20 includes a plurality of second pixel units C arranged in an array and a plurality of second power lines VDD2. The structure of each of the plurality of second pixel units C is as follows: Figure 6A As shown, for example, it includes pixel area A11 and opening area A12.

[0103] For example, multiple second power lines VDD2 are configured to connect to multiple second pixel units C to provide a second power supply voltage to the multiple second pixel units C. For example, the second power supply voltage is the same as the first power supply voltage. For example, it extends along a second direction X1, and one second power line VDD2 provides a second power supply voltage to a column of second pixel units C.

[0104] It should be noted that, in order to distinguish the different areas where the power line 311 is located, the power line 311 located in the first display area 10 is called the first power line VDD1, and the power line 311 located in the second display area 20 is called the second power line VDD2. The signals provided by the two are the same, that is, the first power supply voltage and the second power supply voltage are the same, and there is no essential difference.

[0105] For example, for a second pixel unit C, the opening region A12 of each second pixel unit C at least partially overlaps with the occlusion region LS1 of the occlusion layer LS, that is, the second pixel unit C adopts a reduced size. Figure 6A The pixel structure shown also leaves an opening area to facilitate the connection between the masking layer LS and the second power line VDD2, so as to provide a DC signal to the masking layer LS and avoid the floating of the masking layer LS.

[0106] For example, at least one second pixel unit C has an opening region A12 including a second occlusion connection part SP2. The second occlusion connection part SP2 at least partially overlaps with the occlusion region LS2 of the occlusion layer LS. The occlusion layer LS is connected to at least one of the multiple second power lines VDD2 through the second occlusion connection part SP2 to receive the second power supply voltage, thereby providing a DC signal to the occlusion layer LS and avoiding the floating of the occlusion layer LS.

[0107] Figure 7 This is a schematic cross-sectional view along line AA' provided for at least one embodiment of this disclosure. The following description uses the first pixel unit P0 as an example; however, the embodiments of this disclosure are not limited thereto.

[0108] For example, such as Figure 6A and Figure 7 As shown, the shielding layer LS (e.g., its shielding area LS1) is connected to the first shielding connection part SP1 through the first via V1, and the first shielding connection part SP1 is connected to at least one first power line VDD1 through the second via V2.

[0109] For example, such as Figure 7 As shown, the display substrate further includes a first insulating layer G11, a second insulating layer G12, a third insulating layer ILD, and a fourth insulating layer G10. For example, the first insulating layer G11 is located between the shielding layer LS (e.g., its shielding area LS1) and the first shielding layer connection portion SP1.

[0110] For example, such as Figure 7 As shown, the second insulating layer G12 is located between the first insulating layer G11 and the first shielding connection part SP1, and the third insulating layer ILD is located between the first shielding connection part SP1 and the multiple first power lines VDD1; or, the second insulating layer G12 is located between the first shielding connection part SP1 and the multiple first power lines VDD1, and the third insulating layer ILD is located between the second insulating layer G12 and the multiple first power lines VDD1. Figure 7 The positional relationship of the second insulating layer G12 is not specifically shown in the text and can be determined according to the actual situation. The embodiments disclosed herein do not limit this.

[0111] For example, in some examples, the shielding layer LS is connected to the first shielding connection SP1 through a first via penetrating the first insulating layer G11, and the first shielding connection SP1 is connected to at least one first power line VDD1 through a second via penetrating the second insulating layer G12 and the third insulating layer ILD; or, for example, in other examples, such as Figure 7 As shown, the shielding layer LS is connected to the first shielding connection portion SP1 through a first via V1 penetrating the first insulating layer G11 and the second insulating layer G12. The first shielding connection portion SP1 is connected to at least one first power line VDD1 through a second via penetrating the third insulating layer ILD. That is, the first shielding connection portion SP1 can be located in the first conductive layer or in the second conductive layer. Figure 7 A schematic diagram showing the first shielding connection SP1 located in the second conductive layer is provided, but the embodiments of this disclosure are not limited thereto. The relevant descriptions of the first and second conductive layers will be given below and will not be repeated here. For example, the following description uses the example of the first shielding connection being located in the first conductive layer, but the embodiments of this disclosure are not limited thereto.

[0112] Figure 8 for Figure 6A A plan view of the semiconductor pattern of the display substrate shown; Figure 9 for Figure 6A The diagram shows a plan view of the first conductive layer of the display substrate. Figure 10 for Figure 6A The diagram shows a plan view of the second conductive layer of the display substrate. Figure 11 for Figure 6A The diagram shows a plan view of the third conductive layer of the display substrate.

[0113] like Figure 7 As shown, the fourth insulating layer G10 is located between the shielding layer LS and the active layer of the transistor (e.g., the active layer A7 of the second reset transistor T1).

[0114] For example, such as Figures 8-11 As shown, the first conductive layer LY1 includes a gate line GL1, the second conductive layer LY2 includes the second electrode C12 of the storage capacitor C1, and the third conductive layer LY3 includes a first power line VDD1. For example, in a direction perpendicular to the substrate 100, the first insulating layer G11 is located between the active layer A7 and the first conductive layer LY1, the second insulating layer G12 is located between the gate line and the second conductive layer LY2, and the third insulating layer ILD is located between the second electrode C12 of the storage capacitor C1 and the third conductive layer LY3. For example, the first shielding connection SP1 is located... Figure 9 The first conductive layer LY1 shown is not limited to the embodiments disclosed herein.

[0115] For example, such as Figure 5 As shown, the pixel driving circuit includes a driving transistor T1, a data writing transistor T2, a compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. For example, each transistor and capacitor includes a first terminal and a second terminal. For a description of the connection relationships and working principle of this pixel driving circuit, please refer to the descriptions in this field; further details will not be provided here.

[0116] For example, such as Figure 8 As shown, the active layers A6, A3, A5, and A7 of the first reset transistor T6, compensation transistor T3, second light-emitting control transistor T5, and second reset transistor T7 are located on the first semiconductor layer A01 extending along the first direction Y1. The active layers A2 and A4 of the data writing transistor T2 and the first light-emitting control transistor T4 are located on the second semiconductor layer A02 extending along the second direction X1. The first semiconductor layer A01 and the second semiconductor layer A02 are connected and integrally formed through the active layer A1 of the driving transistor T1.

[0117] For example, such as Figure 6A and 8 As shown, the active layer A1 of the driving transistor T1 is located on the imaginary line of the active layer A6 of the first reset transistor T6 in the first direction Y1. The active layers A3 and A2 of the compensation transistor T3 and the data writing transistor T2 are located on both sides of the active layer A1 of the driving transistor T1, and are located on the side of the active layer A1 of the driving transistor T1 closer to the active layer A6 of the first reset transistor T6. That is, in the second direction Y1, the active layers A3 and A2 of the compensation transistor T3 and the data writing transistor T2 are located above the active layer A1 of the driving transistor T1. The active layers A5 and A4 of the second light-emitting control transistor T5 and the first light-emitting control transistor T4 are located on both sides of the active layer A1 of the driving transistor T1, and are located on the side of the active layer A1 of the driving transistor T1 away from the active layer A6 of the first reset transistor T6. For example, in the second direction Y1, they are located below the active layer A1 of the driving transistor T1.

[0118] For example, such as Figure 6A and 9 As shown, the active layer A7 of the second reset transistor T7 is located on the side of the active layer A5 of the second light-emitting control transistor T5 that is away from the active layer of the compensation transistor T3. The compensation transistor T3 includes a first gate G31 extending along the first direction Y1 and a second gate G32 extending along the second direction X1. The second gate G32, the gate G5 of the second light-emitting control transistor T5 extending along the second direction X2, and the gate of the second reset transistor T7 (not shown in the figure) are arranged side by side in the first direction Y1. The gate G2 of the data writing transistor T2 and the gate G4 of the first light-emitting control transistor T4 extend along the second direction X1 and are arranged side by side in the first direction Y1.

[0119] For example, the gate G6 of the first reset transistor T6 and the gate G1 of the drive transistor T1 extend along the second direction X1 and are arranged side by side in the first direction Y1. The gate G1 of the drive transistor T1 is integrally formed with the first plate C11 of the storage capacitor C1.

[0120] For example, the display substrate also includes a gate line 113 extending along the second direction Y1, a light emission control signal line 110, a first reset signal line 111, and a second reset signal line (integrated with the gate of the second reset transistor T7).

[0121] For example, the gate G6 of the first reset transistor T6 is connected to and integrally formed with the first reset signal line 111; the second gate G32 of the compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to and integrally formed with the gate line 113; the gate G6 of the second light-emitting control transistor T6 and the gate G5 of the first light-emitting control transistor T5 are connected to and integrally formed with the light-emitting control signal line 110; and the gate of the second reset transistor T7 is connected to and integrally formed with the second reset signal line.

[0122] For example, the display substrate also includes a gate line 113 extending along the second direction Y1, a light-emitting control signal line 110, a first reset signal line 111, and a second reset signal line 112. For instance, the gate of the first reset transistor T6 is connected to and integrally formed with the first reset signal line 111, and the second gate G32 of the compensation transistor T3 and the gate G2 of the data writing transistor T2 are connected to and integrally formed with the gate line 113. The gate G5 of the second light-emitting control transistor T5 and the gate G4 of the first light-emitting control transistor T4 are connected to and integrally formed with the light-emitting control signal line 110, and the gate G7 of the second reset transistor T7 is connected to and integrally formed with the second reset signal line 112.

[0123] For example, the display substrate also includes a data line 313, which is connected to the active layer A4 of the data writing transistor T4 and configured to provide a data signal DATA. The orthographic projection of the first power line VDD1 on the substrate 100 at least partially overlaps with the orthographic projections of the active layer A6 of the first reset transistor T6 and the active layer A1 of the driving transistor T1 on the substrate 100. The orthographic projection of the data line 313 on the substrate 100 is located on the side of the orthographic projection of the second semiconductor layer A02 on the substrate 100 that is away from the orthographic projection of the first power line VDD1 on the substrate 100.

[0124] For example, such as Figure 6A and Figure 11 The pixel driving circuit also includes a first transfer electrode EC1. The first transfer electrode EC1 is connected to the active layer of the second light-emitting control transistor T5, the active layer A7 of the second reset transistor T7, and the first electrode E1 of the light-emitting device 20 through a via. The orthogonal projection of the first transfer electrode EC1 on the substrate 100 is located between the orthogonal projections of the active layer A7 of the second reset transistor T7 and the active layer A1 of the driving transistor T1 on the substrate 100.

[0125] For example, for each of the plurality of second pixel units C, the orthographic projection of the second occlusion connection portion SP2 on the substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 on the substrate 100 and the orthographic projection of the second power line VDD2 on the substrate 100, and at least partially overlaps with the orthographic projection of the second power line VDD2 on the substrate 100, thereby freeing up the opening region A12.

[0126] For example, refer to Figure 5 Gate line 113 is configured to provide a scan signal SCAN to pixel circuit 10. Light emission control signal line 110 is configured to provide a light emission control signal EM to sub-pixel P0. Data line 313 is configured to provide a data signal DATA to pixel circuit 10. First power line 311 is configured to provide a constant first voltage signal ELVDD to pixel circuit 10, and third power line 312 is configured to provide a constant second voltage signal ELVSS to pixel circuit 10, wherein the first voltage signal ELVDD is greater than the second voltage signal ELVSS. Initialization signal line 210 is configured to provide an initialization signal Vinit to pixel circuit 10. The initialization signal Vinit is a constant voltage signal, the magnitude of which may, for example, be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto; for example, the initialization signal Vinit may be less than or equal to the second voltage signal ELVSS. For example, under the control of signals such as the scan signal SCAN, data signal DATA, initialization signal Vinit, first voltage signal ELVDD, second voltage signal ELVSS, and light emission control signal EM, the pixel circuit outputs a driving current to drive the light-emitting element 20 to emit light. The light-emitting element 20 emits red, green, blue, or white light under the drive of its corresponding pixel circuit 10.

[0127] like Figure 5 As shown, the driving transistor T1 of the pixel circuit 10 is electrically connected to the light-emitting element 20, and outputs a driving current to drive the light-emitting element 20 to emit light under the control of signals such as scan signal SCAN, data signal DATA, first voltage signal ELVDD, and second voltage signal ELVSS.

[0128] For example, the display panel provided in this embodiment further includes a data driving circuit and a scan driving circuit. The data driving circuit is configured to provide a data signal DATA to the sub-pixel P0 according to the instructions of the control circuit; the scan driving circuit is configured to provide signals such as a light emission control signal EM, a scan signal SCAN, a first reset control signal RST1, and a second reset signal RST2 to the sub-pixel P0 according to the instructions of the control circuit. For example, the control circuit includes an external integrated circuit (IC), but is not limited thereto. For example, the scan driving circuit is a GOA (Gate driver On Array) structure mounted on the display panel, or a driver chip (IC) structure bonded to the display panel. For example, different driving circuits can also be used to provide the light emission control signal EM and the scan signal SCAN respectively. For example, the display panel also includes a power supply (not shown in the figure) to provide the above voltage signals, which can be a voltage source or a current source as needed. The power supply is configured to provide a first voltage signal ELVDD, a second power supply voltage ELVSS, and an initialization signal Vinit to the sub-pixel P0 through a first power line 311, a third power line 312, and an initialization signal line 210 respectively.

[0129] like Figure 5 As shown, the second terminal C12 of storage capacitor C1 is electrically connected to the first power supply line 311, and the first terminal C11 of storage capacitor C1 is electrically connected to the second terminal T12 of threshold compensation transistor T1. The gate T20 of data write transistor T2 is electrically connected to gate line 113, and the first terminal T21 and the second terminal T22 of data write transistor T2 are electrically connected to data line 313 and the first terminal T11 of driving transistor T1, respectively. The gate T30 of threshold compensation transistor T3 is electrically connected to gate line 113, the first terminal T31 of threshold compensation transistor T3 is electrically connected to the second terminal T12 of driving transistor T1, and the second terminal T32 of threshold compensation transistor T3 is electrically connected to the gate T10 of driving transistor T1.

[0130] For example, such as Figure 5 As shown, the gate T40 of the first light-emitting control transistor T4 and the gate T50 of the second light-emitting control transistor T5 are both connected to the light-emitting control signal line 110.

[0131] For example, such as Figure 5As shown, the first electrode T41 and the second electrode T42 of the first light-emitting control transistor T4 are electrically connected to the first power supply line 311 and the first electrode T11 of the driving transistor T1, respectively. The first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T16 and the pixel electrode E1 (which can be the anode of the OLED) of the light-emitting element 20, respectively. The common electrode E2 (which can be the common electrode of the OLED, such as the cathode) of the light-emitting element 20 is electrically connected to the third power supply line 312.

[0132] For example, such as Figure 5 As shown, the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, the first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line 210 (first initialization signal line 211), and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1. The gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first electrode T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (second initialization signal line 212), and the second electrode T72 of the second reset transistor T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.

[0133] Figure 8 The semiconductor pattern SCP is shown. Figure 9 A first conductive layer LY1 is shown, and a first insulating layer G11 is disposed between the first conductive layer LY1 and the semiconductor pattern SCP. Using the first conductive layer LY1 as a mask, the semiconductor pattern SCP is doped, such that the areas of the semiconductor pattern SCP not covered by the first conductive layer LY1 retain semiconductor properties, forming the channel of a thin-film transistor, while the areas of the semiconductor pattern SCP covered by the first conductive layer LY1 are made conductive, forming the source or drain of the thin-film transistor. Figure 6A The active layer formed after the semiconductor pattern SCP is partially conductive is shown.

[0134] like Figure 9 As shown, the first conductive layer LY1 includes a first reset control signal line 111, a second reset control signal line (not shown in the figure), a light emission control signal line 110, a gate line 113, and the first electrode C11 of the storage capacitor C1.

[0135] Figure 10A second conductive layer LY2 is shown, and a second insulating layer G12 is disposed between the second conductive layer LY2 and the first conductive pattern layer LY1. The second conductive layer LY2 includes an initialization signal line 210 and the second terminal C12 of a storage capacitor C1. The second terminal C12 of the storage capacitor C1 has an opening. An interlayer insulating layer ILD is located between the second conductive layer LY2 and the third conductive layer LY3. Details regarding the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, the first conductive layer LY1, the second conductive layer LY2, and the third conductive layer LY3 can be found in the descriptions in the art and will not be repeated here.

[0136] Figure 11 The third conductive layer LY3 is shown. The third conductive layer LY3 includes a first power line 311, a data line 313, a first connection electrode EC1, a second connection electrode EC2, and a first electrode E1 of the light-emitting element 20.

[0137] For example, such as Figure 11 As shown, the first power line 311 includes a protrusion 3111. The orthographic projection of the second via V2 onto the substrate overlaps with the orthographic projection of the protrusion 3111 onto the substrate. That is, the first shielding connection part SP1 is connected to the protrusion 3111 of the first power line S11 through the second via V2. The orthographic projection of the first via V1 onto the substrate overlaps with the orthographic projection of the first power line 311 onto the substrate. For example, as... Figure 6A and Figure 7 As shown, the first via V1 and the second via V2 are arranged horizontally. Of course, they can also be arranged vertically in the first direction Y1. The embodiments disclosed herein do not limit this.

[0138] For example, in the embodiments of this disclosure, the orthographic projections of the first via V1 and the second via V2 on the substrate do not overlap, that is, they are arranged vertically or horizontally. This simplifies the process and avoids problems such as easy film breakage caused by the overlap of the orthographic projections of the first via and the second via on the substrate, as well as difficulties in process implementation and large slope and unevenness of the first power line 311.

[0139] It should be noted that the transistors used in some embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The source and drain of the transistors used here can be structurally symmetrical, so their structures can be indistinguishable. In one embodiment of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal and the other as the second terminal. Therefore, the first and second terminals of all or some transistors in this disclosure can be interchanged as needed. For example, the first terminal of the transistor described in this disclosure can be the source, and the second terminal can be the drain; or, the first terminal of the transistor is the drain, and the second terminal is the source.

[0140] Furthermore, transistors can be classified into N-type and P-type transistors based on their characteristics. This disclosure uses an example where all transistors are P-type. Based on the description and teachings of this disclosure, those skilled in the art can readily conceive of using at least some N-type transistors in the pixel circuit of this disclosure, i.e., using N-type transistors or a combination of N-type and P-type transistors, without any inventive effort. Therefore, these implementations are also within the scope of this disclosure.

[0141] Figure 6A The pixel circuit of 7T1C is used as an example for illustration, and the embodiments of this disclosure include, but are not limited to, this. It should be noted that the embodiments of this disclosure do not limit the number of thin-film transistors or capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display base panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T3C structure; the embodiments of this disclosure do not limit this.

[0142] For example, in at least one embodiment of this disclosure, the substrate 100 can be a glass plate, a quartz plate, a metal plate, or a resin-based plate. For example, the material of the substrate can include organic materials, such as resins like polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. For example, the substrate 100 can be a flexible substrate or a non-flexible substrate; the embodiments of this disclosure do not limit this.

[0143] For example, the materials of the first insulating layer G11, the second insulating layer G12, the third insulating layer ILD, and the fourth insulating layer BL may include inorganic insulating materials such as SiNx, SiOx, and SiNxOy, organic insulating materials such as organic resins, or other suitable materials. The embodiments of this disclosure do not limit this.

[0144] For example, the material of the third conductive layer LY3 may include titanium, titanium alloy, aluminum, aluminum alloy, copper, copper alloy, or any other suitable composite material, and the embodiments disclosed herein do not limit this. For example, the materials of the shielding layer LS, the first conductive layer LY1, and the second conductive layer LY2 may be the same as the material of the third conductive layer LY3, and will not be described again here.

[0145] For example, the material of the semiconductor layer 310 may include oxide semiconductors, organic semiconductors, amorphous silicon, polycrystalline silicon, etc. For example, oxide semiconductors include metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO)), and polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc. The embodiments of this disclosure do not limit this. It should be noted that the source region and drain region mentioned above may be regions doped with n-type impurities or p-type impurities, and the embodiments of this disclosure do not limit this.

[0146] The following are schematic diagrams illustrating several examples of the first occlusion connection. For example, the first occlusion connection may be located in the middle, at both ends, or at one end of two rows of first pixel units in the first display area, and the embodiments of this disclosure are not limited thereto.

[0147] Figure 12A A schematic diagram illustrating an example of a display substrate provided in at least one embodiment of this disclosure; Figure 12B for Figure 12A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown. Figure 12C for Figure 12A A plan view of the semiconductor pattern of the display substrate shown; Figure 12D for Figure 12A The diagram shows a plan view of the first conductive layer of the display substrate. Figure 12E for Figure 12A The diagram shows a plan view of the second conductive layer of the display substrate. Figure 12F for Figure 12A The diagram shows a plan view of the third conductive layer of the display substrate.

[0148] For example, such as Figure 12A As shown, a pixel unit group includes four first pixel units 101, 102, 103, and 104. For example, as... Figure 12A As shown, for each pixel unit group, the first occlusion connection part SP1 is located between two adjacent first pixel units in the first direction Y1 within each pixel unit group. Regarding... Figures 12B to 12F For related information, please refer to Figures 8-11 The description.

[0149] For example, in Figure 12A In the example shown, the orthographic projection of the first shielding connection SP1 on the substrate 100 is located between the orthographic projection of the active layer A7 of the second reset transistor T7 on the substrate 100 and the orthographic projection of the first power line VDD1 on the substrate 100, and at least partially overlaps with the orthographic projection of the first power line VDD1 on the substrate 100 (e.g., as shown). Figure 6A (As shown).

[0150] For example, such as Figure 12AAs shown, in the first direction Y1, the first power line 311 between two adjacent pixel unit groups is connected by a third conductor L3. The first data line DL1 includes a first part DL11 and a second part DL12. The first part DL11 of the first data line DL1 partially overlaps with the third conductor L3, and the second part DL12 of the first data line DL1 at least partially overlaps with the third conductor L3. The first part DL11 and the second part DL12 of the first data line DL1 are located in different layers. For example, Figure 12A The first part of the first data line DL1 on the left side of the middle is DL11. Figure 12E The second conductive layer LY2 shown has the second part DL12 of the first data line DL1 on the right side located in the second conductive layer LY2. Figure 12D The first conductive layer LY1 is shown. For example, see reference... Figure 12A , 12D 12E, the first part DL11 and the second part DL12 of the first data line DL1 and the third conductor L3 are located between adjacent pixel unit groups.

[0151] For example, such as Figure 12F As shown, the third conductor L3 is integrally formed with the first power line 311. The first power line 311 connects two adjacent pixel unit groups, so that adjacent pixel unit groups are connected by only one third conductor, thereby reducing the wiring area and improving the light transmittance.

[0152] For example, refer to Figure 12F Two first data lines DL1 are provided, and each of the two first data lines DL1 is connected to two adjacent columns of sub-pixels. For example, as shown... Figure 12F As shown, the first part DL11 and the second part DL12 are respectively connected to the two first data lines DL1, and overlap with the orthographic projection of the same third conductor L3 on the substrate BS. This arrangement allows the data lines located between pixel unit groups in two adjacent sub-pixel columns to be hidden under the third conductor, thereby reducing the wiring area and improving light transmittance.

[0153] For example, such as Figure 12B As shown, the occlusion area LS1 includes a first part LS11, a second part LS12, a third part LS13, and a fourth part LS14, which are respectively connected to and opposite to the occlusion area LS14. Figure 12A The traces connecting the pixel units shown overlap. For example, the orthographic projection of the third portion LS13 of the occlusion region LS1 onto the substrate is... Figure 12AThe third conductor L3, connected to the previous pixel unit group, and the first portion DL11 and the second portion DL12 of the first data line DL1 overlap in their orthographic projections on the substrate, thereby blocking the third conductor L3, the first portion DL11 and the second portion DL12 of the first data line DL1, and the gap between them. The fourth portion LS14 of the blocking area LS1, in its orthographic projection on the substrate, is... Figure 12A The third conductor L3, which connects to the next pixel unit group, and the first portion DL11 and the second portion DL12 of the first data line DL1 overlap in their orthographic projections on the substrate. The orthographic projections of the first portion LS11 and the second portion LS12 of the occlusion area LS1 on the substrate overlap with the orthographic projections of the traces connecting the left and right pixel unit groups on the substrate, respectively.

[0154] like Figure 12C As shown, since the blocking connection portion SP1 is located in the middle of adjacent first pixel units, in order to facilitate the setting of the blocking connection portion SP1, the active layer of the second reset transistor in the previous first pixel unit in the same column of the same pixel unit group extends along the first direction Y1 and is connected to the active layer of the first reset transistor T6 in the next first pixel unit in the same column. It should be noted that the embodiments of this disclosure are not limited in this respect.

[0155] Figure 13A A schematic diagram illustrating an example of another display substrate provided in at least one embodiment of this disclosure; Figure 13B for Figure 13A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown. Figure 13C for Figure 13A A plan view of the semiconductor pattern of the display substrate shown; Figure 13D for Figure 13A The diagram shows a plan view of the first conductive layer of the display substrate. Figure 13E for Figure 13A The diagram shows a plan view of the second conductive layer of the display substrate. Figure 13F for Figure 13A The diagram shows a plan view of the third conductive layer of the display substrate.

[0156] For example, Figure 13A The display substrate shown is Figure 12AThe display substrate shown is similar, but the difference lies in that: the first blocking connection portion SP1 is located at both ends of each pixel unit group, and is connected to at least one of the multiple first power lines VDD1 corresponding to each pixel unit group. For example, the first blocking connection portion SP1 located at both ends can be connected to the same first power line VDD1, or it can be connected to two different first power lines VDD1 corresponding to the pixel unit group respectively. That is, the two first blocking connection portions can be located in the same column or in different columns. The embodiments disclosed herein do not limit this.

[0157] like Figure 13B As shown, the occlusion area LS1 only includes portions LS21, LS22, LS23, and LS24 extending along the second direction X1, which respectively occlude the traces connected to the left and right pixel unit groups. Because... Figure 13A The third conductor connecting the upper and lower pixel unit groups, the first part and the second part of the first data line DL1 extend along the second direction X1, therefore, with Figure 12B Compared to the examples in, Figure 13B The occlusion area LS1 shown does not include the portion extending along the first direction Y1.

[0158] It should be noted that when the shielding connection SP1 is located at both ends, such as Figure 13B As shown, the semiconductor layers of each first pixel unit are consistent, meaning that first pixel units located in the same column are not connected, and the active layer of the second reset transistor is consistent with... Figure 12C The differences also include the bending section T74.

[0159] Figure 14A A schematic diagram illustrating another example of a display substrate provided in at least one embodiment of this disclosure; Figure 14B for Figure 14A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown. Figure 14C for Figure 14A A plan view of the semiconductor pattern of the display substrate shown; Figure 14D for Figure 14A The diagram shows a plan view of the first conductive layer of the display substrate. Figure 14E for Figure 14A The diagram shows a plan view of the second conductive layer of the display substrate. Figure 14F for Figure 14A The diagram shows a plan view of the third conductive layer of the display substrate. Figure 15A A schematic diagram illustrating another example of a display substrate provided in at least one embodiment of this disclosure; Figure 15B for Figure 15A A plan view of the shielding area LS1 of the shielding layer LS of the display substrate shown. Figure 15C for Figure 15A A plan view of the semiconductor pattern of the display substrate shown; Figure 15D for Figure 15A The diagram shows a plan view of the first conductive layer of the display substrate. Figure 15E for Figure 15A The diagram shows a plan view of the second conductive layer of the display substrate. Figure 15F for Figure 15A The diagram shows a plan view of the third conductive layer of the display substrate.

[0160] For example, such as Figure 14A As shown, a pixel unit group includes two first pixel units 101 and 102. For example, as Figure 15A As shown, a pixel unit group includes three first pixel units 101, 102 and 103.

[0161] Figure 15B The occlusion area in Figure 12B The occlusion area is similar to that in the previous example, except that it also includes the protrusion. The similar parts will not be described again.

[0162] For example, such as Figure 14A and 15A As shown, the first occlusion connection part SP1 is located at one end of each pixel unit group, and is connected to at least one of the multiple first power lines VDD1 corresponding to the pixel unit group. For example, the first occlusion connection part SP1 is connected to the first power line VDD1 connected to the first pixel unit 101, and the embodiments of this disclosure are not limited in this respect.

[0163] For example, such as Figure 14B As shown, when the first occlusion connection part SP1 is located at one end or both ends of each pixel unit group, the occlusion area LS1 of the occlusion layer LS also includes a protrusion LS11 to overlap with the first occlusion connection part SP1, thereby avoiding phenomena such as light diffraction.

[0164] It should be noted that the above embodiments only schematically show the number and position of the first blocking connection part SP1. Of course, the number of the first blocking connection part SP1 corresponding to the display substrate of different embodiments may be more or less, and the position may also be changed. The embodiments disclosed herein do not limit this.

[0165] It should be noted that the way the second shielding part SP2 in the second display area 20 connects to the shielding layer LS and the second power line VDD2 is basically the same as the way the first shielding part SP2 in the first display area 10 is connected. For details, please refer to the above. Figure 7 , Figures 12A-15FThe relevant descriptions will not be repeated here. For example, each second pixel unit C in the second display area 20 corresponds to a second blocking part, so that the ELVDD signal is connected to the blocking layer LS in each pixel circuit, providing a stable DC signal to the blocking layer LD, and forming a large ELVDD signal network in the entire display area, which helps to reduce the voltage drop of the traces, increase the uniformity of the display, and improve the display effect. At the same time, the light blocking layer LS of the first display area 10 and the light blocking layer LS of the second display area 20 are connected and integrally formed, thereby forming a whole ELVDD signal network, further reducing the voltage drop of the power lines (i.e., the first power line VDD1 and the second power line VDD2) that provide the ELVDD signal, and improving the display effect.

[0166] Figure 16 This is a schematic diagram of a display device provided according to at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2, which may include the display substrate 1 of any of the above embodiments.

[0167] For example, such as Figure 16 As shown, the display device 2 may also include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding area of ​​the display substrate 1, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

[0168] For example, a control chip can be a central processing unit (CPU), a digital signal processor (DSP), or a system-on-a-chip (SoC). For example, a control chip can also include memory, a power supply module, etc., and achieve power supply and signal input / output functions through separately provided wires and signal lines. For example, a control chip can also include hardware circuitry and computer-executable code. Hardware circuitry can include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; hardware circuitry can also include field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, etc.

[0169] For example, the display device 2 provided in at least one embodiment of this disclosure can be any product or component with display function, such as an OLED panel, OLED TV, QLED panel, QLED TV, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator. The display device 2 may also include other components, such as data driving circuitry, timing controllers, etc., which are not limited in the embodiments of this disclosure.

[0170] For example, such as Figure 16As shown in FIG. 1, the display device 2 also includes a sensor 192. The sensor 192 is disposed on a second side S2 (e.g., the non-display side) of the display substrate 1. The sensor 192 is configured to receive light (e.g., collimated light or collimated light) from a first side S1 (e.g., the display side of the display substrate) of the display substrate 1. The orthographic projection of the sensor 192 on the substrate 100 at least partially overlaps with the first display area 10.

[0171] For example, sensor 192 can be an image sensor, an infrared sensor, a distance sensor, etc., and sensor 192 can be implemented in the form of a chip, etc. Sensor 192 is disposed on the non-display side S2 (the side away from the user) of the display substrate.

[0172] For example, the sensor 192 and the first display area 10 at least partially overlap in the normal direction of the display surface of the display substrate.

[0173] For example, sensor 192 can be an image sensor, used to acquire images of the external environment facing the light-collecting surface of sensor 192, such as a CMOS image sensor or a CCD image sensor; sensor 192 can also be an infrared sensor, a distance sensor, etc. Sensor 192 can be used to implement cameras in mobile terminals such as mobile phones and laptops, and may further include optical devices such as lenses, mirrors, or optical waveguides to modulate the light path as needed. The embodiments of this disclosure do not limit the type, function, or arrangement of sensor 192.

[0174] Sensor 192 is mounted on the non-display side S2 of the display panel using double-sided adhesive or similar means, and the orthographic projection of sensor 192 on the substrate 100 at least partially overlaps with the first display area 10, configured to receive light from the first side S1. Thus, the first display area 10 not only enables display but also facilitates the mounting of sensor 192.

[0175] It should be noted that, for clarity and brevity, the embodiments of this disclosure do not show all the constituent units of the display device. To realize the substrate function of the display device, those skilled in the art can provide and set other structures (not shown) according to specific needs, and the embodiments of this disclosure do not impose any limitations on this.

[0176] For the technical effects of the display device provided in the above embodiments, please refer to the technical effects of the display substrate provided in the embodiments of this disclosure, which will not be repeated here.

[0177] The following points need to be explained:

[0178] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0179] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0180] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate having a first side for display and a second side opposite to the first side, comprising: Substrate; A display area is disposed on the substrate and includes a first display area and a second display area at least partially surrounding the first display area. The first display area allows light from a first side of the display substrate to be at least partially transmitted to the second side of the display substrate for sensing. The first display area includes a plurality of pixel unit groups arranged at intervals. Each of the plurality of pixel unit groups includes a plurality of first pixel units. Each of the plurality of first pixel units includes a pixel area and an opening area. Multiple first power lines are located in the pixel area and configured to be connected to the multiple pixel unit groups to provide a first power supply voltage to the multiple pixel unit groups; A shielding layer is disposed on the substrate and located on the side of the first power line close to the substrate, including a cutout area and a shielding area. Specifically, for a pixel unit group, the opening area of ​​each first pixel unit at least partially overlaps with the occlusion area of ​​the occlusion layer. The opening area of ​​the at least one first pixel unit includes a first blocking connection portion, which at least partially overlaps with the blocking area of ​​the blocking layer, and the blocking layer is connected to at least one of the plurality of first power lines through the first blocking connection portion to receive the first power supply voltage. The plurality of first power lines are located on the side of the first shielding connection portion away from the substrate, the shielding layer is located on the side of the first shielding connection portion closer to the substrate, and the first shielding connection portion is located between the shielding layer and the plurality of first power lines. Each of the plurality of first pixel units includes a pixel driving circuit, the pixel driving circuit including a driving transistor, a data writing transistor, a compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, a second reset transistor, and a storage capacitor. The driving transistor, data writing transistor, compensation transistor, first light-emitting control transistor, second light-emitting control transistor, first reset transistor, second reset transistor, and storage capacitor are located within the pixel region, and the pixel region is independent of the opening region. 2.The display substrate of claim 1, wherein, The shielding layer is connected to the first shielding connection part through a first through hole, and the first shielding connection part is connected to the at least one first power line through a second through hole. 3.The display substrate of claim 2, wherein, The display substrate further includes a first insulating layer, a second insulating layer, and a third insulating layer, wherein the first insulating layer is located between the shielding layer and the first shielding connection portion. The second insulating layer is located between the first insulating layer and the first shielding connection portion, and the third insulating layer is located between the first shielding connection portion and the plurality of first power lines; or, the second insulating layer is located between the first shielding connection portion and the plurality of first power lines, and the third insulating layer is located between the second insulating layer and the plurality of first power lines. The shielding layer is connected to the first shielding connection portion through a first through-hole penetrating the first insulating layer, and the first shielding connection portion is connected to the at least one first power line through a second through-hole penetrating the second and third insulating layers; or, the shielding layer is connected to the first shielding connection portion through a first through-hole penetrating the first and second insulating layers, and the first shielding connection portion is connected to the at least one first power line through a second through-hole penetrating the third insulating layer. 4.The display substrate of claim 3, wherein, The orthographic projections of the first via and the second via on the substrate do not overlap. The first power line includes a protrusion, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the protrusion on the substrate, and the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first power line on the substrate. 5.The display substrate according to any one of claims 1-4, wherein, Adjacent pixel units are connected by traces, and the orthographic projection of the plurality of pixel units and the traces on the substrate falls within the orthographic projection of the shielding area of ​​the shielding layer on the substrate.

6. The display substrate according to any one of claims 1-4, wherein, The second display area includes a plurality of second pixel units arranged in an array and a plurality of second power lines, each of the plurality of second pixel units including a pixel area and an opening area; The plurality of second power lines are configured to be connected to the plurality of second pixel units to provide a second power voltage to the plurality of second pixel units, wherein the second power voltage is the same as the first power voltage. Specifically, for each second pixel unit, the opening region of each second pixel unit at least partially overlaps with the occlusion region of the occlusion layer. The opening region of the at least one second pixel unit includes a second occlusion connection portion, which at least partially overlaps with the occlusion region of the occlusion layer.

7. The display substrate according to any one of claims 1-4, wherein, The orthographic projection of the second display area on the substrate falls within the orthographic projection of the shielding area of ​​the shielding layer on the substrate. 8.The display substrate of claim 6, wherein, Each of the plurality of second pixel units includes the pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to drive the light-emitting device to emit light. 9.The display substrate of claim 8, wherein, The active layers of the first reset transistor, the compensation transistor, the second light-emitting control transistor, and the second reset transistor are located on a first semiconductor layer extending along a first direction. The active layers of the data writing transistor and the first light-emitting control transistor are located on a second semiconductor layer extending along a second direction. The first semiconductor layer and the second semiconductor layer are connected and integrally formed through the active layer of the driving transistor. The active layer of the driving transistor is located on an imaginary line along the first direction of the active layer of the first reset transistor. The active layers of the compensation transistor and the data write transistor are located on opposite sides of the active layer of the driving transistor, and are located on the side of the active layer of the driving transistor closer to the active layer of the first reset transistor. The active layers of the second light-emitting control transistor and the first light-emitting control transistor are respectively located on both sides of the active layer of the driving transistor, and are located on the side of the active layer of the driving transistor that is farthest from the active layer of the first reset transistor. The active layer of the second reset transistor is located on the side of the active layer of the second light-emitting control transistor that is away from the active layer of the compensation transistor. The compensation transistor includes a first gate extending along the first direction and a second gate extending along the second direction. The second gate, the gate of the second light-emitting control transistor extending along the second direction, and the gate of the second reset transistor are arranged side by side in the first direction. The gate of the data writing transistor and the gate of the first light-emitting control transistor extend along the second direction and are arranged side by side in the first direction. The gates of the first reset transistor and the driving transistor extend along the second direction and are arranged side by side in the first direction. The gate of the driving transistor is integrally formed with the first plate of the storage capacitor.

10. The display substrate according to claim 9, further comprising a gate line extending along the second direction, a light emission control signal line, a first reset signal line, and a second reset signal line. wherein The gate of the first reset transistor and the first reset signal line are connected and integrally formed. The second gate of the compensation transistor and the gate of the data writing transistor are connected to the gate line and integrally formed therefrom. The gates of the second and first light-emitting control transistors are connected to and integrally formed with the light-emitting control signal line. The gate of the second reset transistor is connected to the second reset signal line and is integrally formed thereon.

11. The display substrate according to claim 10, further comprising a data line, wherein, The data line is connected to the active layer of the data writing transistor and is configured to provide a data signal. The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projections of the active layer of the first reset transistor and the active layer of the driving transistor on the substrate. The orthographic projection of the data line on the substrate is located on the side of the orthographic projection of the second semiconductor layer on the substrate that is away from the orthographic projection of the first power line on the substrate.

12. The display substrate according to claim 11, wherein, The pixel driving circuit further includes a first transition electrode, which is connected to the active layer of the second light-emitting control transistor, the active layer of the second reset transistor, and the first electrode of the light-emitting device through a via. The orthographic projection of the first transfer electrode on the substrate is located between the orthographic projections of the active layer of the second reset transistor and the active layer of the driving transistor on the substrate.

13. The display substrate according to claim 12, wherein, For each of the plurality of second pixel units, the orthographic projection of the second occlusion connection portion on the substrate is located between the orthographic projection of the active layer of the second reset transistor on the substrate and the orthographic projection of the second power line on the substrate, and at least partially overlaps with the orthographic projection of the second power line on the substrate.

14. The display substrate according to claim 13, wherein, For each pixel unit group, the first occlusion connection portion is located between two adjacent first pixel units in the first direction within each pixel unit group.

15. The display substrate according to claim 12, wherein, The orthographic projection of the first shielding connection portion on the substrate is located between the orthographic projection of the active layer of the second reset transistor on the substrate and the orthographic projection of the first power line on the substrate, and at least partially overlaps with the orthographic projection of the first power line on the substrate.

16. The display substrate according to any one of claims 1-4, wherein, The first occlusion connection is located at both ends of each pixel unit group, and is connected to at least one of the multiple first power lines corresponding to each pixel unit group.

17. The display substrate according to any one of claims 1-4, wherein, The first occlusion connection is located at one end of each pixel unit group and is connected to at least one of the multiple first power lines corresponding to the pixel unit group.

18. The display substrate according to claim 12, further comprising a fourth insulating layer, a first conductive layer, a second conductive layer, and a third conductive layer; in, The first conductive layer includes the gate line, the second conductive layer includes the second plate of the storage capacitor, and the third conductive layer includes the first power line. In the direction perpendicular to the substrate, The fourth insulation is located between the shielding layer and the active layer of the transistor. The first insulating layer is located between the active layer and the first conductive layer. The second insulating layer is located between the gate line and the second conductive layer. The third insulating layer is located between the second plate of the storage capacitor and the third conductive layer.

19. The display substrate according to claim 18, wherein, The first shielding connection is located in the first conductive layer or the second conductive layer.

20. A display device comprising a display substrate and a sensor as described in any one of claims 1-19, wherein, The sensor is disposed on the second side of the display substrate, and the sensor is configured to receive light from the first side of the display substrate; The orthographic projection of the sensor onto the substrate at least partially overlaps with the first display area.

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