Thin film transistor substrate, manufacturing method thereof and display device including the same

Abstract

The invention also provides a thin film transistor substrate, a method for manufacturing the thin film transistor substrate, and a display device including the thin film transistor substrate. One example of the present disclosure provides a thin film transistor substrate including a buffer layer disposed on a base substrate and a plurality of thin film transistors on the buffer layer, where the plurality of thin film transistors includes a plurality of active layers and a gate electrode overlapping at least a portion of each of the active layers, the buffer layer includes a plurality of flat regions and a plurality of inclined regions alternately disposed with each other, and the plurality of active layers are spaced apart from each other and disposed within the plurality of flat regions.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0138500, filed on October 11, 2024. Technical Field

[0003] This disclosure relates to display devices, thin-film transistor substrates, display devices including thin-film transistor substrates, and manufacturing methods. Background Technology

[0004] Because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching or driving elements in display devices such as liquid crystal displays or organic light-emitting devices.

[0005] Based on the material constituting the active layer, thin-film transistors can be classified into amorphous silicon thin-film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin-film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin-film transistors in which oxide semiconductor is used as the active layer.

[0006] A GIP (Gate in Panel) structure, in which gate drivers are embedded in the display panel as thin-film transistors, can be applied to display devices. When a large number of thin-film transistors are placed in the gate driver to improve the performance of the display device, a method of configuring the thin-film transistors by dividing the active layer can be used.

[0007] In particular, the thin-film transistors in the output cells of the gate driver stage are formed with a large channel width, and when manufactured under the same process conditions, there is a risk of the threshold voltage shifting in the negative direction. Therefore, to solve this problem, a method of configuring thin-film transistors by segmenting the active layer is adopted.

[0008] Recently, research has been conducted to divide the active layers in order to reduce the gaps between them, thereby reducing the area of ​​the bezel region corresponding to the outer portion of the display panel. Summary of the Invention

[0009] One example of this disclosure is a thin-film transistor substrate in which stepped layers are disposed beneath active layers to separate the active layers from each other. This stepped arrangement is achieved by providing multiple active layers spaced apart from each other by multiple inclined regions and disposed in multiple flat regions. The thin-film transistor substrate described herein is suitable for display devices. Display devices may include the thin-film transistor substrate described herein.

[0010] One example of this disclosure is a thin-film transistor substrate in which the gaps between active layers are minimized.

[0011] Another example of this disclosure is a display device with a reduced bezel area.

[0012] An example of achieving the above-described technical advantages provided in this disclosure is a thin-film transistor substrate, which includes a buffer layer disposed on a base substrate and a plurality of thin-film transistors disposed on the buffer layer, wherein the plurality of thin-film transistors include a plurality of active layers and a gate electrode overlapping at least a portion of each of the plurality of active layers, the buffer layer includes flat regions and sloping regions disposed alternately with each other, and the plurality of active layers are spaced apart from each other and disposed in the flat regions.

[0013] Multiple active layers include oxide semiconductor materials and may have a crystal structure.

[0014] Multiple active layers are configured to be spaced apart from each other in a first direction, and flat and sloping regions are configured to extend along a second direction perpendicular to the first direction, and the flat and sloping regions can be configured to be parallel to the first direction.

[0015] The buffer layer includes a first flat surface and a second flat surface disposed in the flat region, and an inclined surface disposed in the inclined region, and multiple active layers may not be disposed on the inclined surface.

[0016] The first flat surface, the inclined surface, and the second flat surface extend along a first direction, the inclined surface is disposed between the first flat surface and the second flat surface, and the shortest distance between the first flat surface and the base substrate can be shorter than the shortest distance between the second flat surface and the base substrate.

[0017] Preferably, the inclined surface may have a taper angle of 45 to 90°. In some examples, the taper angle may be between 45 and 50°. In some examples, the taper angle may be between 50 and 55°. In some examples, the taper angle may be between 45 and 65°. In some examples, the taper angle may be between 65 and 75°. In some examples, the taper angle may be between 75 and 90°.

[0018] Multiple active layers can have a spacing of 0.5 μm or less in a plane.

[0019] The plurality of active layers include a lower active layer disposed on a first flat surface and an upper active layer disposed on a second flat surface, wherein the lower active layer and the upper active layer are alternately disposed along a first direction, and the shortest distance between the upper surface of the lower active layer and the base substrate may be shorter than the shortest distance between the upper surface of the upper active layer and the base substrate.

[0020] The gate electrode can extend across multiple active layers in a first direction and be disposed on flat and sloping regions.

[0021] The thin-film transistor substrate also includes a gate insulating film disposed on a buffer layer, wherein multiple active layers are disposed between the buffer layer and the gate insulating film in a flat region, and the gate insulating film may contact the buffer layer in a sloping region.

[0022] The buffer layer may include grooves, inclined surfaces may be disposed on both sides of the grooves, and a first flat surface may be disposed between the inclined surfaces.

[0023] Another example of this disclosure may provide a method for manufacturing a thin-film transistor substrate, comprising the steps of: forming a buffer layer on a base substrate; forming a photoresist pattern on the buffer layer; using the photoresist pattern as a mask to etch the buffer layer to form alternating flat and sloping regions; forming an active material layer on the buffer layer; annealing the active material layer; and removing a portion of the active material layer disposed in the sloping regions by wet etching.

[0024] The active material layer placed on a flat area can be crystallized through an annealing process.

[0025] The thickness of the active material layer in the inclined region is 10% to 60% compared to the thickness of the active material layer in the flat region, and the thickness of the active material layer can be measured in a direction perpendicular to the surface of the buffer layer.

[0026] Based on the X-direction, the width of a single channel can be approximately 10 to 20 micrometers. Figure 1 The thin-film transistor (TFT) substrate shown can have a width of approximately 60 to 120 + (0.5 × 5 μm) micrometers. The spacing between active layers can be 0.5 μm or less. Based on the Y-direction, the length of a single channel can be approximately 5 to 10 micrometers. In some examples, based on the Y-direction, the length of a single active layer can be approximately 18 to 23 micrometers. Figure 1 The thin-film transistor (TFT) substrate shown can have a length of about 18 to 23 micrometers.

[0027] Another example of this disclosure may provide a display device including a thin-film transistor substrate. Attached Figure Description

[0028] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0029] Figure 1 This is a plan view of a thin-film transistor substrate according to an example of the present disclosure.

[0030] Figure 2 It is along Figure 1The cross-sectional view taken from line I-I'.

[0031] Figure 3 It is along Figure 1 The cross-sectional view taken from line II-II'.

[0032] Figure 4 It is shown in detail Figure 2 A magnified view of region A.

[0033] Figure 5 This is an enlarged view of a thin-film transistor substrate according to another example of this disclosure.

[0034] Figures 6A to 6H This is a process diagram illustrating the manufacturing process of a thin-film transistor substrate according to another example of this disclosure.

[0035] Figure 7 This is a schematic diagram of a display device according to another embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of a display panel as an example of the content of this disclosure.

[0037] Figure 9 This is a schematic diagram illustrating a step, as exemplified by one example of the content of this disclosure.

[0038] Figure 10 It is along Figure 8 The cross-sectional view taken from line III-III'.

[0039] Figure 11 yes Figure 10 A magnified view of region B. Detailed Implementation

[0040] The advantages and features of this disclosure and its examples will be illustrated by the following examples described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0041] The shapes, dimensions, ratios, angles, and quantities shown in the accompanying drawings to illustrate the present disclosure are merely examples, and therefore the present disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the present disclosure.

[0042] When using the terms “including,” “having,” and “containing” as described in this disclosure, an additional part may be added unless “only” is used. Unless otherwise stated, singular terms may include plural forms.

[0043] When interpreting the component, it is explained as including a error band, although there is no explicit description.

[0044] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "next to," one or more parts may be placed between two other parts unless "only" or "directly" is used.

[0045] Spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to readily describe the relationship between one or more elements and another element or elements as shown in the figures. It should be understood that these terms are intended to cover different orientations of the apparatus, in addition to those depicted in the figures. For example, if the apparatus shown in the figures is inverted, an arrangement described as being “below” or “above” another apparatus may be arranged “above” another apparatus. Thus, the exemplary term “below or under” can include both “below or under” and “above” orientations. Similarly, the exemplary term “above” or “upper” can include both “above” and “below or under” orientations.

[0046] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases can be included unless “only” or “directly” is used.

[0047] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0048] It should be understood that the term "at least one" includes all combinations relating to any one item. For example, "at least one of the first element, the second element, and the third element" can include two or more elements selected from the first, second, and third elements, as well as all combinations of each of the first, second, and third elements.

[0049] Features of the various examples of this disclosure may be linked or combined with each other, either partially or entirely, and may operate differently from each other and be technically driven, as will be fully understood by those skilled in the art. Examples of this disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

[0050] When adding reference numerals to components in each of the figures illustrating examples of this disclosure, the same components may have the same reference numerals as those that may be displayed in other figures.

[0051] In the examples of this disclosure, for ease of description, a source electrode and a drain electrode are distinguished, and the source electrode and drain electrode are interchangeable. A source electrode can be a drain electrode, and vice versa. Additionally, in another example, the source electrode in any one example can be a drain electrode, and in yet another example, the drain electrode in any one example can be a source electrode.

[0052] In some examples of the present invention, for ease of description, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode; however, the examples of the present invention are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0053] Figure 1 This is a plan view of a thin-film transistor substrate 100 according to an example of the present disclosure. Figure 2 It is along Figure 1 The cross-sectional view taken from line I-I'. Figure 3 It is along Figure 1 The cross-sectional view taken from line II-II'. Figure 4 It is shown in detail Figure 2 A magnified view of region A. Figure 5 This is an enlarged view of a thin-film transistor substrate according to another example of this disclosure.

[0054] According to one example of this disclosure, a thin-film transistor substrate (100) includes a plurality of thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6.

[0055] although Figure 1 A thin-film transistor substrate 100 is shown, comprising six thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6. However, the examples of this disclosure are not limited thereto, and may include fewer than six thin-film transistors or may include seven or more thin-film transistors.

[0056] According to one example of this disclosure, the multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 are not driven individually, but rather the thin-film transistor substrate 100 operates as a single transistor. That is, the multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 are driven simultaneously. Therefore, the thin-film transistor substrate 100 according to one example of this disclosure can be referred to as a single thin-film transistor.

[0057] According to one example of this disclosure, a buffer layer 120 may be disposed on a base substrate 110, and a plurality of thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 may be disposed on the buffer layer 120.

[0058] According to one example of this disclosure, multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, TR6 include multiple active layers 130 and gate electrodes 150.

[0059] The components of the base substrate 110, buffer layer 120, and multiple thin-film transistors TR1, TR2, TR3, TR4, TR5, and TR6 are described in detail below.

[0060] Glass or plastic can be used as the base substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as the plastic. For example, see reference... Figure 3 The third thin-film transistor TR3 can be disposed on the base substrate 110.

[0061] A light-shielding layer (not shown) may be disposed on the base substrate 110. The light-shielding layer (not shown) blocks light incident from the base substrate 110 and protects the multiple active layers 130. If another structure is used as the light-shielding structure, the light-shielding layer (not shown) may be omitted.

[0062] According to one example of this disclosure, a buffer layer 120 may be disposed on a base substrate 110.

[0063] The buffer layer 120 has insulating properties and protects multiple active layers 130. The buffer layer 120 may include at least one of insulating silicon oxide (SiOx), silicon nitride (SiNx), and metal oxide.

[0064] exist Figure 2 and Figure 3 In this embodiment, buffer layer 120 is shown as a single layer, but the examples of this disclosure are not limited thereto. Buffer layer 120 may include multiple layers. Furthermore, additional layers may be provided between the base substrate 110 and buffer layer 120, and additional layers may be provided between buffer layer 120 and multiple active layers 130.

[0065] According to one example of this disclosure, the buffer layer 120 includes alternately arranged flat regions P1, P2, P3, P4, P5 and sloping regions T1, T2, T3, T4.

[0066] Flat regions P1, P2, P3, P4, and P5 can respectively include the first flat region P1, the second flat region P2, the third flat region P3, the fourth flat region P4, and the fifth flat region P5. Inclined regions T1, T2, T3, and T4 can respectively include the first inclined region T1, the second inclined region T2, the third inclined region T3, and the fourth inclined region T4.

[0067] Figure 2 A buffer layer 120 is shown, comprising alternating flat regions P1, P2, P3, P4, P5 and sloping regions T1, T2, T3, T4. A first sloping region T1 may be located between a first flat region P1 and a second flat region P2. A second sloping region T2 may be located between a second flat region P2 and a third flat region P3. A third sloping region T3 may be located between a third flat region P3 and a fourth flat region P4. A fourth sloping region T4 may be located between a fourth flat region P4 and a fifth flat region P5. Although... Figure 2 Five flat regions P1, P2, P3, P4, and P5 are shown, but this disclosure is not limited to these examples, and there may be six or more, or fewer than five. Furthermore, although... Figure 2 Four inclined regions T1, T2, T3, and T4 are shown, but this disclosure is not limited to these and may have five or more, or fewer than four.

[0068] According to one example of this disclosure, multiple active layers 130 are disposed on buffer layer 120. For example, multiple active layers 130 may be disposed in flat regions P1, P2, P3, P4, while being spaced apart from each other. For example, at least one active layer 130, 131, 132, 133, 134, 135 may exist in each flat region P1, P2, P3, P4, while these active layers are spaced apart from each other by inclined regions T1, T2, T3, T4.

[0069] According to one example of this disclosure, multiple active layers 130 include oxide semiconductor materials.

[0070] The oxide semiconductor material may include at least one of the following: IZO (InZnO)-based oxide semiconductor material, IGO (InGaO)-based oxide semiconductor material, ITO (InSnO)-based oxide semiconductor material, IGZO (InGaZnO)-based oxide semiconductor material, IGZTO (InGaZnSnO)-based oxide semiconductor material, GZTO (GaZnSnO)-based oxide semiconductor material, GZO (GaZnO)-based oxide semiconductor material, ITZO (InSnZnO)-based oxide semiconductor material, and FIZO (FeInZnO)-based oxide semiconductor material. However, the examples in this disclosure are not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0071] Multiple active layers 130 may include a first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, a fifth active layer 135, and a sixth active layer 136. However, the examples of this disclosure are not limited thereto, and may include fewer than six active layers, or may include seven or more active layers.

[0072] For example, Figure 2 The diagram illustrates a configuration in which, among multiple active layers 130, a first active layer 131 is disposed in a first flat region P1, a second active layer 132 is disposed in a second flat region P2, a third active layer 133 is disposed in a third flat region P3, a fourth active layer 134 is disposed in a fourth flat region P4, and a fifth active layer 135 is disposed in a fifth flat region P5. In this example, the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, and the fifth active layer 135 are spaced apart from each other.

[0073] According to one example of this disclosure, when the direction connecting the source electrode 171 and the drain electrode 172 with the shortest distance is referred to as the second direction Y, the direction perpendicular to the second direction Y can be referred to as the first direction X.

[0074] According to one example of this disclosure, a plurality of active layers 130 are configured to be spaced apart from each other in parallel along a first direction X. According to one example of this disclosure, a plurality of active layers 130 are configured to extend along a second direction Y.

[0075] For example, Figure 1 A first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, a fifth active layer 135, and a sixth active layer 136 are shown, arranged parallel to each other along a first direction X. For example, Figure 1The diagram shows a first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, a fifth active layer 135, and a sixth active layer 136, which are configured to extend along the second direction Y.

[0076] According to one example of this disclosure, the flat regions P1, P2, P3, P4, P5 and the sloping regions T1, T2, T3, T4 of the buffer layer 120 are respectively configured to extend along the second direction Y.

[0077] For example, refer to Figure 1 and Figure 3 The third flat region P3 of the buffer layer can extend along the second direction Y.

[0078] According to one example of this disclosure, the flat regions P1, P2, P3, P4, P5 and the inclined regions T1, T2, T3, T4 of the buffer layer 120 may be arranged parallel to a first direction X.

[0079] For example, refer to Figure 1 and Figure 2 The flat regions P1, P2, P3, P4, P5 and the inclined regions T1, T2, T3, T4 of the buffer layer 120 can be arranged parallel to each other along the first direction X. Furthermore, any one of the flat regions P1, P2, P3, P4, P5 can be located between two other inclined regions T1, T2, T3, T4. Additionally, any one of the inclined regions T1, T2, T3, T4 can be located between two other flat regions P1, P2, P3, P4, P5.

[0080] According to one example of this disclosure, buffer layer 120 may include a first flat surface TS1 and a second flat surface TS2 disposed in flat regions P1, P2, P3, P4, P5. Buffer layer 120 may also include an inclined surface SS disposed in each inclined region T1, T2, T3, T4.

[0081] Figure 4 A buffer layer 120 is shown, comprising a first flat surface TS1, a second flat surface TS2, and a sloping surface SS. For example, the first flat surface TS1 may be the surface of the second flat region P2 and the fourth flat region P4, the second flat surface TS2 may be the surface of the first flat region P3, the third flat region P3, and the fifth flat region P5, and the sloping surface SS may be the surface of the sloping regions T1, T2, T3, and T4.

[0082] According to one example of this disclosure, a flat surface may refer to a surface in the buffer layer 120 that is parallel to the upper surface of the base substrate 110. An inclined surface may refer to a surface in the buffer layer 120 that has an angle relative to the upper surface of the base substrate 110.

[0083] According to one example of this disclosure, the shortest distance between the first flat surface TS1 and the base substrate 110 may be shorter than the shortest distance between the second flat surface TS2 and the base substrate 110. For example, the first flat surface TS1 is configured to be closer to the base substrate 110 than the second flat surface TS2.

[0084] According to one example of this disclosure, a second active layer 132 is disposed on a first flat surface TS1, and a third active layer 133 is disposed on a second flat surface TS2. The second active layer 132 and the third active layer 133 are not disposed on an inclined surface SS (e.g., Figure 4 (As shown).

[0085] According to one example of this disclosure, multiple active layers 130 may be disposed on a first flat surface TS1 and a second flat surface TS2. Each active layer 132, 133 may include regions a1, a2. Regions a1, a2 are configured to remain at the ends of the inclined surface SS (e.g., Figure 5 (As shown). Regions a1 and a2 are configured to be located at the ends of the inclined surface SS. The thickness of regions a1 and a2 retained at the ends of the inclined surface SS can be less than the thickness of the plurality of active layers 132 and 133 disposed on the first flat surface TS1 and the second flat surface TS2.

[0086] Since regions a1 and a2 retained at the ends of the inclined surface SS are provided along the inclined surface SS, regions a1 and a2 retained at the ends of the inclined surface SS can be configured to extend along the second direction Y. Regions a1 and a2 retained at the ends of the inclined surface SS may include region a1 retained at the lower end of the inclined surface SS and region a2 retained at the upper end of the inclined surface SS.

[0087] According to one example of this disclosure, a first flat surface TS1, an inclined surface SS, and a second flat surface TS2 extend along a first direction X.

[0088] Figure 2 and Figure 4 A first flat surface TS1, an inclined surface SS, and a second flat surface TS2 are shown extending sequentially along a first direction X. That is, along the first direction X, the first flat surface TS1 extends to the inclined surface SS, and the inclined surface SS extends to the second flat surface TS2.

[0089] According to one example of this disclosure, an inclined surface SS is disposed between a first flat surface TS1 and a second flat surface TS2. Figure 4 The diagram shows a state where a first flat surface TS1 is disposed on one side of an inclined surface SS and a second flat surface TS2 is disposed on the other side of the inclined surface SS.

[0090] According to one example of this disclosure, when an active material layer 130m is formed in the flat regions P1, P2, P3, P4, P5 and the inclined regions T1, T2, T3, T4 of the buffer layer 120, the active material layer 130m has a thin thickness in the inclined regions T1, T2, T3, T4 due to the cone angle of the buffer layer 120 (see [link to relevant documentation]). Figure 6C On the other hand, since the flat regions P1, P2, P3, P4, and P5 are flat relative to the base substrate 110, the active material layer 130m is formed with a thicker thickness in the flat regions P1, P2, P3, P4, and P5 compared to the inclined regions T1, T2, T3, and T4.

[0091] For example, compared with the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, P5, the thickness of the active material layer 130m in the inclined regions T1, T2, T3, T4 can be 10% to 60% of the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, P5.

[0092] For example, when the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, and P5 is 30nm, the thickness of the active material layer 130m in the inclined regions T1, T2, T3, and T4 can be from 3nm to 18nm. In this example, the thickness of the active material layer 130m is measured in a direction perpendicular to the surface of the buffer layer 120.

[0093] Subsequently, when the active material layer 130m is annealed, the active material layer 130m formed in the flat regions P1, P2, P3, P4, and P5 can have a thickness sufficient for crystallization, and thus can have a crystalline structure.

[0094] On the other hand, the active material layer 130m formed in the inclined regions T1, T2, T3, and T4 does not have sufficient thickness for crystallization, so it can have an amorphous structure, or it can have both a crystalline and amorphous structures at the same time.

[0095] According to one example of this disclosure, a layer is referred to as having a crystalline structure when the total area of ​​regions with particle sizes of 1 nanometer or larger accounts for 50% or more of the total cross-sectional area. For example, in an active material layer 130m formed in a first flat region P1, the total area of ​​regions with particle sizes of 1 nanometer or larger can account for 50% or more of the total cross-sectional area, preferably 80% or more. In another example, in an active material layer 130m formed in a first inclined region T1, the total area of ​​regions with particle sizes of 1 nanometer or larger can account for less than 50% of the total cross-sectional area. Specifically, the particle size is measured based on a transmission electron microscope (TEM) image of the cross-section of the layer to be measured.

[0096] Subsequently, when wet etching is performed on the active material layer 130m, the active material layer 130m with an amorphous structure can be removed. However, the active material layer 130m without an amorphous structure has strong resistance to wet etching and can be left unremoved.

[0097] At this point, if the active material layer 130m with an amorphous structure is completely removed, then multiple active layers 130 do not need to be disposed on the inclined surface SS, such as... Figure 4 As shown. However, if the active material layer 130m with an amorphous structure is not completely removed by wet etching, or if the active material layer 130m with both a crystalline and amorphous structure is removed by wet etching, multiple active layers 130 will be partially retained at the ends of the inclined surface SS.

[0098] Therefore, multiple active layers 130 with crystal structures can be formed in the flat regions P1, P2, P3, P4, and P5 of the buffer layer 120.

[0099] If the thickness of the active material layer of 130 μm in the tilted regions T1, T2, T3, and T4 is too high, crystallization may occur in the tilted regions T1, T2, T3, and T4 during the annealing process, and may not be removed by wet etching even if wet etching is performed.

[0100] Furthermore, if the thickness of the active material layer 130m in the inclined regions T1, T2, T3, and T4 is too low, the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, and P5 will also become low, preventing crystallization during the annealing process.

[0101] According to one example of this disclosure, the inclined surface SS of the buffer layer 120 may have a cone angle of 45 to 90°.

[0102] When the cone angle of the inclined surface SS is less than 45°, the difference between the thickness of the active material layer 130m in the flat regions P1, P2, P3, P4, P5 and the thickness of the active material layer 130m in the inclined regions T1, T2, T3, T4 decreases, so it may be difficult to completely separate the multiple active layers 130.

[0103] Additionally, when the cone angle of the inclined surface SS exceeds 90°, it may be difficult to actually implement the cone angle of the inclined surface SS as 90° or greater.

[0104] Therefore, in order to separate multiple active layers 130, the inclined surface SS of the buffer layer 120 needs to have a cone angle of 45 to 90°.

[0105] According to one example of this disclosure, multiple active layers 130 may have a spacing of 0.5 μm or less in a plane.

[0106] Reference Figure 4 Multiple active layers 130 can have a spacing W of less than 0.5 μm.

[0107] exist Figure 2 and Figure 4 In the multiple active layers 130, the second active layer 132 and the third active layer 133 can have a spacing W of 0.5 μm or less.

[0108] According to one example of this disclosure, the plurality of active layers 130 may include lower active layers 132 and 134 disposed on a first flat surface TS1 and upper active layers 131, 133, and 135 disposed on a second flat surface TS2. For example, the lower active layers 132 and 134 may include a second active layer 132 and a fourth active layer 134, and the upper active layers 131, 133, and 135 may include a first active layer 131, a third active layer 133, and a fifth active layer 135.

[0109] According to one example of this disclosure, the shortest distance between the upper surface of the lower active layers 132, 134 and the base substrate 110 may be shorter than the shortest distance between the upper surface of the upper active layers 131, 133, 135 and the base substrate 110. For example, Figure 2 It is shown that the lower active layers 132 and 134 are positioned closer to the base substrate 110 than the upper active layers 131, 133 and 135.

[0110] refer to Figure 2 and Figure 4A lower active layer (such as a second active layer 132 and a second active layer 134) is disposed on a first flat surface TS1, and an upper active layer (such as a first active layer 131, a third active layer 133, and a fifth active layer 135) is disposed on a second flat surface TS2. For example, the lower active layer is disposed on the second flat region P2 and the fourth flat region P4, and the upper active layer is disposed on the first flat region P1, the third flat region P3, and the fifth flat region P5.

[0111] According to one example of this disclosure, the lower active layer and the upper active layer may be alternately arranged along a first direction X. For example, Figure 2 An example is shown where the lower active layer and the upper active layer are alternately arranged. For example, the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134 and the fifth active layer 135 can be arranged sequentially along the first direction X.

[0112] According to one example of this disclosure, buffer layer 120 may include trench 126. According to one example of this disclosure, trench 126 may represent an etched area of ​​buffer layer 120.

[0113] Reference Figure 2 and Figure 4 Inclined surfaces SS can be disposed on both sides of the groove 126, and a first flat surface TS1 can be disposed between the inclined surfaces SS located on both sides.

[0114] According to one example of this disclosure, a gate insulating film 140 is disposed on a plurality of active layers 130. Specifically, the gate insulating film 140 is disposed between the plurality of active layers 130 and the gate electrode 150.

[0115] According to one example of this disclosure, the gate insulating film 140 may cover the entire upper surface of a plurality of active layers 130. Figure 2 and Figure 3 The diagram shows a gate insulating film 140 covering the entire upper surface of a plurality of active layers 130. However, the examples of this disclosure are not limited thereto, and the gate insulating film 140 may expose a portion of the plurality of active layers 130.

[0116] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single-layer or multi-layer structure. The gate insulating film 140 protects multiple active layers 130.

[0117] According to one example of this disclosure, a plurality of active layers 130 are disposed between a buffer layer 120 and a gate insulating film 140 in flat regions P1, P2, P3, P4, P5. For example, the plurality of active layers 130 are disposed between the buffer layer 120 and the gate insulating film 140 in regions overlapping with the flat regions P1, P2, P3, P4, P5. For example, see reference... Figure 2 The third active layer 133 can be disposed between the buffer layer 120 and the gate insulating film 140 in the region overlapping with the third flat region P3.

[0118] According to one example of this disclosure, the gate insulating film 140 may contact the buffer layer 120 in the inclined regions T1, T2, T3, T4. For example, the gate insulating film 140 may contact the buffer layer 120 in the region overlapping with the inclined regions T1, T2, T3, T4. For example, refer to... Figure 2 The gate insulating film 140 can contact the buffer layer 120 in the region that overlaps with the second tilted region T2.

[0119] According to one example of this disclosure, the gate electrode 150 may be disposed on the gate insulating film 140.

[0120] refer to Figure 1 , Figure 2 and Figure 3 The gate electrode 150 may overlap at least a portion of each of the plurality of active layers 130. For example, refer to Figure 1 The gate electrode 150 may overlap with a portion of each of the first active layer 131, the second active layer 132, the third active layer 133, the fourth active layer 134, the fifth active layer 135, and the sixth active layer 136. Each of the multiple active layers 130 may have a channel region overlapping with the gate electrode 150.

[0121] The gate electrode 150 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may also have a multilayer film structure comprising at least two conductive films with different physical properties.

[0122] According to one example of this disclosure, the gate electrode 150 may extend across a plurality of active layers 130 along a first direction X.

[0123] Figure 1A gate electrode 150 is shown extending along a first direction X across a first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, a fifth active layer 135, and a sixth active layer 136. For example, the gate electrode 150 may be disposed on the flat regions P1, P2, P3, P4, P5 and the sloping regions T1, T2, T3, T4 of the buffer layer 120.

[0124] An interlayer insulating film 160 is disposed on the gate electrode 150. The interlayer insulating film 160 is an insulating layer made of insulating material. Specifically, the interlayer insulating film 160 may be made of organic material, inorganic material, or a laminate of organic material layer and inorganic material layer.

[0125] Source electrode 171 and drain electrode 172 are disposed on interlayer insulating film 160. Source electrode 171 and drain electrode 172 are spaced apart from each other and each is connected to a plurality of active layers 130. Source electrode 171 and drain electrode 172 are each connected to the plurality of active layers 130 through contact holes formed in interlayer insulating film 160. According to one example of this disclosure, source electrode 171 may be integrally formed. According to one example of this disclosure, drain electrode 172 may be integrally formed. According to one example of this disclosure, source electrode 171 may be integrally formed, and drain electrode 172 may also be integrally formed.

[0126] The source electrode 171 and the drain electrode 172 may each comprise at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. The source electrode 171 and the drain electrode 172 may each be formed as a single layer of metal or metal alloy, or may be formed as a multilayer having two or more layers.

[0127] Figures 6A to 6H This is a manufacturing process diagram of a thin-film transistor substrate 100 according to another example of this disclosure. Details of the configuration already described above have been omitted.

[0128] Figures 6A to 6H The cross-sectional view shown corresponds to Figure 2 The cross-sectional view shown.

[0129] refer to Figure 6A A buffer layer 120 can be formed on the base substrate 110, and a photoresist pattern 125 can be formed on the buffer layer 120. For example, the photoresist pattern 125 is configured to overlap a portion of the buffer layer 120.

[0130] Referring to Figure 6b, the photoresist pattern 125 can be used as a mask to etch the buffer layer 120 to form trenches 126. Specifically, the buffer layer 120 can be etched to form alternating flat regions P1, P2, P3, P4, P5 and sloping regions T1, T2, T3, T4. More specifically, after etching the buffer layer 120, the photoresist pattern 125 disposed on the buffer layer 120 can be removed.

[0131] According to one example of this disclosure, the buffer layer 120 may have a cone angle of 45 to 90° in the inclined regions T1, T2, T3, T4.

[0132] Reference Figure 6C An active material layer 130m can be formed on the buffer layer 120. The active material layer 130m may include an oxide semiconductor material. The oxide semiconductor material may include at least one of the following materials: IZO (InZnO) based oxide semiconductor material, IGO (InGaO) based oxide semiconductor material, ITO (InSnO) based oxide semiconductor material, IGZO (InGaZnO) based oxide semiconductor material, IGZTO (InGaZnSnO) based oxide semiconductor material, GZTO (GaZnSnO) based oxide semiconductor material, GZO (GaZnO) based oxide semiconductor material, ITZO (InSnZnO) based oxide semiconductor material, and FIZO (FeInZnO) based oxide semiconductor material. However, the examples in this disclosure are not limited thereto, and the active material layer 130m may be formed of other oxide semiconductor materials known in the art.

[0133] According to one example of this disclosure, the thickness L2 of the active material layer 130m disposed in the inclined regions T1, T2, T3, T4 can be 10% to 60% of the thickness L1, compared to the thickness L1 of the active material layer 130m disposed in the flat regions P1, P2, P3, P4, P5. The thickness of the active material layer 130m is measured in a direction perpendicular to the surface of the buffer layer 120.

[0134] refer to Figure 6D The active material layer 130m can be annealed. When the active material layer 130m is annealed, the active material layer 130m formed in the flat regions P1, P2, P3, P4, and P5 has a thickness sufficient for crystallization, and therefore can have a crystalline structure. On the other hand, the active material layer 130m formed in the inclined regions T1, T2, T3, and T4 does not have a thickness sufficient for crystallization, and therefore can have an amorphous structure. Thus, it is possible to have both a crystalline and amorphous structure simultaneously.

[0135] For example, the annealing step can be performed at a temperature of 350°C to 450°C. However, as an example of this disclosure, it is not limited to this, and the temperature can vary from 350°C to 450°C.

[0136] refer to Figure 6E A portion of the 130m active material layer can be removed by wet etching.

[0137] For example, the active material layer 130m located in the inclined regions T1, T2, T3, and T4 that has not undergone crystallization can be selectively removed by wet etching.

[0138] According to one example of this disclosure, a plurality of active layers 130 spaced apart from each other can be formed by wet etching. For example, a first active layer 131, a second active layer 132, a third active layer 133, a fourth active layer 134, and a fifth active layer 135 spaced apart from each other can be formed.

[0139] According to one example of this disclosure, a separate mask is not required in the wet etching process. Specifically, even if wet etching is performed on the entire active material layer 130m, the active material layer 130m, which has a crystalline structure, may not be selectively removed because it is highly resistant to the etchant.

[0140] refer to Figure 6F A gate insulating film 140 may be formed on the buffer layer 120 and the plurality of active layers 130. A description of the gate insulating film 140 is omitted because it is repeated above.

[0141] refer to Figure 6G A gate electrode 150 can be formed on the gate insulating film 140. A description of the gate electrode 150 is omitted because it is repetitive with the previous content.

[0142] refer to Figure 6H An interlayer insulating film 160 can be formed on the gate electrode 150. A description of the interlayer insulating film 160 is omitted because it is repeated from the previous content.

[0143] Figure 7 A schematic diagram of a display device 1000, which is yet another example of the contents of this disclosure.

[0144] like Figure 7 As shown, a display device 1000 according to another example of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0145] The display panel 310 includes gate lines GL and data lines DL, and a pixel P is disposed at the intersection of the gate lines GL and DL. An image is displayed by driving the pixel P. The gate lines GL, DL, and pixel P can be disposed on the base substrate 110.

[0146] The controller 340 controls the gate driver 320 and the data driver 330.

[0147] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using a signal provided by an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, realigns the sampled data, and provides the realigned digital image data (RGB) to the data driver 330.

[0148] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Furthermore, control signals for controlling the shift register can be included in the gate control signal GCS.

[0149] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0150] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and supplies the data voltage to the data line DL.

[0151] According to one example of this disclosure, the gate driver 320 can be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 310 is referred to as a Gate In Panel (GIP) structure. Specifically, in a GIP structure, the gate driver 320 can be disposed on the base substrate 110.

[0152] A display device 1000 according to one example of the present disclosure may include the aforementioned thin-film transistor substrate 100. According to one example of the present disclosure, a gate driver 320 may include the aforementioned thin-film transistor substrate 100.

[0153] Gate driver 320 may include shift register 350.

[0154] The shift register 350 sequentially supplies gate pulses to the gate line GL for one frame using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage that enables the switching device (thin-film transistor) disposed in the pixel P to conduct.

[0155] In addition, shift register 350 provides a turn-off signal to gate line GL during another frame cycle in which no gate pulse is provided, enabling the gate of the switching device to turn off. Hereinafter, the gate pulse and the gate turn-off signal will be collectively referred to as the scan signal SS or Scan.

[0156] The shift register 350 may include the thin-film transistor substrate 100 described above.

[0157] See Figure 7 According to one example of this disclosure, shift register 350 may include multiple stages ST.

[0158] Figure 8 This is a schematic diagram of a display panel 310 as an example of the present disclosure.

[0159] The display panel may include a display area AA and a non-display area IA.

[0160] Multiple pixels P can be set in the display area AA to display an image. No image can be displayed in the non-display area IA. The non-display area IA can be configured to surround the display area AA. The gate driver 320 can be located in the non-display area IA.

[0161] The display panel may include a first thin-film transistor (T3). The first thin-film transistor (T3) may be disposed in a non-display area (IA). The first thin-film transistor (T3) may include a first active layer (A3) having a plurality of mutually spaced sub-active layers (A31, A32, A33, A34, A35, A36, A37). The first thin-film transistor (T3) may include a first gate electrode (G3) overlapping at least a portion of the first active layer (A3). The display panel may include a second thin-film transistor (T4) disposed in the non-display area (IA). The second thin-film transistor may include a buffer layer (112) disposed on a base substrate (110), a second active layer (A4) disposed on the buffer layer (112), and a second gate electrode (G4) overlapping at least a portion of the second active layer (A4). The buffer layer (112) may include a plurality of alternately disposed flat regions and a plurality of sloping regions. The plurality of sub-active layers may be mutually spaced and disposed in the plurality of flat regions.

[0162] Figure 9This is a schematic block diagram of a level ST as an example of the content of this disclosure.

[0163] See Figure 9 The stage ST includes a node controller 105. The node controller 105 is configured to control the voltages of the first and second nodes Q and Qb. The node controller 105 is configured to control the voltages of the first and second nodes Q and Qb according to a carry signal CR and a reset signal RST. The stage ST includes an output unit 200. The output unit 200 is configured to output an input clock signal CLK as a scan pulse and an auxiliary scan pulse according to the voltage levels of the first and second nodes Q and Qb. In this case, the scan pulse is output through the first output terminal OUT1 of the stage ST, and the auxiliary scan pulse is output through the second output terminal OUT2 of the stage ST.

[0164] Stage ST can receive the turn-on voltage VGH. Stage ST can receive the first cut-off voltage VGL1. Stage ST can receive the second cut-off voltage VGL2.

[0165] Figure 10 It is along Figure 8 The cross-sectional view taken from line III-III'. Figure 11 yes Figure 10 A magnified view of the central area B.

[0166] See Figure 10 The first thin-film transistor T1 and the second thin-film transistor T2 are disposed in the display area AA. The display element 710 can be disposed in the display area AA. The third thin-film transistor T3 and the fourth thin-film transistor T4 are disposed in the non-display area IA. The first thin-film transistor T1 can be disposed on the base substrate 110. The second thin-film transistor T2 can be disposed on the base substrate 110. The third thin-film transistor T3 can be disposed on the base substrate 110. The fourth thin-film transistor T4 can be disposed on the base substrate 110.

[0167] Specifically, the gate driver 320 disposed in the non-display area IA may include a third thin-film transistor T3 and a fourth thin-film transistor T4.

[0168] The description of the base substrate 110 is omitted here because it is a repetition of the previous description.

[0169] The first buffer layer 111 and the second buffer layer 112 can be disposed on the base substrate 110.

[0170] The first buffer layer 111 and the second buffer layer 112 are each made of insulating material. Therefore, advantageously, the first buffer layer 111 and the second buffer layer 112 can protect the active layers A1, A2, A3, and A4 of the thin-film transistors T1, T2, T3, and T4 from externally introduced moisture, oxygen, etc. The second buffer layer 112 can extend from the non-display area IA to the display area AA.

[0171] According to one example of this disclosure, the second buffer layer 112 may include a trench TCH. The trench TCH may have a first cone angle θ1. The first cone angle θ1 of the trench TCH may be smaller than the second cone angle θ2 of the second intermediate buffer layer 138, which will be described below. In some examples, the first cone angle θ1 of the trench TCH may be 5 degrees smaller than the second cone angle θ2 of the second intermediate buffer layer 138. In some examples, the first cone angle θ1 of the trench TCH may be 0 to 10 degrees smaller than the second cone angle θ2 of the second intermediate buffer layer 138. In some examples, the first cone angle θ1 of the trench TCH may be 10 to 20 degrees smaller than the second cone angle θ2 of the second intermediate buffer layer 138. Multiple trench TCHs may be provided.

[0172] According to one example of this disclosure, the trench TCH of the second buffer layer 112 may overlap with the third thin-film transistor T3. The trench TCH of the second buffer layer 112 may not be located in the display area AA. Furthermore, the trench TCH of the second buffer layer 112 may not overlap with the fourth thin-film transistor T4. Specifically, the trench TCH of the second buffer layer 112 may not overlap with the fourth active layer A4 of the fourth thin-film transistor T4. According to one example of this disclosure, at least a portion of the trench TCH of the second buffer layer 112 may overlap with the third active layer A3 of the third thin-film transistor T3.

[0173] According to one example of this disclosure, the second buffer layer 112 may correspond to Figure 1 The buffer layer 120 is shown. Therefore, a detailed description of the second buffer layer 112 will be omitted.

[0174] The fourth active layer A4 of the fourth thin-film transistor T4 is disposed on the second buffer layer 112. The fourth active layer A4 may include a fourth channel region CN4 that overlaps with the fourth gate electrode G4 of the fourth thin-film transistor T4.

[0175] The bottom shielding metal (BSM) can be disposed below the fourth thin-film transistor T4. The bottom shielding metal (BSM) can be disposed on the first buffer layer 111.

[0176] A first bottom interlayer insulating film 121 is disposed on the second buffer layer 112. The first bottom interlayer insulating film 121 has insulating properties.

[0177] See Figure 10 The first capacitor electrode CE1, the first light-shielding layer LS1, the third light-shielding layer LS3, and the fourth gate electrode G4 can be disposed on the first bottom interlayer insulating film 121. The first capacitor electrode CE1, the first light-shielding layer LS1, the third light-shielding layer LS3, and the fourth gate electrode G4 can be disposed on the same layer and can be made of the same material.

[0178] A second bottom interlayer insulating film 122 is disposed on the first capacitor electrode CE1, the first light-shielding layer LS1, the third light-shielding layer LS3, and the fourth gate electrode G4. A second capacitor electrode CE2 may be disposed on the second bottom interlayer insulating film 122. The first capacitor electrode CE1 and the second capacitor electrode CE2 overlap to form a first capacitor C1.

[0179] According to one example of this disclosure, the fourth gate electrode G4 of the fourth thin-film transistor T4 may be integrally formed with the third light-shielding layer LS3 of the third thin-film transistor T3.

[0180] The first intermediate buffer layer 137 is disposed on the second capacitor electrode CE2. The second light-shielding layer LS2 may be disposed on the first intermediate buffer layer 137.

[0181] See Figure 10 The second intermediate buffer layer 138 can be disposed on the second light-shielding layer LS2.

[0182] Active layers A1, A2, and A3 are disposed on the second intermediate buffer layer 138. Active layers A1, A2, and A3 may include the first active layer A1 of the first thin-film transistor T1, the second active layer A2 of the second thin-film transistor T2, and the third active layer A3 of the third thin-film transistor T3.

[0183] The active layers A1, A2, and A3 may include, for example, an oxide semiconductor material. The active layers A1, A2, and A3 may be oxide semiconductor layers formed of an oxide semiconductor material. Specifically, the third active layer A3 may have a crystal structure.

[0184] According to one example of this disclosure, after the third active layer A3 is formed from an amorphous oxide semiconductor material, the third active layer A3 can be crystallized by annealing and formed by wet etching to form a third active layer A3 with a crystal structure.

[0185] The fourth active layer A4 may include a low-temperature polycrystalline silicon (LTPS) semiconductor material. However, this disclosure is not limited thereto.

[0186] The active layers A1, A2 and A4 can each have channel regions CN1, CN2 and CN4 respectively.

[0187] See Figure 10 and Figure 11 The third active layer A3 may include multiple sub-active layers A31, A32, A33, A34, A35, A36 and A37. Figure 10 and Figure 11 The third active layer A3 shown corresponds to Figure 1 The active layer 130 shown corresponds to multiple sub-active layers A31, A32, A33, A34, A35, and A36. Figure 1 The multiple active layers 131, 132, 133, 134, 135 and 136 shown.

[0188] A gate insulating film 140 is disposed on the active layers A1, A2, and A3. The gate insulating film 140 has insulating properties and separates the active layers A1, A2, and A3 from the gate electrodes G1, G2, and G3. The gate insulating film 140 may cover the entire upper surface of the active layers A1, A2, and A3.

[0189] Gate electrodes G1, G2, and G3 are disposed on gate insulating film 140. Interlayer insulating film 160 is disposed on gate electrodes G1, G2, and G3.

[0190] Source electrodes S1, S2 and S4 and drain electrodes D1, D2 and D4 are disposed on the interlayer insulating film 160.

[0191] The first gate electrode G1 can be connected to the first light-shielding layer LS1 via a connecting electrode. Therefore, the same voltage as the first gate electrode G1 can be applied to the first light-shielding layer LS1. Figure 10 The first thin-film transistor T1 shown can be considered to have a dual-gate structure.

[0192] The first thin-film transistor T1 may include a first active layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first thin-film transistor T1 can be used as a switching transistor to control the data voltage Vdata applied to the pixel driving unit.

[0193] The second thin-film transistor T2 may include a second active layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second thin-film transistor T2 serves as a driving transistor for controlling the driving voltage applied to the display element 710.

[0194] A passivation film 170 is disposed on the source electrodes S1, S2, S4 and the drain electrodes D1, D2, D4. A first planarization layer 180 is disposed on the passivation film 170. The first planarization layer 180 planarizes the upper parts of the first thin-film transistor T1, the second thin-film transistor T2, the third thin-film transistor T3 and the fourth thin-film transistor T4.

[0195] The connecting electrode 185 can be disposed on the first planarization layer 180. The connecting electrode 185 can be used to connect the second source electrode S2 and the pixel electrode 711.

[0196] The second planarization layer 190 is disposed on the first planarization layer 180 and the connecting electrode 185. The second planarization layer 190 planarizes the upper surface of the pixel driving unit.

[0197] The pixel electrode 711 of the display element 710 is disposed on the second planarization layer 190. A barrier layer 730 is disposed at the edge of the pixel electrode 711. The barrier layer 730 defines the light-emitting area of ​​the display element 710.

[0198] An organic light-emitting layer 712 is disposed on a pixel electrode 711, and a common electrode 713 is disposed on an organic light-emitting layer 712.

[0199] The common electrode 713 is disposed on the organic light-emitting layer 712, or it can be disposed on the barrier layer 730.

[0200] The pixel electrode 711, the organic light-emitting layer 712, and the common electrode 713 constitute the display element 710. Figure 10 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 1000 according to an example of this disclosure is an organic light-emitting display device.

[0201] A cover layer can be disposed on the common electrode 713. The cover layer is used to protect the display element 710 and can have insulating properties.

[0202] See Figure 10 The first encapsulation layer 751 is disposed on the common electrode 713. The first encapsulation layer 751 can protect the upper part of the display element 710.

[0203] The second encapsulation layer 752 is disposed on the first encapsulation layer 751. The second encapsulation layer 752 may also be referred to as a particle cover layer (PCL). The second encapsulation layer 752 can prevent irregularities from appearing on the surface of the display device 1000 due to particles generated during the manufacturing process of the display device 1000.

[0204] The third encapsulation layer 753 can be disposed on the second encapsulation layer 752. The third encapsulation layer 753 can be formed of an inorganic film having a dense thin film structure. The third encapsulation layer 753 can prevent or inhibit the penetration of moisture or oxygen.

[0205] According to one example of this disclosure, the first encapsulation layer 751, the second encapsulation layer 752, and the third encapsulation layer 753 may be collectively referred to as encapsulation components.

[0206] Based on this disclosure, the following beneficial effects can be obtained.

[0207] According to one example of the present disclosure, a thin-film transistor substrate can separate the active layers from each other by providing a stepped layer below the active layer.

[0208] According to another example of this disclosure, the thin-film transistor substrate can minimize the gap between active layers.

[0209] According to another example of this disclosure, the display device may have a reduced border area.

[0210] In addition to the effects described above, other features and advantages of this disclosure are described below, or may be clearly understood by those skilled in the art from such description and explanation.

[0211] It will be apparent to those skilled in the art that the above disclosure is not limited to the examples and drawings described above, and that various substitutions, modifications, and variations may be made in the disclosure without departing from its spirit or scope. Therefore, the scope of the disclosure is defined by the appended claims, and all variations or modifications intended to be derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of this disclosure.

[0212] This document describes a thin-film transistor substrate (100) comprising: a buffer layer (120) disposed on a base substrate (110) and a plurality of thin-film transistors (TR1, TR2, TR3, TR4, TR5, TR6) disposed on the buffer layer (120), wherein the plurality of thin-film transistors (TR1, TR2, TR3, TR4, TR5, TR6) includes a plurality of active layers (130, 131, 132, 133, 134, 135, 136) and the plurality of active layers Gate electrodes (150) overlapping at least a portion of each of (130, 131, 132, 133, 134, 135, 136), wherein the buffer layer (120) includes a plurality of flat regions (P1, P2, P3, P4, P5) and a plurality of sloping regions (T1, T2, T3, T4) alternately disposed with each other, and wherein the plurality of active layers (130, 131, 132, 133, 134, 135, 136) are spaced apart from each other and disposed in the plurality of flat regions (P1, P2, P3, P4, P5).

[0213] This article also describes a display device including the aforementioned thin-film transistor substrate.

[0214] This document describes a method for manufacturing a display device including a thin-film transistor substrate (100), the method comprising the following steps: forming a buffer layer (120) on a base substrate (110); forming a photoresist pattern (125) on the buffer layer (120); etching the buffer layer (120) using the photoresist pattern (125) as a mask to form alternately arranged flat regions (P1, P2, P3, P4, P5) and tilted regions (T1, T2, T3, T4); forming an active material layer (130m) on the buffer layer (120); annealing the active material layer (130m); and removing the active material layer (130m) from the tilted regions (T1, T2, T3, T4) by wet etching. A portion of the T4 region; and optionally, the active material layer (130m) disposed in the flat region (P1, P2, P3, P4, P5) is crystallized by annealing; and optionally, the buffer layer (120) has a cone angle of 45 to 90° in the inclined region (T1, T2, T3, T4); and optionally, the thickness of the active material layer (130m) disposed in the inclined region (T1, T2, T3, T4) is 10% to 60% compared with the thickness of the active material layer (130m) disposed in the flat region (P1, P2, P3, P4, P5), and wherein the thickness of the active material layer (130m) is measured in a direction perpendicular to the surface of the buffer layer (120).

[0215] This document also describes the following terms:

[0216] C1. A display device, comprising: a display area (AA) and a non-display area (IA) surrounding the display area (AA); a first thin-film transistor (T3) disposed in the non-display area (IA), the first thin-film transistor (T3) including a first active layer (A3) and a first gate electrode (G3), the first active layer (A3) having a plurality of mutually spaced sub-active layers (A31, A32, A33, A34, A35, A36, A37), the first gate electrode (G3) overlapping at least a portion of the first active layer (A3); and a non-display area disposed in the non-display area. The second thin-film transistor (T4) in region (IA) includes a buffer layer (112) disposed on a base substrate (110), a second active layer (A4) disposed on the buffer layer (112), and a second gate electrode (G4) overlapping at least a portion of the second active layer (A4). The buffer layer (112) includes alternately disposed flat regions and sloping regions, and a plurality of sub-active layers (A31, A32, A33, A34, A35, A36, A37) are spaced apart from each other and disposed in the flat regions.

[0217] C2. The display device according to Clause C1, wherein a buffer layer (112) extends from a non-display area (IA) to a display area (AA), wherein the buffer layer (112) includes a trench (TCH), wherein at least a portion of the trench (TCH) overlaps with a first active layer (A3) of a first thin-film transistor (T3).

[0218] C3. The display device according to clause C2, wherein the trench (TCH) is not provided in the display area (AA).

[0219] C4. A display device according to any one of clauses C2 to C3, wherein the trench (TCH) does not overlap with the second active layer (A4) of the second thin-film transistor (T4).

[0220] C5. The display device according to any one of clauses C2 to C4, wherein the first active layer (A3) comprises an oxide semiconductor material, and wherein the second active layer (A4) comprises a low-temperature polycrystalline silicon semiconductor material.

[0221] C6. The display device according to any one of clauses C2 to C5, wherein the first thin film transistor (T3) includes a first light-shielding layer (LS3) overlapping with the first active layer (A3), and wherein the first light-shielding layer (LS3) is integrally formed with the second gate electrode (G4).

[0222] C7. The display device according to clause C6, wherein the first thin film transistor (T3) includes an intermediate buffer layer (138) disposed below the first active layer (A3), wherein the first active layer (A3) is disposed on the upper surface of the intermediate buffer layer (138), wherein the buffer layer (112) has a first cone angle (θ1), and wherein the intermediate buffer layer (138) has a second cone angle (θ2) greater than the first cone angle (θ1).

[0223] C8. The display device according to any one of clauses C1 to C7 further includes a first bottom interlayer insulating film (121) and a second bottom interlayer insulating film (122); the display device further includes a first capacitor electrode (CE1), a first light-shielding layer (LS1), a third light-shielding layer (LS3) and a fourth gate electrode (G4) disposed on the first bottom interlayer insulating film (121); wherein the second bottom interlayer insulating film (122) is disposed on the first capacitor electrode (CE1), the first light-shielding layer (LS1), the third light-shielding layer (LS3) and the fourth gate electrode (G4); and the second capacitor electrode (CE2) is disposed on the second bottom interlayer insulating film (122) such that the first capacitor electrode (CE1) and the second capacitor electrode (CE2) overlap to form a first capacitor (C1).

[0224] C9. The display device according to clause C8, wherein the fourth gate electrode (G4) is integrally formed with the third light-shielding layer (LS3).

[0225] C10. The display device according to any one of clauses C8 to C9 further includes a first intermediate buffer layer (137) disposed on the second capacitor electrode (CE2); and a second intermediate buffer layer (138) disposed on the second light-shielding layer (LS2); wherein the second light-shielding layer (LS2) is disposed on the first intermediate buffer layer (137).

[0226] C11. The display device according to any one of clauses C8 to C9, wherein the display device is an organic light-emitting display device.

[0227] C12. The display device according to any one of clauses C1 to C11, wherein a plurality of sub-active layers (A31, A32, A33, A34, A35, A36, A37) are spaced apart from each other by inclined regions.

[0228] This article also provides the following terms:

[0229] 1. A thin-film transistor substrate, comprising:

[0230] A buffer layer, wherein the buffer layer is disposed on a base substrate; and

[0231] Multiple thin-film transistors, the multiple thin-film transistors being located on the buffer layer,

[0232] The plurality of thin-film transistors include a plurality of active layers and a gate electrode that overlaps at least a portion of each of the plurality of active layers.

[0233] The buffer layer includes flat areas and sloping areas that are alternately arranged with each other, and

[0234] The plurality of active layers are spaced apart from each other and disposed in the flat region.

[0235] 2. The thin-film transistor substrate according to Clause 1, wherein the plurality of active layers comprise an oxide semiconductor material and have a crystal structure.

[0236] 3. The thin-film transistor substrate according to Clause 1, wherein the plurality of active layers are spaced apart from each other in a first direction.

[0237] The flat region and the inclined region are arranged to extend along a second direction perpendicular to the first direction, and

[0238] The flat region and the sloping region are configured to be parallel along the first direction.

[0239] 4. The thin-film transistor substrate according to Clause 3, wherein the plurality of active layers are configured to extend along the second direction.

[0240] 5. The thin-film transistor substrate according to Clause 1, wherein the buffer layer includes a first flat surface and a second flat surface disposed in the flat region, and an inclined surface disposed in the inclined region, and

[0241] The plurality of active layers are not located in the inclined region.

[0242] 6. The thin-film transistor substrate according to Clause 1, wherein the buffer layer includes a first flat surface and a second flat surface disposed in the flat region, and an inclined surface disposed in the inclined region, and

[0243] The plurality of active layers include regions retained at the ends of the inclined surface.

[0244] 7. The thin-film transistor substrate according to Clause 6, wherein the plurality of active layers are configured to be spaced apart in parallel along a first direction.

[0245] The flat region and the inclined region are respectively positioned to extend along a second direction perpendicular to the first direction, and

[0246] The region retained at the end of the inclined surface is configured to extend along the second direction.

[0247] 8. The thin-film transistor substrate according to Clause 5, wherein the first flat surface, the inclined surface, and the second flat surface extend along the first direction.

[0248] The inclined surface is disposed between the first flat surface and the second flat surface, and

[0249] The shortest distance between the first flat surface and the base substrate is shorter than the shortest distance between the second flat surface and the base substrate.

[0250] 9. The thin-film transistor substrate according to Clause 5, wherein the inclined surface has a taper angle of 45 to 90°.

[0251] 10. The thin-film transistor substrate according to Clause 1, wherein the plurality of active layers have a spacing of 0.5 μm or less in the plane.

[0252] 11. The thin-film transistor substrate according to Clause 6, wherein the plurality of active layers comprises:

[0253] A lower active layer disposed on the first flat surface; and

[0254] An active layer is disposed on the upper part of the second flat surface.

[0255] The lower active layer and the upper active layer are alternately arranged along the first direction, and

[0256] The shortest distance between the upper surface of the lower active layer and the base substrate is shorter than the shortest distance between the upper surface of the upper active layer and the base substrate.

[0257] 12. The thin-film transistor substrate according to Clause 1, wherein the gate electrode extends across the plurality of active layers in a first direction and is disposed on the flat region and the inclined region.

[0258] 13. The thin-film transistor substrate according to Clause 1 further includes a gate insulating film disposed on the buffer layer.

[0259] The plurality of active layers are disposed in the flat region between the buffer layer and the gate insulating film, and

[0260] The gate insulating film is in contact with the buffer layer in the inclined region.

[0261] 14. The thin-film transistor substrate according to Clause 5, wherein the buffer layer includes trenches.

[0262] The inclined surfaces are disposed on both sides of the groove, and

[0263] The first flat surface is disposed between the inclined surfaces.

[0264] 15. A method for manufacturing a thin-film transistor substrate, comprising the following steps:

[0265] The step of forming a buffer layer on a base substrate;

[0266] A photoresist pattern is formed on the buffer layer;

[0267] The buffer layer is etched using the photoresist pattern as a mask to form alternating flat and sloping regions.

[0268] An active material layer is formed on the buffer layer;

[0269] Annealing the active material layer; and

[0270] A portion of the active material layer is removed by wet etching in the inclined region.

[0271] 16. The method for manufacturing a thin-film transistor substrate according to Clause 15, wherein the active material layer disposed on the flat region is crystallized by the annealing.

[0272] 17. The method for manufacturing a thin-film transistor substrate according to Clause 15, wherein the buffer layer has a taper angle of 45 to 90° in the inclined region.

[0273] 18. The method for manufacturing a thin-film transistor substrate according to Clause 15, wherein the thickness of the active material layer disposed in the inclined region is 10% to 60% compared to the thickness of the active material layer disposed in the flat region, and

[0274] The thickness of the active material layer is measured in a direction perpendicular to the surface of the buffer layer.

[0275] 19 A display device comprising a thin-film transistor substrate as described in any one of clauses 1-14.

[0276] This document also describes the following terms:

[0277] D1. A display device comprising a thin-film transistor substrate, the thin-film transistor substrate including: a buffer layer disposed on a base substrate and a plurality of thin-film transistors disposed on the buffer layer, wherein the plurality of thin-film transistors include a plurality of active layers and gate electrodes overlapping at least a portion of the plurality of active layers.

[0278] The buffer layer includes flat and sloping regions that are alternately arranged, and multiple active layers are spaced apart from each other and arranged in the flat regions.

[0279] D2. The display device according to clause D1, wherein a plurality of active layers are spaced apart from each other by inclined regions and disposed in flat regions.

[0280] D3. The display device according to clause D1, wherein a plurality of active layers are spaced apart from each other in a first direction, wherein flat regions and inclined regions extend along a second direction perpendicular to the first direction, and wherein the flat regions and inclined regions are arranged parallel to the first direction.

[0281] D4. The display device according to clause D3, wherein a plurality of active layers extend along a second direction.

[0282] D5. The display device according to clause D1, wherein the flat region includes a first flat surface and a second flat surface; and wherein each of the inclined regions includes an inclined surface, and wherein a plurality of active layers are not disposed on the inclined surfaces; and optionally, wherein the buffer layer includes a trench, wherein the inclined surfaces are located on both sides of the trench, and wherein the first flat surface is located between the inclined surfaces; and optionally, wherein each inclined surface has a taper angle of 45 to 90°.

[0283] D6. The display device according to clause D1, wherein the flat region includes a first flat surface and a second flat surface; and wherein each of the inclined regions includes an inclined surface, and the plurality of active layers include segments located at both ends of the inclined surfaces.

[0284] D7. The display device according to clause D6, wherein a plurality of active layers are arranged parallel to each other along a first direction, wherein flat regions and inclined regions extend along a second direction perpendicular to the first direction, and wherein the aforementioned sections extend along the second direction.

[0285] D8. The display device according to clause D5, wherein a first flat surface, an inclined surface and a second flat surface extend along a first direction, wherein the inclined surface is located between the first flat surface and the second flat surface, and wherein the shortest distance between the first flat surface and the base substrate is shorter than the shortest distance between the second flat surface and the base substrate.

[0286] D9. The display device according to clause D1, wherein the plurality of active layers comprise an oxide semiconductor material and have a crystal structure; and optionally, wherein the plurality of active layers have a spacing of 0.5 μm or less in the plane.

[0287] D10. The display device according to clause D6, wherein a plurality of active layers include: a first flat surface forming a lower active layer; and a second flat surface forming an upper active layer, wherein the lower active layer and the upper active layer are alternately disposed along a first direction, and wherein the shortest distance between the upper surface of the lower active layer and the base substrate is shorter than the shortest distance between the upper surface of the upper active layer and the base substrate.

[0288] D11. The display device according to clause D1, wherein the gate electrode extends along a first direction across a plurality of active layers, and wherein the gate electrode is disposed on a flat region and a sloping region.

[0289] D12. The display device according to clause D1 further includes a gate insulating film disposed on a buffer layer, wherein a plurality of active layers are disposed between the buffer layer and the gate insulating film in a flat region, and wherein the gate insulating film contacts the buffer layer in a sloping region.

[0290] D13. The display device according to clause D1 further includes a source electrode and a drain electrode, the source electrode and the drain electrode being respectively connected to a plurality of active layers and configured to be spaced apart from each other, and optionally, wherein the source electrode is integrally formed and the drain electrode is integrally formed.

[0291] D14. The display device according to clause D1, wherein a plurality of thin-film transistors are configured to be driven simultaneously.

[0292] D15. A method for manufacturing a thin-film transistor substrate for a display device, the method comprising the steps of: forming a buffer layer on a base substrate; forming a photoresist pattern on the buffer layer; etching the buffer layer using the photoresist pattern as a mask to form alternating flat regions and sloping regions; forming an active material layer on the buffer layer; annealing the active material layer; and removing a portion of the active material layer disposed in the sloping regions by wet etching.

[0293] D16. The method according to clause D15, wherein the active material layer disposed on the flat region is crystallized by annealing; and optionally, wherein the buffer layer has a cone angle of 45 to 90° in the inclined region; and optionally, the thickness of the active material layer disposed in the inclined region is 10% to 60% compared with the thickness of the active material layer disposed in the flat region, and wherein the thickness of the active material layer is measured in a direction perpendicular to the surface of the buffer layer.

[0294] D17. A display device, comprising: a display area and a non-display area surrounding the display area; a first thin-film transistor disposed in the non-display area, the first thin-film transistor including a first active layer having a plurality of sub-active layers spaced apart from each other, and a first gate electrode overlapping at least a portion of the first active layer; and a second thin-film transistor disposed in the non-display area, the second thin-film transistor including a buffer layer disposed on a base substrate, a second active layer disposed on the buffer layer, and a second gate electrode overlapping at least a portion of the second active layer, wherein the buffer layer includes alternately disposed flat regions and inclined regions, and wherein the plurality of sub-active layers are spaced apart from each other by the inclined regions and disposed in the flat regions.

[0295] D18. The display device according to clause D17, wherein a buffer layer extends from a non-display area to a display area, wherein the buffer layer includes a trench; wherein at least a portion of the trench overlaps with a first active layer of a first thin-film transistor.

[0296] D19. The display device according to clause D17, wherein the first thin-film transistor includes an intermediate buffer layer disposed below the first active layer, wherein the first active layer is disposed on the upper surface of the intermediate buffer layer, wherein the buffer layer has a first cone angle, and wherein the intermediate buffer layer has a second cone angle greater than the first cone angle.

[0297] D20. The display device according to clause D18, wherein the groove is not provided in the display area;

[0298] Optionally, the trench does not overlap with the second active layer of the second thin-film transistor; and optionally, the second active layer comprises a low-temperature polycrystalline silicon semiconductor material; and optionally, the first thin-film transistor includes a first light-shielding layer overlapping with the first active layer, and wherein the first light-shielding layer is integrally formed with the second gate electrode.

Claims

1. A display device comprising a thin-film transistor substrate, the thin-film transistor substrate comprising: A buffer layer is disposed on a base substrate; as well as Multiple thin-film transistors, the multiple thin-film transistors being located on the buffer layer, The plurality of thin-film transistors include a plurality of active layers and a gate electrode that overlaps at least a portion of each of the plurality of active layers. The buffer layer includes flat areas and sloping areas that are alternately arranged with each other, and The plurality of active layers are spaced apart from each other and disposed in the flat region.

2. The display device according to claim 1, wherein the plurality of active layers are spaced apart from each other by inclined regions and disposed in the flat region.

3. The display device according to claim 1, wherein the plurality of active layers are spaced apart from each other in a first direction. The flat region and the inclined region are arranged to extend along a second direction perpendicular to the first direction, and The flat region and the sloping region are configured to be parallel along the first direction.

4. The display device according to claim 3, wherein the plurality of active layers are configured to extend along the second direction.

5. The display device according to claim 1, wherein... The flat region includes a first flat surface and a second flat surface; and Each of the inclined regions mentioned above includes an inclined surface; and The plurality of active layers are not disposed on the inclined surface.

6. The display device according to claim 1, wherein the flat region comprises a first flat surface and a second flat surface; and Each of the inclined regions includes an inclined surface; and The plurality of active layers include regions located at both ends of the inclined surface.

7. The display device of claim 6, wherein the plurality of active layers are configured to be spaced apart in parallel along a first direction.

8. The flat region and the inclined region are respectively positioned to extend along a second direction perpendicular to the first direction, and The region is configured to extend along the second direction.

9. The display device of claim 5, wherein the first flat surface, the inclined surface, and the second flat surface extend along the first direction. The inclined surface is disposed between the first flat surface and the second flat surface, and The shortest distance between the first flat surface and the base substrate is shorter than the shortest distance between the second flat surface and the base substrate.

10. The display device according to claim 1, wherein the plurality of active layers comprises an oxide semiconductor material and has a crystal structure.

11. The display device according to claim 6, wherein the plurality of active layers comprises: The first flat surface forms the lower active layer; as well as The second flat surface of the upper active layer is formed. The lower active layer and the upper active layer are alternately arranged along the first direction, and The shortest distance between the upper surface of the lower active layer and the base substrate is shorter than the shortest distance between the upper surface of the upper active layer and the base substrate.

12. The display device of claim 1, wherein the gate electrode extends across the plurality of active layers in a first direction and wherein the gate electrode is disposed on the flat region and the sloping region.

13. The display device according to claim 1, further comprising a gate insulating film disposed on the buffer layer, The plurality of active layers are disposed in the flat region between the buffer layer and the gate insulating film, and The gate insulating film is in contact with the buffer layer in the inclined region.

14. The display device according to claim 1, further comprising a source electrode and a drain electrode, the source electrode and the drain electrode being respectively connected to the plurality of active layers and disposed spaced apart from each other. Furthermore, the source electrode is integrally formed, and the drain electrode is integrally formed.

15. The display device of claim 1, wherein the plurality of thin-film transistors are configured to be driven simultaneously.

16. A method for manufacturing a thin-film transistor substrate for a display device, the method comprising the steps of: The step of forming a buffer layer on a base substrate; A photoresist pattern is formed on the buffer layer; The buffer layer is etched using the photoresist pattern as a mask to form alternating flat and sloping regions. An active material layer is formed on the buffer layer; The active material layer is annealed; as well as A portion of the active material layer is removed by wet etching in the inclined region.

17. The method of claim 15, wherein the active material layer disposed on the flat region is crystallized by the annealing; and wherein the buffer layer has a cone angle of 45 to 90° in the inclined region; and wherein the thickness of the active material layer disposed in the inclined region is 10% to 60% compared to the thickness of the active material layer disposed in the flat region, and The thickness of the active material layer is measured in a direction perpendicular to the surface of the buffer layer.

18. A display device, comprising: The display area and the non-display area surrounding the display area; A first thin-film transistor disposed in the non-display area, the first thin-film transistor including a first active layer and a first gate electrode, the first active layer having a plurality of sub-active layers spaced apart from each other, and the first gate electrode overlapping at least a portion of the first active layer; as well as A second thin-film transistor is disposed in the non-display area. The second thin-film transistor includes a buffer layer disposed on a base substrate, a second active layer disposed on the buffer layer, and a second gate electrode overlapping at least a portion of the second active layer. The buffer layer includes alternating flat and sloping regions, and The plurality of sub-active layers are spaced apart from each other by the inclined region and disposed in the flat region.

19. The display device of claim 17, wherein the buffer layer extends from the non-display area to the display area. The buffer layer includes grooves. At least a portion of the trench overlaps with the first active layer of the first thin-film transistor.

20. The display device of claim 17, wherein the first thin-film transistor includes an intermediate buffer layer disposed below the first active layer. The first active layer is disposed on the upper surface of the intermediate buffer layer. The buffer layer has a first cone angle, and The intermediate buffer layer has a second cone angle that is greater than the first cone angle.

21. The display device according to claim 18, wherein the groove is not disposed in the display area.

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