Tunable probabilistic MRAM element

Abstract

The invention relates to a tunable probabilistic MRAM element. A spin electronic device (100; 200) for random bit generation and a related method. The device comprises a magnetic tunnel junction (302) formed in a multilayer stack (301) of magnetoresistors (112; 300), wherein a free layer (303) of the magnetic tunnel junction exhibits a perpendicular magnetic anisotropy associated with an electric field. The device further comprises means (306) for generating a magnetic bias field along a predefined axis in the plane of the free layer, a junction bias circuit (110) for eliminating an energy barrier associated with the magnetic anisotropy, a probability tuning circuit (130) for applying a controllable spin torque to the free layer, and a readout circuit (120; 220). The junction bias circuit is configured to apply a controllable bias voltage (VB) across the magnetic tunnel junction, allowing thermal random flipping of free layer magnetization (FL-M). The spin torque applied on the free layer varies an expected value of the magnetization intensity of the free layer. The readout circuit senses and digitizes fluctuations in the reluctance signal.

Description

Technical Field

[0001] This invention relates to the field of tunable spintronic devices for random bit generation and probabilistic computation networks for using these devices in optimization and machine learning applications. Background Technology

[0002] The prior art has proposed and demonstrated the generation of random bits using thermally unstable magnetic memory elements.

[0003] Document US10607674B2 discloses a thermally unstable in-plane magnetized nanomagnet, which serves as the free layer of a magnetic tunnel junction (MTJ) and operates in the superparamagnetic region to induce random fluctuations in the resistance of the MTJ. The MTJ is connected to an inverter, which amplifies the voltage fluctuations across the MTJ. The average value of the output signal generated by the inverter can be controlled by the gate voltage of a transistor connected in series with the MTJ. A drawback of this proposed device is that the thermally unstable nanomagnet requires a very low energy barrier, which is difficult to reproduce reliably. Furthermore, a larger tunnel magnetoresistance (TMR) coefficient is required to achieve voltage fluctuations on the same order of magnitude as the supply voltage level.

[0004] In “Magnetic TunnelJunction Mimics Stochastic Cortical Spiking Neurons”, Sci. Rep. 6, 30039 (2016), Sengupta, A., Panda, P., Wijesinghe, P., et al., proposed a neuromorphic system using stochastic magnetic tunnel junctions (MTJs) to simulate probabilistic cortical spiking neurons. The in-plane component of the magnetization of the nanomagnets was considered equivalent to the membrane potential of biological neurons, and neuronal firing events were associated with the MTJ flipping from an initial parallel state (P) to an antiparallel state (AP). The torque generated by the effective magnetic field and the damping term of the magnetization dynamics were considered leakage terms, while the spin moment was associated with the integral of the input pulse during the write phase. Furthermore, the potential neuronal flipping during the write phase was verified in the subsequent read phase, which also served the purpose of resetting the neuron back to the P state even if the MTJ had flipped to the AP state. The authors also investigated a spiking neural network of stochastic MTJ neurons for solving the standard digit recognition problem. Current pulses with amplitudes of several hundred microamps are required as input to MTJ neurons. The magnetic freedom layer of MJT neurons is a nanomagnet with an energy barrier height of 20 kT. A drawback of the proposed random MJT neurons is that they require two phases of operation: a write phase and a read phase with neuron reset, which reduces their operating speed and increases energy consumption. Summary of the Invention

[0005] The purpose of embodiments of the present invention is to provide a reliable and scalable spintronic random bit generator with adjustable bit expectations.

[0006] The above objectives are achieved by the device and method according to the present invention.

[0007] In a first aspect, the present invention relates to a spintronic device for probabilistic or random bit generation. The random bit generation spintronic device includes a magnetic tunnel junction formed in a multilayer stack of magnetoresistive elements, wherein the magnetic free layer of the magnetic tunnel junction exhibits magnetic anisotropy related to an electric field in a direction perpendicular to the magnetic tunnel junction. The spintronic device further includes means for generating a magnetic bias field along a predefined axis in the plane of the magnetic free layer; a junction bias circuit for completely or partially eliminating the energy barrier associated with the magnetic anisotropy; a probabilistic tuning circuit configured to apply a controllable spin moment to the free layer of the magnetoresistive magnetic tunnel junction; and a readout circuit. The junction bias circuit is configured to apply a controllable bias voltage across the magnetoresistive magnetic tunnel junction, thereby allowing thermal random flips in the free layer magnetization as it precesses about a predefined axis of the magnetic bias field, such that the perpendicular magnetic anisotropy disappears when the energy barrier height is zero. The random flip event corresponds to a reversal (direction reversal) of the component of the free layer magnetization vector that is parallel / antiparallel to the magnetization direction of the magnetic reference layer of the magnetic tunnel junction. The spin moment applied to the magnetic free layer of the magnetic tunnel junction controls the statistical mean of the free layer magnetization over a set of thermal random reversal events. The readout circuitry is adapted to detect magnetoresistive fluctuations at a rate compatible with these thermal random reversal events and generates a binary output signal indicating the currently detected resistance state (i.e., antiparallel or parallel magnetoresistive configuration). The readout circuitry can sense and digitize fluctuating voltage signals across the magnetoresistive layer, or sense and digitize fluctuating currents flowing through the magnetoresistive layer.

[0008] In the case where the energy barrier is partially eliminated, the precession axis of each equilibrium state of the magnetic free layer magnetization tilts away from the easy axis associated with the residual vertical magnetic anisotropy of the free layer, and tilts towards the predefined axis of the magnetic bias field, wherein the angle between the free layer magnetization vector and the magnetic bias field vector is smaller than the angle between the free layer magnetization vector and the easy axis. Here, partial elimination of the energy barrier refers to the energy barrier height in the vertical direction of the free energy landscape associated with the free layer magnetization, which is less than 10 kT, preferably less than 5 kT.

[0009] After applying a junction bias voltage, which causes the barrier to decrease or be eliminated, the magnetic tunnel junction exhibits strong random behavior, where the orientation of the magnetic moments of the free layers is affected by thermal noise. This results in random telegraph noise in the corresponding readout signal regarding magnetoresistance (e.g., sensed by voltage or current), which translates into a time stream of fluctuating random bits.

[0010] In embodiments of the present invention, the magnetoresistive field can be a nanodevice, transforming the nanoscale magnetic free layer into a nanomagnet. The magnetic bias field can be an externally generated magnetic field or the magnetic field inherent in the free layer of the magnetic tunnel junction.

[0011] A magnetic hard mask can be disposed in a layer above or below the free magnetic layer, and the hard mask is permanently magnetized in a direction parallel to the free magnetic layer. In this case, the predefined axis of the externally generated magnetic bias field corresponds to the magnetization direction of the hard mask. The magnetic hard mask can have an elongated cross-sectional shape (in a plane parallel to the free magnetic layer), which determines the magnetization direction of the hard mask due to magnetic shape anisotropy, or it can exhibit magnetocrystalline anisotropy in a plane parallel to the free magnetic layer.

[0012] For example, for a magnetic free layer with a long and narrow cross-sectional shape (such as an ellipse), the inherent magnetic bias field can be set within the magnetic free layer as a result of the anisotropy of the magnetic shape.

[0013] In embodiments of the invention, the stacked material layers may have a circular or non-circular shape (e.g., an elliptical shape) when viewed along the stacking direction. Furthermore, the thermal stability constant (i.e., barrier height) associated with the magnetic tunnel junction is preferably at least 20 kT for an unbiased magnetic junction with magnetoresistance (e.g., a 0V junction bias voltage).

[0014] In embodiments of the present invention, the magnetization direction of the reference layer of each magnetic tunnel junction may be perpendicular to the magnetic free layer or lie in the plane of the magnetic free layer.

[0015] In embodiments of the present invention, the magnetoresistive element may include a plurality of magnetoresistive elements connected in parallel, wherein each magnetoresistive element includes a magnetic tunnel junction formed in a respective multilayer stack.

[0016] Embodiments of the present invention may include a voltage divider network formed by a reference resistor and a magnetoresistive resistor, wherein the reference resistor serves as the first resistor of the voltage divider network and the magnetoresistive resistor serves as the second resistor of the voltage divider network. The readout circuit may include a comparator, an inverter, or a series of inverters (e.g., two or more inverters) connected to a sensing node between the first and second resistors of the voltage divider network. The reference resistor may be a resistor or a transistor used as a current source.

[0017] The junction bias voltage of the transmagnetic tunnel junction and / or the current-induced spin torque applied to the magnetic free layer can be applied as a DC signal or a pulse signal. The pulse duration is preferably several times the precession period of the free layer magnetization, for example, tens to hundreds of nanoseconds.

[0018] Spintronic random bit generators based on nanopillar magnetoresistance, according to embodiments of the present invention, allow for energy-efficient and compact device designs. They also offer the following benefits: high throughput per unit area and per unit energy (e.g., gigahertz sampling rates), desired high tunability associated with random bits, and massive parallelization.

[0019] The advantage of this invention is that the spin-moment induced charge current density is significantly lower than the threshold current density required for flipping in conventional thermally stable magnetic tunnel junctions. In this invention, the spin-moment induced charge current density can be from 100 kΩ / cm² to 500 kΩ / cm², or less than 100 kΩ / cm².

[0020] The advantage of this invention is that the spin-electron random position generator is configured to reduce the energy barrier associated with the perpendicular magnetic anisotropy of the magnetic tunnel junction by voltage-controlled magnetic anisotropy (VCMA) effect. This avoids the design of thermally unstable nanomagnets—such nanomagnets are difficult to scale up and accurately reproduce due to the very small diameter required for their rapid thermal flipping. Furthermore, with the perpendicular energy barrier reduced or completely eliminated, applying a small in-plane magnetic bias field to the magnetic free layer allows for larger diameters of the magnetic free layer and multilayer stacks at a constant random flipping rate.

[0021] In embodiments of the invention, a higher resistivity area (e.g., 100-500 Ω) is used. The (µm²) junction temperature advantageously reduces the tunneling current flowing through the magnetic tunnel junction when a junction bias voltage is applied, while still causing self-heating of the magnetic tunnel junction (e.g., an increase of 10-50 K compared to ambient temperature). Higher junction temperatures increase the amplitude of thermal random field fluctuations and can further improve the switching rate.

[0022] The advantages of this invention are that spintronic random bit generators can be interconnected to form a random bit generator network, where no analog-to-digital (ADC) or digital-to-analog (DAC) stages are required between connected random bit generators. The random bit generators in this network can be updated asynchronously or synchronously, allowing the network to operate asynchronously or synchronously. Furthermore, the random bit generators in this network enable efficient sampling of random bits, random numbers, and random distributions derived from these random bits within the framework of probabilistic computation and in machines used for probabilistic computation (e.g., probabilistic implementations of machine learning models or combinatorial optimization problems). This random bit generator network can be built on a chip, and its sampling rate scales with the number of spintronic random bit generators; for example, in an asynchronously operating network, the sampling rate scales linearly with the number of spintronic random bit generators. Additionally, the junction bias circuit of each spintronic random number generator can optionally be programmed to apply a predefined amount of offset voltage across the magnetic tunnel junction before removing the energy barrier, to account for and compensate for differences in the critical junction bias voltages of the respective spintronic devices in the network. In this way, a common critical junction bias voltage can be uniformly applied to all magnetic tunnel junctions in the network.

[0023] Another advantage of this invention is that the spintronic random bit generator can be implemented in a compact manner and requires fewer transistors than a conventional digital implementation of a random bit generator.

[0024] Another advantage of this invention is that the magnetoresistive state of the spin electron random position generator can be flipped at a high time rate, and the fluctuation of the magnetoresistive state can occur within a nanosecond timescale.

[0025] The present invention also relates to a method for generating probability bits using magnetoresistance. The method includes the following steps: (i) A bias voltage is applied to a transmagnetic tunnel junction, wherein the magnetic free layer of the magnetic tunnel junction exhibits electric field-dependent magnetic anisotropy in a direction perpendicular to the magnetic tunnel junction. (ii) Generate a magnetic bias field along a predefined axis in the plane of the magnetic free layer; (iii) Adjust the bias voltage of the transmagnetic tunnel junction so that the energy barrier associated with magnetic anisotropy is completely or partially eliminated, thereby allowing thermal random flipping as the free layer magnetization precesses about a predefined axis of the magnetic bias field. (iv) Apply a controllable spin moment to the free layer of a magnetoresistive magnetic tunnel junction, thereby adjusting the mean of the free layer magnetization based on a set of thermal random flip events; (v) Detect and digitize the fluctuating voltage signal across the magnetoresistive field or the fluctuating current signal flowing through the magnetoresistive field at a rate matching the thermal random reversal event.

[0026] Steps (iii)-(v) are performed simultaneously. The partially eliminated energy barrier has a remaining energy barrier height of less than 10 kT, preferably less than 5 kT.

[0027] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features of the dependent claims may be suitably combined with features of the independent and other dependent claims, not merely as expressly set forth in the claims.

[0028] For the purpose of summarizing the invention and its advantages over the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all such objects or advantages may be achieved according to any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention can be embodied or practiced in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0029] The above and other aspects of the invention will be apparent from the embodiments described below and will be illustrated with reference to the embodiments. Attached Figure Description

[0030] The invention will now be further described by way of example with reference to the accompanying drawings, in which: Figure 1 and Figure 2 This is a circuit diagram of a spin-electron random position generator according to an embodiment of the present invention; Figure 3 and Figure 4 This is a cross-sectional view of a magnetoresistive element that can be used in a spin-electron random position generator according to the present invention; Figure 5 These are circuit diagrams of spin-electron random position generators using multiple magnetic tunnel junctions according to different embodiments of the present invention; Figure 6 This is a schematic diagram illustrating the working principle of a spintronic random position generator during operation. Figure 7 This is a block diagram of a network for a spintronic random bit generator that can be used in probabilistic computer hardware according to an embodiment of the present invention. Figure 8 This is a flowchart illustrating the steps of generating a random bit stream using a random magnetic tunnel junction according to an embodiment of the present invention.

[0031] These accompanying drawings are merely illustrative and not restrictive. In the drawings, some elements may be enlarged and not drawn to scale for illustrative purposes. Scale and relative scale do not necessarily correspond to an actual simplification of the practice of this invention.

[0032] Any reference numerals in the claims should not be construed as limiting the scope.

[0033] In different accompanying drawings, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0034] The invention will be described with respect to specific embodiments and with reference to certain accompanying drawings, but the invention is not limited thereto, but is defined only by the claims.

[0035] The terms first, second, etc., used in the specification and claims are used to distinguish between similar elements and are not necessarily used to describe a temporal, spatial, hierarchical, or any other order. It is to be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can operate in an order different from that described or illustrated herein.

[0036] Furthermore, directional terms such as top, bottom, front, back, first, last, lower, and upper in the specification and claims are used for illustrative purposes with reference to the orientation of the described drawings and are not necessarily used to describe relative positions. Since the components of the embodiments of the invention can be positioned in many different orientations, directional terms are used for illustrative purposes only and do not constitute a limitation of the invention unless otherwise stated. Therefore, it is to be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can operate in orientations different from those described or illustrated herein.

[0037] It is important to note that the term "comprising" as used in the claims should not be construed as limiting oneself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the features, integers, steps, or components stated as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of the expression "device comprising means A and B" should not be limited to a device consisting solely of components A and B. It means that for the purposes of this invention, the only relevant components of the device are A and B.

[0038] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in an embodiment" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner as will be apparent to those skilled in the art from this disclosure.

[0039] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this approach of the disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive aspect lies in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the claims appended to the Detailed Description are thus explicitly incorporated into this Detailed Description, wherein each claim itself represents a separate embodiment of the invention.

[0040] Furthermore, although some embodiments described herein include some features included in other embodiments but not all other features included in those other embodiments, as will be understood by those skilled in the art, combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments.

[0041] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention can be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0042] Combination Figure 1This invention describes a spintronic device for generating random bits with an adjustable expectation (also referred to as an expected value, average value, or mean) according to embodiments of the invention. The spintronic device 100 includes a voltage divider circuit 110, in which a resistor network is formed by a first resistor 111 and a second resistor 112 connected in series. In this resistor network, the first resistor 111 acts as a reference resistor, while the second resistor 112 is a reversible magnetoresistive element. In embodiments of the invention, the first resistor may be configured as a resistor, a transistor (e.g., a MOSFET) used as a resistor, a thermally stable magnetic tunnel junction with fixed resistance (non-reversible), or any other suitable resistive element; while the second resistor includes at least one magnetoresistive element, for example, consisting of a single magnetoresistive cell or multiple magnetoresistive elements connected in parallel. The at least one magnetoresistive element (e.g., each magnetoresistive element) includes a magnetic tunnel junction (MJT) formed in a multilayer stack. The magnetically free layer of the MJT exhibits field-dependent magnetic anisotropy in a direction perpendicular to the material interface of the multilayer stack. In other words, the amount of perpendicular magnetic anisotropy in the magnetic free layer of an MJT can be electrically controlled (VCMA effect) by means of the electric field at the tunnel barrier-free layer interface. Specifically, it allows for the complete elimination of the energy barrier that separates the two opposite (bistable) magnetization states of the free layer within the device's permissible operating temperature range (e.g., -40°C to 120°C).

[0043] The readout circuit 120 is connected to the sensing node N1 between the two resistors 111 and 112 of the voltage divider circuit 110, and is configured to convert the voltage signal fluctuations at the sensing node N1 into a corresponding digital output voltage signal V(OUT). Due to the magnetoresistive effect, the resistance value R(AP) of the second resistor in the antiparallel state is greater than its resistance value R(P) in the parallel state. The first resistor is typically designed to have a resistance value R(Ref) that is approximately equal to the average resistance level of the second resistor, for example, R(Ref) ≈ [R(AP) + R(P)] / 2, such that the voltage signal at the sensing node N1 fluctuates around the average voltage level (approximately half the device supply voltage), for example...<V(N1)> ≈0.5 V0. In embodiments of the invention, the readout circuit may include a voltage comparator for thresholding the voltage signal V(N1) at the sensing node, for example, comparing V(N1) with a reference voltage (e.g., V(REF) = 0.5). The voltage signal fluctuation at sensing node N1 is compared. If the voltage signal fluctuation at sensing node N1 is too small, it can be amplified by an optional amplification stage of the readout circuit. Alternatively, an inverter or a series of inverters (e.g., CMOS inverters) can be used to generate a random bit stream at the device output, such as a full-swing digital output signal V(OUT), starting from the thermally induced voltage fluctuation at sensing node N1. The readout circuit 120 is capable of tracking fast thermal voltage fluctuations at sensing node N1 (typically occurring in the sub-GHz to gigahertz range, e.g., greater than 0.1 GHz), provided that it has a sufficiently large frequency bandwidth (i.e., exceeding the thermal fluctuation rate at sensing node N1). In embodiments of the invention, the random flipping behavior of each magnetic tunnel junction can be described by a process (e.g., a noise process dominated by random telegraph noise) whose spectral bandwidth is limited by the reciprocal of the RC time constant of the magnetic tunnel junction. Therefore, it is advantageous to keep the RC time constant of the magnetic tunnel junction small (e.g., by reducing the junction capacitance value) to improve the noise bandwidth and the final readout signal fluctuation amplitude. The digital output signal V(OUT) generated by the readout circuit is a binary random variable (e.g., taking one of two distinct values, "0" and "1"), thereby generating random bits (also called probabilistic bits or p-bits). The fluctuation of the output signal V(OUT) over time corresponds to the continuous generation of random bits (repeated sampling or sampling of the random variable), and this fluctuation is attributed to abrupt changes in the tunneling magnetoresistance of the second resistor caused by thermal noise combined with the spin moment. Thus, a random bit stream can be generated at the device output, where each volume p-bit is generated at a random point in time. In other words, the random bit streams of two random bit generating spintronics devices are asynchronous. This has the advantage that a large number of random bit generating spintronics devices can operate asynchronously in parallel. Of course, it is also possible to provide sampling units at the device output to periodically sample the output voltage V(OUT) (e.g., according to a clock signal). This allows multiple random bit generating spintronics devices to operate synchronously.

[0044] A switching element 140 (e.g., a transistor) is optionally positioned between the voltage source V0 and the voltage divider circuit 110 to disconnect the voltage divider circuit from the supply voltage when not in use. This can save energy and extend the lifespan of the magnetoresistive element. The connection state of the voltage divider circuit 110 and possibly other components of the spintronic device (such as the readout circuit 120 and / or the control circuit system 130) is controlled by applying an enable signal V(EN) to the control terminal of the switching element 140. The switching element 140 can also be used to generate supply voltage pulses, and thus generate junction bias voltage pulses across at least one NTJ of magnetoresistive voltage with a predetermined duration (e.g., tens of nanoseconds).

[0045] In this embodiment, the voltage divider circuit 110 applies an average voltage level V(N1) at the sensing node across at least one magnetic tunnel junction of the second resistor. Therefore, it functions as the junction bias circuit of device 100, configured to apply a controllable bias voltage across at least one MJT of the magnetoresistive layer, thereby completely eliminating the energy barrier associated with magnetic anisotropy in the magnetic free layer. This means that when the magnetoresistive layer operates in the random telegraph switching region, the voltage fluctuation at the sensing node N1 should have a limited amplitude, for example, in the sense that the energy characteristics of the magnetic free layer in the junction are not altered (i.e., no energy barrier is reformed), and it has no significant effect on the bias voltage across the MJT. The junction bias of at least one MTJ across the magnetoresistive layer is controlled by the supply voltage level 'V0'.

[0046] Furthermore, the spintronic device 100 includes a control circuitry 130 for tuning the desired (average) p-bit in the output stream. This control circuitry is configured to apply a current-induced spin moment to the magnetization of the MJT free layer. In a preferred embodiment of the invention, the spin moment applied to the MJT free layer is a spin orbital moment induced by a charge current flowing through the MJT free layer (e.g., adjacent to the MJT free layer interface). In this case, the probabilistic tuning control circuitry 130 includes an adjustable current source and a charge current delivery device, such as a current conductor or conductive trace disposed beneath a vertical material layer stack (MTJ stack) of magnetoresistive elements and interfacing with the magnetic free layer of each MTJ stack, which converts at least a portion of the transferred charge current into a spin current and / or an interface spin current. Thus, a portion of the control circuitry can be implemented by components of the magnetoresistive element itself (e.g., conductive traces beneath the MTJ stack). Changing the amplitude of the charge current provided by the current source of the probabilistic tuning control circuitry allows control over the amount of spin moment applied to the magnetic free layer of each magnetoresistive element. After this is eliminated by biasing the MTJ junction voltage, in the absence of any perpendicular magnetic anisotropy, for a magnetization vector that has tilted out of plane, the in-plane configuration of the effective magnetic field controlling the dynamics of the magnetic free layer is perturbed by increasing the small perpendicular component of the demagnetizing field. On average, despite the influence of a strong thermal noise field, the precession cone and relaxation state of the oscillating magnetic free layer magnetization are shifted in the perturbed direction. Ultimately, this changes the probability of generating p-bits with values ​​of "0" and "1," respectively. Here, "on average" refers to considering a large number of random flip-flop events. The magnetoresistive elements constituting the magnetoresistive components of the voltage divider circuit are typically implemented as three-terminal elements, such as MTJ stacks, each MTJ stack including a top contact and two bottom contacts, which are implemented as the two terminals of a conductive SOT trace shared by all MJT stacks.

[0047] In an alternative embodiment, the spin moment applied to the free layer of the MJT is a spin-transfer torque induced by a (partially) spin-polarized charge current passing through the magnetic tunnel junction. In this case, the probabilistic tuning control circuit 130 includes an adjustable current source and a charge current delivery device that spin-polarizes at least a portion of the charge current injected into the magnetic free layer of the MTJ (e.g., the magnetic reference layer of the MTJ acting as a spin polarizer). Thus, a portion of the control circuit system can be implemented by components of the magnetoresistive itself (e.g., the magnetic reference layer of the MTJ stack). Changing the amplitude of the charge current provided by the current source of the probabilistic tuning control circuit allows control over the amount of spin moment transferred to the magnetic free layer of each magnetoresistive element. On average, this adds a small vertical component to the magnetization of the magnetic free layer, which is in-plane configuration when the MTJ junction voltage bias eliminates vertical magnetic anisotropy. The magnetoresistive elements constituting the magnetoresistive circuit can then be implemented as two-terminal elements, such as each MTJ stack including a top contact and a bottom contact.

[0048] Figure 2 Another embodiment of a random bit-generating spintronic device is shown. The spintronic device 200 differs from the aforementioned device 100 in that the voltage at node N1 is directly controlled by connecting node N1 to a voltage source or supply voltage VB. Therefore, the junction bias voltage across at least one MTJ of the magnetoresistive 112 is set and controlled by the applied voltage level 'VB' and does not fluctuate over time when the device temperature is stable. Furthermore, a reference current I(REF) is injected into node N1, which can be generated by the first resistor 111 or a current source (e.g., a transistor used as a current source, such as a MOSFET transistor with or without source degradation). The reference current can be selected to be equal to the tunneling current flowing through the magnetoresistive oscillator in its highest resistance state. Under random reversal events of the magnetoresistive oscillator, the sensed current I(SEN) flowing out of node N1 increases or decreases. This change in the sensed current I(SEN) can be detected by the sense amplifier 220 and converted into a digital output signal V(OUT) representing the random bit flow at the device output.

[0049] In the foregoing embodiments, the junction bias voltage across at least one MTJ of the magnetoresistive field can be adjusted according to the device operating temperature (which may include self-heating effects in the case of a spintronic device in use). Since the height of the energy barrier that needs to be eliminated by the junction bias voltage via the VCMA effect depends on the MTJ temperature, the applied junction bias voltage needs to be changed accordingly. The control loop associated with the junction bias circuitry can use temperature information (e.g., temperature sensor data), or derive temperature information from device behavior, to determine the correct value of the junction bias voltage applied across at least one MTJ of the magnetoresistive field. As a supplement or alternative, the random bit current at the device output can be monitored to detect and compensate for temperature-induced deviations in the random flip-flop rate of the magnetoresistive field.

[0050] Now for reference Figure 3 The diagram illustrates a cross-section of an exemplary magnetoresistive element 300 along the xz plane, which can be used as a magnetoresistive element in embodiments of the present invention. The magnetoresistive element 300 includes a multilayer stack 301 (MJT stack) projecting vertically from a conductive trace 307 formed on a substrate or buffer layer 308. A magnetic tunnel junction 302 along the vertical multilayer stack 301 includes an insulating tunnel barrier 304 sandwiched between a pair of magnetic electrodes 303 and 305. The first magnetic electrode 303 acts as a free layer of the MJT and faces the conductive trace 307; while the second magnetic electrode 305 acts as a reference layer for vertical magnetization (e.g., along the z-direction) or in-plane magnetization (e.g., along the x-direction or y-direction) of the MJT and faces away from the conductive trace 307.

[0051] The tunnel barrier 304 typically comprises dielectric spacers, such as oxide layers like MgO, Al2O3, Gd2O3, BaO3Ti, or MgAl2O4 layers; compared to conventional MTJ designs for magnetic memory (e.g., MRAM) cells, this tunnel barrier can be fabricated to be thicker (e.g., 1.0–2.2 nm thick) to increase the resistive area (RA) product of the insulating barrier film. A larger RA product (e.g., at 100 Ω) is achieved when a bias voltage is applied across junction 302. µm² and 500100 Ω (Between µm²) This advantageously reduces the tunneling current flowing through junction 302, thereby ensuring that the STT effect induced by the tunneling current remains negligible. Near the tunnel barrier, the magnetic free layer exhibits interfacial vertical magnetic anisotropy energy associated with the bias voltage applied across junction 302. Therefore, the vertical magnetic anisotropy field can be tuned, or even completely eliminated, by the bias voltage across the junction. The linear magnetoelectric coefficient 'ξ' associated with the VCMA effect of the free layer's vertical magnetization can be ξ = 30…100 fJ / V / m, or greater.

[0052] The free layer 303 may include any of the following: ferromagnetic materials, ferromagnetic alloys such as CoFeB, ferrimagnetic alloys, hybrid magnetic layers, synthetic antiferromagnets (SAF), and a combination of synthetic antiferromagnets-hybrid free layers (SAF-HF). The reference layer 305 and any hard layers formed above the reference layer may include any of the following: ferromagnetic or ferrimagnetic alloys, SAF, repeating Co / NM layers, repeating ferromagnetic or ferrimagnetic alloy / NM layers (where NM represents a nonmagnetic material such as a refractory metal or alloy), and a combination of SAF-HF. The capping layer 306 may be inserted into the MJT stack 301 to improve adhesion properties, for example, inserted between the reference layer 305 and the top contact C0, and includes, for example, a nonmagnetic transition metal or alloy, TiN, or a magnetic hard mask. If a magnetic hard mask / layer is disposed within the capping layer or below the MTJ, the hard mask is preferably elongated (e.g., in the xy plane) to generate a magnetic bias field relative to the free layer, such that the direction of the magnetic bias field is determined by the long axis of the shape. When relaying charge current between side electrodes C1 and C2, the conductive trace 307 includes a material that generates a considerable spin-orbit moment at the interface with the free layer 303. Exemplary choices for the SOT trace 307 are: a ferromagnetic / antiferromagnetic bilayer, a ferromagnetic / PtX bilayer, or PtX; where X is one of the group consisting of: nonmagnetic materials (NM), W, 5d-NM materials and 4d-NM materials and their alloys, NiOx, topological insulators, and two-dimensional transition metal dichalcogenides. In a particular embodiment of the invention, using an in-plane magnetic bias field applied relative to the outside of the magnetic free layer, the hard magnetic layer can be disposed below the SOT trace rather than within the capping layer.

[0053] A weak in-plane magnetic bias field (e.g., less than 10 mT) is applied to the free layer, for example along the x or y direction, resulting in a tilted configuration of the static free layer magnetization vector, where the tilt angle relative to the vertical z-axis is small. Once the MTJ is biased at a critical level and the vertical magnetic anisotropy disappears, this magnetic bias field determines the precession axis of the free layer magnetization under the influence of thermal perturbations and effective damping. The effective Gilbert damping factor used in the Landau-Lifshitz-Gilbert (LLG) equations describing the free layer magnetization dynamics can be α ≥ 0.01, for example, α = 0.05, and includes contributions from volume damping and interface damping and can be related to the junction bias voltage. In embodiments of the invention, the magnetic bias field can originate from: a magnetic hard mask within the capping layer (external magnetic field), in-plane magnetic shape anisotropy within the free layer (inherent magnetic field along the easy axis), or uncompensated magnetic stray fields from the reference layer. Unlike MJT stacks with elliptical cross-sections, magnetic hard masks are preferred in MJT stacks with circular cross-sections (perpendicular to the z-axis) that do not exhibit any magnetic shape anisotropy.

[0054] MJT stacks 301 can be configured as cylinders of various shapes and lateral dimensions, such as circular or elliptical cylinders or nanopillars, wherein the cross-sectional area of ​​the nanopillars in a plane parallel to the stacked layers is typically less than 100. 100 nm², for example, less than 60 60 nm². For such a small volume of magnetic free layer, the magnetization of the free layer is usually well described by a macro-spin model. Even if the magnetic free layer does not necessarily constitute a single magnetic domain, the nucleation process of random flip events in the device usually affects the entire free layer volume. In other words, the magnetization flips are mainly coherent, and the domain walls do not shift significantly in the presence of domain walls.

[0055] The magnetoresistive element 300 is implemented as a three-terminal device, wherein a junction bias voltage is applied to the top contact C0, a first side contact C1 is disposed at one end of the SOT trace 307 for receiving an adjustable SOT current, and a second side contact C2 is disposed at the other end of the SOT trace 307 for electrical connection to a reference potential (e.g., ground). Therefore, biasing the junction 302 via the top contact is decoupled from injecting the SOT current via one of the side contacts, and the junction bias voltage and the SOT current can be controlled independently.

[0056] Figure 4 A cross-section of another exemplary magnetoresistive element 400 along the xz plane is shown. (Compared to...) Figure 3 Compared to the magnetoresistive element 300 in the stack 401, the corresponding positions of the free layer 303 and the reference layer 305 are interchanged, and the magnetoresistive element 400 is configured as a two-terminal device that utilizes the STT effect instead of the SOT effect to tune the desired p-bit by inducing spin torque via current. Given that there are only two control terminals C0 and C1, the junction bias voltage and the STT current flowing through junction 302 are interdependent. In fact, the current I(STT) injected into the multilayer stack 401 is not negligible and causes an additional voltage drop across junction 302, although this additional voltage drop is typically small (e.g., less than 10%) compared to the applied junction bias voltage. One approach therefore involves ignoring this small interdependence and continuing to adjust the STT current and junction bias voltage as if they were independent. Another approach involves determining a set of orthogonal control variables, such as combinations of source current variations and bias voltage variations, which can be stored in a lookup table and directed to the desired values ​​of the STT current and junction bias voltage.

[0057] For embodiments of the invention using magnetoresistive element 400, the RA product associated with the tunnel oxide is typically designed to be less than 100 Ω. µm², for example through a reduced cross-sectional area cylinder in the xy plane and / or the use of a thinner tunnel oxide, facilitates the delivery of larger STT currents and improves the efficiency of converting the STT current into the transferable spin torque desired for tuning the p-position. For STT-assisted magnetoresistive elements using the VCMA effect, the use of a smaller RA product is typically accompanied by a reduction in the linear magnetoelectric coefficient 'ξ' of the free layer, for example, ξ = 50…100 fJ / V / m, or greater.

[0058] The capping layer 306 of the vertical stack 401 may include a nonmagnetic or low coercivity material, such as FeyOx, HfOx, CryOx, or transition metals and their alloys. The free layer 303 in the stack 401 may include the following materials: ferromagnetic materials, ferromagnetic alloys, ferrimagnetic or ferrimagnetic materials doped with transition metals, SAF, or a SAF-HF combination. The reference layer 305 and any hard layer (if present in the stack) in the stack 401 may include the following materials: SAF, a SAF-HF combination, ferromagnetic or ferrimagnetic alloys, repeating Co / NM layers, repeating ferromagnetic or ferrimagnetic alloy / NM layers, where NM represents a nonmagnetic material such as a refractory metal or alloy. The insulating tunnel barrier layer 304 in the stack 401 may include the following materials: MgO, Al2O3, Gd2O3, BaO3Ti, or MgAl2O4.

[0059] In both magnetoresistive elements 300 and 400, the polarity of the charge current converted into spin current and applying a spin moment to the free layer can be unipolar or bipolar. In the first case, the desired value of the generated p-bit can be adjusted within the half-range [0, 0.5] or [0.5, 1], while the second case allows adjustment of the desired value within the full range [0, 1]. In either magnetoresistive element 300 or 400, the applied junction bias voltage should not exceed the damage threshold, otherwise the tunnel barrier 304 of the MJT will break down. For typical magnetoresistive elements in the embodiments of the present invention, with thermal stability constants in the range of 10-20 kT (when the junction bias is zero), the damage threshold is typically above 2 V.

[0060] Figure 5This is a variation of the spintronic random position generator. The spintronic device 500 differs from the aforementioned embodiment in that the second resistor 512 (i.e., magnetoresistive) comprises two equivalent but independent magnetoresistive elements 501 and 502, whose magnetic tunnel junctions are connected in parallel without magnetic crosstalk. Multiple layers of magnetoresistive elements 501 and 502 are stacked on a common conductive trace 531. As long as the number of magnetoresistive elements arranged on the same trace is less than the maximum number of magnetoresistive elements, the resistive losses between the spaced-apart magnetoresistive elements along the trace and the corresponding voltage drops are negligible. In practice, the number 'N' of the magnetically decoupled, spaced-apart magnetoresistive elements along the trace is typically in the range of N = 2, …, 16, for example, N = 2…8, or N = 2…4.

[0061] Conductive trace 531 may include a heavy metal exhibiting spin Hall behavior upon injection of a charged current. In this case, a controlled charge current I (SOT) is generated by current source 530, injected into common trace 531, and flows through the interface with the material stack of magnetoresistive elements 501 and 502. This charge current induces a spin current in a direction perpendicular to both the charge current I (SOT) and the interface with the material stack of magnetoresistive elements 501 and 502 (e.g., along the perpendicular stacking direction of magnetoresistive elements 501 and 502), causing spin to accumulate near the magnetic free layers of magnetoresistive elements 501 and 502. The accumulated spin then imposes a spin moment on the magnetization vector of these two magnetic free layers. In an alternative embodiment of the invention, the material interface between the conductive trace and the magnetoresistive elements may be designed for other forms of spin-orbit coupling, such as through a Rashba or Dresselhaus mechanism.

[0062] The advantage of the spintronic device in this embodiment is that the combination of two random MJTs accelerates the generation of probabilistic bits. In fact, the two magnetoresistive elements are not coupled to each other, and their magnetization states flip independently over time. Assuming that the flipping events of individual MJTs are accurately described by two uncorrelated Poisson processes with rates r1 and r2, the combination of these two Poisson processes is another Poisson process with a rate r that is the sum of the two rates: r = r1 + r2. In other words, voltage fluctuations originating from the two independent MTJs are superimposed at the sensing node N1 and change at a much faster rate, for example, twice the rate of a single MTJ if r1 and r2 are sufficiently close. However, since the injected charge current I(SOT), the resulting spin moment, and the applied junction bias voltage are substantially the same for both magnetoresistive elements, the average resistance values ​​of the two MJTs are identical.

[0063] The combination of two randomly toggled MJTs also reduces any residual probability bias (e.g., any residual perpendicular magnetic anisotropy), which favors one outcome over the other. This results in improved p-bit statistics and a higher-quality random bit generator. While the combination of two or more randomly toggled MJTs has been explained for the case of SOT-type magnetoresistive elements, embodiments of the invention also combine two or more STT-type randomly toggled magnetoresistive elements. For example, this can be achieved by replacing the common SOT trace with a common bottom contact C1 and providing a shunt circuit that divides the source current into a number N approximately equal STT currents, where N is equal to the number of parallel magnetoresistive elements constituting the magnetoresistive reluctance. Alternatively, a number N independent, calibrated current sources can be used independently.

[0064] The spintronic random number generator according to the present invention may have two device outputs (e.g., V+(OUT) and V-(OUT)), at which a random bit stream and its logical inverse stream are generated. Figure 5 As shown in the embodiments, this can be achieved by providing another inverter circuit 521 at the output of the readout circuit 120, which converts the digital signal V+(OUT) into its inverted signal V-(OUT). Furthermore, in embodiments of the invention, the corresponding positions of the first and second resistive elements in the voltage divider network can be interchanged.

[0065] Figure 6 This paper explains how to manipulate the magnetoresistive element of a spintronic device to generate random bits through random flips, and how to adjust the desired random bits. If no junction bias voltage 'VB' is applied, the static free-layer magnetization of the MJT in the magnetoresistive element can be in one of two bistable states, separated by an energy barrier of height ΔE. The magnetization directions of the free layer (FL) and reference layer (RL) in a magnetic tunnel junction with a tunneling barrier (TB) are depicted for these two states, designated as a parallel state (P) and an antiparallel state (AP) with a fixed perpendicular magnetization direction relative to the reference layer, respectively. Each of these bistable states is characterized by the strong perpendicular component and the weak in-plane component, respectively, attributed to the effective perpendicular magnetic anisotropy field (H-PMA) and the in-plane magnetic bias field (HB). The energy barrier is high enough to suppress thermally activated random flips of the free-layer magnetization between these two bistable states. AP, or MJT, is in a thermally stable configuration. In embodiments of the invention, the free-layer volume and energy density with perpendicular magnetic anisotropy are designed such that at room temperature T = 300 K, the barrier height is 10 kT ≤ ΔE (VB = 0) ≤ 20 kT, which is lower than the barrier height in a stable memory cell of conventional MRAM (e.g., 40 kT ≤ ΔE). Experiments show that MJTs with low barrier heights of only a few kT are difficult to scale; various attempts show that the degree of device variability is large relative to the achieved barrier height. However, good scalability and repeatability are crucial for spintronic random bit generators intended for use in large-scale computing hardware (e.g., probabilistic computing architectures such as Ising machines, Bayesian network machines, belief networks, or Boltzmann machines). In embodiments of the invention, a barrier height variability of 4-5 kT is acceptable on large arrays of spintronic random bit generators. On the other hand, excessively high energy barriers are detrimental because they require very large junction bias voltages to reduce the energy barrier to the region of thermally activated random flipping via the VCMA effect, which has the consequence of higher energy consumption or electrical breakdown.

[0066] Due to the magnetoresistance effect, i.e., the resistance of an MJT is a function of the polar angle (θ) between the magnetization vectors of the reference layer and the free layer, the resistance R(P) of the P-state MTJ is less than the resistance R(AP) of the AP-state MTJ. The TMR coefficient of the MTJ is defined as TMR = 1 + R(AP) / R(P), and for embodiments of the present invention, it is in the range between 100% and 250% under zero junction bias.

[0067] Next, a critical junction bias voltage is applied across the MJT, which completely eliminates or at least significantly reduces the energy barrier that would otherwise separate the two bistable states (e.g., ΔE < 5 kT, for example, ΔE ≈ 0). The critical junction bias voltage can be instantaneously turned on and subsequently applied as a DC signal, or it can be applied in the form of a long voltage pulse (i.e., lasting much longer than the oscillation period of the resulting free-layer magnetization relaxation oscillation, e.g., tens or hundreds of nanoseconds). Through the VCMA effect, the easy axis associated with the magnetic anisotropic energy density is transformed into a easy surface, and the energy distribution tracked as a function of the free-layer magnetization polar angle θ abruptly becomes bowl-shaped, with a minimum energy at the polar angle θ = π / 2. This defines at least one new equilibrium state of the free-layer magnetization vector (FL-M) in the plane of the free layer (azimuth plane, θ = π / 2). More precisely, if the in-plane magnetic bias field is attributable to (e.g., for a multilayer stack where the magnetically free layers are elongated in a cross-section perpendicular to the vertical stacking direction) an effective magnetic field of magnetocrystalline anisotropy or shape anisotropy, then along the axis defined by the in-plane magnetic bias field, two new energy minima appear at opposite azimuths (e.g., at the antipodal point in the azimuth plane θ = π / 2). =0° and =180°). In the case of an externally applied in-plane magnetic bias field and an isotropic static magnetic free energy surface, there exists a single energy minimum in the azimuth plane aligned with the direction of the magnetic bias field. If the energy barrier is only partially lowered in the easy axis direction of the free layer, the externally applied in-plane magnetic bias field cancels out the remaining effective perpendicular magnetic anisotropy field, causing the equilibrium magnetization vector of the free layer to tilt toward the azimuth plane. Depending on the relative strength of the externally applied in-plane magnetic bias field and the residual effective perpendicular magnetic anisotropy field, the Stoner-Wohlfahrth model predicts one or two equilibrium states of the free layer magnetization. However, in all the above cases, the initial magnetization of the free layer is nearly perpendicular to the free layer, causing the free layer magnetization vector to begin to relax toward one of its new equilibrium states. The dynamics of this relaxation process can be accurately described by the LLG equations, which are well-known in the field of magnetism and predict a damped precession of the free-layer magnetization around a new equilibrium magnetization vector, which is substantially aligned with the in-plane magnetic bias field. In various embodiments, the effective damping can be quite strong, and the precession can stop after 2 to 20 oscillation cycles, with the oscillation frequency in the sub-gigahertz to gigahertz range, for example, hundreds of megahertz. The seemingly regular relaxation process is actually strongly influenced by thermal perturbations. The thermal noise is well described by a Gaussian white noise process of the thermal random magnetic field, which contributes to the effective magnetic field. The correlated noise power of the thermal random magnetic field is NP = α / (1+α²). kT / (γ M V); where α is the effective Gilbert damping constant, γ is the gyromagnetic ratio, M is the saturation magnetization, and V is the free layer (macrospin) volume. In embodiments of the invention, the influence of the thermal fluctuation field becomes very important because the damping can be quite strong and the free layer volume is often small in nanopillar MJT stacks. As a result, irregular behavior is superimposed on the relaxation oscillations of the free layer magnetization, causing the magnetization vector to randomly flip between opposite sides of the easy plane (i.e., random flipping of magnetization), and even when the extreme barrier is reduced to zero, the magnetization vector also randomly flips between antipodal points within the easy plane. The extreme components of the thermal random magnetic field and the azimuth anisotropy bias direction imposed by the hard mask or the elongated (e.g., elliptical) structure of the stack control the flipping rate and thus the sampling rate of the probability bits. Although the TMR coefficient (VB=Vcrit) associated with random fluctuations in free layer magnetization at the applied junction bias voltage is significantly reduced relative to the original value when the junction bias is zero, it can still be in the range of 20% to 50%, or even higher. Since the thermal noise is isotropic and the dynamics of the free layer magnetization are unbiased, the probability of a random bit taking "0" or "1" due to random flips in the free layer magnetization is equal, both being p=0.5.

[0068] When the energy barrier is completely eliminated and the junction voltage exceeds the critical junction bias voltage, the contribution of the effective vertical magnetic anisotropy energy to the total energy surface passes through zero and changes sign. This results in a strong energy gradient in the pole direction (e.g., out-of-plane direction), which greatly reduces the influence of the polar component of the thermal noise field and effectively confines the random precession of the free layer magnetic moment to the vicinity of the azimuth plane. Only during a thermally induced reversal event (crossing the azimuth energy barrier) in the free layer magnetization state between the azimuth and antipodal points, where the free layer magnetization has sufficient energy to briefly progress to a larger polar angle, does the effective vertical magnetic field control the precession dynamics and cause a rapid rotation about the vertical axis and into another energy valley. Therefore, in embodiments where the reference layer magnetization has an in-plane configuration (e.g., within the plane of the reference layer), an improved TMR coefficient (e.g., between 100% and 250%, or greater) can be obtained in the random reversal region. Furthermore, the smaller the magnitude of the in-plane magnetic bias field applied to the free layer, the smaller the azimuth barrier between the antipodal points of the easy surface, and the faster the random flip-off event between the two new equilibrium states. It should be noted that the azimuth barrier is different from the poloidal barrier, which is in the vertical direction and is eliminated by the VCMA effect induced by the applied junction bias voltage.

[0069] To adjust the desired value of the generated random position, the free-layer magnetization vector (FL-M) must be biased such that its equilibrium position is tilted relative to the easy plane of the free layer. Isotropic thermal noise contributes zero on average to the angular deviation (θ) of the free-layer magnetization, but non-thermal bias does not cancel out on average under thermal fluctuations. Out-of-plane bias can be achieved by the net spin moment 'N-STT' acting on the free-layer magnetization. In the case shown in this figure, the spin moment 'N-STT' is generated by the spin-polarized current 'I-STT' flowing through the free layer. In an alternative embodiment, the spin moment can be generated by a charge current in the presence of spin-orbit coupling. The direction of the current 'I-STT' flowing through the free layer can be reversed, resulting in a tilt of the free-layer magnetization vector relative to the easy plane in the opposite direction. The current magnitude controls the order of the resulting spin moment and, consequently, determines the final average angular deviation (θ) of the free-layer magnetization. The larger the angular deviation, the longer it takes for thermal fluctuations (random walks) to temporarily flip the magnetization of the free layer to the opposite half of the easy plane. Therefore, the probability of observing a random bit in a "0" state is higher than the probability of observing a random bit in a "1" state, and vice versa. Thus, the expectation of a binary random variable can be tuned by the direction and amplitude of the current. The functional relationship between the expectation and the control current 'I' (e.g., I-STT or I-SOT) can be described by a sigmoid function 'σ', i.e., p = σ(I / I0), where I0 is a normalization constant.

[0070] The random bit generating spintronics devices according to embodiments of the present invention can be used as independent random bit generators, or multiple random bit generating spintronics devices can be used in combination, for example, to obtain new random variables as functions of multiple random bits or to construct random variables with multi-bit resolution. Specifically, it is desirable to assemble multiple random bit generating spintronics devices into larger asynchronous networks or networks with reconfigurable connections between subsets of random bit generating spintronics devices. The connections between random bit generating spintronics devices in the network depend on the application. For example, nearest neighbors in a network of random bit generating spintronics devices arranged in a grid are often used in Ising machines—a specific type of probabilistic computing hardware. For machine learning and optimization applications, Boltzmann machines, belief networks, or other types of hierarchical probabilistic machine learning structures can be constructed according to groups or blocks of random bit generating spintronics devices, which are assigned to network layers and the random bit generating spintronics devices in different blocks are interconnected. In this way, skip connections can also be achieved.

[0071] Figure 7Basic building blocks 701, 702 of a network forming a random bit-generating spintronic device according to an embodiment of the present invention are shown. For example, Bayesian networks or random neural networks can be built from these building blocks, where Monte Carlo or Gibbs samplers are required to update intermediate results related to high-dimensional integrals or probabilistic inference processes. A set of N random bit generators p1, p2, ..., pN is organized into a column, forming the first building block 701 of network 700. This column of random bit generators can be identified as a layer of network 700. The second building block 702 is provided by interconnect modules. Each random bit generator has two outputs, V+ and V-, for delivering two complementary random bit streams (e.g., complementary bits represented by opposite voltage polarities). Alternatively or supplementarily, it is possible to use a random bit generator with only a single output (e.g., V+ or V-), which delivers a single random bit stream. The outputs of each random bit generator p1 to pN are connected to the corresponding row of a crossbar switch array, which serves as an interconnect module. Each column of the crossbar switch array is connected to M random bit generators q1, q2, ..., qM in another block / layer 704. N = M if the network layers are of the same size, but this is not mandatory. Reconfigurable (e.g., programmable) conductive elements 703 are positioned at each intersection of the rows and columns of the interconnect module. These conductive elements digitally or analogally weight the random bit signals driving the row associated with them. As a result, the random bit signals from the N random bit generators are first weighted by the conductive elements in the same column of the crossbar switch array and then accumulated over that column, for example, in the form of a weighted sum current. In other words, an N×M interconnect module 702 is configured to perform M multiplication-accumulation operations on N random bit input signals, with each column of the module acting as a synaptic element. The reconfigurable conductive element 703 can be implemented as a magnetic nanodevice, such as a single-bit or multi-bit MRAM cell, a memristor, a resistor-capacitor (RC) element, etc., which can optionally be paired with a capacitor to achieve time averaging of the incoming random bit current. Therefore, the cross-switch array forms a tunable resistor bank. In some embodiments of the invention, the interconnect module also additionally performs a nonlinear transformation on the weighted sum current. The input of each random bit generator q1, q2, ..., qM of another module 704 is fed by the corresponding column current of the cross-switch array. (See reference...) Figure 3 and Figure 4As shown by the magnetoresistive element, this current acts as the adjustable SOT or STT drive current for the probability tuning circuit, thereby achieving input-related control of the mean value of the random bits contained in the random bit generators q1, q2, ..., qM. Specifically, a zero-input SOT or STT current (i.e., I / I0 = 0) does not bias the random bit generator, and the resulting unbiased probability bits have equal probabilities of '0' and '1' (p = 0.5). Conversely, a positive or negative normalized input SOT or STT current (i.e., I / I0 ≠ 0) effectively biases the random bit generator, and the resulting biased probability bits have unequal probabilities of '0' and '1' (p ≠ 0.5). In the case of large positive or negative normalized input SOT or STT currents (i.e., I / I0 → ±1), the expected value p of the probability bit approaches and is quasi-fixed to p = 1 or p = 0, thus meaning that the output stream essentially contains only '1 bit' or only '0 bit'. The aforementioned building blocks 701 and 702 can be repeated and / or modified to construct more complex networks, such as multilayer networks and / or recurrent networks. For example, each of the N random bit generators in a multilayer Bayesian network can be used to generate a Gaussian prior distribution with adjustable mean and / or variance, where a larger number of N random bit generators produces a better approximation of the Gaussian distribution, and interconnect modules can be used to store and apply conditional probabilities. The weighted sum output of the interconnect modules represents the posterior probability distribution, which can be passed to the next layer of the Bayesian network.

[0072] The network 700 described above can also be used to solve optimization problems in probabilistic computational hardware contexts, serving as a well-regarded alternative to conventional computation based on deterministic Turing machines. For example, a node of the Ising machine is represented by a column of N random bit generators in block 701. The column current generated by interconnect module 702 is fed back to the random bit generators in block 701, meaning that in this case, blocks 701 and 704 are equivalent and mutually recognized. The optimization problem (e.g., an NP-complete combinatorial optimization problem) is programmed into interconnect module 702 of network 700: first, the optimization problem is mapped to an energy function (e.g., the Hamiltonian or equivalent cost function of the Ising model), and the spin variables of the Ising model are encoded into probabilistic bits, with the weights of the conductive elements subsequently set according to the interaction strength (coupling coefficient) of the energy function. Additional connections can be added to incorporate constant inputs (e.g., linear terms in the energy or cost function). Asynchronous flipping events of the magnetization states of the random bit generators correspond to sampling or exploration of the energy surface of the system according to the Boltzmann probability distribution. When the system temperature is sufficiently low, the network evolves towards its ground state, which has the lowest system energy, and the output behavior of the random bit generator becomes fixed to a static '1 bit' or '0 bit'. However, if the system gets stuck in a local energy minimum, the time required to finally observe the ground state can become extremely long. Therefore, it is advantageous to run a simulated annealing algorithm on the network 700 to solve the optimization problem: it starts at a relatively high system temperature (where the output flow of the network's random bit generator changes frequently) and gradually decreases the temperature to reduce the frequency of output flow changes, eventually blocking the network at its ground state or at least at an acceptable suboptimal energy state. The annealing temperature can be set by reducing the applied junction bias voltage over time and increasing the (extreme) energy barrier of the random bit generator. Through alternating annealing steps and system relaxation, the network slowly relaxes to the ground state (energy minimum) representing the optimal solution. Solving the optimization problem in this way has another advantage: the output state of the random bit generator does not need to be continuously monitored by a control unit such as a microcontroller, and considering that the output current of the random bit generator is converted into a drive current, no additional components (such as a DAC) are needed to generate the simulated SOT or STT current. Although simulated annealing is given as an example algorithm that can run on this network, other sampling-based algorithms such as Monte Carlo or Quantum Monte Carlo algorithms can also be executed on networks of random bit generating spintronics devices.

[0073] Figure 8The steps of a method 800 for generating probabilistic bits by means of magnetoresistive reluctance according to another aspect of the invention are shown. The magnetoresistive reluctance comprises at least one vertical multilayer stack, and the stack includes a magnetic tunnel junction. In an unbiased state (i.e., with an applied junction bias voltage of zero), the magnetic tunnel junction is thermally stable within the operating temperature conditions. Furthermore, the magnetic free layers of the at least one magnetic tunnel junction exhibit vertical magnetic anisotropy related to the electric field, for example, susceptibility to the VCMA effect.

[0074] In the first step 801, a bias voltage is applied across at least one magnetic tunnel junction across the magnetoresistance, thereby completely or partially eliminating the energy barrier associated with perpendicular magnetic anisotropy. Partial elimination of the barrier to perpendicular magnetic anisotropy is achieved if the applied junction bias voltage is below a predetermined critical junction bias voltage, but large enough to make the magnetic tunnel junction thermally unstable. This is practically the case if the remaining barrier height is less than 10 kT, for example, less than or about 5 kT. Here, k is the Boltzmann constant, and T is the junction temperature, which may be higher than the ambient temperature due to self-heating effects. Controlling the applied junction bias voltage allows the barrier to be adjusted to a lower height, or even eliminated completely. The magnetization vector of the free layer is then perturbed by thermal noise.

[0075] Next, in step 802, a magnetic bias field is applied to the magnetic free layer of the at least one magnetic tunnel junction (MTJ). This defines a preferred axis for the free layer magnetization vector to precess around it when subjected to thermal noise. Thermal noise allows the free layer magnetization to randomly flip between two energy minimums of the energy surface associated with the free magnetic layer. The applied magnetic bias field is oriented perpendicularly to the multilayer stack with the MTJ and is preferably weaker than an effective vertical magnetic field applied to a free layer without bias on the MTJ. For example, the magnetic bias field is less than about 10 mT and can be generated by a hard layer (hard mask) in the stack, and / or by the in-plane shape anisotropy of the free layer, such as in a multilayer stack with an elongated cross-sectional shape (e.g., an elliptical cross-sectional shape) in a plane perpendicular to the stack direction.

[0076] Step 803 involves applying a controllable spin moment to the free layer of the magnetic tunnel junction of the at least one magnetoresistive element, thereby adjusting the mean of the free layer magnetization in relation to a set of thermal random reversal events. The spin moment is induced by a charge current via the STT or SOT effect. In the former case, the controllable charge current is injected into the multilayer stack and flows through each MTJ, while in the latter case, the controllable charge current flows through the free layers of one or more material stacks formed on the same conductive trace. This charge current can be provided by a gate-controlled or pulsed current source, wherein the pulse lasts for several precession time periods of the free layer magnetization in the thermal reversal region, for example, at least 10 precession periods, i.e., between 1 ns and 1 µs. The polarity of the controllable current can be unipolar or bipolar (i.e., reversible).

[0077] Random flips in the free-layer magnetization are converted into changes in the TMR coefficient associated with each MTJ of the magnetoresistive layer. In step 804, the fluctuating tunneling current flowing through the MTJ of the magnetoresistive layer is detected against the applied junction bias voltage and converted into a digital output voltage signal in step 805 at a rate compatible with thermal random flips. This may include comparing the tunneling current with a reference current (e.g., the average current flowing through the unbiased MTJ). Alternatively, a constant current source is used to generate a sense current across the magnetoresistive layer and the fluctuating voltage across the magnetoresistive layer is measured and digitized at a rate compatible with thermal random flips. The sense current is chosen to be small enough not to cause any measurable STT effect in the MTJ, and the AC voltage fluctuation across the magnetoresistive layer is typically smaller than the applied DC or quasi-DC junction bias voltage. The digitization step may include comparing the fluctuating voltage signal across the magnetoresistive layer with a reference voltage signal (e.g., the average voltage level of the unbiased MTJ) or providing the fluctuating voltage signal across the magnetoresistive layer to the input of an inverter stage or a series of inverter stages. Optionally, prior to the digitization in step 805, the sensed voltage or current fluctuations are amplified. The resulting digital output signal contains a series of random transitions (i.e., bit flips) that represent thermally induced reversal events in the free layer magnetization.

[0078] Optionally, in step 806, the binary output signal obtained in step 805 is converted into a digital current signal with multi-bit resolution. This conversion can be implemented by a programmable or configurable conductive element, and the current signal can be applied to multiple other current signals output by different conductive elements. Alternatively, the conversion is to an analog current signal. The current signal obtained in step 806 can be used to generate the spin moment relative to the same magnetoresistive element or another magnetoresistive element in step 803.

[0079] This invention can be implemented in various ways and is not limited to the disclosed embodiments. By studying the drawings, this disclosure, and the appended claims, those skilled in the art can understand and implement other variations of the disclosed embodiments when practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plural. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be advantageously used. Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A spintronic device (100; 200; 500) for probability bit generation, comprising: Magnetoresistive (112), the magnetoresistive includes a magnetic tunnel junction (302) formed in a multilayer stack (301) and a magnetic free layer (303) of the magnetic tunnel junction, the magnetic free layer exhibiting magnetic anisotropy related to the electric field in a direction perpendicular to the magnetic tunnel junction; A device for generating a magnetic bias field along a predefined axis in the plane of the magnetic free layer; A junction bias circuit (110) for eliminating the energy barrier associated with the magnetic anisotropy is configured to apply a controllable bias voltage across the magnetic tunnel junction of the magnetoresistance, thereby allowing thermal random flipping to occur as the free layer magnetization precesses about the predefined axis of the magnetic bias field. A probabilistic tuning circuit (130) is configured to apply a controllable spin moment to the free layer of the magnetic tunnel junction of the magnetoresistive reluctance, thereby adjusting the mean value of the magnetization of the free layer for a set of thermal random flip events. Readout circuits (120, 220) are adapted to sense and digitize voltage fluctuations across the magnetoresistive field or current fluctuations flowing through the magnetoresistive field at a rate matching the thermal random flip-flop event.

2. The spintronic device (500) according to claim 1, characterized in that, The magnetoresistive (512) includes a plurality of parallel magnetic tunnel junctions, which are formed in a plurality of corresponding spaced multilayer stacks extending vertically from the conductive bottom trace (531), and the magnetic free layer of each magnetic tunnel junction exhibits electric field-dependent magnetic anisotropy in a direction perpendicular to the magnetic tunnel junction. The junction bias circuit (110) is configured to apply the controllable bias voltage across the magnetic tunnel junction of the magnetoresistive reluctance; The free layer of the magnetic tunnel junction is in contact with the conductive bottom trace; as well as The probability tuning circuit (530) is configured to allow current to flow through the bottom trace, and the current to flow is adjustable to control the amount of spin-orbit moment applied to the free layer of the magnetic tunnel junction of the magnetoresistive reluctance.

3. The spintronic device according to claim 1 or 2, characterized in that, The tunnel barrier (304) of the magnetic tunnel junction of the magnetoresistive type comprises a single dielectric layer having a resistive area RA ≤ 500 Ωµm².

4. The spintronic device according to any one of the preceding claims, characterized in that, The apparatus for generating the magnetic bias field includes a hard magnetic layer (306) for generating the magnetic bias field at the magnetic free layer of each magnetic tunnel junction. The hard magnetic layer is formed above or below the magnetic free layer and is magnetized in a direction parallel to the plane of the magnetic free layer. Alternatively, the means for generating the magnetic bias field may include an elongated shape structure of the magnetic free layer (303) to form an intrinsic magnetic shape anisotropy along the predefined axis in the magnetic free layer.

5. The spintronic device according to claim 1, characterized in that, The probability tuning circuit is configured to allow a spin-polarized current to flow through the magnetic tunnel junction of the magnetoresistor. The spin-polarized current to flow is adjustable to control the amount of spin-transfer torque applied to the free layer of the magnetic tunnel junction of the magnetoresistor.

6. The spintronic device according to claim 5, characterized in that, The probability tuning circuit includes an adjustable current source connected to one side of the magnetic tunnel junction.

7. The spintronic device according to claim 6, characterized in that, The tunnel barrier (304) of the magnetic tunnel junction of the magnetoresistive type comprises a single dielectric layer having a resistive area RA ≤ 100 Ωµm².

8. The spintronic device according to any one of the preceding claims, characterized in that, The operating frequency bandwidth of the readout circuit is in the GHz range.

9. The spintronic device according to any one of the preceding claims, characterized in that, One or more multilayer stacks of the magnetoresistive material are configured as nanopillars.

10. The spintronic device according to any one of the preceding claims, characterized in that, For an unbiased junction, the energy barrier associated with magnetic anisotropy is at least 20 kBT.

11. The spintronic device according to any one of the preceding claims, characterized in that, The multilayer stack of at least one magnetic tunnel junction of the magnetoresistive reluctance also includes a capping layer, the material of which comprises Fe. y O x HfO x Cr y O x At least one of transition metals and transition metal alloys.

12. The spintronic device according to any one of the preceding claims, characterized in that, The magnetic free layer (303) of the magnetic tunnel junction is one of a ferromagnet, a ferromagnetic alloy, a ferrimagnetic alloy, and a ferromagnet or ferrimagnet doped with a transition metal, and the magnetic free layer does not include synthetic antiferromagnets.

13. A probabilistic sampling computing device comprising a network (700) of spintronic devices as described in any one of the preceding claims, the spintronic devices in the network being coupled by synaptic elements, wherein each synaptic element is configured to generate a weighted sum of output signals of a readout circuit of a subset of the spintronic devices in the network, derive a spin moment control signal from the weighted sum, and apply the spin moment control signal to a probabilistic tuning circuit of at least one spintronic device of the network.

14. The computing device according to claim 13, characterized in that, The synaptic element is configured as an adjustable resistor group (702), which is arranged between the various blocks of the spintronic device to form a multilayer network.

15. A method (800) for generating probability bits using magnetoresistance, the method comprising: (i) A bias voltage (801) is applied across the magnetic tunnel junction of the magnetic reluctance, wherein the magnetic free layer of the magnetic tunnel junction exhibits electric field-dependent magnetic anisotropy in a direction perpendicular to the magnetic tunnel junction; (ii) Generate (802) a magnetic bias field along a predefined axis in the plane of the magnetic free layer; (iii) Adjust (801) the bias voltage across the magnetic tunnel junction so that the energy barrier associated with the magnetic anisotropy is eliminated, thereby allowing thermal random flipping as the free layer magnetization precesses about a predefined axis of the magnetic bias field. (iv) Apply a (803) controllable spin moment to the free layer of the magnetic tunnel junction of the magnetoresistive layer to adjust the mean of the magnetization of the free layer for a set of thermal random flip events. (v) Sensing (804) and digitizing (805) the fluctuating voltage signal across the magnetoresistive or the fluctuating current signal flowing through the magnetoresistive at a rate matching the thermal random flip-flop event.

16. The method according to claim 15, characterized in that, The magnetic free layer of the magnetic tunnel junction is one of a ferromagnet, a ferromagnetic alloy, a subferromagnetic alloy, and a ferromagnet or subferromagnet doped with a transition metal, and the magnetic free layer does not include synthetic antiferromagnets.

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