Semiconductor device

Abstract

Provided is a semiconductor device in which solder spreading due to excessive wetting is suppressed. A semiconductor device is provided with: an insulating circuit board (1) having an insulating substrate (11), and an upper conductor layer (12a) and an upper conductor layer (12b) provided on the upper surface of the insulating substrate (11) so as to be separated from each other; a semiconductor chip (3) mounted on the upper conductor layer (12a) via solder; an external terminal (4) having a bonding portion (41) bonded to a first bonding region (14), which is one region of the upper surface of the upper conductor layer (12b), via solder (2b); a printed circuit board (6) disposed above the semiconductor chip (3); a pin terminal (51) that is inserted into the printed circuit board (6), and that is bonded to a second bonding region (15), which is the other region of the upper surface of the upper conductor layer (12b), via solder (9a); and a solder resist part (7) provided on the upper surface side of the upper conductor layer (12b) and adjacent to the first bonding region (14).

Description

Technical Field

[0001] This invention relates to a semiconductor device (semiconductor module) equipped with a power semiconductor chip. Background Technology

[0002] Semiconductor devices equipped with power semiconductor chips (hereinafter referred to as "semiconductor chips") are mainly used in variable speed drive applications such as motors and inverters, as well as power conversion applications. In addition to the semiconductor chips, components forming wiring are also bonded to the substrate of the semiconductor device. Sometimes, solder resist is formed by irradiating the upper surface of a metal layer disposed on such a substrate with a laser.

[0003] Patent Document 1 describes a technique in which one end of an external terminal is bonded to the upper surface of an upper conductive layer via a bonding material such as solder. It also describes a technique in which a semiconductor chip is disposed at the center of a semiconductor device, and the external terminal is disposed at the periphery of the semiconductor device.

[0004] Patent Document 2 describes a power semiconductor device comprising: a lower substrate on which a power semiconductor element is mounted; an upper substrate facing the lower substrate; a plate-shaped connecting member that electrically connects an element electrode formed on the power semiconductor element to a circuit pattern formed on the upper substrate; and a control terminal.

[0005] Patent document 3 describes metal plates, leads, chip pads, and solder pads.

[0006] Patent document 4 describes the following technology: a circuit pattern of a gate connection terminal and an emitter signal terminal fixed to a printed circuit board, and the ends of which are also fixed to a first copper plate on an insulating board.

[0007] Patent document 5 describes the following technique: forming a low-wetting portion with low wettability for solder on the electrode pads of a semiconductor chip, printing solder paste containing flux to cover the top of the low-wetting portion, forming solder bumps that are connected to the electrode pads by reflow soldering the solder paste, and forming voids in the solder bumps by allowing gas generated from the flux to contact the top of the low-wetting portion and remain there.

[0008] Patent document 6 describes the following technique: forming a nickel plating (Ni) layer on the surface of the circuit layer of a circuit board for a semiconductor device, and arranging a solder bonding predetermined portion for soldering semiconductor elements and a deteriorated portion caused by laser irradiation adjacent to each other in the planar direction on the formed nickel plating layer.

[0009] Patent document 7 describes the following technology: a substrate is bonded to a main surface of a heat sink via a solder layer, a semiconductor element is bonded to a main surface of the substrate via a solder layer, a housing is bonded to a main surface of the heat sink in a manner that surrounds the substrate, an internal electrode electrically connected to the semiconductor element is included on the inner circumferential side of the housing, and the bonding surface of the main surface of the heat sink to the housing has a first region with a solder resist layer and a second region without a solder resist layer, the second region being formed to include a region that overlaps with the internal electrode when viewed from above.

[0010] Patent document 8 describes the following technique: a semiconductor chip is soldered to one side of an insulating circuit substrate with conductive patterns on both sides to form a cell unit; an insulating inorganic layer is formed by bonding the portion of the cell unit to a metal substrate used to dissipate heat generated by the semiconductor chip using a metal mask. The cell unit is then soldered to the metal substrate and encapsulated with insulating resin.

[0011] Patent Document 9 describes a method for providing a hydrophobic portion formed by laser irradiation on a circuit board of a ceramic circuit substrate. Additionally, Patent Document 1 describes a technique where the hydrophobic portion is provided between areas where semiconductor chips and contact components are respectively disposed.

[0012] Existing technical documents

[0013] Patent documents

[0014] Patent Document 1: Japanese Patent No. 7409035

[0015] Patent Document 2: Japanese Patent Application Publication No. 2015-142018

[0016] Patent Document 3: Japanese Patent Application Publication No. 2021-068783

[0017] Patent Document 4: Japanese Patent No. 5644440

[0018] Patent Document 5: Japanese Patent Application Publication No. 2015-076429

[0019] Patent Document 6: Japanese Patent Application Publication No. 2014-167983

[0020] Patent Document 7: Japanese Patent Application Publication No. 2019-197831

[0021] Patent Document 8: Japanese Patent Application Publication No. 2008-172066

[0022] Patent Document 9: Japanese Patent Application Publication No. 2021-118350 Summary of the Invention

[0023] The problem the invention aims to solve

[0024] When lead terminals are used instead of wires to form wiring, a portion of the lead terminal is bonded to the metal layer of the substrate via a bonding material such as solder. During reflow soldering, the molten solder may sometimes wet and spread.

[0025] In view of the above problems, the object of the present invention is to provide a semiconductor device that suppresses excessive solder wetting and propagation.

[0026] Solution for solving the problem

[0027] The subject of one aspect of the present invention is a semiconductor device comprising: (a) an insulating circuit substrate having an insulating substrate and a first conductor layer and a second conductor layer disposed separately on the upper surface of the insulating substrate; (b) a semiconductor chip mounted on the first conductor layer via solder; (c) an external terminal having a bonding portion and the bonding portion being bonded to a region, namely a first bonding region, on the upper surface of the second conductor layer via solder; (d) a printed circuit board disposed above the semiconductor chip; (e) a first pin terminal inserted into the printed circuit board and bonded to another region, namely a second bonding region, on the upper surface of the second conductor layer via solder; and (f) a solder resist portion disposed on the upper surface side of the second conductor layer and adjacent to the first bonding region.

[0028] Alternatively, the second conductor layer may be disposed close to the first side, which is one side of the insulating substrate. In the case where the side of the second conductor layer that is close to the first side is designated as the second side and the side that is opposite to the second side is designated as the third side, the first bonding area is the area close to the second side and the second bonding area is the area close to the third side.

[0029] Alternatively, the solder mask portion can be disposed between the first bonding area and the second bonding area.

[0030] Alternatively, the solder mask portion can be disposed between the first bonding area and the second side.

[0031] Alternatively, the external terminals can be separated from the printed circuit board.

[0032] Alternatively, a boss protruding toward the second conductor layer may be provided at the joint.

[0033] Alternatively, the thickness of the solder between the joint and the second conductor layer may be 50 μm or more and 500 μm or less in the portion of the joint where no boss is provided.

[0034] Alternatively, the insulating substrate may contain a resin material.

[0035] Alternatively, copper can be exposed on the surfaces of the first and second conductor layers.

[0036] Alternatively, the solder resist portion can be a laser solder resist portion formed by irradiating the upper surface of the second conductor layer with a laser.

[0037] Furthermore, the above summary of the invention does not list all the essential features of the invention. Additionally, sub-combinations of these feature groups can also constitute an invention.

[0038] The effects of the invention

[0039] According to the present invention, a semiconductor device that suppresses excessive solder wetting and propagation can be provided. Attached Figure Description

[0040] Figure 1 This is a cross-sectional view showing a portion of the longitudinal structure of the semiconductor device according to the first embodiment.

[0041] Figure 2 This is a top view showing a portion of the insulating circuit board of the semiconductor device according to the first embodiment.

[0042] Figure 3 This is a top view showing the positional relationship between the first bonding region, the second bonding region, and the solder mask on the upper conductor layer according to the first embodiment.

[0043] Figure 4 This is a cross-sectional view showing a portion of the longitudinal structure of the semiconductor device involved in the comparative example.

[0044] Figure 5 This is a top view showing the positional relationship between the first bonding region, the second bonding region, and the solder mask on the upper conductor layer involved in the first variation of the first embodiment.

[0045] Figure 6 This is a top view showing the positional relationship between the first bonding region, the second bonding region, and the solder mask on the upper conductor layer involved in the second variation of the first embodiment. Detailed Implementation

[0046] The first embodiment and its variations will now be described with reference to the accompanying drawings. In the drawings, the same or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may sometimes differ from reality. Furthermore, the drawings may contain parts with different dimensional relationships or ratios. Additionally, the first embodiment and its variations shown below illustrate apparatus and methods for embodying the technical concept of the present invention; the technical concept of the present invention does not specify the material, shape, structure, arrangement, etc., of the structural components as described below.

[0047] Furthermore, the definitions of up and down directions in the following description are merely for ease of explanation and do not limit the technical concept of the present invention. For example, if the object is rotated 90° for observation, up and down is read as left and right; if the object is rotated 180° for observation, up and down are read in reverse order. This is self-evident.

[0048] (First Implementation)

[0049] <Structure of Semiconductor Devices>

[0050] like Figure 1 As shown, the semiconductor device according to the first embodiment includes: an insulating circuit board 1; a semiconductor chip (semiconductor element) 3a mounted on the insulating circuit board 1 via solder 2a; an external terminal 4 connected to the insulating circuit board 1 via solder 2b; and a printed circuit board 6 disposed above the semiconductor chip 3a in a manner separated from it. The semiconductor chip 3a and the printed circuit board 6 are sealed around a sealing member 8, thereby electrically insulating them from their surroundings.

[0051] <Insulated Circuit Board>

[0052] The insulating circuit board 1 includes an insulating substrate 11, upper conductor layers 12a and 12b disposed on the upper surface of the insulating substrate 11 on the circuit surface side, and a lower conductor layer 13 disposed on the lower surface of the insulating substrate 11 on the cooling surface side. Figure 2 As shown, the upper conductor layers 12a and 12b are disposed separately from each other and are not electrically connected. Upper conductor layer 12a is an example of a first conductor layer, and upper conductor layer 12b is an example of a second conductor layer. Upper conductor layers other than upper conductor layers 12a and 12b may also be disposed on the upper surface of the insulating substrate 11. The number of separate upper conductor layers may also be three or more.

[0053] The insulating circuit board 1 can be, for example, a direct copper bonding (DCB) substrate or an active brazing (AMB) substrate. The insulating substrate 11 is, for example, made of a ceramic substrate containing alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc., or a resin insulating substrate using a resin material such as a polymer. The resin insulating substrate may also contain ceramic fillers such as boron nitride. In this embodiment, the insulating substrate 11 is described as being made of a resin insulating substrate. The upper conductor layers 12a and 12b and the lower conductor layer 13 are, for example, made of copper (Cu), aluminum (Al), etc., conductor foils or conductive plates. On the surfaces (upper surfaces) of the upper conductor layers 12a and 12b, the metal constituting the upper conductor layers 12a and 12b can be directly exposed, or a nickel plating layer can be formed. The upper conductor layers 12a and 12b form a predetermined circuit pattern. Figure 1 and Figure 2 As shown, a solder resist portion 7 is provided on the upper surface of the upper conductor layer 12b. The solder resist portion 7 is a laser solder resist portion.

[0054] like Figure 1 As shown, the semiconductor chip 3a is bonded to the upper conductor layer 12a via solder 2a. The external terminal 4 is bonded to the upper conductor layer 12b via solder 2b. For example, the semiconductor chip 3a is mounted only on the upper conductor layer 12a of the upper conductor layer 12a and the upper conductor layer 12b. Solders 2a and 2b are bonding materials. For example, tin-antimony (SnSb) based solders and tin-silver (SnAg) based solders can be used.

[0055] The type of semiconductor chip 3a varies depending on its application. For example, it can be a power semiconductor device such as an insulated-gate bipolar transistor (IGBT), a reverse-biased IGBT (RC-IGBT), a field-effect transistor (FET), an electrostatic induction (SI) thyristor, a gate turn-off (GTO) thyristor, or a rectifier device such as a freewheeling diode (FWD). Semiconductor chips 3a, 3b, and 3c can be made of, for example, a silicon (Si) substrate, or a compound semiconductor substrate containing wide-bandgap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). Semiconductor chip 3a is, for example, a power semiconductor chip.

[0056] exist Figure 1 In this example, a semiconductor chip 3a is mounted on the upper conductor layer 12a, but the number of semiconductor chips is not particularly limited. For example, such as... Figure 2As shown, four semiconductor chips 3a, 3b, 3c, and 3d can be present on the upper conductor layer 12a, or more than five semiconductor chips can be present. Alternatively, the semiconductor chips can be disposed on an upper conductor layer other than the upper conductor layer 12b. When semiconductor chips 3a, 3b, 3c, and 3d are not distinguished from each other, they are sometimes simply referred to as semiconductor chip 3.

[0057] For example, when the semiconductor chip 3 is a field-effect transistor, it has a control electrode (gate electrode) and a first main electrode (source electrode) on its upper surface and a second main electrode (drain electrode) on its lower surface. Furthermore, when the semiconductor chip 3 is an IGBT or RC-IGBT, it has a control electrode (gate electrode) and a first main electrode (emitter electrode) on its upper surface and a second main electrode (collector electrode) on its lower surface. When the semiconductor chip 3 is an electrostatic induction thyristor, a gate turn-off thyristor, or a freewheeling diode, it has a first main electrode (e.g., anode electrode) on its upper surface and a second electrode (e.g., cathode electrode) on its lower surface. The first main electrode is the main electrode that is bonded to the pin terminals described later via solder. In this embodiment, the semiconductor chip 3 is described as a field-effect transistor. Figure 2 As shown, the semiconductor chip 3 has a source electrode 31 and a gate electrode 32 on its upper surface.

[0058] like Figure 1 As shown, a printed circuit board 6 is disposed above the semiconductor chip 3. The printed circuit board 6 includes an insulating layer 61, an upper wiring layer (not shown) disposed on the upper surface of the insulating layer 61, and a lower wiring layer (not shown) disposed on the lower surface of the insulating layer 61. The upper wiring layer and the lower wiring layer constitute a predetermined circuit pattern.

[0059] The insulating layer 61 is made of insulating materials such as ceramics and resins, with aluminum oxide (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4) as the main components. The insulating layer 61 can also be a resin substrate made of a combination of glass fiber and epoxy resin. The upper wiring layer and the lower wiring layer are made of conductor foils containing copper (Cu), aluminum (Al), etc., for example.

[0060] like Figure 1As shown, a plurality of through-holes (vias) 6x are provided on the printed circuit board 6, which permeate the insulating layer 61, the upper wiring layer, and the lower wiring layer. A plurality of pin terminals (pillar electrodes) 50 are inserted (pressed in) and fixed to the plurality of through-holes 6x on the printed circuit board 6. The printed circuit board 6 and the pin terminals 50 constitute the implantation substrate (6, 50). Alternatively, a conductive layer (not shown) is formed on the inner surface of the through-holes 6x to conduct the upper and lower wiring layers. This conductive layer on the inner surface is connected to the inserted pin terminals 50, thereby making the upper and lower wiring layers at the same potential.

[0061] The lead terminal 50 may be rod-shaped (pin-shaped) or cylindrical, specifically, it may be a cylindrical, elliptical, triangular, or quadrangular prism, or other polygonal prism. Conductive materials such as copper (Cu) can be used as the material for the lead terminal 50. The lead terminal 50 includes... Figure 1 The pin terminals 51, 52 and shown Figure 2 The pin terminal 53 is shown. (As shown in the image) Figure 1 As shown, the lower end of pin 51 is bonded to the upper conductor layer 12b via solder 9a. Pin 51 is an example of a first pin terminal. Figure 2 As shown, multiple pin terminals 51 are provided, although not limited to this, but for example, arranged in a row. The pin terminals 51 are connected to the upper conductor layer 12b, which is one of the multiple upper conductor layers to which the external terminal 4 is joined. Furthermore, the number of pin terminals 51 is not limited to... Figure 2 The number of roots shown. For example... Figure 2 As shown, the lower end of pin terminal 52 is bonded to the source electrode 31 of semiconductor chip 3a via solder 9b. Furthermore, Figure 2 The solder 2b and 9a are shown before reflow soldering (heat treatment). Four pin terminals 52 are bonded to the source electrode 31, but the number of pin terminals 52 bonded to the semiconductor chip 3a can be three or less, or five or more.

[0062] like Figure 2 As shown, the lower end of pin terminal 53 is bonded to the gate electrode 32 of semiconductor chip 3a via solder 9c. The drain electrode (not shown) on the lower surface side of semiconductor chip 3a is bonded to... Figure 1The upper conductor layer 12a shown is bonded. Solder 9a, 9b, and 9c are bonding materials. For example, tin-antimony (SnSb) based or tin-silver (SnAg) based solders can be used. Furthermore, the structures of semiconductor chips 3b, 3c, and 3d are the same as those of semiconductor chip 3a, and the structures of the pin terminals 50 connected to semiconductor chips 3b, 3c, and 3d are also the same as those of semiconductor chip 3a, therefore, descriptions are omitted. Pin terminals 50 may also include pin terminals other than pin terminals 51 to 53. For example, pin terminals 50 may also include positioning pin terminals (not shown) for fixing the relative positional relationship between the insulating circuit board 1 and the printed circuit board 6.

[0063] <External terminal>

[0064] like Figure 1 As shown, the external terminal 4 is separate from and not connected to the printed circuit board 6. The lead terminal 50 is fixed within the through-hole 6x of the printed circuit board 6, while the external terminal 4 is not fixed to the printed circuit board 6. The external terminal 4 has a joint portion 41, a connecting portion 42, and an intermediate portion 43. The joint portion 41 is the portion that is joined to the upper conductor layer 12b via solder 2b, the connecting portion 42 is the portion that connects to an external circuit, and the intermediate portion 43 is the portion that connects the joint portion 41 and the connecting portion 42. The joint portion 41 extends in a direction parallel to the upper conductor layer 12b, and its lower surface is joined to the upper conductor layer 12b via solder 2b. A boss 41a protruding (formed as a convex shape) towards the upper conductor layer 12b is provided in the joint portion 41. During reflow soldering, the external terminal 4 is held in place by a clamp while being pressed towards the upper conductor layer 12b. At this time, the boss 41a approaches the upper conductor layer 12b. Even when pressed, the portion of the joint 41 without the boss 41a cannot approach the upper conductor layer 12b to the extent that the boss 41a is present. Thus, by providing the boss 41a, it is possible to prevent the gap between the portion of the joint 41 without the boss 41a and the upper conductor layer 12b from becoming too small. Consequently, it is possible to prevent the amount of solder 2b between the joint 41 and the upper conductor layer 12b from becoming too small. The thickness of the solder 2b in the portion of the joint 41 without the boss 41a is, for example, approximately 50 μm or more and 500 μm or less.

[0065] The connecting portion 42 is located above the joining portion 41. The connecting portion 42 extends in a direction parallel to the joining portion 41, and at least a portion of it is exposed on the outside of the sealing member 8. The portion of the connecting portion 42 exposed on the outside of the sealing member 8 connects to an external circuit. The intermediate portion 43 extends in a direction perpendicular to the upper conductor layer 12b, with one end connected to the joining portion 41 and the other end connected to the connecting portion 42. Alternatively, the joining portion 41 and the connecting portion 42 may be integrally formed continuously. The external terminal connection structure (4, 51, 12b) is constituted by the external terminal 4, the pin terminal 51, and the upper conductor layer 12b.

[0066] For example, in the case of a three-terminal inverter according to the first embodiment, the external terminal 4 can be any terminal among the anode-side (P-side), cathode-side (N-side), and output terminals. Alternatively, for example, the aforementioned external terminal connection structure (4, 51, 12b) can be provided for each or a portion of the terminals among the anode-side (P-side), cathode-side (N-side), and output terminals. In the case of a four-terminal inverter according to the first embodiment, the aforementioned external terminal connection structure (4, 51, 12b) can also be provided for the M terminal. Furthermore, conductive materials such as copper (Cu) can be used as the material for the external terminal 4.

[0067] <First joint region and second joint region>

[0068] like Figure 2 As shown, the upper conductor layer 12b is disposed close to the first side 11a, which is one side of the insulating substrate 11 when viewed from above. "Close" means that no other upper conductor layer is disposed between the upper conductor layer 12b and the first side 11a. The upper surface of the insulating substrate 11 is exposed around the upper conductor layer 12b and between the upper conductor layer 12b and the first side 11a. The upper conductor layer 12a is disposed on the upper surface of the insulating substrate 11 on the side opposite to the first side 11a, sandwiching the upper conductor layer 12b between them. The upper conductor layer 12a is spaced apart from the upper conductor layer 12b. Figure 3This is a magnified top view of the upper conductor layer 12b. The joint portion 41 (not shown) of the external terminal 4 is joined to a region, namely the first joint region 14, of the upper surface of the upper conductor layer 12b via solder 2b. The lower end of the lead terminal 51 (not shown) is joined to another region, namely the second joint region 15, of the upper surface of the upper conductor layer 12b via solder 9a. When the side of the upper conductor layer 12b closest to the first side 11a is designated as the second side 12b1, and the side opposite to the second side 12b1 is designated as the third side 12b2, the first joint region 14 is the region closest to the second side 12b1, and the second joint region 15 is the region closest to the third side 12b2.

[0069] The first mating region 14 and the second mating region 15 are areas envisioned for connecting the external terminal 4 and the pin terminal 51. Figure 3 In the diagram, the first bonding area 14 and the second bonding area 15 are represented as rectangular areas using dashed lines, but the shapes of the first bonding area 14 and the second bonding area 15 are not limited to this. The first bonding area 14 and the second bonding area 15 are the areas where solder 2b and 9a are disposed. Figure 3 The solder 2b and 9a are shown before reflow soldering. Solder 2b and 9a can also be wetted and extended to the outside of the first bonding region 14 and the second bonding region 15 through reflow soldering. Alternatively, multiple solder 9a disposed at each pin terminal 51 can be wetted and extended to connect with each other through reflow soldering.

[0070] <Solder Resistance Section>

[0071] like Figure 3 As shown, a solder resist portion 7 is provided on the upper surface of the upper conductor layer 12b. More specifically, the solder resist portion 7 is provided on the upper surface of the upper conductor layer 12b at a position adjacent to (close to) the first bonding region 14. In this embodiment, the solder resist portion 7 is provided between the first bonding region 14 and the second bonding region 15. Figure 2As shown, the solder mask 7 extends along the X direction. The dimension of the solder mask 7 along the X direction (length of the long side) can be greater than or equal to the width occupied by the joint portion 41 of the external terminal 4 along the X direction, or greater than or equal to the width occupied by the lower end of the pin terminal 51 along the X direction. Alternatively, for example, the dimension of the solder mask 7 along the long side can be greater than or equal to the greater of the width occupied by the joint portion 41 of the external terminal 4 along the X direction and the width occupied by the lower ends of the plurality of pin terminals 51 along the X direction. Furthermore, in the case of a plurality of pin terminals 51, the width occupied by the lower end of the pin terminal 51 along the X direction is equal to the width occupied by the plurality of pin terminals 51 along the X direction. The dimension of the solder mask 7 along the Y direction (short side) can also be determined based on the spacing between the joint portion 41 of the external terminal 4 and the pin terminal 51. That is, the dimension of the solder mask 7 along the short side can also be determined based on the spacing between the first bonding area 14 and the second bonding area 15. To save space, it is desirable that the spacing between the joint portion 41 of the external terminal 4 and the pin terminal 51 be as small as possible. The dimension of the short side of the solder resist 7 is set to be approximately 0.1 mm or more and 1 mm or less. By providing the solder resist 7, the solder 2b and solder 9a that melt during reflow soldering are less likely to stick together.

[0072] <Manufacturing Method of Solder Resist Parts>

[0073] The manufacturing method of the solder mask part 7 will be described below. For example... Figure 1 As shown, the solder resist 7 is a laser-applied solder resist formed by irradiating the upper surface of the upper conductor layer 12b with a laser. Below, two examples are shown regarding the laser wavelength, output, frequency, and scanning conditions. For example, the solder resist 7 is constructed by arranging multiple lines formed by laser irradiation along its long side.

[0074] Condition example 1

[0075] Wavelength: 1064 nm

[0076] Output: 5 (W)

[0077] Frequency: 5 (kHz)

[0078] Scanning speed: 8 (mm / s)

[0079] Line spacing: 100 (μm)

[0080] Condition example 2

[0081] Wavelength: 532 nm

[0082] Output: 4.8 (W)

[0083] Frequency: 30 (kHz)

[0084] Scanning speed: 300 (mm / s)

[0085] Line spacing: 10 (μm)

[0086] When a laser is irradiated onto the upper surface of the upper conductor layer 12b, an uneven surface is formed on the upper surface of the upper conductor layer 12b, reducing the wettability of the solder. Additionally, an oxide film is formed on the upper surface of the upper conductor layer 12b, further reducing the wettability of the solder.

[0087] <Comparative Example>

[0088] Below, on Figure 4 The comparative example shown will be used for illustration. In the semiconductor device involved in the comparative example, no solder resist 7 is formed on the upper surface of the upper conductor layer 12b. If the solder resist 7 is not provided, the solder 2b and solder 9a, which are melted by reflow soldering, may wet and spread together. If the molten solder 2b and solder 9a are connected, the solder may be attracted from one side of the external terminal 4 to the other side of the lead terminal 51. For example, the solder may be attracted from the external terminal 4 side and move to the lead terminal 51 side. Moreover, if the solder is attracted and moves, the solder may be biased between the external terminal 4 side and the lead terminal 51 side. In addition, the solder 2b and 9a may become thinner as a whole due to the wetting and spreading of the solder 2b and 9a. If the solder 2b and 9a become thinner, the reliability of the solder joint and the bonding strength between the external terminal 4 and the lead terminal 51 and the upper conductor layer 12b may be reduced.

[0089] Furthermore, if wire bonding is used for electrical connections, it offers greater freedom of movement and can more effectively suppress the influence of solder flow. On the other hand, wire bonding requires a certain amount of wiring space.

[0090] In view of this, the semiconductor device according to the first embodiment of the present technology, such as Figure 3 As shown, a solder resist portion 7 is provided on the upper surface of the upper conductor layer 12b and adjacent to the first bonding region 14. Since the solder resist portion 7 has lower wettability compared to the other upper surfaces of the upper conductor layer 12b, it hinders the excessive wetting and expansion of the solders 2b and 9a, making them less likely to connect to each other (less prone to bridging). Therefore, it is possible to prevent the solder film thickness of 2b and 9a from becoming too thin, stabilize the filler shape of the solders 2b and 9a, and suppress the decrease in the yield of the semiconductor device.

[0091] Furthermore, according to the first embodiment of this technology, such as... Figure 3As shown, the solder resist 7 is disposed between the first bonding region 14 and the second bonding region 15. The solders 2b and 9a do not easily move across the solder resist 7 and do not easily connect with each other. As a result, it is possible to prevent the film thickness of the solders 2b and 9a from becoming too thin, and the filler shape of the solders 2b and 9a is stable, thereby preventing the yield of semiconductor devices from decreasing.

[0092] Furthermore, the semiconductor device according to the first embodiment of this technology includes: a printed circuit board 6 disposed above the semiconductor chip 3; and a lead terminal 51 inserted into the printed circuit board 6 and bonded to another region, namely a second bonding region 15, on the upper surface of the upper conductor layer 12b via solder 9a. Therefore, wiring can be constructed with high density compared to the case where electrical connections are made using wire bonding.

[0093] Furthermore, in the semiconductor device according to the first embodiment of this technology, the solder resist 7 is a laser solder resist, so the process of forming the solder resist 7 can be easily performed.

[0094] <First Variation of the First Embodiment>

[0095] The semiconductor device involved in the first variation of the first embodiment and Figure 1 The difference between the semiconductor device involved in the first embodiment shown is that, as Figure 5 As shown, the solder mask 7 is disposed between the first bonding region 14 and the second bonding region 15, and between the first bonding region 14 and the second side 12b1. The other structures of the semiconductor device according to the first variation of the first embodiment are the same as those according to the semiconductor device according to the first embodiment, therefore repeated descriptions are omitted.

[0096] like Figure 1 As shown, the external terminal 4, which connects to the external circuit, needs to be positioned at the end (first side 11a) closest to the insulating circuit substrate 1 (insulating substrate 11) when viewed from above. Additionally, the lower conductor layer 13 overlaps the entire lower surface of the insulating substrate 11. The area of ​​the lower conductor layer 13 when viewed from above is the same as that of the insulating substrate 11, and it is configured to cover the entire lower surface of the insulating substrate 11. The end 13a of the lower conductor layer 13 overlaps with the first side 11a of the insulating substrate 11 when viewed from above. The upper conductor layer 12b is not positioned to the first side 11a, as shown... Figure 2 As shown, the upper surface of the insulating substrate 11 is exposed between the first side 11a and the second side 12b1. By exposing the upper surface of the insulating substrate 11 between the first side 11a and the second side 12b1, the distance between the lower conductor layer 13 and the upper conductor layer 12b is increased, thus ensuring insulation.

[0097] During reflow soldering, the molten solder 2b may wet and spread onto the insulating substrate 11 exposed between the first side 11a and the second side 12b1. If the solder 2b wets and spreads onto the insulating substrate 11, the distance used to ensure the insulation between the lower conductor layer 13 and the upper conductor layer 12b becomes smaller.

[0098] In response to this, the semiconductor device according to the first embodiment of the present invention, a solder resist 7 is provided between the first bonding region 14 and the second side 12b1, thereby suppressing the wetting and propagation of solder 2b onto the insulating substrate 11 and suppressing the reduction of insulation between the lower conductor layer 13 and the upper conductor layer 12b. Furthermore, even the semiconductor device according to the first embodiment of the first modification has the same effects as the semiconductor device according to the first embodiment.

[0099] <Second variation of the first embodiment>

[0100] The semiconductor device involved in the second variation of the first embodiment and Figure 5 The difference between the semiconductor device involved in the first embodiment variation 1 shown is that, as Figure 6 As shown, the solder mask 7 is only provided between the first bonding region 14 and the second side 12b1. The other structures of the semiconductor device involved in the second modification of the first embodiment are the same as those of the semiconductor device involved in the first modification of the first embodiment, so repeated descriptions are omitted.

[0101] (Other implementation methods)

[0102] As described above, the present invention has been explained through first embodiments and variations thereof, but it should not be construed that the discussions and drawings, which constitute a part of this disclosure, are intended to limit the invention. Based on this disclosure, those skilled in the art will be able to identify various alternative embodiments, examples, and techniques employed.

[0103] For example, the structures disclosed in the first embodiment and its variations can be appropriately combined within a range that does not produce contradictions.

[0104] As such, it is self-evident that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the inventive features addressed in the claims, which are appropriate according to the foregoing description.

[0105] Explanation of reference numerals in the attached figures

[0106] 3, 3a, 3b, 3c, 3d: Semiconductor chip; 6: Printed circuit board; 7: Solder resist; 1: Insulating circuit board; 11: Insulating board; 11a: First side; 12a: Upper conductor layer (first conductor layer); 12b: Upper conductor layer (second conductor layer); 12b1: Second side; 12b2: Third side; 13: Lower conductor layer; 13a: End; 14: First bonding area; 15: Second bonding area; 4: External terminal; 41: Bond; 41a: Boss; 50, 52, 53: Pin terminal; 51: Pin terminal (first pin terminal).

Claims

1. A semiconductor device comprising: An insulating circuit board has an insulating substrate and a first conductor layer and a second conductor layer disposed separately from each other on the upper surface of the insulating substrate. A semiconductor chip, which is mounted on the first conductor layer via solder; An external terminal having a bonding portion, and the bonding portion being bonded to a region, namely a first bonding region, on the upper surface of the second conductor layer via solder; A printed circuit board disposed above the semiconductor chip; The first pin terminal is inserted into the printed circuit board and is bonded to another area, namely the second bonding area, on the upper surface of the second conductor layer via solder. as well as A solder resist portion is disposed on the upper surface side of the second conductor layer and adjacent to the first bonding area.

2. The semiconductor device according to claim 1, wherein, The second conductor layer is disposed close to the first edge, which is one side of the insulating substrate. When the edge of the second conductor layer that is closer to the first edge is designated as the second edge, and the edge that is opposite to the second edge is designated as the third edge, the first bonding region is the region that is closer to the second edge, and the second bonding region is the region that is closer to the third edge.

3. The semiconductor device according to claim 1 or 2, wherein, The solder resist portion is disposed between the first bonding area and the second bonding area.

4. The semiconductor device according to claim 2, wherein, The solder resist portion is disposed between the first bonding area and the second side.

5. The semiconductor device according to claim 1 or 2, wherein, The external terminals are separated from the printed circuit board.

6. The semiconductor device according to claim 1 or 2, wherein, A boss protruding toward the second conductor layer is provided at the joint.

7. The semiconductor device according to claim 6, wherein, The thickness of the solder between the joint and the second conductor layer is 50 μm or more and 500 μm or less in the portion of the joint where the boss is not provided.

8. The semiconductor device according to claim 1 or 2, wherein, The insulating substrate comprises a resin material.

9. The semiconductor device according to claim 1 or 2, wherein, Copper is exposed on the surfaces of the first conductor layer and the second conductor layer.

10. The semiconductor device according to claim 1 or 2, wherein, The solder resist portion is a laser solder resist portion formed by irradiating the upper surface of the second conductor layer with a laser.

Images