Semiconductor device
By setting a solder resist on the insulating circuit board, the problem of excessive wetting and expansion of solder during reflow soldering is solved, improving the reliability of the bonding and the yield of semiconductor devices, and enabling high-density wiring.
CN121866904APending Publication Date: 2026-04-14FUJI ELECTRIC CO LTD
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Patent Information
- Application Number
- CN202580004589.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-15
- Filing Date
- 2025-01-27
- Publication Date
- 2026-04-14
AI Technical Summary
Technical Problem
When using pin terminals for wiring, the solder is prone to over-wetting and spreading during reflow soldering, which reduces the reliability of the connection.
Method used
The circuit employs an insulating circuit board with first and second conductor layers. Semiconductor chips and external terminals are bonded to the first conductor layer by solder, and pin terminals are bonded to the second conductor layer. Solder resist is provided on the second conductor layer to prevent excessive wetting and spread of solder.
Benefits of technology
It effectively suppresses excessive solder wetting and propagation, improving the reliability of the joint and the yield of semiconductor devices, while allowing high-density wiring.
✦ Generated by Eureka AI based on patent content.
Abstract
Provided is a semiconductor device in which solder spreading due to excessive wetting is suppressed. A semiconductor device is provided with: an insulating circuit board (1) having an insulating substrate (11), and an upper conductor layer (12a) and an upper conductor layer (12b) provided on the upper surface of the insulating substrate (11) so as to be separated from each other; a semiconductor chip (3) mounted on the upper conductor layer (12a) via solder; an external terminal (4) having a bonding portion (41) bonded to a first bonding region (14), which is one region of the upper surface of the upper conductor layer (12b), via solder (2b); a printed circuit board (6) disposed above the semiconductor chip (3); a pin terminal (51) that is inserted into the printed circuit board (6), and that is bonded to a second bonding region (15), which is the other region of the upper surface of the upper conductor layer (12b), via solder (9a); and a solder resist part (7) provided on the upper surface side of the upper conductor layer (12b) and adjacent to the first bonding region (14).
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