Channel deviation calibration device and method based on high-precision time synchronization protocol

Abstract

The invention belongs to the field of integrated circuit test calibration, and particularly discloses a channel deviation calibration device and method based on a high-precision time synchronization protocol. Through the cooperation of the clock synchronization module, the signal generation module and the processing module, the test error caused by the lack of calibration means of the digital channel in a comparator mode is solved. Firstly, the clock synchronization module is connected with all the components and achieves time synchronization of the whole system based on a time protocol, a unified reference is provided for subsequent calibration, and errors caused by time inconsistency are eliminated. On the basis, the signal generation module outputs a synchronous test signal, and the signal processing module collects the signal and determines a first time difference of inputting the signal into different channels, namely an ideal transmission deviation; meanwhile, the system obtains a second time difference of actual response of the channel comparator; the time sequence deviation of the channel comparator can be directly deduced by comparing the time differences obtained under the two synchronization conditions, so that the accurate calibration of the time sequence error in the comparator mode is realized.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit testing and calibration, and more specifically, relates to a channel deviation calibration device and method based on a high-precision time synchronization protocol. Background Technology

[0002] Current integrated circuit testing and metrology standards (such as JJG(Electronics) 310008-2006) primarily focus on timing deviations in digital channel drivers for channel offset calibration. This emphasis stems from the early testing needs focused on functional verification and driving signals, as well as the relatively direct technical approach of calibrating driver outputs. However, these standards generally lack calibration requirements for timing deviations in digital channel comparators. This results in uncalibrated system errors in the critical stages of signal reception and timing decision-making in the test system, making it impossible to guarantee the accuracy of precise measurements of high-speed signals such as setup time and hold time, thus constituting a significant blind spot in the calibration system.

[0003] This limitation is no longer adequate for the high timing accuracy testing requirements of modern integrated circuits, especially high-speed interfaces and SoC chips. Independent deviations in comparator channels directly affect the accuracy of high-speed signal sampling and decision-making. Therefore, comprehensive "channel alignment" calibration of test systems has become an essential part of high-end testing in industry practice, highlighting a significant gap between general metrology standards and cutting-edge practical needs. Promoting standard updates to include comparator channel deviations in mandatory calibration items is a key technological foundation for achieving comprehensive, high-precision metrology of test systems and supporting industrial development. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this application is to provide a channel deviation calibration device and method based on a high-precision time synchronization protocol, aiming to solve the problem of test error caused by the current lack of deviation calibration methods for digital channels of test systems in comparator mode.

[0005] To achieve the above objectives, in a first aspect, this application provides a channel deviation calibration device based on a high-precision time synchronization protocol, comprising: a clock synchronization module, a signal generation module, and a signal processing module; the three output terminals of the clock synchronization module are respectively connected to the input terminal of the signal generation module, and the first input terminal of the signal processing module is connected to the first input terminal of the test system to be calibrated; the output terminal of the signal processing module is connected to multiple channels of the test system to be calibrated; the second input terminal of the signal processing module is connected to multiple channels of the test system to be calibrated; the clock synchronization module is configured to synchronize the test system to be calibrated, the signal generation module, and the signal processing module in time based on the time synchronization protocol; the signal generation module is configured to output a test signal to the test system to be calibrated under time synchronization conditions; the signal processing module is configured to synchronously acquire the test signal generated by the signal generation module and sent to the test system to be calibrated under time synchronization conditions, and determine the first input time difference of the test signal; the clock synchronization module is further configured to acquire the second response time difference of the multiple channel comparators in the test system to respond to the test signal; the signal processing module is further configured to calculate the timing deviation of the channel comparators based on the first input time difference and the second response time difference.

[0006] In one embodiment, the clock synchronization module includes: a master clock unit, a slave clock unit, and a clock reference unit; the first output terminal of the master clock unit is communicatively connected to the first input terminal of the test system to be calibrated; the second output terminal of the master clock unit is connected to the input terminal of the slave clock unit; the output terminal of the slave clock unit is also communicatively connected to the input terminal of the clock reference unit; the first and second output terminals of the clock reference unit are respectively connected to the input terminal of the signal generation module and the first output terminal of the signal processing module; the master clock unit is used to provide a master clock signal to the test system to be calibrated and the slave clock unit; the slave clock unit is used to achieve master-slave time synchronization with the slave clock unit based on the master clock signal, and output a clock synchronization signal to the clock reference unit; the clock reference unit is configured to generate and output a coordinated clock signal to the signal generation module and the signal processing module based on the clock synchronization signal, so as to control the output time and acquisition time of the test signal; the master clock unit is further configured to acquire the second response time difference of the response signals of multiple channel comparators in the test system to be calibrated.

[0007] In one embodiment, the signal generation module includes: a pattern generator; the clock input of the pattern generator is connected to the first output of the clock reference unit to receive a coordinated clock signal; the signal output of the pattern generator is connected to the test system to be calibrated; the pattern generator is configured to generate and output a test signal with a known timing relationship at a preset time based on the coordinated clock signal.

[0008] In one embodiment, the signal generation module further includes: a counter subtractor; the output terminal of the counter subtractor is connected to the control terminal of the code pattern generator; the counter subtractor is configured to perform subtraction counting from a preset initial value after outputting the test signal, so as to control the output timing of the test signal.

[0009] In one embodiment, the signal processing module includes an oscilloscope and a host computer; the clock input of the oscilloscope is connected to the second output of the clock reference unit to receive a coordinated clock signal; the signal input of the oscilloscope is connected to the test system to be calibrated for acquiring test signals; the oscilloscope is configured to synchronously acquire test signals under the control of the coordinated clock signal and send the acquired data to the host computer; the host computer is configured to determine a first input time difference based on the acquired data and obtain a second response time difference from the clock synchronization module to calculate the timing deviation.

[0010] In one embodiment, the communication connection between the signal generation module, the signal processing module, and the test system to be calibrated is achieved through a connection module. The connection module includes a signal input terminal, a first signal output terminal, and a second signal output terminal. The signal input terminal is connected to the signal generation module and is used to receive test signals. The first signal output terminal is connected to the test system to be calibrated and is used to output test signals. The second signal output terminal is connected to the signal processing module and is used to output test signals. The connection module is configured to synchronously distribute the test signals from the signal generation module to the test system to be calibrated and the signal processing module.

[0011] In one embodiment, the connection module includes: a calibration interface board; the channel of the test system to be calibrated is connected to the calibration interface board via spring pins; a signal generation module and a signal processing module are connected to the calibration interface board via an SMA interface.

[0012] Secondly, this application provides a channel deviation calibration method, comprising: synchronizing the test system to be calibrated, the signal generation module, and the signal processing module based on a time synchronization protocol; under time synchronization conditions, controlling the signal generation module to output a test signal with a known timing relationship to the test system to be calibrated; under time synchronization conditions, controlling the signal processing module to synchronously acquire test signals from multiple channels and determine a first input time difference of the test signals; then acquiring a second response time difference between the multiple channel comparators in the test system to respond to the test signals; and calculating the timing deviation of the channel comparators based on the first input time difference and the second response time difference.

[0013] In one embodiment, time synchronization of the test system to be calibrated, the signal generation module, and the signal processing module is performed based on a time synchronization protocol. This includes: sending a first message to the slave clock via the master clock and recording the first transmission time; then recording the first reception time of the slave clock receiving the first message; sending the first transmission time to the slave clock at the next moment after the master clock sends the first message; sending a second message to the master clock via the slave clock and recording the second transmission time; then recording the second reception time of the master clock receiving the second message; sending the second reception time to the slave clock at the next moment after the master clock receives the second message; and obtaining the clock deviation of the slave clock relative to the master clock based on the first transmission time, the first reception time, the second transmission time, and the second reception time to achieve master-slave synchronization, thereby synchronizing the time of the test system to be calibrated under the master clock and the signal generation module and the signal processing module under the slave clock control clock reference unit.

[0014] In one embodiment, the timing deviation of the channel comparator is calculated based on the first input time difference and the second response time difference. The method further includes: converting the calculated timing deviation of each channel comparator into a channel delay compensation value; and writing or configuring the channel delay compensation value to the test system to be calibrated, so that the test system to be calibrated can perform time compensation on the input signal or output response of each channel according to the compensation value in subsequent work, thereby calibrating the timing deviation.

[0015] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: The technical solution proposed in this application solves the test error problem caused by the lack of deviation calibration means for the digital channel of the test system in comparator mode by adopting a collaborative design of clock synchronization module, signal generation module and signal processing module.

[0016] Specifically, the clock synchronization module establishes communication connections with the signal generation module, signal processing module, and the test system under calibration, providing a basis for coordinated operation of each component. The signal generation module and signal processing module are connected to multiple channels of the test system under calibration, ensuring a smooth path for signal acquisition and response. Based on this, the clock synchronization module achieves system-wide time synchronization using a time synchronization protocol, eliminating errors introduced by inconsistent time bases. This allows the signal generation module to output test signals under precise synchronization conditions, avoiding uncertainties in transmission time.

[0017] The signal processing module acquires test signals and determines the first input time difference under synchronized conditions, reflecting the ideal time deviation of signal transmission to different channels. Simultaneously, the clock synchronization module obtains the second response time difference of the channel comparators in the test system to be calibrated in response to the test signals. Due to synchronization guarantees, this response time difference accurately characterizes the actual timing characteristics. Finally, the signal processing module calculates the timing deviation based on the first input time difference and the second response time difference. By comparing the time difference between the ideal input and the actual response, the timing deviation of the channel comparator itself is directly derived, thereby achieving accurate calibration of the digital channels in comparator mode. Compared with existing technologies, this effectively reduces test errors and improves the reliability of the test system. Attached Figure Description

[0018] Figure 1 This is one of the structural block diagrams of the channel deviation calibration device based on a high-precision time synchronization protocol provided in the embodiments of this application; Figure 2 This is the second structural block diagram of the channel deviation calibration device based on a high-precision time synchronization protocol provided in the embodiments of this application; Figure 3 This is a schematic diagram illustrating the configuration of the clock synchronization module, signal generation module, and signal processing module provided in the embodiments of this application; Figure 4 This is a schematic diagram of clock synchronization provided in an embodiment of this application; Figure 5 This is a schematic diagram of deviation acquisition provided in an embodiment of this application; Figure 6 This is a diagram showing the relationship between clock synchronization and offset acquisition provided in an embodiment of this application; Figure 7 This is a schematic flowchart of the channel deviation calibration method provided in the embodiments of this application.

[0019] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 10 is the clock synchronization module; 20 is the signal generation module; 30 is the signal processing module. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] In this article, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists alone, A and B exist simultaneously, and B exists alone. The symbol " / " in this article indicates that the related objects are in an "or" relationship; for example, A / B means A or B.

[0022] The terms "first" and "second," etc., used in the specification and claims herein are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0025] Currently, in automated test equipment or high-performance digital test systems, digital channels are used to drive or compare signals. The timing accuracy of these channels is a key factor affecting the reliability of test results. Current calibration of digital channels primarily focuses on timing deviations in driver mode, i.e., calibrating the timing accuracy of the channel's output signal. However, when a digital channel operates in comparator mode, its function is to receive external signals and compare them with preset voltage thresholds to determine the signal's logic state. The response time of this process also has inherent deviations. Due to the lack of specific calibration methods for channel timing deviations in comparator mode, these deviations directly introduce test errors, affecting the measurement accuracy of the test system.

[0026] In this embodiment, the channel deviation calibration device based on the high-precision time synchronization protocol includes: a clock synchronization module 10, a signal generation module 20, and a signal processing module 30.

[0027] It should be noted that the three output terminals of the clock synchronization module 10 are respectively connected to the input terminal of the signal generation module 20, the first input terminal of the signal processing module 30 and the first input terminal of the test system to be calibrated; the output terminal of the signal processing module 30 is connected to multiple channels of the test system to be calibrated; and the second input terminal of the signal processing module 30 is connected to multiple channels of the test system to be calibrated.

[0028] Understandably, the connections between the modules form the basic pathway for calibration: one output of the clock synchronization module 10 is connected to the input of the signal generation module 20 to distribute a synchronization clock or timestamp to the signal generation module 20; its second output is connected to the first input of the signal processing module 30 to synchronize the acquisition timing of the signal processing module 30; and its third output is connected to the first input of the test system to be calibrated to synchronize the clock inside the test system with the entire calibration device. The output of the signal processing module 30 is connected to the inputs of multiple digital channels to be calibrated in the test system to send test signals to these channels; simultaneously, the second input of the signal processing module 30 is also connected to the outputs of these digital channels to acquire the input signals of the channel comparators.

[0029] It is understandable that the clock synchronization module 10, signal generation module 20, signal processing module 30, and the interface of the test system to be calibrated can be integrated into the same chip or used as different IP cores on the same chip. Therefore, a communication connection is established, specifically through the metal interconnect layers manufactured on the chip, such as the physical path formed by aluminum or copper traces.

[0030] It should be noted that the clock synchronization module 10 is configured to synchronize the test system to be calibrated, the signal generation module 20, and the signal processing module 30 based on a time synchronization protocol.

[0031] Understandably, the clock synchronization module 10 is responsible for establishing a globally unified time reference. It is configured to operate based on a time synchronization protocol, such as the IEEE 1588 Precision Time Protocol (PTP) or a similar technology. This module adjusts the timestamp counters within the signal generation module 20, signal processing module 30, and the test system to a highly synchronized state by sending synchronization messages, performing delay measurements, and implementing compensation mechanisms. This ensures that all devices perceive the same moment consistently. This is a prerequisite for the comparability of all subsequent time interval measurements.

[0032] It should be noted that the signal generation module 20 is configured to output a test signal to the test system to be calibrated under time synchronization conditions; the signal processing module 30 is configured to synchronously acquire the test signal generated by the signal generation module 20 and sent to the test system to be calibrated under time synchronization conditions, and determine the first input time difference of the test signal.

[0033] Understandably, the signal generation module 20 operates under time synchronization conditions. Specifically, it can be implemented as a high-precision arbitrary waveform generator or a pulse signal generator. This module is configured to generate a known test signal upon receiving a synchronization trigger or according to a synchronization clock, and output it to multiple digital channels of the test system to be calibrated. Due to time synchronization, the start time of signal generation is determined.

[0034] Understandably, the signal processing module 30 possesses high-precision synchronous acquisition capabilities, which can be specifically implemented as a dedicated circuit for a multi-channel high-speed digitizer or an integrated high-speed ADC. Under time synchronization conditions, it performs two key operations: First, it synchronously acquires the test signals generated by the signal generation module 20 and sent to the multiple channel input terminals of the test system under calibration through its multiple acquisition channels. By analyzing the waveforms of these synchronously acquired signals, the first input time difference of the same test signal arriving at different channel input connection points can be accurately determined. This time difference mainly reflects the fixed delay difference introduced by the differences in the length and impedance of the transmission path from the signal distribution point to each channel input terminal.

[0035] It should be noted that the clock synchronization module 10 is also configured to acquire the second response time difference of multiple channel comparators in the test system to be calibrated in response to the test signal; the signal processing module 30 is also configured to calculate the timing deviation of the channel comparators based on the first input time difference and the second response time difference.

[0036] Understandably, the function of obtaining the second response time difference of multiple channel comparators in the test system to be calibrated in response to the test signal can be completed by the clock synchronization module 10 or the signal processing module 30 in collaboration with the test system. One implementation is as follows: when the comparator output of its digital channel changes, the test system to be calibrated records a precise time stamp based on the synchronization clock and feeds these time stamps back to the clock synchronization module 10 or the signal processing module 30, thereby calculating the second response time difference between the actual responses of each comparator. This time difference includes the combined effects of the first input time difference, the different signal arrival times, and the timing deviations of each comparator itself. Finally, the signal processing module 30, or the host computer processing unit connected to it, is configured to perform the calculation. It subtracts the known first input time difference from the second response time difference to eliminate the influence of transmission path differences, thereby separating and calculating the pure timing deviation of each channel comparator. This deviation value can be used for software compensation in subsequent tests or to guide hardware adjustments, thereby achieving calibration.

[0037] Understandably, in practical implementation, the time synchronization protocol is not limited to PTP; synchronous Ethernet, White Rabbit protocol, or GPS / BeiDou time synchronization can also be used. The signal generation module 20 is not limited to a standalone AWG; it can also be a dedicated signal source chip integrated within the digital tester. The acquisition and calculation functions of the signal processing module 30 can be separated; for example, data acquisition can be performed by a high-speed acquisition card, while time difference calculation can be performed by computer software. The communication connection method can be selected from direct cable connection, switch network, dedicated backplane bus, etc., depending on accuracy and distance requirements.

[0038] In this embodiment, by employing a collaborative design of a clock synchronization module, a signal generation module, and a signal processing module, the problem of test error caused by the lack of deviation calibration methods for the digital channel of the test system in comparator mode is solved.

[0039] Specifically, the clock synchronization module establishes communication connections with the signal generation module, signal processing module, and the test system under calibration, providing a basis for coordinated operation of each component. The signal generation module and signal processing module are connected to multiple channels of the test system under calibration, ensuring a smooth path for signal acquisition and response. Based on this, the clock synchronization module achieves system-wide time synchronization using a time synchronization protocol, eliminating errors introduced by inconsistent time bases. This allows the signal generation module to output test signals under precise synchronization conditions, avoiding uncertainties in transmission time.

[0040] The signal processing module acquires test signals and determines the first input time difference under synchronized conditions, reflecting the ideal time deviation of signal transmission to different channels. Simultaneously, the clock synchronization module obtains the second response time difference of the channel comparators in the test system to be calibrated in response to the test signals. Due to synchronization guarantees, this response time difference accurately characterizes the actual timing characteristics. Finally, the signal processing module calculates the timing deviation based on the first input time difference and the second response time difference. By comparing the time difference between the ideal input and the actual response, the timing deviation of the channel comparator itself is directly derived, thereby achieving accurate calibration of the digital channels in comparator mode. Compared with existing technologies, this effectively reduces test errors and improves the reliability of the test system.

[0041] Furthermore, this application proposes improved embodiments. Please refer to... Figure 2 , Figure 2 This is the second structural block diagram of the channel deviation calibration device based on a high-precision time synchronization protocol provided in the embodiments of this application.

[0042] In this embodiment, the communication connection between the signal generation module 20, the signal processing module 30, and the test system to be calibrated is achieved through a connection module. The connection module includes a signal input terminal, a first signal output terminal, and a second signal output terminal. The signal input terminal is connected to the signal generation module 20 and is used to receive test signals. The first signal output terminal is connected to the test system to be calibrated and is used to output test signals. The second signal output terminal is connected to the signal processing module 30 and is used to output test signals. The connection module is configured to synchronously distribute the test signals from the signal generation module 20 to the test system to be calibrated and the signal processing module 30.

[0043] As can be understood, a connection module refers to a dedicated hardware interface unit designed to synchronously and with low deviation distribute a single input signal to multiple destinations. Its core design principle is to ensure signal integrity and minimize physical and timing differences between output paths. Synchronous distribution refers to the connection module replicating and transmitting the received single-channel test signal to two or more output terminals with minimal delay, through its internal physical structure.

[0044] In one embodiment, the connection module includes: a calibration interface board; the channel of the test system to be calibrated is connected to the calibration interface board via spring pins; and the signal generation module 20 and the signal processing module 30 are connected to the calibration interface board via an SMA interface.

[0045] Understandably, the calibration interface board is a standalone printed circuit board designed to establish a reliable, repeatable electrical connection between the test system and the signal generation and processing modules. The digital channel inputs of the test system are typically located in a high-density array, such as test sockets or connectors. The calibration interface board connects to these inputs via spring-loaded pins. These spring-loaded pins are precision probes with springs that compensate for flatness errors, ensuring uniform pressure and stable contact resistance at each channel contact. Furthermore, high-quality spring-loaded pins support GHz-level signal transmission, meeting the demands of high-speed digital testing, and facilitating easy insertion and replacement between the test system, interface board, and maintenance calibration equipment.

[0046] Understandably, the connection to the signal generation / processing module is via an SMA interface to the calibration interface board. SMA is a threaded coaxial connector that provides excellent electromagnetic shielding, prevents external interference, has a standard characteristic impedance of 50 ohms, and is compatible with common test instruments and high-speed transmission lines, reducing signal reflection. Simultaneously, the threaded locking mechanism ensures a reliable connection and prevents dislodgement due to vibration.

[0047] For further details, please refer to Figure 3 , Figure 3 This is a schematic diagram showing the setup of the clock synchronization module, signal generation module, and signal processing module provided in the embodiments of this application.

[0048] In this embodiment, the clock synchronization module 10 includes a master clock unit, a slave clock unit, and a clock reference unit. The first output of the master clock unit is communicatively connected to the first input of the test system to be calibrated; the second output of the master clock unit is connected to the input of the slave clock unit; the output of the slave clock unit is also communicatively connected to the input of the clock reference unit; the first and second outputs of the clock reference unit are respectively connected to the input of the signal generation module 20 and the first output of the signal processing module 30.

[0049] It is understood that the clock synchronization module 10 in this embodiment adopts a hierarchical, master-slave collaborative design, specifically including a master clock unit, a slave clock unit, and a clock reference unit. This architecture decouples the time synchronization function, improving the system's flexibility and final synchronization accuracy.

[0050] It should be noted that the master clock unit is used to provide a master clock signal to the test system to be calibrated and the slave clock unit; the slave clock unit is used to achieve master-slave time synchronization with the slave clock unit based on the master clock signal, and outputs a clock synchronization signal to the clock reference unit; the clock reference unit is configured to generate and output a coordinated clock signal to the signal generation module 20 and the signal processing module 30 based on the clock synchronization signal, so as to control the output time and acquisition time of the test signal; the master clock unit is further configured to acquire the second response time difference of the response signals of multiple channel comparators in the test system to be calibrated.

[0051] Understandably, the master clock unit is the primary device or time source in the clock domain for the entire calibration system. Its main function is to generate a highly stable, low-jitter master clock signal as the most fundamental time reference for the entire system. In physical implementation, it can be composed of a high-stability, temperature-controlled crystal oscillator, an atomic clock, or a phase-locked loop connected to an external high-level reference clock circuit.

[0052] Understandably, the slave clock unit, acting as a slave device, receives the master clock signal from the master clock unit. Its core function is to run a time synchronization protocol, such as PTP-based slave logic, adjusting its own phase and frequency to achieve high-precision time synchronization with the master clock unit and outputting a synchronized clock signal. This essentially regenerates the master clock signal and eliminates the initial deviation caused by the transmission path. The clock reference unit receives the synchronized clock signal from the slave clock units. Its role is to condition, amplify, and distribute this signal, generating one or more low-jitter, high-drive coordinated clock signals, and distributing them to modules requiring precise timing control.

[0053] Therefore, the first output of the master clock unit is connected to the test system under test, directly providing the master clock signal to the test system so that its internal digital circuits (including the comparator's sampling and decision logic) operate based on this master clock. This is the first step in achieving time alignment between the test system and external devices. The second output of the master clock unit is connected to the input of the slave clock unit, meaning the master clock signal is transmitted to the slave clock unit through this path as its synchronization reference source. The output of the slave clock unit is connected to the input of the clock reference unit, where a precisely phase-aligned clock synchronization signal generated after synchronization processing by the slave clock unit is sent to the clock reference unit. The outputs of the two clock reference units are connected to the signal generation module and the signal processing module, respectively. The coordinated clock signal generated by the clock reference units is simultaneously provided to both the signal generation module 20 and the signal processing module 30. The signal generation module 20 uses this coordinated clock to trigger the generation of the test signal, precisely controlling the start time of its output. The signal processing module 30 uses this coordinated clock to drive the sampling clock of its high-speed analog-to-digital converter or time-to-digital converter, accurately acquiring the sampling time of data acquisition. Thus, the generation and acquisition of test signals are controlled by the same high-precision coordinated clock, achieving strict synchronization between the two at the clock cycle level.

[0054] Specifically, please refer to Figure 4 , Figure 4 This is a schematic diagram of clock synchronization provided in an embodiment of this application. The master clock sends a Sync message to the slave clock and records the time T1. After receiving the Sync message, the slave clock records the reception time T2. After sending the Sync message, the master clock immediately sends a message with the value T1 to the slave clock. The slave clock sends a message to the master clock and records the sending time T3. After receiving the message, the master clock records the reception time T4. The master clock then sends a message carrying T4 to the slave clock. Thus, the slave clock obtains all the times T1, T2, T3, and T4, and can calculate the round-trip time difference. Then, it takes the average value: [(T2 - T1) + (T4 - T3)] / 2. From this, the clock offset of the slave clock relative to the master clock can be calculated: Offset = (T2 - T1) - [(T2 - T1) + (T4 - T3)] / 2, and synchronization compensation is performed.

[0055] In addition, the master clock unit is further configured to acquire the second response time difference of the response signals of multiple channel comparators in the test system to be calibrated. This can be achieved in a typical manner as follows: It should be noted that the test system to be calibrated integrates a high-precision timestamp unit. When the comparator output of any channel changes, this timestamp unit immediately captures the current master clock count value, as the test system uses the master clock as a reference. The master clock timestamps corresponding to the responses of each channel are fed back to the master clock unit of the clock synchronization module 10 via communication interfaces such as SPI or parallel bus. By comparing these timestamps, the master clock unit can calculate the second response time difference between the responses of each channel. Since all timestamps are based on the same master clock, the measurement of this time difference has inherent high precision.

[0056] Understandably, by using an independent clock unit for synchronous regeneration, jitter and offset that may occur during the long-distance transmission of the master clock signal to different physical locations can be effectively filtered out and compensated. Furthermore, local driving by the clock reference unit provides a clean and strongly driven clock for critical modules, reducing the adverse effects of clock signal quality degradation on timing accuracy.

[0057] Understandably, the master clock unit focuses on providing a reference and collecting response timestamps for the system under test (SUT), while the slave clock and clock reference units focus on providing high-quality synchronization clocks for the signal generation and acquisition modules. Each unit performs its specific function, reducing the coupling complexity of the system design. Since the generation time, acquisition time, and recording of the response time within the test system all ultimately trace back to the same master clock unit, the first input time difference and the second response time difference are measured in the same time coordinate system. Their difference calculations have clear physical meaning and can be directly used to calculate the comparator's inherent bias.

[0058] In one feasible implementation, the signal generation module 20 includes: a pattern generator; the clock input of the pattern generator is connected to the first output of the clock reference unit to receive a coordinated clock signal; the signal output of the pattern generator is connected to the test system to be calibrated; the pattern generator is configured to generate and output a test signal with a known timing relationship at a preset time based on the coordinated clock signal.

[0059] It should be noted that a code pattern generator refers to a programmable digital sequence generator. It can continuously output corresponding electrical signals based on preset code pattern data, driven by a clock. Its "based on a coordinated clock signal" means that the generator's internal shifts or state transitions are entirely controlled by the coordinated clock signal provided by the clock reference unit, thus ensuring that each edge of the output signal has a definite and highly accurate absolute time reference.

[0060] Understandably, the signal output of the pattern generator is connected directly or via the aforementioned connection module to the test system to be calibrated. The pattern generator is configured to, upon receiving a specific trigger command or reaching an internal state, begin outputting the corresponding level at each valid edge of the coordinating clock according to its stored pattern, thereby generating a test signal with a known, deterministic timing relationship. For example, it can generate a single pulse or a sequence of pulses with specific intervals to test different response characteristics of the comparator.

[0061] In one feasible implementation, the signal generation module 20 further includes: a counter subtractor; the output terminal of the counter subtractor is connected to the control terminal of the code pattern generator; the counter subtractor is configured to perform subtraction counting from a preset initial value after the output test signal, so as to control the output timing of the test signal.

[0062] It should be noted that a counter subtractor is a type of digital counter that operates by starting from a preset initial value and decreasing it in each clock cycle or upon triggering a specific event until it reaches zero or a specific condition is met. In this solution, it functions as a programmable precision delay controller or a sequence trigger controller.

[0063] Understandably, please refer to Figure 5 , Figure 5 This is a schematic diagram of deviation acquisition provided in an embodiment of this application. When the system initiates a calibration process, the counter subtractor is loaded with a preset initial value. Subsequently, after a certain start event, it begins subtraction counting based on a coordinated clock. When the count value decreases to a specific value, such as zero, the counter subtractor outputs a control signal to the code generator. The code generator then begins outputting a preset test signal. Alternatively, multiple triggers can be implemented and the average value taken. By programming the initial value of the counter subtractor, the delay time between the start event and the actual start of the test signal output can be precisely controlled. This mechanism achieves a high degree of programmability and determinism in the test signal output timing.

[0064] In one embodiment, the signal processing module 30 includes an oscilloscope and a host computer; the clock input terminal of the oscilloscope is connected to the second output terminal of the clock reference unit to receive a coordinated clock signal; the signal input terminal of the oscilloscope is connected to the test system to be calibrated for acquiring test signals; the oscilloscope is configured to synchronously acquire test signals under the control of the coordinated clock signal and send the acquired data to the host computer; the host computer is configured to determine a first input time difference based on the acquired data and obtain a second response time difference from the clock synchronization module 10 to calculate the timing deviation.

[0065] It should be noted that an oscilloscope refers to a high-precision, multi-channel synchronous acquisition digital measuring instrument. Its core function is to sample the input analog voltage signal at specific points in time and convert it into a digital value. Here, it is responsible for accurately recording the signal waveform. The host computer usually refers to a general-purpose computer that runs dedicated calibration control and analysis software. It is responsible for controlling the entire calibration process, receiving and processing data, and executing core algorithm calculations.

[0066] Understandably, the oscilloscope's clock input is connected to the second output of the clock reference unit to receive the coordinated clock signal. This connection is crucial for ensuring a unified time base. The oscilloscope is configured to use this coordinated clock signal as its sampling clock or high-precision trigger reference. This ensures a definite and stable phase relationship between the oscilloscope's sampling time and the time the signal generation module generates the test signal, thus achieving true synchronous acquisition. The oscilloscope's multiple signal inputs are connected via a connection module to the test signal reference path, i.e., the outputs of the comparators in each channel of the test system to be calibrated. Therefore, it can synchronously capture the original input test signal.

[0067] Understandably, after completing one or more acquisitions, the oscilloscope will send the obtained waveform acquisition data, usually a voltage sequence with timestamps, to the host computer through the data interface.

[0068] Understandably, the host computer runs the calibration software, and its processing flow is as follows: The software analyzes the waveform data transmitted from the oscilloscope, corresponding to the raw test signal directly acquired from the connection module. Through waveform analysis algorithms (such as over-threshold detection, interpolation fitting, etc.), the absolute time of the test signal arriving at each acquisition channel of the oscilloscope can be accurately calculated. Since these signals are synchronously allocated from the same source, the time difference between them is the first input time difference, which mainly reflects the slight differences in the path from the allocation point to each acquisition channel; the host computer obtains the second response time difference of the comparator response signal of each channel from the clock synchronization module 10. The acquisition method can be to receive the timestamp data recorded and reported by the test system through a separate communication interface; finally, the calibration software of the host computer performs the core calculation.

[0069] Understandably, for each channel to be calibrated, the timing deviation of its comparator can be derived through the following relationship: subtract the difference between the channel's comparator response time and the reference channel's response time (i.e., a portion of the second response time difference) from the difference between the channel's test signal input time and the reference channel's response time (i.e., the corresponding portion of the first input time difference). The result is the comparator's inherent response time deviation after eliminating external transmission path differences.

[0070] Therefore, please refer to Figure 6 , Figure 6 This is a diagram showing the relationship between clock synchronization and offset acquisition provided in an embodiment of this application. Figure 6 The diagram clearly illustrates the interaction and data flow between various functional modules during the calibration process. The master clock, as the top-level time source for the entire system, is responsible for publishing the synchronization protocol and time information. This information is transmitted to the slave clocks. Upon receiving the information, the slave clocks calculate the line delay and time difference, and adjust their local time and phase frequency difference accordingly to generate a high-precision synchronization clock signal. This synchronization clock signal coordinates the actions of subsequent modules. The code generator triggers a start pulse upon receiving the synchronization clock signal. A counter bar performs a subtraction counting operation to precisely control the timing delay of the test signal output. Under timing control, the system under test (i.e., the system to be calibrated) runs the calibration program and outputs pulses to its digital channel.

[0071] It should be noted that the oscilloscope, under the control of a synchronous clock, receives and synchronously acquires response signals from digital channel 1 and digital channel 2. The arrows in the diagram clearly indicate the coordinated control flow from the master clock to the slave clock, and then distributed to the pattern generator, the system under test (DUT), and the oscilloscope, as well as the signal acquisition flow from the DUT to the oscilloscope.

[0072] Understandably, this diagram presents an orderly workflow: a unified time base is established through master-slave clock synchronization; the code generator produces test stimuli under precise timing control; the system under test outputs a response; and the oscilloscope synchronously acquires the response signal. This process ensures that the first input time difference and the second response time difference are acquired in the same time coordinate system, laying a solid foundation for the final accurate calculation of the timing deviation of the channel comparator.

[0073] In addition, this application also proposes an embodiment of a channel deviation calibration method. Please refer to... Figure 7 , Figure 7 This is a schematic flowchart of the channel deviation calibration method provided in the embodiments of this application.

[0074] In this embodiment, the channel deviation calibration method includes steps S10 to S40.

[0075] Step S10: Based on the time synchronization protocol, synchronize the test system to be calibrated, the signal generation module, and the signal processing module in time.

[0076] Understandably, this step forms the basis for all subsequent precise time measurements. Its core is to establish a unified, high-precision time reference, eliminating the inherent clock skew between individual devices.

[0077] Specifically, step S10 includes: sending a first message to the slave clock via the master clock and recording the first transmission time, then recording the first reception time of the slave clock receiving the first message; sending the first transmission time to the slave clock at the next moment after the master clock sends the first message; sending a second message to the master clock via the slave clock and recording the second transmission time, then recording the second reception time of the master clock receiving the second message; sending the second reception time to the slave clock at the next moment after the master clock receives the second message; obtaining the clock deviation of the slave clock relative to the master clock based on the first transmission time, the first reception time, the second transmission time, and the second reception time to achieve master-slave synchronization, thereby synchronizing the time of the test system under the master clock and the signal generation module and signal processing module under the slave clock control clock reference unit.

[0078] Understandably, after master-slave synchronization is achieved, the test system under calibration operates its internal timing based on the master clock, while the signal generation and signal processing modules are coordinated by a clock reference unit synchronized with the slave clock. Therefore, the entire system (test system under calibration, signal generation module, and signal processing module) is unified under the same high-precision time coordinate system. This ensures direct comparability of times recorded on different devices.

[0079] Step S20: Under time synchronization conditions, the control signal generation module outputs a test signal with a known timing relationship to the test system to be calibrated.

[0080] Understandably, this step generates the excitation signal required for calibration, provided that global time synchronization is maintained. Control can be achieved through host computer software instructions or hardware trigger circuits. Upon receiving the trigger, the signal generation module (such as a pattern generator) generates and outputs the test signal at a preset, precise absolute time, strictly following the coordinated clock tick obtained from the clock reference unit. Known timing relationships mean that the pulse width, edge rate, pulse interval, and other characteristics of the test signal are preset and known, and its output time is determined relative to the system time reference. The test signal is synchronously applied to the input terminals of multiple calibration channels of the test system through the connection module.

[0081] Step S30: Under time synchronization conditions, the control signal processing module synchronously acquires test signals from multiple channels and determines the first input time difference of the test signals; then, it acquires the second response time difference of the comparators of multiple channels in the test system to be calibrated in response to the test signals.

[0082] Understandably, this step is the data acquisition phase, simultaneously capturing both the ideal transmission time difference and the actual response time difference. The signal processing module (such as an oscilloscope) also synchronously performs the acquisition action under the control of a coordinating clock. It synchronously acquires the test signals generated and distributed by the signal generation module through the second signal output terminal of the connection module. By analyzing these synchronously acquired test signal waveforms from the same source but leading to different channels, the first input time difference between the arrival of the same test signal at each channel input terminal can be accurately calculated. This time difference reflects the inherent differences such as the length difference and delay difference of the physical path from the signal distribution point to each channel input terminal.

[0083] Understandably, this method also requires obtaining a second response time difference, which is the time difference between the actual response (output transition) of each channel comparator in the test system to the input test signal. This can be achieved by having a high-precision timestamp unit within the test system record a timestamp based on the master clock when the comparator transitions, and then reporting this timestamp information to the processing unit to calculate the time difference.

[0084] Step S40: Calculate the timing deviation of the channel comparator based on the first input time difference and the second response time difference.

[0085] Understandably, the host computer performs calculations based on the two time difference data obtained in step S30. For any two channels i and j, the relative timing deviation of the channel comparators can be derived through the following relationship: (Channel j comparator deviation - Channel i comparator deviation) ≈ (Second response time difference) - (First input time difference). By setting one channel as a reference channel (with its deviation set to 0), the timing deviation values ​​of all other channel comparators relative to that reference channel can be calculated. This calculation eliminates the influence of differences in the test signal transmission path, and the obtained deviation is the inherent response time difference of the comparator itself.

[0086] Step S40 and subsequent steps include: converting the calculated timing deviation of each channel comparator into a channel delay compensation value; writing or configuring the channel delay compensation value to the test system to be calibrated, so that the test system to be calibrated can perform time compensation on the input signal or output response of each channel according to the compensation value in subsequent work, thereby calibrating the timing deviation.

[0087] Understandably, the calculated theoretical timing deviation is further converted into an actual channel delay compensation value. This compensation value can be written to the configuration register of the test system to be calibrated or stored in a calibration file. In subsequent actual testing, when the test system is operating in comparator mode, the system can use this compensation value to perform delay correction on the time stamp of the data acquired by each channel in software or hardware, or advance / delay the timing reference point of the internal sampling judgment, thereby calibrating the timing deviation in actual effect and improving the consistency and accuracy of time measurement between multiple channels.

[0088] It is understood that the beneficial effects of the channel deviation calibration method provided in this application are the same as those of the channel deviation calibration device based on the high-precision time synchronization protocol provided in the above embodiments, and other technical features in the channel deviation calibration method are the same as those disclosed in the above embodiments, and will not be repeated here.

[0089] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0090] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A channel deviation calibration device based on a high-precision time synchronization protocol, characterized in that, include: Clock synchronization module, signal generation module, and signal processing module; The three output terminals of the clock synchronization module are respectively connected to the input terminal of the signal generation module, and the first input terminal of the signal processing module is connected to the first input terminal of the test system to be calibrated; the output terminal of the signal processing module is connected to multiple channels of the test system to be calibrated; the second input terminal of the signal processing module is connected to multiple channels of the test system to be calibrated. The clock synchronization module is configured to synchronize the test system to be calibrated, the signal generation module, and the signal processing module in time based on a time synchronization protocol. The signal generation module is configured to output a test signal to the test system to be calibrated under time synchronization conditions; the signal processing module is configured to synchronously acquire the test signal generated by the signal generation module and sent to the test system to be calibrated under time synchronization conditions, and determine the first input time difference of the test signal. The clock synchronization module is also configured to acquire the second response time difference of the multiple channel comparators in the test system to be calibrated responding to the test signal; The signal processing module is further configured to calculate the timing deviation of the channel comparator based on the first input time difference and the second response time difference.

2. The channel deviation calibration device based on a high-precision time synchronization protocol as described in claim 1, characterized in that, The clock synchronization module includes: a master clock unit, a slave clock unit, and a clock reference unit; The first output terminal of the master clock unit is communicatively connected to the first input terminal of the test system to be calibrated; the second output terminal of the master clock unit is connected to the input terminal of the slave clock unit; the output terminal of the slave clock unit is also communicatively connected to the input terminal of the clock reference unit; the first output terminal and the second output terminal of the clock reference unit are respectively connected to the input terminal of the signal generation module and the first output terminal of the signal processing module. The master clock unit is used to provide a master clock signal to the test system to be calibrated and the slave clock unit; the slave clock unit is used to achieve master-slave time synchronization with the slave clock unit based on the master clock signal, and output a clock synchronization signal to the clock reference unit. The clock reference unit is configured to generate and output a coordinated clock signal to the signal generation module and the signal processing module based on the clock synchronization signal, so as to control the output time and acquisition time of the test signal; The master clock unit is further configured to acquire the second response time difference of the response signals of multiple channel comparators in the test system to be calibrated.

3. The channel deviation calibration device based on a high-precision time synchronization protocol as described in claim 2, characterized in that, The signal generation module includes: a code pattern generator; The clock input terminal of the pattern generator is connected to the first output terminal of the clock reference unit to receive the coordinated clock signal; the signal output terminal of the pattern generator is connected to the test system to be calibrated. The code generator is configured to generate and output a test signal with a known timing relationship at a preset time based on the coordinated clock signal.

4. The channel deviation calibration device based on a high-precision time synchronization protocol as described in claim 3, characterized in that, The signal generation module further includes: a counter subtractor; The output of the counter subtractor is connected to the control terminal of the code generator; The counting subtractor is configured to perform subtraction counting starting from a preset initial value after the output test signal, so as to control the output timing of the test signal.

5. The channel deviation calibration device based on a high-precision time synchronization protocol as described in claim 2, characterized in that, The signal processing module includes: an oscilloscope and a host computer; The clock input terminal of the oscilloscope is connected to the second output terminal of the clock reference unit to receive the coordinated clock signal; the signal input terminal of the oscilloscope is connected to the test system to be calibrated to acquire the test signal. The oscilloscope is configured to synchronously acquire the test signal under the control of the coordinated clock signal and send the acquired data to the host computer. The host computer is configured to determine the first input time difference based on the collected data and obtain the second response time difference from the clock synchronization module to calculate the timing deviation.

6. The channel deviation calibration device based on a high-precision time synchronization protocol as described in claim 2, characterized in that, The communication connection between the signal generation module, the signal processing module and the test system to be calibrated is achieved through a connection module. The connection module includes a signal input terminal, a first signal output terminal, and a second signal output terminal; the signal input terminal is connected to the signal generation module and is used to receive test signals; the first signal output terminal is connected to the test system to be calibrated and is used to output test signals; the second signal output terminal is connected to the signal processing module and is used to output test signals. The connection module is configured to synchronously distribute the test signal from the signal generation module to the test system to be calibrated and the signal processing module.

7. The channel deviation calibration device based on a high-precision time synchronization protocol as described in claim 6, characterized in that, The connection module includes: a calibration interface board; The channel of the test system to be calibrated is connected to the calibration interface board via spring pins; the signal generation module and the signal processing module are connected to the calibration interface board via SMA interfaces.

8. A channel deviation calibration method, characterized in that, include: Based on the time synchronization protocol, the test system to be calibrated, the signal generation module, and the signal processing module are synchronized in time; Under time synchronization conditions, the control signal generation module outputs a test signal with a known timing relationship to the test system to be calibrated; Under time synchronization conditions, the control signal processing module synchronously acquires test signals from multiple channels and determines the first input time difference of the test signals; then it acquires the second response time difference of the comparators of multiple channels in the test system to be calibrated in response to the test signals. The timing deviation of the channel comparator is calculated based on the first input time difference and the second response time difference.

9. The channel deviation calibration method as described in claim 8, characterized in that, Based on a time synchronization protocol, the test system to be calibrated, the signal generation module, and the signal processing module are synchronized in time, including: The master clock sends the first message to the slave clock and records the first transmission time. Then, the slave clock records the first reception time of receiving the first message. At the next moment after the master clock sends the first message, the first transmission time is sent to the slave clock. The second message is sent from the slave clock to the master clock and the second sending time is recorded. Then, the second receiving time of the master clock is recorded. At the next moment after the master clock receives the second message, the second receiving time is sent to the slave clock. By obtaining the clock deviation of the slave clock relative to the master clock based on the first transmission time, the first reception time, the second transmission time, and the second reception time, master-slave synchronization is achieved, thereby synchronizing the time of the test system under the master clock and the signal generation module and signal processing module under the slave clock-controlled clock reference unit.

10. The channel deviation calibration method as described in claim 8, characterized in that, Based on the first input time difference and the second response time difference, the timing deviation of the channel comparator is calculated, and then the process further includes: The calculated timing deviations of each channel comparator are converted into channel delay compensation values; The channel delay compensation value is written or configured to the test system to be calibrated, so that the test system to be calibrated can perform time compensation on the input signal or output response of each channel according to the compensation value in subsequent work, thereby calibrating the timing deviation.

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