Identification generation system based on FIFO (First In First Out)

Abstract

The invention relates to the technical field of integrated circuit design, in particular to an FIFO (First In First Out)-based identifier generation system, which provides identifier information for read instructions through an identifier FIFO memory, can realize order preservation of read results of multi-read instructions in a multi-read instruction concurrence scene, can reuse the identifier information, and is convenient to use. In this way, it is not needed to set a plurality of bits in each read instruction to serve as the identification information corresponding to the read instruction, the convenience of generation of the identification information of the read instruction is improved, and then the data reading efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a FIFO-based identifier generation system. Background Technology

[0002] In chip application scenarios, the data volume of the data packets corresponding to the program is usually large. It is necessary to split the data packets into multiple sub-data packets and then allocate each sub-data packet to different computing modules for parallel computing, thereby improving the efficiency of program execution.

[0003] Since the speed of sub-data packet splitting is faster than the speed of sub-data packet processing by the computing module, a corresponding memory is usually set up for the computing module to store multiple sub-data packets allocated to the corresponding computing module. This allows for simultaneous sub-data packet splitting and sub-data packet processing, improving overall processing efficiency.

[0004] However, since there may be dependencies between data packets, that is, the processing of a certain data packet depends on the results of other data packets that have been processed, the data packet that depends on the processing results of other data packets must wait for the data packets it depends on to be processed before it can be retrieved and split.

[0005] To address the aforementioned issues, existing technologies propose sending read commands in parallel to an address storing the processing status of each dependent data packet via event commands. When all read commands return a "processed complete" status, the data packets to be processed can be retrieved and split. However, since the read commands return at different times, identification information needs to be set in the read commands to ensure the order of the read command results. However, setting the identification information usually requires consideration of specific data packets, pipelines, queues, etc., making the identification information setting quite complex. Furthermore, to distinguish different read commands, the identification information needs to use a long bit width, resulting in an excessively large instruction bit width and reduced processing efficiency.

[0006] Therefore, improving the ease of generating and reusability of identification information has become an urgent problem to be solved. Summary of the Invention

[0007] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: A FIFO-based identifier generation system includes: a client, a storage module, a cache module, and an identifier FIFO memory. The storage module contains data packet processing record addresses corresponding to N initial data packets, and each data packet processing record address corresponds to a record value. The identifier FIFO memory contains K identifier information, and the cache module includes cache addresses corresponding to K identifier information, where N and K are both positive integers.

[0008] After receiving a synchronization event command for N initial data packets, the system sends a read command to the data packet processing record address corresponding to each of the N initial data packets in the storage module.

[0009] The identifier FIFO memory is used to provide identifier information to read instructions.

[0010] The caching module is used to temporarily store the record value read back by the read instruction at the cache address corresponding to the identifier information of the read instruction, so that the client can read it.

[0011] After any cached address is read by the client, the identification information corresponding to that cached address is input into the identification FIFO memory.

[0012] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the FIFO-based identifier generation system provided by the present invention achieves considerable technological progress and practicality, and has broad industrial application value. It has at least the following advantages: This invention provides identification information for read instructions by identifying the FIFO memory, which can maintain the order of read results in scenarios with multiple concurrent read instructions. Moreover, the identification information can be reused, eliminating the need to set several bits as the identification information for each read instruction, thus improving the convenience of generating the identification information for read instructions and thereby improving the efficiency of data reading. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of a data synchronization system based on event commands provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a FIFO-based identifier generation system provided in Embodiment 2 of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This embodiment provides a data synchronization system based on event commands. See [link to documentation]. Figure 1 This is a schematic diagram of the structure of a data synchronization system based on event commands provided in Embodiment 1 of the present invention. The system includes: a storage module, a packet retrieval module, a data packet distribution module, firmware, M memory modules and M computing modules, wherein the memory modules correspond one-to-one with the computing modules, and M is a positive integer. The packet retrieval module is used to read the initial data packet corresponding to the packet retrieval instruction from the storage module after receiving the packet retrieval instruction; The data packet distribution module is used to receive the initial data packet sent by the packet retrieval module, extract the target data packet from the initial data packet, and send the target data packet to the arbitrated memory; The memory is used to receive target data packets and send the received target data packets to the corresponding computing module; The calculation module is used to perform calculations on the received target data packets; The firmware is used to update the record value of the corresponding data packet processing record address in the storage module after the calculation and processing of any target data packet is completed; After receiving a synchronization event instruction for N initial data packets, the system simultaneously sends a read instruction to the corresponding data packet processing record address in the storage module for each of the N initial data packets. The read instruction includes identification information, where N is a positive integer. For any read instruction, the record value read back by the read instruction is written into the register corresponding to the identification information contained in the read instruction; If the record values ​​in the registers corresponding to the initial data packet identifier information of the N initial data packets meet the preset conditions, then data synchronization is completed, and a new packet retrieval instruction is generated and sent to the packet retrieval module.

[0017] The storage module can refer to the chip's memory. Access to the storage module requires the interface provided by the storage module. In this embodiment, reading the initial data packet and reading the record value both need to be done through the interface of the storage module.

[0018] The memory can refer to a First-In-First-Out (FIFO) memory, meaning that the sub-data packets that enter the memory first will be sent to the computing unit first.

[0019] Firmware can refer to RCICV firmware, which is used to perform specific functions. In this embodiment, the firmware is used to update the corresponding record value according to the processing status of the target data packet.

[0020] The packet retrieval instruction can contain the packet retrieval address in the storage module. The packet retrieval module reads the initial data packet corresponding to the packet retrieval instruction from the storage module according to the packet retrieval address.

[0021] The arbitration method for the memory can be configured by the implementer through software. The arbitration method can include polling arbitration, out-of-order arbitration, weighted arbitration, etc.

[0022] In one specific implementation, the step of updating the record value of the corresponding data packet processing record address in the storage module after any target data packet has been calculated and processed includes: After any target data packet has been processed, the record value of the corresponding data packet processing record address of the initial data packet to which the target data packet belongs in the storage module is decremented by one, thus completing the update of the record value.

[0023] The initial data packet to which the target data packet belongs can refer to the source of the split of the target data packet.

[0024] In one specific implementation, for any initial data packet, the record value corresponding to the initial data packet is initially the number of target data packets split from the initial data packet.

[0025] Since the data volume of the initial data packet is known, and the data volume of the target data packet can be set by the implementer, the number of target data packets to be split from the initial data packet can be determined based on the data volume of the initial data packet and the data volume of the target data packet.

[0026] In one embodiment, the update method of the record value can also be as follows: after any target data packet is calculated and processed, the record value of the corresponding data packet processing record address of the initial data packet to which the target data packet belongs in the storage module is incremented by one. Accordingly, for any initial data packet, the record value corresponding to the initial data packet is initially 0. The record value in the registers corresponding to the initial data packet identification information of N initial data packets satisfies the preset condition, which means that the record value in the registers corresponding to the initial data packet identification information of N initial data packets is consistent with the number of target data packets corresponding to N initial data packets.

[0027] In one specific implementation, the identification information includes an initial data packet identifier.

[0028] The identification information includes the initial data packet identifier, and each initial data packet corresponds to a register.

[0029] In one specific implementation, the identification information also includes a production line identification.

[0030] A pipeline can process multiple initial data packets, and multiple pipelines can be executed in parallel. When the identification information includes initial data packet identifiers and pipeline identifiers, each initial data packet of each pipeline corresponds to a register.

[0031] In one embodiment, the identification information may also include queue identifiers. A queue may contain multiple pipelines, and multiple queues may share computing resources using a time-slice allocation method.

[0032] In one specific implementation, the addresses of the registers corresponding to the initial data packet identification information of N initial data packets form an address range, and the address range corresponds to a read pointer, which initially points to the starting address of the address range; When the value of the record in the register pointed to by the read pointer is 0, the read pointer increments by 1; When the value of the read pointer is greater than the end address of the address range, the record values ​​in the registers corresponding to the initial data packet identifier information of the N initial data packets are determined to satisfy the preset conditions.

[0033] In this embodiment, for ease of processing, the addresses of the registers corresponding to the initial data packet identifiers of the N initial data packets are set to be consecutive, so that the addresses of the registers corresponding to the initial data packet identifiers of the N initial data packets can form an address range.

[0034] Specifically, when the value of the read pointer is greater than the end address of the address range, it means that the record values ​​in the registers corresponding to the initial data packet identifier information of the N initial data packets are all 0. At this time, it can be indicated that the N initial data packets have been processed and the preset conditions can be met.

[0035] In one specific implementation, for any read instruction, if the record value read back by the read instruction is not 0, then a read instruction is sent again to the data packet processing record address corresponding to the read instruction.

[0036] If the record value read back by a certain read instruction is not 0, it means that the corresponding initial data packet has not been processed yet. Therefore, the read instruction is resent to the data packet processing record address corresponding to the read instruction until the record value read back by the read instruction is 0.

[0037] Specifically, since this embodiment sets different registers for different initial data packets, the above-mentioned method of resending the read command will not cause the read record values ​​to be out of order, thus improving the efficiency of data synchronization.

[0038] In one specific implementation, when the initial data packet to be read has a dependency relationship with N initial data packets that have already been read, a synchronization event instruction for generating N initial data packets is sent to the system; Accordingly, if the record values ​​in the registers corresponding to the initial data packet identifier information of the N initial data packets respectively meet the preset conditions, then data synchronization is completed, and a new packet retrieval instruction is generated and sent to the packet retrieval module, including: If the record values ​​in the registers corresponding to the initial data packet identifier information of the N initial data packets meet the preset conditions, then data synchronization is completed, and a new packet retrieval instruction corresponding to the initial data packet to be read is generated and sent to the packet retrieval module.

[0039] If the processing of the initial data packet to be read requires the processing results of the N initial data packets already read, it indicates that there is a dependency relationship between the initial data packet to be read and the N initial data packets already read.

[0040] In this first embodiment, read commands are sent to multiple data packet processing record addresses simultaneously, avoiding mutual waiting between read operations of different data packet processing record addresses and improving data synchronization efficiency. In addition, the read command contains identification information, and different identification information corresponds to different registers. The record value read back by the read command is stored in the corresponding register, avoiding the out-of-order situation of the read record value due to different return times when read commands are sent at the same time, thus ensuring the feasibility of reading the record value of multiple data packet processing record addresses in parallel.

[0041] This embodiment 2 provides a FIFO-based identifier generation system. The system includes: a client, a storage module, a cache module, and an identifier FIFO memory. The storage module contains data packet processing record addresses corresponding to N initial data packets, and each data packet processing record address corresponds to a record value. The identifier FIFO memory contains K identifier information, and the cache module includes cache addresses corresponding to K identifier information. N and K are both positive integers. After receiving a synchronization event instruction for N initial data packets, the system sends a read instruction to the data packet processing record address corresponding to each of the N initial data packets in the storage module. The identifier FIFO memory is used to provide identifier information to read commands; The caching module is used to temporarily store the record value read back by the read instruction at the cache address corresponding to the identifier information of the read instruction, so that the client can read it; After any cached address is read by the client, the identification information corresponding to that cached address is input into the identification FIFO memory.

[0042] The recorded value can represent the processing status of the corresponding initial data packet. For ease of processing, the K identifiers contained in the FIFO memory can be consecutive, for example, from 1 to K.

[0043] The identifier FIFO memory can refer to a FIFO memory carrying initial values. K identifier information is stored in the identifier FIFO memory in ascending order. Since the FIFO memory is first-in-first-out, the identifier information output by the identifier FIFO memory is also in ascending order.

[0044] It should be noted that this embodiment only uses the reading of recorded values ​​as an example. Implementers can apply this embodiment in scenarios where multiple read instructions need to be read and the order needs to be preserved, according to the actual situation.

[0045] In one specific implementation, for any read instruction, before the read instruction is sent to the storage module, the identifier FIFO memory outputs an identifier information to form a target read instruction corresponding to the read instruction, and then sends the target read instruction corresponding to the read instruction to the storage module.

[0046] Specifically, the identifier FIFO memory can output an identifier information and concatenate it with a read instruction to form the target read instruction corresponding to the read instruction.

[0047] Specifically, after the identifier FIFO memory outputs an identifier, the identifier that is adjacent to and greater than the identifier is used as the next output of the identifier FIFO memory.

[0048] In one specific implementation, when any target read instruction reads back a record value, the record value read back by the target read instruction is stored in the cache module at the cache address corresponding to the identifier information, according to the identifier information corresponding to the target read instruction.

[0049] When multiple target read commands are issued, the return times of each target read command may be different. By using the identification information of the target read command, the record value read back by the target read command is stored in the cache module at the cache address corresponding to the identification information, so that the return results of each target read command can be kept in order.

[0050] In one specific implementation, the cache module has a corresponding read pointer, and the start of the read pointer is the same as the smallest identifier in the identifier FIFO memory.

[0051] In this context, the read pointer starting point being the same as the smallest identifier in the identifier FIFO memory can mean that the read pointer starting point points to the cache address corresponding to the smallest identifier in the identifier FIFO memory.

[0052] In one specific implementation, after the client reads the record value in the cache address pointed to by the read pointer, the read pointer is incremented by one.

[0053] In this context, incrementing the read pointer by one could mean that the read pointer points to the cache address corresponding to the next identifier information.

[0054] In one specific implementation, when the read pointer is greater than the maximum identifier information, the read pointer is set to the minimum identifier information.

[0055] When the read pointer is greater than the largest identifier, it means that all identifiers have been used for one round, and the read pointer is then set to the smallest identifier.

[0056] In one specific implementation, when any identifier information is less than the read pointer, the identifier information is input into the identifier FIFO memory.

[0057] When any identifier is less than the read pointer, it means that the record value corresponding to the identifier has been read by the client and the identifier can be reused. The identifier is then input into the identifier FIFO memory and will be assigned to a new read instruction.

[0058] In one specific implementation, when the record values ​​corresponding to the N initial data packets read by the client are all preset values, it is determined that the synchronization event instruction has been executed.

[0059] The preset value can be 0. When the synchronization event instruction is completed, a packet retrieval instruction can be generated to instruct the initial data packet to be read from the storage module for splitting and processing.

[0060] It should be noted that the identifier generation system provided in this embodiment 2 can be applied to embodiment 1 to provide identifier information for the read command in embodiment 1.

[0061] In this second embodiment, by identifying the FIFO memory to provide identification information for read instructions, the order of read instructions can be maintained in scenarios with multiple concurrent read instructions. Moreover, the identification information can be reused, eliminating the need to set several bits as the identification information corresponding to each read instruction. This improves the convenience of generating the identification information of read instructions and thus improves the efficiency of data reading.

[0062] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A FIFO-based identification generation system, characterized by, The system includes: a client, a storage module, a cache module, and an identifier FIFO memory. The storage module contains data packet processing record addresses corresponding to N initial data packets, and each data packet processing record address corresponds to a record value. The identifier FIFO memory contains K identifier information, and the cache module contains cache addresses corresponding to K identifier information. N and K are both positive integers. After receiving a synchronization event instruction for N initial data packets, the system sends a read instruction to the data packet processing record address corresponding to each of the N initial data packets in the storage module. The identifier FIFO memory is used to provide identifier information to read commands; The caching module is used to temporarily store the record value read back by the read instruction at the cache address corresponding to the identifier information of the read instruction, so that the client can read it; After any cached address is read by the client, the identification information corresponding to that cached address is input into the identification FIFO memory.

2. The FIFO-based identifier generation system according to claim 1, characterized in that, For any read instruction, before the read instruction is sent to the storage module, the identification FIFO memory outputs an identification information to form a target read instruction corresponding to the read instruction, and then sends the target read instruction corresponding to the read instruction to the storage module.

3. The FIFO-based identifier generation system according to claim 2, characterized in that, When any target read instruction reads back a record value, the record value read back by the target read instruction is stored in the cache module at the cache address corresponding to the identifier information, according to the identifier information corresponding to the target read instruction.

4. The FIFO-based identifier generation system according to claim 1, characterized in that, The cache module has a corresponding read pointer, and the start of the read pointer is the same as the smallest identifier in the identifier FIFO memory.

5. The FIFO-based identifier generation system according to claim 4, characterized in that, After the client reads the record value at the cache address pointed to by the read pointer, the read pointer is incremented by one.

6. The FIFO-based identifier generation system according to claim 5, characterized in that, When the read pointer is greater than the maximum identifier information, the read pointer is set to the minimum identifier information.

7. The FIFO-based identifier generation system according to claim 6, characterized in that, When any identifier is less than the read pointer, the identifier is input into the identifier FIFO memory.

8. The FIFO-based identifier generation system according to claim 1, characterized in that, When the record values ​​corresponding to the N initial data packets read by the client are all preset values, it is determined that the synchronization event instruction has been executed.

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