Double precision floating point division computing device, method and chip

Abstract

The application provides a double-precision floating-point division calculation device, method and chip, relates to the technical field of computer chip design, and a pre-processing unit receives a dividend and a divisor in a double-precision floating-point format, detects the number of leading zeros of the mantissas of the two, and determines the exponent attribution of a quotient result in combination with the exponent values; if the quotient result is a non-normalized number, the corresponding right shift amount is determined according to the exponent attribution. A dynamic iteration unit generates an iteration total number control signal according to the right shift amount, accesses a look-up table to output a quotient value candidate based on the specific high bit combination of the remainder and the divisor in each clock cycle, updates the remainder, synchronously generates and adjusts a quotient value selection function, and left shifts the effective quotient value of each round according to the remaining iteration number and the right shift amount. A post-processing unit outputs a double-precision floating-point division result according to the final quotient value selection function, the sign and value of the remainder of the last round and a preset rounding rule when the iteration is completed. The application reduces the operation delay and power consumption.

Description

Technical Field

[0001] This application relates to the field of computer chip design technology, and in particular to a double-precision floating-point division calculation device, method and chip. Background Technology

[0002] In existing SRT-4 double-precision floating-point division implementations, a fixed iteration cycle architecture is commonly used. This means that regardless of the difference in exponents between the input operands, a sufficient number of iterations to cover all possible operand ranges is always performed to ensure accurate calculation even in the most complex cases, such as generating a normalized quotient and achieving full mantissa precision and rounding requirements. This approach results in a denormalized quotient when the difference between the dividend and divisor exponents is large. The actual quotient has far fewer effective mantissa bits than the standard mantissa in double-precision format, yet the hardware still forces all iterations to be completed, leading to redundant computation. Redundant iterations not only prolong critical path latency and exacerbate instruction-level pipeline congestion (especially in RAW-dependent scenarios), but also cause unnecessary dynamic power consumption. Summary of the Invention

[0003] The purpose of this application is to provide a double-precision floating-point division calculation device, method, and chip to alleviate the aforementioned technical problems existing in the prior art.

[0004] In a first aspect, the present invention provides a double-precision floating-point division calculation device, comprising a preprocessing unit, a dynamic iteration unit, and a post-processing unit connected in sequence, wherein:

[0005] The preprocessing unit is used to receive the dividend and divisor in double-precision floating-point format, detect the number of leading zeros in the mantissas of the two numbers, and determine the exponent assignment of the quotient result obtained by the division operation based on the number of leading zeros and the exponent value; when the exponent assignment of the quotient result indicates that it is a denormalized number, the right shift amount corresponding to the quotient result is determined based on the exponent assignment.

[0006] The dynamic iteration unit is used to generate a total number of iterations control signal based on the right shift amount, and to perform SRT-4 iteration operation in each clock cycle: accessing the lookup table based on a specific high-order bit combination of the current remainder and divisor, and outputting quotient candidates; updating the remainder; synchronously generating and adjusting the quotient selection function; and performing a left shift operation on the effective quotient generated in each round based on the remaining number of iterations and the right shift amount.

[0007] The post-processing unit is used to extract the mantissa significant bits, rounding bits, and sticky bits of the quotient when the number of iterations reaches the total number of iterations, based on the final quotient selection function, the sign and value of the remainder in the last round, and the preset rounding rules, and output the double-precision floating-point division result.

[0008] In an optional implementation, the preprocessing unit is further configured to, when the quotient result is a denormalized number, compare a difference between a number and the exponent with the mantissa width plus one, and determine the right shift amount based on the comparison result, such that the right shift amount is equal to the difference or equal to the mantissa width plus one.

[0009] In an optional implementation, the dynamic iteration unit is further configured to add the high-order part and the low-order part of the right shift amount, and subtract the sum from the base iteration number as the total number of iterations.

[0010] In an optional implementation, the dynamic iteration unit is further configured to access the lookup table using the high-order bit segment in the current remainder used to determine the quotient candidate and the high-order bit segment in the divisor used to determine the quotient candidate as a combined index.

[0011] In an optional implementation, the dynamic iteration unit is further configured to, in each iteration, use the difference between four times the current remainder and the product of the quotient candidate and the divisor as the remainder for the next iteration.

[0012] In an optional implementation, the dynamic iteration unit is further configured to determine, in each iteration, the number of bits to perform a left shift operation on the effective quotient based on the remaining number of iterations and the least significant bit of the right shift amount.

[0013] In an optional implementation, the post-processing unit is further configured to extract the mantissa of a corresponding length from the quotient selection function according to the state of the most significant bit of the quotient selection function, and determine the rounding bit and sticky bit according to the state of the most significant bit and the remainder of the last round.

[0014] In an optional implementation, the post-processing unit is further configured to adjust the exponent of the quotient result based on the exponent prediction error and rounding carry-over situation of the pre-processing unit.

[0015] Secondly, this invention provides a double-precision floating-point division calculation method, executed by a chip, comprising:

[0016] The system receives a dividend and a divisor in double-precision floating-point format, detects the number of leading zeros in the mantissas of both, and determines the exponent assignment of the quotient result obtained by the division operation based on the number of leading zeros and the exponent value; when the exponent assignment of the quotient result indicates that it is a denormalized number, the system determines the right shift amount corresponding to the quotient result based on the exponent assignment.

[0017] The total number of iterations is generated based on the right shift amount, and the SRT-4 iteration operation is performed in each clock cycle: the lookup table is accessed based on a specific high-order bit combination of the current remainder and the divisor, and the quotient candidate is output; the remainder is updated; the quotient selection function is generated and adjusted synchronously; and the effective quotient generated in each round is left-shifted based on the remaining number of iterations and the right shift amount.

[0018] When the number of iterations reaches the total number of iterations, the significant digits, rounding digits, and sticky digits of the quotient are extracted based on the final quotient selection function, the sign and value of the remainder in the last round, and the preset rounding rules, and the double-precision floating-point division result is output.

[0019] Thirdly, the present invention provides a chip that integrates the double-precision floating-point division calculation device described in any of the foregoing embodiments.

[0020] The double-precision floating-point division calculation device, method, and chip provided in this application have a preprocessing unit that predicts the normalization / denormalization attribute of the quotient result by jointly analyzing the number of leading zeros and the exponent value, and determines the right shift amount accordingly, providing a basis for dynamic pruning in the iteration process. The dynamic iteration unit generates a variable total number of iterations based on this shift amount, allowing the number of iterations to adaptively adjust according to the characteristics of the input data, avoiding over-computation of denormalization scenarios under a fixed-cycle architecture, thereby shortening the operation latency and alleviating the performance bottleneck caused by register write-after-read dependency. The left shift operation executed synchronously during the iteration process directly positions the valid bits of the quotient value to the final output position, so that the post-processing unit does not need to configure a dedicated right shifter for normalization post-processing of the denormalization result, simplifying the hardware structure and improving timing convergence. Overall, this device reduces operation latency and power consumption without sacrificing accuracy and compatibility, while also optimizing hardware resources. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 A structural diagram of a double-precision floating-point division calculation device provided in an embodiment of this application;

[0023] Figure 2 A flowchart of a double-precision floating-point division calculation method provided in this application embodiment;

[0024] Figure 3The flowchart illustrates a fast calculation method for double-precision floating-point division based on the SRT-4 algorithm, provided for embodiments of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0028] This application provides a double-precision floating-point division calculation device; see [link to documentation]. Figure 1 As shown, its hardware architecture includes a preprocessing unit (PREUnit), a dynamic iteration unit (ITERUnit), and a postprocessing unit (POSTUnit), which are connected sequentially in the direction of data flow to form a floating-point division calculation path. Among them:

[0029] I. Preprocessing Unit

[0030] The preprocessing unit is used to receive the dividend and divisor in double-precision floating-point format, detect the number of leading zeros in the mantissas of the two numbers, and determine the exponent assignment of the quotient result obtained by the division operation based on the number of leading zeros and the exponent value; when the exponent assignment of the quotient result indicates that it is a denormalized number, the right shift amount corresponding to the quotient result is determined based on the exponent assignment.

[0031] Specifically, this unit first checks in parallel whether the dividend and divisor are denormalized numbers: if their exponent fields are all zeros and their mantissa fields are non-zero, they are determined to be denormalized numbers, and leading zero detection is initiated, outputting the number of leading zeros in the mantissa of the dividend and the mantissa of the divisor; if they are normalized numbers, the corresponding number of leading zeros is 0. Subsequently, based on the exponent values ​​of the dividend and divisor and the detected number of leading zeros, the theoretical exponent of the quotient is calculated; when the theoretical exponent is less than or equal to 0, it indicates that the quotient is denormalized. At this time, based on the absolute value relationship of the theoretical exponent, a right shift amount for compensating bit alignment is determined. This right shift amount will directly participate in the dynamic adjustment of the quotient position in subsequent iterations, rather than being physically shifted in the post-processing stage.

[0032] II. Dynamic Iterative Unit (ITERUnit)

[0033] The dynamic iteration unit is used to generate a total number of iterations control signal based on the right shift amount, and to perform SRT-4 iteration operation in each clock cycle: accessing the lookup table based on a specific high-order bit combination of the current remainder and divisor, outputting quotient candidates; updating the remainder; synchronously generating and adjusting the quotient selection function; and performing a left shift operation on the effective quotient generated in each round based on the remaining number of iterations and the right shift amount.

[0034] The specific high-order bit combination of the remainder and divisor mentioned above refers to the discriminant bit of the normalized interval of the current remainder and the valid discriminant bit of the normalized mantissa of the divisor. That is, the index is used to access the lookup table based on the discriminant bit of the normalized interval of the current remainder and the valid discriminant bit of the normalized mantissa of the divisor to output the quotient candidate.

[0035] In practice, the dynamic iteration unit decomposes the value of the right shift amount into its bit field and substitutes it into a predetermined mapping relationship to generate a total number of iterations control signal. In each iteration, the high six bits (excluding the two highest bits) of the current remainder and the high three bits (excluding the two highest bits) of the divisor are concatenated to form a lookup table index to find the 2-bit quotient candidate for this round. The remainder is updated using this quotient candidate. At the same time, based on the difference between the total number of iterations and the number of iterations already executed, and the least significant bit of the right shift amount, the left shift number to be executed for the quotient in this round is calculated, and the newly generated valid quotient is left-shifted by this number and accumulated in the quotient selection function. This process continues until the number of iterations reaches the total number of iterations.

[0036] III. Post-processing Unit (POSTUnit)

[0037] The post-processing unit is used to extract the mantissa significant bits, rounding bits, and sticky bits of the quotient when the number of iterations reaches the total number of iterations, based on the final quotient selection function, the sign and value of the remainder in the last round, and the preset rounding rules, and output the double-precision floating-point division result. Specifically,

[0038] This unit first identifies the position of the most significant bit in the quotient selection function based on the quotient value obtained from the last iteration and the right shift amount, thus determining the most significant bit. Based on this, the quotient value obtained from the lookup table is processed according to the state of the most significant bit: if the most significant bit is 1, the quotient value does not need to be shifted; 53 consecutive bits are extracted directly as the mantissa significant bits, with the second-to-last bit as the rounding bit. The sticky bit is obtained by performing a logical OR operation between the least significant bit of the quotient value and the remainder from the last iteration. If the most significant bit is 0, the quotient value is shifted left by 1 bit; in this case, the least significant bit of the original quotient value becomes the rounding bit, and the sticky bit is obtained by performing a logical OR operation between the remainder from the last iteration. Then, 53 consecutive bits are extracted from the shifted quotient value as the mantissa significant bits. Subsequently, based on the preset rounding mode and the combined state of the rounding bit and the sticky bit, it is determined whether to perform a mantissa increment operation. If a carry occurs, the exponent value is adjusted accordingly. Finally, the sign bit, the adjusted exponent field, and the processed mantissa field are combined to output the 64-bit double-precision floating-point division result.

[0039] Therefore, this invention dynamically analyzes the exponent and mantissa characteristics of the dividend and divisor during the preprocessing stage to determine in advance whether the quotient is a denormalized number, and determines the right shift amount accordingly. This shift amount drives the iterative unit to implement variable-cycle operations, and adaptively shifts the quotient to the left in each iteration, so that the final quotient is naturally aligned with the target position. The post-processing unit is thus exempt from the right shift normalization operation required in traditional schemes. Overall, while strictly ensuring the correctness of IEEE 754 double-precision floating-point division, it significantly reduces average computation latency, dynamic power consumption, and hardware resource overhead, and improves the processor's energy efficiency and throughput in mixed-precision computing scenarios.

[0040] In an optional implementation, the preprocessing unit is further configured to, when the quotient result is a denormalized number, compare the difference between a number and the exponent with the mantissa width plus one, and determine the right shift amount based on the comparison result, such that the right shift amount is equal to the difference or equal to the mantissa width plus one. In a specific implementation, the following right shift amount determination operation is performed:

[0041] When the preprocessing unit determines that the quotient result is a denormalized number, it calculates the theoretical exponent assignment of the quotient (i.e., the exponent value) and calculates the difference between "one minus the exponent assignment". Simultaneously, it compares this difference with the specified mantissa width for double-precision floating-point numbers plus one (i.e., 53 mantissa bits plus 1 rounding bit, totaling 54 bits). If the difference is greater than or equal to 54, the right shift amount is set to 54; if the difference is less than 54, the right shift amount is directly set to the difference. This process ensures that in subsequent iterations and post-processing, the quotient selection function always retains sufficient bit width to cover all valid bits and redundant bits required for rounding, avoiding precision loss due to excessive shifting.

[0042] Furthermore, the aforementioned dynamic iteration unit is also used to add the high-order and low-order parts of the right shift amount, and subtract this sum from the baseline iteration count to obtain the total number of iterations. This unit treats the right shift amount as a six-bit binary number, defining its high-order five bits as the high-order part and its low-order bit as the low-order part; then, it performs an addition operation on the value represented by the high-order part and the value represented by the low-order part to obtain an integer sum; this sum is then subtracted from the baseline iteration count, and the difference is the total number of iterations required for this division operation. The baseline iteration count corresponds to the fixed number of iterations when the quotient is a normalized number, which is twenty-eight times in double-precision floating-point division; this mechanism ensures that as the right shift amount increases, the total number of iterations decreases accordingly, thereby achieving on-demand allocation of computing resources.

[0043] In one optional implementation, the aforementioned dynamic iteration unit is further configured to access a lookup table using a combination of the high-order bit segments used to determine the quotient candidate in the current remainder and the high-order bit segments used to determine the quotient candidate in the divisor as a combined index. This unit uses the high six bits (excluding the two most significant bits) of the current remainder as the remainder's high-order bit segment; simultaneously, it extracts the three most significant bits (excluding the most significant bit) from the divisor data as the divisor's high-order bit segment; these two bit segments are concatenated in a fixed order to form a nine-bit combined index; this index is used to access a built-in read-only lookup table to retrieve the three-bit quotient candidate corresponding to the current iteration, whose value range includes -2, -1, zero, +1, and +2; this lookup table is pre-built based on the redundant quotient selection logic of the SRT-4 algorithm, ensuring that, given local information about the remainder and divisor, the selected quotient value guarantees convergence of the absolute value of the remainder.

[0044] In one specific implementation, the aforementioned dynamic iteration unit is further used to take the difference between four times the current remainder and the product of the quotient candidate and the divisor as the remainder for the next iteration in each iteration. Within the current iteration cycle, this unit first shifts the value of the current remainder two positions to the left (equivalent to multiplying by four) to obtain four times the current remainder; then it calculates the product of the quotient candidate and the divisor; finally, it subtracts this product from four times the current remainder, and the resulting difference is the remainder used in the next iteration. This remainder serves as the input for the next iteration, participating in the generation of the lookup table index and the update of the quotient candidate in a new round. The entire process strictly follows the remainder update rules of the SRT-4 algorithm, ensuring that the absolute value of the remainder monotonically decreases with the increase of the iteration rounds, and finally converges to a range that meets the accuracy requirements within a predetermined number of iterations.

[0045] In one embodiment, the post-processing unit is further configured to extract the mantissa of a corresponding length from the quotient selection function according to the state of the most significant bit of the quotient selection function, and determine the rounding bit and sticky bit according to the state of the most significant bit and the remainder of the last round.

[0046] The quotient selection function refers to the intermediate quotient expression formed by successively concatenating the quotients of each round through shifting and bitwise OR operations during the high-precision fixed-point division iterative operation. It is stored in its original form without final normalization. The output of this function is a multi-bit wide binary number whose numerical range covers the complete possible range of quotient values. However, the high bits may have leading zeros, and the actual starting position of the mantissa needs to be located by detecting its most significant valid bit (MSVB).

[0047] The most significant bit (LSB) state refers to the position information of the most significant bit in the quotient selection function, identified based on the quotient value obtained in the last iteration and the right shift amount. The bit corresponding to this position is the most significant bit of the quotient. Extracting the mantissa of a corresponding length requires including implicit bits in the specific implementation. Therefore, single-precision (24 bits) and double-precision (53 bits) methods are used. Based on the starting index indicated by the LSB state, a continuous bit segment of a specified length is extracted from the output bus of the quotient selection function using a 2-to-1 multiplexer. This bit segment constitutes the original mantissa value to be rounded.

[0048] Furthermore, the round bit and sticky bit are determined based on the state of the most significant bit and the remainder of the last round. The round bit is taken from the bit immediately following the significant bit of the extracted mantissa, and its physical location is determined by the state of the most significant bit and the width of the mantissa. The generation of the sticky bit depends on the state of the most significant bit of the quotient: if the most significant bit is 1, the sticky bit is obtained by logically ORing the least significant bit of the quotient with the aggregated result of the last round remainder; if the most significant bit is 0, the quotient is shifted left by one bit, and the sticky bit is determined solely by the aggregated result of the last round remainder. Specifically, the aggregated remainder of the last round can be obtained by inputting its absolute value into a one-bit wide OR-tree circuit, the output of which indicates whether the remainder is non-zero.

[0049] The post-processing unit is also used to adjust the exponent of the quotient result based on the exponent prediction error and rounding carry situation of the preprocessing unit. Specifically, if the exponent prediction needs to be reduced by 1 due to the highest valid bit of the quotient being 0 during the preprocessing stage, the post-processing unit first records the correction amount; at the same time, if the mantissa is added by 1 during the rounding operation, resulting in an upward overflow carry, the exponent needs to be corrected by adding 1. The final exponent adjustment amount is determined by both of these: when the prediction of subtraction by 1 and the rounding addition by 1 occur simultaneously, they cancel each other out, and the exponent remains unchanged; otherwise, the exponent is updated accordingly based on the actual effective correction amount. The condition for generating the rounding carry signal is: after the mantissa's valid bits are truncated, it is determined that the mantissa needs to be added by 1 based on the rounding mode and the combination of rounding bits and sticky bits, and this operation causes all bits of the mantissa to be 1. After adding 1, a carry chain is generated that runs through the entire mantissa field, and a carry signal is output outside the highest bit of the mantissa, which is the mantissa overflow carry.

[0050] After completing the mantissa truncation and rounding judgment, the post-processing unit comprehensively considers the exponent prediction error and rounding carry-over situation in the preprocessing stage to make a final adjustment to the exponent of the quotient result. Specifically, the exponent correction consists of two parts: first, the preprocessing correction determined by the state of the most significant bit of the quotient (if the most significant bit is 0, the actual exponent needs to be reduced by 1, and the correction is -1; otherwise, it is 0); second, the rounding correction determined by the rounding carry-over (if the mantissa is increased by 1 and an upward overflow carry-over occurs, the correction is +1; otherwise, it is 0). The final exponent update value is the sum of the original exponent and the algebraic sum of the two. When a rounding carry-over occurs, regardless of whether the preprocessing correction exists, the mantissa needs to be shifted one bit to the right to convert the carry-over into a new implicit bit; if a preprocessing subtraction correction of 1 also exists, the right-shifted mantissa still maintains its normalized form, and the exponent corrections cancel each other out and remain unchanged. If there is only a preprocessing subtraction correction without any rounding carry, then the exponent is decremented by 1 and the mantissa is shifted left by one bit (i.e., restoring the normalized form where the most significant bit of the quotient is 1); if there is only a rounding carry, then the exponent is incremented by 1 and the mantissa is shifted right by one bit. Through this comprehensive judgment, precise normalization adjustment of the exponent and mantissa is achieved.

[0051] Furthermore, if the updated exponent exceeds the maximum exponent value allowed by the target floating-point format (e.g., 1023 for double precision), the post-processing unit generates an overflow exception signal and sets the quotient result to the infinite sign bit. If the updated exponent is lower than the minimum representable normalized exponent (e.g., -1022 for double precision), the exponent clamping and mantissa right shift compensation mechanism is activated. This exponent update process is executed by a dedicated exponent correction logic module, whose inputs include: mantissa overflow carry signal, original exponent field, indication information that the significant highest bit is 0 / 1 (if the significant highest bit is 1, it means that the quotient exponent predicted by the PRE module has no error; if the significant highest bit is 0, it means that the quotient exponent predicted by the PRE module has an error and needs to be -1), the sign bit of the remainder in the last round, and the currently configured floating-point format parameters (e.g., bias value, exponent bit width). All operations are completed within a single cycle, without relying on the main division iteration path, thereby maintaining the overall throughput efficiency and deterministic latency of the division operation.

[0052] In summary, this device performs dynamic iterative double-precision floating-point division based on the SRT-4 algorithm. It predicts whether the result is denormalized based on the difference between the exponents of the dividend and divisor, and dynamically determines the iteration count and quotient shifting strategy accordingly. Compared to existing solutions, this application compresses the iteration cycle for denormalized quotients to 1–27 clock cycles (normal remains 28 cycles), significantly reducing average latency. Simultaneously, by pre-calculating the right shift using the PRE module and combining on-the-fly quotient generation and adaptive left shift using the ITER module, the quotient is directly aligned to the target position during iteration, eliminating the need for a dedicated right shifter in the POST module, saving area, improving timing, and reducing dynamic power consumption caused by invalid calculations. Overall, it balances high performance, low power consumption, and hardware efficiency.

[0053] Applied to the aforementioned double-precision floating-point division calculation device, this invention provides a double-precision floating-point division calculation method, executed by a chip, see [link to relevant documentation]. Figure 2 As shown, the method mainly includes the following steps:

[0054] S210 receives the dividend and divisor in double-precision floating-point format, detects the number of leading zeros in the mantissas of the two numbers, and determines the exponent assignment of the quotient result obtained by division based on the number of leading zeros and the exponent value; when the exponent assignment of the quotient result indicates that it is a denormalized number, the right shift amount corresponding to the quotient result is determined based on the exponent assignment.

[0055] S220 generates the total number of iterations based on the right shift amount and performs SRT-4 iteration operation in each clock cycle: accesses the lookup table based on a specific high-order bit combination of the current remainder and divisor, outputs quotient candidate; updates the remainder; synchronously generates and adjusts the quotient selection function; and performs a left shift operation on the valid quotient generated in each round based on the remaining number of iterations and the right shift amount.

[0056] S230: When the number of iterations reaches the total number of iterations, the significant digits, rounding digits, and sticky digits of the quotient are extracted based on the final quotient selection function, the sign and value of the remainder in the last round, and the preset rounding rules, and the result of double-precision floating-point division is output.

[0057] Figure 3 This document provides a specific implementation flowchart to illustrate the structure and implementation method of the aforementioned device. The flowchart only covers the processing of denormal / normal floating-point operands and floating-point results. The processing of special floating-point operands (NaN / infinity / zero) and floating-point result overflow / underflow is not detailed here. The method includes:

[0058] (1) PRE module:

[0059] The dividend / divisor is preprocessed, including left-shifting the mantissa of the denormalized number to the mantissa form of the normalized number (MSB is 1), determining the exponent of the division result, and determining the right shift amount (only for scenarios where the quotient is denormalized), etc., to prepare for the ITER / POST module.

[0060] 1-1. Determine whether the dividend (a) and divisor (b) are denormal. If they are denormal, perform a leading zero check on the mantissa to determine the number of leading zeros (a_ldz_cnt / b_ldz_cnt); if they are normal, the number of leading zeros in the mantissa is 0.

[0061] 1-2, the mantissas of the dividend (a) and divisor (b) are shifted to the left. The shift amount is the number of leading zeros. The shift results are used as the initial remainder and divisor of the ITER module, respectively.

[0062] 1-3. Based on the exponents of the dividend / divisor (a_exp / b_exp) and the number of leading zeros in the mantissa (a_ldz_cnt / b_ldz_cnt), determine the exponent of the quotient: rst_exp = (a_exp - a_ldz_cnt) - (b_exp - b_ldz_cnt) + bias. For double-precision floating-point numbers, bias = 1023. It is important to note that the quotient exponent obtained here is not an exact result. When the mantissa of the dividend is less than the mantissa of the divisor, the effective MSB of the quotient value obtained by looking up the table is 0. In this case, the exponent has a 1-bit error and needs to be corrected in the POST module.

[0063] 1-4. Determine the right shift amount `rsh_num` for the quotient. If the quotient is normal (rst_exp > 0), the mantissa does not need to be right-shifted, and the right shift amount `rsh_num = 0`. If the quotient is denormal (rst_exp <= 0), the theoretical right shift amount is 1 - `rst_exp`. Considering that the mantissa of a double-precision floating-point number is 53 bits and the 1-bit roundbit required for rounding, the right shift amount is processed as follows: when 1 - `rst_exp >= 54`, the right shift amount `rsh_num = 54`; when 1 - `rst_exp < 54`, the right shift amount `rsh_num = 1 - `rst_exp`. Determining the right shift amount of the quotient in advance reduces the number of subsequent iterations.

[0064] Steps 1-5: Clear the iteration counter, i.e., iter_cnt=0.

[0065] (2) ITER module:

[0066] Iterative calculations are performed using SRT-4, with each iteration yielding a 2-bit quotient value. For double-precision floating-point division, the mantissa of the result is 53 bits. Rounding requires 1 bit. Additionally, the MSB of the quotient obtained from the lookup table may be 0, requiring a 1-bit left shift for normalization. Therefore, the iterative module retains a 56-bit quotient value. If the result is normal, the iterative module requires 28 clock cycles; if the result is denormal, the iterative module requires 1-27 clock cycles.

[0067] 2-1. Determine the number of iterations: iter_cycle = 27 - (rsh_num[5:1] + rsh_num[0]). If the result is normal, i.e., rsh_num = 0, then the iteration module needs 28 clock cycles; if the result is denormal, i.e., rsh_num > 0, then the iteration module needs 1-27 variable clock cycles.

[0068] 2-2, using the SRT-4 algorithm P j+1 =rP j -q j+1 D, the remainder (P) j The high 6 bits (excluding the highest 2 bits) of the divisor (D) and the high 3 bits (excluding the highest 1 bit) of the divisor (D) are used as the index for table lookup; where r=4, P j+1 / P j q represents the remainder in the (j+1 / j)th iteration. j+1 Let rP represent the quotient of the (j+1)th iteration, and D represent the divisor. For the first iteration, rP j Determined based on the left shift of the mantissa of the dividend in the Pre module; for iterations other than the first round, P... j The value is determined based on the remainder obtained from the previous iteration; D remains unchanged for each iteration.

[0069] 2-3. By looking up the table, obtain the 3-bit quotient value, which has a range of {-2, -1, 0, +1, +2}.

[0070] 2-4, using P j+1 =rP j -q j+1 D calculates the remainder P j+1 It will participate in the next round of iterative calculations.

[0071] 2-5, employing the on-the-fly transformation technique, and simultaneously determining the quotient selection function Q / QM, where Q... j+1 / Q j Let QM represent the positive quotient value of the (j+1 / j)th iteration. j+1 / QM jDenotes the negative quotient value of the (j + 1) / j-th iteration, q j+1 Denotes the quotient value of the (j + 1)-th iteration, r = 4. For the first iteration, Q = QM = 0. In each iteration, according to the 3-bit quotient value obtained by looking up the table, Q / QM is updated. In this process, only 2-bit valid quotient values are retained, and the 2-bit quotient value needs to be shifted left to ensure that the quotient value obtained in this iteration is placed in the correct bit position of the final result. The left shift amount is lsh_num = (iter_cycle - iter_cnt) × 2 + rsh_num[0].

[0072]

[0073]

[0074] In 2 - 6, the iteration counter is incremented, that is, iter_cnt = iter_cnt + 1; if iter_cnt < iter_cycle, continue the iteration; if iter_cnt = iter_cycle, end the iteration.

[0075] (3)POST module:

[0076] According to the quotient value selection function generated by the iteration, determine the quotient value and rounding bit of the double-precision floating-point division. After performing the rounding operation, the final floating-point division operation result is obtained.

[0077] In 3 - 1, according to the sign of the remainder generated in the last iteration and the valid MSB of the quotient selection function Q / QM, determine the tail number bit of the quotient value of the floating-point division and the roundbit / stickybit required for rounding judgment. If the remainder is positive, select Q, otherwise select QM; if the valid MSB of Q / QM is 1, the tail number bit of the quotient value takes the [54:2]-bit of the 56-bit Q / QM, roundbit takes the [1]-bit of Q / QM, and stickybit takes the result obtained by performing a bitwise "OR" operation on the [0]-bit of Q / QM and the remainder; if the valid MSB of Q / QM is 0, the tail number bit of the quotient value takes the [53:1]-bit of the 56-bit Q / QM, roundbit takes the [A]-bit of Q / QM, and stickybit takes the result obtained by performing a bitwise "OR" operation on the remainder. The valid MSB mentioned above is equivalent to the MSB corresponding to Q / QM after shifting left by rsh_num. In this application, the following method is used to obtain it: MSB = |(({1’b1, 54’b0} >> rsh_num) & Q / QM); this method does not require introducing a left shift shifter, and has better timing performance and smaller hardware overhead.

[0078] It should be noted that there is an error in the original text where 'roundbit takes the [A]-bit of Q / QM' in the translation of item

[20] . It should be 'roundbit takes the [0]-bit of Q / QM'. The above translation has been corrected accordingly.3-2. Based on the rounding method, the LSB of the quotient obtained above, and the roundbit / stickybit, determine whether a rounding operation is required.

[0079] 3-3, Determine the exponent / mantissa for the rounding operation. If rounding is required, increment the mantissa of the quotient by 1; otherwise, leave the mantissa unchanged. If the mantissa rounding operation results in a carry, theoretically the exponent of the quotient should be incremented by 1. However, as mentioned earlier, the exponent generated by the PRE module may have a 1-bit error. If the effective MSB of the quotient is 0, theoretically the exponent of the quotient should be decremented by 1. Combine the rounding result with the effective MSB of the quotient to determine whether the exponent of the quotient needs to be updated.

[0080] In summary, this application dynamically adjusts the number of iterations based on the exponents of the dividend and divisor, pre-determines the denormalization result, determines the final required right shift, and controls the left shift of the quotient during iteration. This effectively reduces the clock cycles required for computation, thereby improving computational performance and reducing power consumption. In the ITER module, by controlling the left shift of the quotient, the denormalized result is directly placed in the valid bit, eliminating the need for additional processing in the POST module. This optimization saves one right shifter, effectively reducing circuit area and improving timing performance.

[0081] The present invention also provides a chip that integrates a double-precision floating-point division calculation device as described in any of the foregoing embodiments; the device includes a preprocessing module, an iteration module, and a post-processing module, configured to: dynamically determine whether the quotient is a denormalized number based on the difference between the exponents of the input dividend and the divisor, and generate a right shift amount accordingly; determine a variable iteration period based on the right shift amount, and achieve bit alignment of the quotient value through adaptive left shift control during the iteration process, so that the post-processing module can complete rounding and result assembly without additional normalization shift; thereby reducing average latency, dynamic power consumption, and hardware area overhead while ensuring the correctness of double-precision floating-point division operation.

[0082] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A double-precision floating-point division calculation device, characterized in that, It includes a preprocessing unit, a dynamic iteration unit, and a postprocessing unit connected in sequence, wherein: The preprocessing unit is used to receive the dividend and divisor in double-precision floating-point format, detect the number of leading zeros in the mantissas of the two numbers, and determine the exponent assignment of the quotient result obtained by the division operation based on the number of leading zeros and the exponent value; when the exponent assignment of the quotient result indicates that it is a denormalized number, the right shift amount corresponding to the quotient result is determined based on the exponent assignment. The dynamic iteration unit is used to decompose the value of the right shift amount into a bit field, substitute it into a predetermined mapping relationship, generate a total iteration count control signal, and perform SRT-4 iteration operation in each clock cycle: access the lookup table based on a specific high-order bit combination of the current remainder and divisor, output quotient candidate, where the specific high-order bit combination of the remainder and divisor is the discrimination bit of the normalized interval of the current remainder and the valid discrimination bit of the normalized mantissa of the divisor; update the remainder; synchronously generate and adjust the quotient selection function; and perform a left shift operation on the valid quotient value generated in each round according to the remaining iteration count and the right shift amount. The post-processing unit is used to extract the mantissa significant bits, rounding bits, and sticky bits of the quotient when the number of iterations reaches the total number of iterations, based on the final quotient selection function, the sign and value of the remainder in the last round, and the preset rounding rules, and output the double-precision floating-point division result.

2. The double-precision floating-point division calculation device according to claim 1, characterized in that, The preprocessing unit is further configured to, when the quotient result is a denormalized number, compare the difference between one and the exponent with the mantissa width plus one, and determine the right shift amount based on the comparison result, such that the right shift amount is equal to the difference or equal to the mantissa width plus one.

3. The double-precision floating-point division calculation device according to claim 1, characterized in that, The dynamic iteration unit is further configured to add the high-order part and the low-order part of the right shift amount to obtain a sum, and subtract the sum from the baseline iteration number as the total number of iterations.

4. The double-precision floating-point division calculation device according to claim 1, characterized in that, The dynamic iteration unit is also used to access the lookup table using the high-order bit segment in the current remainder used to determine the quotient candidate and the high-order bit segment in the divisor used to determine the quotient candidate as a combined index.

5. The double-precision floating-point division calculation device according to claim 1, characterized in that, The dynamic iteration unit is also used to take the difference between four times the current remainder and the product of the quotient candidate and the divisor as the remainder for the next iteration in each iteration.

6. The double-precision floating-point division calculation device according to claim 1, characterized in that, The dynamic iteration unit is also used to determine, in each iteration, the number of bits to perform a left shift operation on the effective quotient value based on the remaining number of iterations and the least significant bit of the right shift amount.

7. The double-precision floating-point division calculation device according to claim 1, characterized in that, The post-processing unit is further configured to extract the corresponding length of mantissa significant bits from the quotient selection function according to the significant most significant bit state of the quotient selection function, and determine the rounding bits and sticky bits respectively according to the significant most significant bit state and the last round remainder.

8. The double-precision floating-point division calculation device according to claim 1, characterized in that, The post-processing unit is also used to adjust the exponent of the quotient result based on the exponent prediction error and rounding carry-over situation of the pre-processing unit.

9. A double-precision floating-point division calculation method, executed by a chip, characterized in that, include: The system receives a dividend and a divisor in double-precision floating-point format, detects the number of leading zeros in the mantissas of both, and determines the exponent assignment of the quotient result obtained by the division operation based on the number of leading zeros and the exponent value; when the exponent assignment of the quotient result indicates that it is a denormalized number, the system determines the right shift amount corresponding to the quotient result based on the exponent assignment. After decomposing the right shift amount into its bit field, the value is substituted into a predetermined mapping relationship to generate the total number of iterations. Within each clock cycle, an SRT-4 iteration operation is performed: a lookup table is accessed based on a specific high-order bit combination of the current remainder and divisor, outputting candidate quotients. This specific high-order bit combination of the remainder and divisor serves as the discrimination bit for the normalized interval of the current remainder and the valid discrimination bit for the normalized mantissa of the divisor; the remainder is updated; the quotient selection function is synchronously generated and adjusted; and a left shift operation is performed on the valid quotients generated in each round based on the remaining iteration count and the right shift amount. When the number of iterations reaches the total number of iterations, the significant digits, rounding digits, and sticky digits of the quotient are extracted based on the final quotient selection function, the sign and value of the remainder in the last round, and the preset rounding rules, and the double-precision floating-point division result is output.

10. A chip, characterized in that, The device integrates the double-precision floating-point division calculation device according to any one of claims 1 to 8.

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