Heterogeneous processor-oriented reciprocal calculation instruction sequence generation method

Abstract

The invention discloses a reciprocal calculation instruction sequence generation method oriented to a heterogeneous processor, and belongs to the field of compilation optimization and code generation. Aiming at the problems of instruction redundancy, weak precision control, poor hardware adaptation and high manual dependence of an existing method in a heterogeneous environment, characteristics of a reciprocal instruction and an operand are accurately identified by linearly scanning heterogeneous object codes (including vectorization, scalar and complex instruction sequences); in combination with hardware characteristics of RISC / SIMD / VLIW / DSP and the like, a multi-round iteration precision improvement and temporary register optimization allocation strategy is adopted, differential generation logic is formulated, and a high-precision low-redundancy instruction sequence is generated. The method comprises linear code scanning classification, reciprocal instruction and operand identification, cross-architecture generation logic rule formulation, instruction sequence generation and legality verification. Full-process automation is achieved, manual intervention is reduced, the execution efficiency and precision of reciprocal calculation of the heterogeneous processor are improved, and the method is suitable for embedded systems, high-performance calculation and other scenes.

Description

Technical Field

[0001] This invention relates to the field of compiler optimization and code generation technology, specifically to a method for generating reciprocal calculation instruction sequences for heterogeneous processors. This method linearly scans the linear assembly code related to reciprocal calculations on heterogeneous processors, identifies the characteristics of different types of reciprocal instructions and operands, and combines core technologies such as multi-round iterative precision improvement logic for reciprocal calculations and optimized allocation of temporary registers. It then formulates cross-architecture differentiated generation logic and secure generation rules to achieve automated, high-precision, and low-redundancy generation of reciprocal instruction sequences. This method is suitable for embedded systems and high-performance computing scenarios based on heterogeneous architectures such as RISC / SIMD / VLIW / DSP. Background Technology

[0002] In heterogeneous computing systems, reciprocal calculation is a core fundamental operation in numerical computation, signal processing, and other fields, widely used in filtering, Fourier transforms, matrix operations, and other scenarios. The derived calculation of the reciprocal square root is also a key step in many algorithms. Heterogeneous processors (such as RISC, SIMD, VLIW, and DSP), with their architectural diversity, can meet the computational needs of different scenarios; however, the automatic generation of reciprocal instruction sequences still faces many challenges.

[0003] Poor hardware compatibility: The instruction sets of different heterogeneous architectures differ significantly. Existing methods do not fully adapt to the register usage rules and special instruction constraints of specific architectures, resulting in problems such as register conflicts and disordered instruction execution timing in the generated instruction sequences. For example, Zhong Bing et al. focused on instruction scheduling and register allocation for ARM architecture in "Optimization of Assembly Language Programs for Embedded Devices Based on ARM Architecture," but did not design an adaptation mechanism for the countdown special instructions of heterogeneous architectures, nor did they consider the dynamic allocation requirements of temporary registers, making it difficult to migrate the optimization scheme to other architectures.

[0004] Insufficient precision control: Simple reciprocal approximation instructions can only provide 8 bits of precision, which cannot meet the needs of high-precision calculations. Existing methods lack standardized iterative precision improvement processes, and manually designing iterative logic can easily lead to instruction redundancy, chaotic data dependencies, and difficulty in adapting to different precision requirements (float / double). Although the linear assembler designed by Shi Yang et al. in "Independent Software Stack Design for Phytium Maichuang DSP" achieves automatic register allocation, it does not design a multi-round iterative precision control mechanism for reciprocal calculations, making it difficult to guarantee precision consistency in different scenarios.

[0005] Instruction redundancy is severe: the generation of traditional reciprocal calculation instructions does not fully utilize the parallel capabilities of heterogeneous hardware and lacks optimized allocation strategies for temporary registers, resulting in unnecessary register moves and data copy operations, which increase memory access overhead and execution cycle. Especially in vector reciprocal calculations, the batch processing advantages of the SIMD architecture are not fully utilized, and the generated instruction sequence does not conform to the hardware parallelism characteristics.

[0006] High reliance on manual intervention: The generation of reciprocal instruction sequences in heterogeneous environments heavily depends on expert experience, especially in complex scenarios such as complex number reciprocals and vector complex number reciprocals. Manually adapting iterative logic and register allocation for different architectures is inefficient, error-prone, and difficult to guarantee consistency, significantly increasing development costs. Kang Yuhan et al., in their paper "A Deep Learning Programming Framework for the Maichuang + MatrixZone Heterogeneous System," pointed out that the generation of vectorized assembly code in heterogeneous systems requires manual intervention, particularly in the design of complex reciprocal operation instruction combinations and precision control, which drastically reduces development efficiency.

[0007] Therefore, it is necessary to design an automatic generation method for reciprocal instruction sequences that is compatible with heterogeneous processors, integrating core technologies such as multi-round iteration accuracy improvement of reciprocal calculation and dynamic allocation of temporary registers, to achieve automated, high-precision, and low-redundancy generation of reciprocal calculations, thereby improving code execution efficiency and development efficiency. Summary of the Invention

[0008] This invention aims to solve the problems of poor hardware adaptability, insufficient accuracy, instruction redundancy, and high dependence on manual operation in existing automatic generation methods for reciprocal calculations in heterogeneous environments. It provides a method for generating instruction sequences for reciprocal calculations on heterogeneous processors, integrating technologies such as multi-round iterative accuracy improvement and optimized allocation of temporary registers to achieve automated and efficient generation of reciprocal instruction sequences on heterogeneous processors.

[0009] To address the aforementioned technical problems, this invention provides a method for generating reciprocal calculation instruction sequences for heterogeneous processors, specifically including the following steps:

[0010] Step S1: Linear code scanning and instruction parsing

[0011] Scan the input heterogeneous processor reciprocal linear assembly code in linear order to generate an intermediate representation adapted to multiple architecture characteristics:

[0012] Instruction Classification and Key Information Extraction: Instructions are scanned sequentially in the code, and classified into reciprocal calculation instructions and non-reciprocal calculation instructions based on their mnemonics, operand characteristics, and architecture identifiers. For reciprocal calculation instructions, key information such as operand type, register binding relationship, precision requirements, and target architecture type is extracted. For non-reciprocal calculation instructions, only their dependency relationship with reciprocal calculation instructions is recorded. R / VR register operands, constant operands, and hexadecimal operands are identified through regular expression matching, and a cross-architecture operand type tagging table is established to provide a basis for subsequent iterative generation and register allocation.

[0013] Instruction dependency graph construction: Based on branch instructions and jump instructions, basic blocks are divided to generate an "instruction dependency graph" - nodes represent basic blocks, and edges represent data dependencies and control dependencies between instructions. It is compatible with heterogeneous architectures such as RISC, SIMD, VLIW, and DSP, and provides context support for instruction generation after linear scan.

[0014] Operand-register relationship modeling: Establish a bidirectional mapping table of "operand-physical register" across architectures, record the binding relationship and timing of various operands and scalar / vector registers under different heterogeneous architectures in the linear scan order; clarify the operand usage order and register occupancy of each reciprocal calculation instruction, avoid overlapping conflicts of register lifecycles, provide data support for dynamic allocation of temporary registers, and build the mapping relationship based solely on the linear scan results without relying on complex data flow chain analysis.

[0015] Step S2: Linear recognition of countdown instructions and operands

[0016] Based on the linear scan results of step S1, the reciprocal instruction to be generated and its associated operands are accurately identified:

[0017] Instruction to be generated identification: The instruction sequence within each basic block is traversed in linear order, and valid instructions to be generated are identified through "instruction mnemonic matching + operand type verification + architecture compatibility judgment". For example, the scalar instruction RECIP under RISC architecture with an operand that is an R register or a constant, the vector instruction VRECIP under SIMD architecture with an operand that is a VR register, and the complex number instruction RECIP_CP / VRECIP_CP with an operand that is a register pair are identified as valid instructions to be generated; at the same time, the pre-reciprocal calculation requirements of derivative instructions such as the reciprocal square root are also identified.

[0018] Associative operand identification: For valid instructions to be generated, the features of their associated operands are extracted in a linear scan order. For scalar / vector reciprocal instructions, the register binding relationship and architecture adaptation requirements of the source operand (Src) and the destination operand (Dst) are recorded; for complex reciprocal instructions, the register pairs corresponding to the real / imaginary parts are additionally identified, and their data flow and calculation timing are recorded to provide a basis for denominator iterative optimization and precision verification; for constants and hexadecimal operands, the timing requirements for loading them into temporary registers are marked.

[0019] Step S3: Cross-architecture generation logic and security rule formulation and instruction generation

[0020] Based on the identified characteristics of the instructions and operands to be generated, and integrating techniques such as multi-round iterative accuracy improvement and temporary register optimization allocation, cross-architecture differentiated generation logic and safe generation rules are formulated to perform instruction generation and normalization:

[0021] Cross-architecture differentiated generation logic design: For different heterogeneous architectures and instruction types, a differentiated generation process is designed by integrating the core precision optimization logic of reciprocal calculation.

[0022] Scalar register type reciprocal: It adopts the process of "initializing constant register → integer to floating point → reciprocal approximation → multi-round iterative generation → result storage". The float type performs two iterations and the double type performs three iterations. Each round of iteration achieves doubled precision through the instruction combination of "multiplication-subtraction-multiplication", which is adapted to the instruction execution characteristics of scalar architecture.

[0023] Vector register type reciprocal: adopts a parallel process of "batch initialization → batch conversion to floating point → batch approximation → batch iteration → batch storage", the number of iterations is consistent with the scalar process, giving full play to the batch processing advantages of SIMD architecture, and generating an independent vector temporary register group to avoid conflicts;

[0024] Reciprocal of complex numbers: First, calculate the denominator (squared real part + squared imaginary part) using the dot product instruction. Perform at least two iterations to optimize the denominator to ensure accuracy. Then, calculate the real part (real part × reciprocal of denominator) and the imaginary part (-imaginary part × reciprocal of denominator) of the result. Add an extra step to check for overflow in the denominator to avoid calculation errors.

[0025] Scalar constant type reciprocal: Based on the scalar register type process, add the step of "loading the constant to a temporary register". The temporary register is allocated independently, and then the conversion to floating point and subsequent processes are executed.

[0026] Safe generation rule execution: Follow register safety constraints, dynamically generate unique temporary registers in linear scan order, allocate a sufficient number of temporary registers according to instruction type to avoid conflicts; configure the number of iterations according to accuracy requirements, twice for float type and three times for double type to ensure accuracy meets the standard; adjust instructions in the order of "initialization → conversion → approximation → iteration → storage" to adapt to hardware pipeline timing, and vector instructions ensure the synchronization of batch operations.

[0027] Step S4: Validation and Code Output

[0028] After instruction generation is complete, the generated instruction sequence undergoes cross-architecture validity verification. Verification includes register usage validity (no conflicts, no out-of-bounds errors), computational precision validity (iteration count meets requirements), architecture adaptability validity (complies with instruction set constraints), and instruction dependency validity (consistent context logic). Once verification passes, all non-reciprocal computation instructions and their dependencies are retained, and linear assembly code adapted to the target heterogeneous processor is output in linear order.

[0029] Compared with the prior art, the beneficial effects of this invention are as follows:

[0030] Strong cross-architecture adaptability: By formulating differentiated generation logic, it adapts to heterogeneous processors such as RISC, SIMD, VLIW, and DSP, integrates temporary register dynamic allocation strategies, and adapts to the dedicated countdown instructions and register usage rules of various architectures to avoid register conflicts.

[0031] Controllable computational precision: Integrating multi-round iterative precision improvement logic, float type is iterated twice, double type is iterated three times, and complex number reciprocals are additionally checked for denominator precision, which fully meets the requirements of high-precision numerical calculation and significantly improves precision consistency;

[0032] High degree of automation: Based on linear sequential scanning, the entire process is automated, eliminating the dependence on manual generation and eliminating the need for complex data flow chain analysis. In large-scale heterogeneous code scenarios, the generation cycle is greatly shortened, and the problem of misjudgment caused by manual adaptation is avoided.

[0033] Excellent execution efficiency: By reducing redundant register operations and memory access overhead, and integrating batch parallel generation logic, the generated instruction sequence is tailored to the characteristics of heterogeneous hardware pipelines and parallel computing capabilities, significantly improving execution efficiency;

[0034] Standardized generation logic: Integrating standardized iterative processes and register allocation strategies, the generated instruction sequence logic is unified, reducing technology migration costs and enabling direct adaptation to the existing heterogeneous processor software ecosystem. Attached Figure Description

[0035] Figure 1This is a diagram illustrating the overall architecture of the present invention, showcasing the entire process of an automatic generation method for inverse instruction sequences for heterogeneous processors. The diagram visually demonstrates the automated processing chain from input linear assembly code to output inverse instruction sequence code.

[0036] Figure 2 The diagram shown in this embodiment of the invention is a sequence of instructions with inverse opcodes. The nodes represent basic blocks (BB1~BB3) for the analysis of global inverse instruction sequences across basic blocks. Detailed Implementation

[0037] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments.

[0038] Example 1: Overall Process Implementation (Based on Embedded VLIW / DSP Multi-core Heterogeneous Architecture)

[0039] This embodiment uses linear assembly code of a reciprocal instruction sequence based on an embedded VLIW / DSP multi-core heterogeneous architecture as an example to illustrate the specific implementation process of the present invention.

[0040] Step S1: Linear code scanning and instruction parsing

[0041] The input code is linearly scanned, and four types of instructions to be generated are identified in sequence: RECIP (reciprocal of scalar real number), VRECIP (reciprocal of vector real number), RECIP_CP (reciprocal of scalar complex number), and VRECIP_CP (reciprocal of vector complex number). Regular expression matching is used to identify R12 (R register operand), VR0 (VR register operand), 100 (constant operand), and 0x1A3 (hexadecimal operand), and an operand type tagging table for embedded VLIW / DSP multi-core heterogeneous architecture is established.

[0042] Construct operand-register mappings in a linear order: “R12 → Scalar Register R12”, “VR0 → Vector Register VR0”, “100 → Temporary Register RS_1”, “0x1A3 → Temporary Register RS_2”, and record the timing order of each mapping; divide the basic blocks BB1~BB3 according to the branch instructions, generate an instruction dependency graph adapted to the embedded VLIW / DSP multi-core heterogeneous architecture, and mark the data dependency relationship between BB1 and BB2.

[0043] Step S2: Linear recognition of countdown instructions and operands

[0044] Traverse BB1~BB3 in linear order:

[0045] In BB1, RECIP R12 and R15 (embedded VLIW / DSP multi-core heterogeneous architecture scalar instructions, operands are R registers, which are valid) are identified. The source operand R12 and the target operand R15 are recorded. The precision requirement is float (two iterations are required).

[0046] In BB2, VRECIP VR0 and VR5 (embedded VLIW / DSP multi-core heterogeneous architecture vector instructions, with VR registers as operands, are valid) are identified. The source operand VR0 and the target operand VR5 are recorded. The precision requirement is float (two iterations are required).

[0047] In BB3, RECIP_CP RBR:RBI, RZR:RZI (embedded VLIW / DSP multi-core heterogeneous architecture complex instruction, operands are register pairs, which is valid) is identified. The real part register RBR, the imaginary part register RBI, the result real part register RZR, and the result imaginary part register RZI are recorded. The denominator needs to be optimized in two iterations.

[0048] Step S3: Generate logic and instruction generation

[0049] Combining the instruction characteristics of embedded VLIW / DSP multi-core heterogeneous architecture with iterative accuracy improvement logic, a differentiated generation process is executed:

[0050] For RECIP R12, R15 (scalar register type, float): Execution process: Load constant 2 into temporary register RFC2_1 → Integer to floating-point conversion instruction RFC2_1 → Reciprocal approximation instruction processes R12, and the result is stored in RA_1 → First iteration (scalar multiplication instruction calculates R12 and RA_1, and the result is stored in RB_1 → scalar subtraction instruction calculates RB_1 and RFC2_1, and the result is stored in RB_1 → scalar multiplication instruction calculates RA_1 and RB_1, and the result is stored in RA_1) → Second iteration (repeated multiplication-subtraction-multiplication instruction combination from the first iteration) → Result storage (scalar multiplication instruction calculates RA_1 and RB_1, and the result is stored in destination register R15).

[0051] For VRECIP VR0, VR5 (vector register type, float): Execute the vector generation process: Load vector constant 2 into temporary register VRFC2_1 → Vector integer to floating-point conversion instruction VRFC2_1 → Vector reciprocal approximation instruction processes VR0, and the result is stored in VRA_1 → First iteration (vector multiplication instruction calculates VR0 and VRA_1, and the result is stored in VRB_1 → vector subtraction instruction calculates VRB_1 and VRFC2_1, and the result is stored in VRB_1 → vector multiplication instruction calculates VRA_1 and VRB_1, and the result is stored in VRA_1) → Second iteration (repeated the multiplication-subtraction-multiplication instruction combination of the first iteration) → Result storage (vector multiplication instruction calculates VRA_1 and VRB_1, and the result is stored in the destination register VR5).

[0052] For RECIP_CP RBR:RBI, RZR:RZI (complex number): Execute the complex number generation process: Load constant 2 into temporary register RFC2_1 → Integer to floating-point conversion instruction RFC2_1 → Dot product instruction calculates the denominator (the sum of the products of RBR and RBR, RBI and RBI, the result is stored in Rdenominator) → Reciprocal approximation instruction processes Rdenominator, the result is stored in RA_1 → First iteration of the denominator (combination of multiplication-subtraction-multiplication instructions) → Second iteration of the denominator (repeated combination of multiplication-subtraction-multiplication instructions, the result is stored in RD_1) → Real part calculation (multiplication instruction calculates RBR and RD_1, the result is stored in RZR) → Imaginary part calculation (multiplication instruction calculates RBI and RD_1, the result is stored in RT_1 → subtraction instruction calculates RFC0_1 and RT_1, the result is stored in RZI).

[0053] Safe generation rule execution: Dynamically generate unique temporary registers such as RFC2_1 and RA_1 in sequence, and add them to the legal list of embedded VLIW / DSP multi-core heterogeneous architecture through scalar configuration instructions and vector configuration instructions; ensure that scalar floats are iterated twice and complex denominators are iterated twice; arrange instructions in the order of "initialization → transformation → approximation → iteration → storage" to adapt to DSP pipeline timing.

[0054] Step S4: Validation and Code Output

[0055] Legality verification: Verify that there are no conflicts in the temporary registers, the number of iterations meets the standard, the data dependencies are not broken, and the instructions conform to the constraints of the embedded VLIW / DSP multi-core heterogeneous architecture; after the verification is passed, retain the non-reciprocal calculation instructions in BB1~BB3 in linear order, and output linear assembly code adapted to the embedded VLIW / DSP multi-core heterogeneous architecture.

[0056] Example 2: Implementation of key modules (based on code snippets)

[0057] This embodiment, based on core code snippets, illustrates the implementation details of key modules in the scenario of generating instruction sequences for calculating reciprocals on heterogeneous processors.

[0058] Module 1: Linear Identification of Operand Types (including Regular Expression Matching)

[0059] This code uses regular expression matching to accurately identify different types of operands, adapting to the characteristics of operands in heterogeneous architectures. The code logic is as follows:

[0060] start

[0061] / / Initialize regular expression matching rules

[0062] R_REG_RULE = matches strings starting with R (case-insensitive) → R register

[0063] VR_REG_RULE = matches strings starting with VR (case-insensitive) → VR register

[0064] NUM_RULE = Matches pure numbers → constant

[0065] HEX_RULE = Match hexadecimal numbers starting with 0x / 0X → hexadecimal operand

[0066] / / Linear scan instruction, identifying operand types and architecture compatibility

[0067] Traverse all instruction sequences:

[0068] Iterate through all operands of the current instruction:

[0069] If it matches R_REG_RULE → operand type = R register

[0070] If it matches VR_REG_RULE → operand type = VR register

[0071] If it matches NUM_RULE / HEX_RULE → operand type = constant

[0072] Record the operand-architecture-timing mapping relationship to the mapping table

[0073] / / Output core mapping results

[0074] Print "Operand Type Mapping Table:"

[0075] Traverse the mapping table:

[0076] Print "Operand: %s, Type: %s, Adapted Architecture: %s" (operand name, type, architecture)

[0077] Finish

[0078] Module 2: Scalar Reciprocal Instruction Generation (double type)

[0079] For the scalar constant reciprocal instruction RECIP (double type, requiring three iterations), the generation process is as follows:

[0080] start

[0081] / / Input parameters: source constant src, destination register dst, temporary register counter counter

[0082] Define temporary registers: RS = RS_counter, RA = RA_counter, RB = RB_counter, RFC2 = RFC2_counter

[0083] / / Core generation process (following the source code through three iterations)

[0084] Load constants: The scalar load instruction loads src into RS.

[0085] Initialize constants 2.0: Scalar constant initialization instruction load 2 into RFC2 → Scalar-integer to double precision instruction conversion RFC2

[0086] Constant to double: Scalar-integer to double precision instruction conversion RS

[0087] Reciprocal approximation: The scalar reciprocal approximation instruction processes RS, and the result is stored in RA (8-bit precision).

[0088] First iteration:

[0089] The scalar multiplication instruction calculates RS and RA, and stores the result in RB.

[0090] The scalar subtraction instruction calculates RB and RFC2, and stores the result in RB.

[0091] The scalar multiplication instruction calculates RA and RB, and stores the result in RA.

[0092] Second iteration:

[0093] The scalar multiplication instruction calculates RS and RA, and stores the result in RB.

[0094] The scalar subtraction instruction calculates RB and RFC2, and stores the result in RB.

[0095] The scalar multiplication instruction calculates RA and RB, and stores the result in RA.

[0096] Third iteration + result storage:

[0097] The scalar multiplication instruction calculates RS and RA, and stores the result in RB.

[0098] The scalar subtraction instruction calculates RB and RFC2, and stores the result in RB.

[0099] The scalar multiplication instruction calculates RA and RB, and stores the result in dst.

[0100] / / Register a temporary register (core step in the project)

[0101] Add RS, RA, RB, and RFC2 to the list of valid registers using the scalar configuration instruction.

[0102] The message "Scalar double reciprocal instruction generation complete, destination register: %s" (dst) is printed.

[0103] Finish

[0104] Module 3: Generating Reciprocals of Vector Complex Numbers

[0105] For RECIP_CP VRYR:VRYM, VRZR:VRZM (vector complex number, float type, denominator iterated twice), the core part of the generation process is executed:

[0106] start

[0107] / / Input parameters: source vector register src, destination vector register dst, temporary register counter

[0108] Define temporary registers: VRFC2 = VRFC2_counter, VRA = VRA_counter, VRB = VRB_counter

[0109] / / Core generation process (following the source code through two iterations)

[0110] Initialize vector constants 2.0: Vector constant initialization instructions are loaded into VRFC2 → Vector integer to floating-point conversion instructions VRFC2

[0111] Vector reciprocal approximation: The vector reciprocal approximation instruction processes src, and the result is stored in VRA (8-bit precision).

[0112] First iteration:

[0113] The vector multiplication instruction calculates src and VRA, and stores the result in VRB.

[0114] The vector subtraction instruction calculates VRB and VRFC2, and stores the result in VRB.

[0115] The vector multiplication instruction calculates VRA and VRB, and stores the result in VRA.

[0116] Second iteration + result storage:

[0117] The vector multiplication instruction calculates src and VRA, and stores the result in VRB.

[0118] The vector subtraction instruction calculates VRB and VRFC2, and stores the result in VRB.

[0119] The vector multiplication instruction calculates VRA and VRB, and stores the result in dst.

[0120] / / Register vector temporary register

[0121] Add VRFC2, VRA, and VRB to the list of valid registers using vector configuration instructions.

[0122] The message "Vector float reciprocal instruction generated successfully, destination register: %s" (dst) is printed.

[0123] Finish

[0124] This invention effectively solves the problems of adaptability, accuracy, and automation in generating reciprocal instruction sequences in heterogeneous processor environments. It simplifies the analysis process through linear scanning, integrates core technologies such as multi-round iteration for accuracy improvement and dynamic allocation of temporary registers, and formulates cross-architecture differentiated generation logic to achieve automatic generation of high-precision, low-redundancy instruction sequences. It is suitable for heterogeneous computing scenarios such as embedded systems and high-performance computing, and fully meets the generation requirements of various architectures such as RISC, SIMD, VLIW, and DSP.

Claims

1. A method for generating instruction sequences for calculating reciprocals on heterogeneous processors, characterized in that, Includes the following steps: Step S1: Perform linear sequential scanning and parsing on the inverse-dependent linear assembly code of the heterogeneous processor to construct operand-register mapping relationships and instruction dependency graphs; wherein, constructing the instruction dependency graph specifically involves: dividing the linear assembly code into basic blocks, analyzing the data dependencies and control dependencies between instructions based on the linear scan results, and generating an instruction dependency graph with basic blocks as nodes and dependencies as edges, adapting to heterogeneous architectures such as RISC, SIMD, VLIW, and DSP; Step S2: Based on the linear scan results, combined with instruction type, operand characteristics, and architectural features, identify the reciprocal instruction to be generated and its associated operands. The reciprocal instruction to be generated includes scalar reciprocal instruction (RECIP), vector reciprocal instruction (VRECIP), complex reciprocal instruction (RECIP_CP), and vector complex reciprocal instruction (VRECIP_CP). The associated operands include R / VR register operands, constant operands, and hexadecimal operands. Step S3: Based on the mathematical principles of reciprocal calculation, the characteristics of heterogeneous processor instruction sets, and the instruction context obtained by linear scanning, formulate cross-architecture differentiated generation logic and safe generation rules. Under the premise of ensuring instruction semantics and calculation accuracy, automatically generate high-precision, low-redundancy reciprocal instruction sequences and output linear assembly code adapted to heterogeneous processors. The security generation rules are formulated by combining the lifecycle of vector registers in heterogeneous architectures, operand type adaptation, and instruction execution cycle constraints to clarify the generation logic and precision control strategy of reciprocal calculation instructions under different architectures, including iteration number configuration, temporary register allocation, and instruction order arrangement. Step S3 also includes: normalizing the generated instruction sequence, adjusting the instruction order to adapt to the characteristics of the target architecture hardware pipeline, while maintaining the consistency of data dependencies; The method improves the execution efficiency and accuracy of reciprocal calculations on heterogeneous processors by reducing redundant memory accesses and register operations.

2. The method for generating reciprocal calculation instruction sequences for heterogeneous processors according to claim 1, characterized in that, Step S1, "Linear sequential scanning and parsing of the inverse-dependent linear assembly code of heterogeneous processors," specifically includes: The linear assembly code is scanned in linear order, and instructions are divided into reciprocal calculation instructions and non-reciprocal calculation instructions based on instruction mnemonics, operand characteristics, and architecture identifiers. Reciprocal calculation instructions are scalar / vector / complex number instructions containing the mnemonics RECIP, VRECIP, RECIP_CP, and VRECIP_CP, and key information such as operand type, register binding relationship, precision requirements, and target architecture type (RISC / SIMD / VLIW / DSP) is extracted. Non-reciprocal calculation instructions are instructions that do not contain the above mnemonics; only their dependency relationship with reciprocal calculation instructions is recorded, and they do not participate in the core generation process. Extract key operand characteristics of reciprocal calculation instructions using regular expression matching: identify R / VR register operands (matching patterns starting with R / VR, case-insensitive), constant operands (matching pure numeric patterns), and hexadecimal operands (matching hexadecimal numeric patterns starting with 0x / 0X) and establish a cross-architecture operand type tagging table; The "operand-physical register" mapping relationship is constructed according to the linear scan order, and the binding timing and life cycle of the operands and corresponding registers of each reciprocal calculation instruction are recorded, providing a basis for the dynamic allocation of temporary registers.

3. The method for generating reciprocal calculation instruction sequences for heterogeneous processors according to claim 1, characterized in that, The specific steps in step S1, "constructing the operand-register mapping relationship," are as follows: A bidirectional mapping table for operands and physical registers across architectures is established to record the binding relationships and timing between various operands and scalar registers (R0~R63) and vector registers (VR0~VR63) in countdown calculation instructions under different heterogeneous architectures. By linearly traversing the instruction sequence, the operand usage order and register occupancy of each countdown calculation instruction are recorded to clarify the dynamic binding relationship between operands and registers and avoid register conflicts. Register usage in non-reciprocal calculation instructions only records dependencies and is not included in the core analysis of the mapping table.

4. The method for generating reciprocal calculation instruction sequences for heterogeneous processors according to claim 1, characterized in that, Step S2, "Identifying the reciprocal instruction to be generated and its associated operands," also includes: The validity of the instruction to be generated is confirmed by "linear scan instruction mnemonic matching + operand type verification + architecture compatibility judgment". For example, under the RISC architecture, the scalar instruction RECIP with an operand that is an R register or a constant is determined to be a valid instruction to be generated; under the SIMD architecture, the vector instruction VRECIP with an operand that is a VR register is determined to be a valid instruction to be generated. For the complex reciprocal instruction (RECIP_CP / VRECIP_CP), the register pairs corresponding to the real / imaginary parts of the complex number (such as RBR:RBI, VRYR:VRYM) are extracted by linear scanning. The binding relationship of the register pairs, the data flow and the architecture adaptation requirements are recorded, and the calculation timing of the real and imaginary parts is clarified, which provides a basis for denominator precision verification.

5. The method for generating reciprocal calculation instruction sequences for heterogeneous processors according to claim 1, characterized in that, Step S3, "Formulate cross-architecture differentiation generation logic," specifically includes: For different heterogeneous architectures and instruction types, a differentiated generation process is designed by combining the multi-round iterative precision improvement logic of reciprocal calculation with the characteristics of instruction combination: Scalar register type reciprocal (RECIP+R register): It adopts a multi-step process of "initializing constant register → integer to floating point → reciprocal approximation → multi-round iterative generation → result storage". The RISC / DSP architecture uses dedicated scalar instructions to implement each step. Among them, the float type adopts two iterations and the double type adopts three iterations. Each round of iteration follows the instruction combination logic of "multiplication → subtraction → multiplication" to achieve doubling of precision in each round. Scalar constant reciprocal (RECIP + constant / hexadecimal number): Based on the above process, add the "constant loading register" step. The constant is loaded into a temporary register through architecture-specific loading instructions, and then the integer to floating point conversion and subsequent generation process are executed. The temporary register is allocated independently to avoid conflicts. Vector register type inverse (VRECIP+VR register): Adapted to the vector parallelism of SIMD / VLIW architecture, it uses vector-specific instructions to implement the parallel process of "batch initialization → batch conversion → batch approximation → batch iteration → batch storage". The number of iterations is consistent with the scalar process, and an independent vector temporary register group is generated to avoid conflicts. Reciprocal of complex numbers (RECIP_CP / VRECIP_CP): First, calculate the denominator (squared real part + squared imaginary part) using the dot product instruction. Perform at least two iterations to optimize the denominator to ensure accuracy. Then, calculate the real part (real part × reciprocal of denominator) and imaginary part (-imaginary part × reciprocal of denominator) of the result using the complex multiplication instruction. An additional denominator overflow check step is added. The process for generating the reciprocal square root is as follows: Based on the scalar / vector reciprocal generation result, an additional process of "approximation of the reciprocal square root + two iterations of optimization" is added. A dedicated square root instruction is used, and the iteration logic and reciprocal generation maintain architectural consistency.

6. The method for generating reciprocal calculation instruction sequences for heterogeneous processors according to claim 1, characterized in that, The "safe generation rules" in step S3 specifically include: Register safety constraints: Unique temporary register names are dynamically generated in linear scan order and added to the corresponding architecture's legal register list via scalar configuration instructions and vector configuration instructions (scalar architecture is associated with SCR / SFCR control registers, and vector architecture is associated with VCR / VFCR control registers) to avoid register conflicts; the number of temporary registers is allocated according to the instruction type, with at least 10 reserved for complex reciprocal calculations, at least 4 reserved for vector reciprocal calculations, and at least 3 reserved for scalar reciprocal calculations, to adapt to the register requirements of different types of instructions; Precision control rules: Based on the Newton-Raphson iteration method, scalar / vector reciprocal calculations are generated by default using two iterations. The float type supports the option of two iterations, and the double type supports three iterations. Through a three-step process of "reciprocal approximation → iteration correction → result calibration", the calculation precision is improved to the 32-bit / 64-bit floating-point standard. Complex reciprocal calculations additionally add denominator precision verification to ensure that there is no overflow in the denominator calculation. Instruction order rules: Follow the order of "initialization instructions first → type conversion instructions followed by → iterative generation instructions arranged in a fixed combination → result storage instructions to finish", adapt to the execution timing of different heterogeneous architecture hardware pipelines, and vector instructions additionally ensure the synchronization of batch operations to avoid parallel execution conflicts.

7. The method for generating reciprocal calculation instruction sequences for heterogeneous processors according to claim 1, characterized in that, Step S3, before "outputting linear assembly code adapted to heterogeneous processors," also includes cross-architecture validity verification, which includes: Register usage validity: temporary register names are unique, register types match the target architecture instruction requirements (R registers for scalar architecture, VR registers for vector architecture), registers are not out of bounds (R0~R63, VR0~VR63), and register lifetimes do not overlap or conflict. Computational precision validity: The number of iterations meets the precision requirements of the target architecture (at least 2 iterations for the reciprocal of scalar / vector types, 2 iterations for float types, 3 iterations for double types, and at least 2 iterations for the denominator of complex number reciprocals), with no risk of precision loss; Architecture compatibility: The instruction sequence conforms to the instruction set constraints of the target architecture (such as the register usage specifications of DSP architecture and the vector parallelism requirements of SIMD architecture) and there are no instruction conflicts; Instruction dependency validity: The generated instruction sequence does not disrupt the original data dependencies, and the instruction context logic obtained by linear scan is consistent; After successful verification, all non-reciprocal calculation instructions and dependencies are retained, and linear assembly code adapted to the target heterogeneous processor is output.

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