Memory system and error correction method thereof

Abstract

The invention provides a memory system and an error correction method thereof. The error correction method for a plurality of memory devices includes: an error check operation of generating an error sum data segment by performing a parity operation on a plurality of data segments from each of the memory devices; a test preparation operation of generating a third data segment by performing a parity operation between the error sum data segment and a second data segment from the target memory device to generate test data by replacing the second data segment with the third data segment; error correction operation: generating a correction data segment by correcting errors in the test data; judging operation: when the error correction operation is successful, judging whether error correction occurs in the correction data segment; and determining operation: determining whether the error correction method is successful or not according to a result of the judgment operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0141095, filed on October 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to a memory system, and more particularly, to a memory system comprising a plurality of memory devices and an error correction device, and an error correction method for the memory system. Background Technology

[0004] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices in which data is lost when the power supply is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which data is retained even when the power supply is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly divided into NOR type memory and NAND type memory.

[0005] On the other hand, semiconductor memory is widely used in various computing systems, and with the development of computing technology, the demand for large-capacity memory is increasing. To meet this demand, multiple memory devices are currently provided in the form of memory modules such as dual in-line memory modules (DIMMs).

[0006] In memory devices, errors may occur in the stored bit data due to physical damage or other reasons. To recover such corrupted data, error correction codes (hereinafter referred to as ECC) are primarily used. In particular, Single Device Data Correction (SDDC) errors may occur; SDDC errors are a phenomenon where errors are concentrated in a specific memory device among multiple memory devices provided in the form of memory modules. To correct these SDDC errors, attempts have been made to directly incorporate individual ECC codes into the memory modules. However, directly incorporating ECC codes into memory modules can lead to problems such as increased production costs and increased operational latency. Summary of the Invention

[0007] Various embodiments of this disclosure are intended to provide a memory system and an error correction method for the memory system, the memory system being able to effectively detect and correct single-device data correction (SDDC) errors, the SDDC errors indicating the phenomenon that errors are concentrated in a specific memory device among multiple memory devices.

[0008] The technical problems to be solved by this disclosure are not limited to the aforementioned technical problems, and those skilled in the art will clearly understand other unmentioned technical problems from the following description.

[0009] According to embodiments of this disclosure, an error correction method for a memory system is provided. The memory system includes multiple memory devices, each storing data and an error correction code. The method may include: an error checking operation, which generates an error sum data segment by performing a parity check operation on multiple first data segments read from each memory device using the error correction code; a test preparation operation, which generates a third data segment by performing a parity check operation between the error sum data segment and a second data segment based on the result of the error checking operation, so as to generate test data by replacing the second data segment with the third data segment, wherein the second data segment is a data segment read from a target memory device among the multiple first data segments, and the target memory device is selected from the multiple memory devices; an error correction operation, which generates a corrected data segment by correcting errors in the test data using the error correction code; a judgment operation, which determines whether a miscorrection has occurred in the corrected data segment when the error correction operation is successful; and a determination operation, which determines whether the error correction method is successful or unsuccessful based on the number of times the judgment operation is performed as a result of repeating the test preparation operation, the error correction operation, and the judgment operation on each first data segment, and the result of the judgment operation.

[0010] According to embodiments of this disclosure, a memory system may include: a plurality of memory devices, each configured to store data and error correction codes; and an error correction device configured to perform an error correction method, the error correction method including: an error checking operation, generating an error sum data segment by performing a parity check operation on a plurality of first data segments read from each memory device using the error correction codes; a test preparation operation, generating a third data segment by performing a parity check operation between the error sum data segment and a second data segment based on the result of the error checking operation, so as to generate test data by replacing the second data segment with the third data segment, the second data segment being a data segment read from a target memory device among the plurality of first data segments, the target memory device being selected from the plurality of memory devices; an error correction operation, generating a corrected data segment by correcting errors in the test data using the error correction codes; a judgment operation, determining whether a miscorrection occurred in the corrected data segment when the error correction operation is successful; and a determination operation, determining whether the error correction method is successful or unsuccessful based on the number of times the judgment operation is performed as a result of repeating the test preparation operation, the error correction operation, and the judgment operation on each first data segment, and the result of the judgment operation.

[0011] According to this disclosure, in a memory system comprising multiple memory devices, by appropriately adjusting the timing and method of error detection operations such as parity check and cyclic redundancy check (CRC) and error correction operations such as Bose-Chaudhuri-Hocquenghem (BCH) code and Reed-Solomon (RS) code for data read from multiple memory devices, single-device data correction (SDDC) errors can be effectively detected and effectively corrected. SDDC errors indicate the phenomenon that errors are concentrated in a specific memory device among multiple memory devices. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating a memory system for performing an error correction process according to embodiments of the present disclosure.

[0013] Figure 2 This is a diagram illustrating data read from a plurality of memory devices included in a memory system according to embodiments of the present disclosure.

[0014] Figure 3 This is a diagram illustrating the error checking operations performed during an error correction process according to an embodiment of the present disclosure.

[0015] Figure 4A and Figure 4BThis is a diagram illustrating the test preparation operation and error correction operation performed by a memory system according to embodiments of the present disclosure.

[0016] Figure 5A and Figure 5B This is a diagram illustrating another test preparation operation and error correction operation performed by a memory system according to an embodiment of the present disclosure.

[0017] Figures 6A to 6D This is a flowchart illustrating the sequence of error correction processes performed by a memory system according to an embodiment of the present disclosure.

[0018] Figure 7A and Figure 7B This is a diagram illustrating the configuration of a memory system according to embodiments of the present disclosure. Detailed Implementation

[0019] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0020] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may be combined in the same embodiment or may not necessarily be combined in the same embodiment.

[0021] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components (e.g., interface units, circuitry, etc.).

[0022] In this disclosure, various units, circuits, or other components may be described or claimed to be “configured to” perform one or more tasks. In such a context, “configured to” is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, even when a specified block / unit / circuit / component is not currently in operation (e.g., not opened or activated), it can be said that the block / unit / circuit / component is configured to perform a task. Blocks / units / circuits / components used with the “configured to” language include hardware, such as circuits, memory storing program instructions executable to perform operations, etc. Additionally, “configured to” can include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the tasks in question. “Configured to” can also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) for performing or implementing one or more tasks.

[0023] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation of analog and / or digital circuits only); (b) a combination of circuits and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) a portion of processor / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit, such as a microprocessor or a portion of a microprocessor, which requires software or firmware for operation even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all uses of the term in this application, including in any claim. As a further example, as used in this application, the terms “circuit” or “logic” also cover an implementation of a processor (or multiple processors) or a portion of a processor and its accompanying software and / or firmware. For example, and if applicable to a particular claim element, the terms “circuit” or “logic” also cover integrated circuits for storage devices.

[0024] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for nouns following a term and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second value. Furthermore, while these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0025] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude additional factors that may influence the determination. That is, the determination may be based solely on these factors or at least partially on them. For example, the statement "A is determined based on B." While B is a factor influencing the determination of A in this case, such a statement does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0026] In this document, a data item, data entry, or data term can be a sequence of bits. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a sequence of bits. According to an embodiment, a data item may include discrete objects. According to another embodiment, a data item may include units of information within a data packet transmitted between two different components.

[0027] Figure 1 This is a diagram illustrating a memory system for performing an error correction process according to embodiments of the present disclosure.

[0028] Reference Figure 1 The memory system according to embodiments of the present disclosure includes a memory module 11 and a memory controller 12. Additionally, the memory controller 12 may include an error correction device 13.

[0029] Memory module 11 includes multiple memory devices 1 <a:j>In this case, data and error correction codes (not shown) are stored in multiple memory devices 1 <a:j>middle.

[0030] According to an embodiment, the memory module 11 includes a plurality of memory devices 1 <a:j>Each of these is a volatile memory device, such as static RAM (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM).

[0031] According to another embodiment, the memory module 11 includes a plurality of memory devices 1 <a:j>Each of these is a non-volatile memory device, such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).

[0032] Memory controller 12 controls the operation of memory module 11, i.e., multiple memory devices 1 <a:j>Each operation within it.

[0033] According to an embodiment, when multiple memory devices 1 <a:j>When each of the memory devices is a volatile memory device, the memory controller 12 controls the storage of data input from the outside into the multiple memory devices 1. <a:j>The write and read operations are stored in multiple memory devices 1 <a:j>Data reading operations within the system.

[0034] According to another embodiment, when multiple memory devices 1 <a:j>When each of the multiple memory devices is a non-volatile memory device, the memory controller 12, in addition to controlling write and read operations, further controls the deletion of data stored in the multiple memory devices 1. <a:j>The data erasure operation in the memory and in multiple memory devices 1 <a:j>Operations for moving or copying data between different data sources.

[0035] In addition, the error correction device 13 included in the memory controller 12 performs an error correction process on the data transmitted between the memory controller 12 and the memory module 11.

[0036] Specifically, the error correction device 13 includes an error correction encoder (not shown) and an error correction decoder (not shown). The error correction encoder encodes externally input data during a write operation to generate error correction codes, thereby allowing the error correction codes to be stored along with the externally input data in multiple memory devices 1. <a:j>The error correction code generated by the error correction encoder according to embodiments of the present disclosure is a product code formed by multiplying together a polynomial (generator polynomial) generated in response to either Bose-Chaudhuri-Hocquenghem (BCH) code or Reed-Solomon (RS) code, a polynomial generated in response to a parity check code, and a polynomial generated in response to a cyclic redundancy check (CRC) code. That is, the encoding operation performed by the error correction encoder according to embodiments of the present disclosure is the same as performing an encoding operation using either Bose-Chaudhuri-Hocquenghem (BCH) code or Reed-Solomon (RS) code, performing an encoding operation using a parity check code, or performing an encoding operation using a cyclic redundancy check (CRC) code. The method of generating a new code by multiplying multiple polynomials is a known technique and will not be described in detail here.

[0037] Additionally, the error correction decoder performs read operations on data from multiple memory devices 1 <a:j>The read data undergoes an error correction process. In this case, the error correction apparatus 13 according to an embodiment of the present disclosure performs an error correction process including an error checking operation 14, a test preparation operation 15, an error correction operation 16, a judgment operation 17, and a determination operation 18. In the error correction decoder, in the error checking operation 14 and the error correction operation 16, a decoding operation using either Bose-Chaudhuri-Hocquenghem (BCH) code or Reed-Solomon (RS) code, a decoding operation using a parity check code, and a decoding operation using a cyclic redundancy check (CRC) code are further performed.

[0038] The error correction decoder can check and correct errors in the controller 130 and memory device 1. <a:j>Errors in data transmitted between 150 or 160. According to embodiments, the error correction device 13 can be implemented as a separate module, circuit, or firmware within the controller 130, but it can also be located in the memory device 1. <a:j>Or implement in 150.

[0039] An error correction decoder may include all circuits, modules, systems and / or devices that perform error correction operations based on at least one of the codes described above.

[0040] More specifically, the error checking operation 14 performed by the error correction device 13 is the following operation: by utilizing the data stored in multiple memory devices 1 <a:j>Error correction codes in each memory device 1 <a:j>Multiple first data segments (not shown) are read and parity checks are performed to generate an error sum data segment (not shown).

[0041] Furthermore, the test preparation operation 15 performed by the error correction device 13 is as follows: based on the result of the error checking operation 14, a third data segment (not shown) is generated by performing a parity check operation between the error sum data segment and the second data segment (not shown), and then test data (not shown) is generated by replacing the second data segment with the third data segment. The second data segment (not shown) is one of a plurality of first data segments from a plurality of memory devices 1. <a:j>The data segment read by any target memory device.

[0042] Furthermore, the error correction operation 16 performed by the error correction device 13 is the following operation: by utilizing the multiple memory devices 1 <a:j>Error correction codes in the test data are used to correct errors to generate a correction data segment (not shown).

[0043] In addition, the judgment operation 17 performed by the error correction device 13 is as follows: when the error correction operation 16 is successful, it is determined whether a miscorrection has occurred in the correction data segment.

[0044] Furthermore, the determination operation 18 performed by the error correction device 13 is the following operation: based on the fact that it is used for multiple memory devices 1 <a:j>The results of the corresponding first data segment are used to repeat the test preparation operation 15, error correction operation 16 and judgment operation 17. The number of times the judgment operation 17 is executed and the result of the judgment operation 17 are used to determine whether the error correction process is successful or unsuccessful.

[0045] On the other hand, refer to Figure 7A and Figure 7B as well as Figure 1 , Figure 1 The memory controller 12 and multiple memory devices 1 shown <a:j>yes Figure 7A and Figure 7B Some components of the memory system 110 shown. That is, Figure 1 The memory controller 12 shown refers to Figure 7A and Figure 7B Among the various components included in the controller 130 of the memory system 110 shown, there are components for controlling the memory controller 12 and the plurality of memory devices 1. <a:j>The components that perform error correction processes on the data transmitted between them. Therefore, it can be seen that... Figure 1 The reference numerals 11 to 13 of the components shown are similarly included in the figures. Figure 7A and Figure 7B middle.

[0046] Specifically, the memory system 110 includes a memory device 150 or 1 <a:j>and controller 130.

[0047] Memory device 150 or 1 <a:j>The controller 130 and the memory device 150 are physically distinct components. <a:j>The controller 130 and the memory device 150 are functionally distinct components. <a:j>The controller 130 is connected via at least one data path. For example, the data path consists of a channel and / or a way. Additionally, the memory device 150 or 1 <a:j>The controller 130 is implemented via one or more semiconductor device chips. Where the memory system 110 requires high integration, the memory device 150 or 1... <a:j>The controller 130 consists of a semiconductor device chip.

[0048] Controller 130 controls memory device 150 or 1 in response to a request from host 102. <a:j>It performs operations such as reading, programming / writing, and erasing. Additionally, controller 130 controls memory device 150 or 1... <a:j>To operate the memory system 110 independently, regardless of requests from the host 102.

[0049] According to an embodiment, Figure 7A The memory device shown to be functionally distinct from the controller 130 of the memory system 110 is the non-volatile memory device 150. That is, Figure 7A Showing based on reference Figure 1 Multiple memory devices described 1 <a:j>It is an operation memory used for control operations of controller 130, multiple memory devices 1 <a:j>Included in controller 130. Multiple memory devices 1 <a:j>Each of them is a volatile memory device or a non-volatile memory device.

[0050] In this case, Figure 7A Among the components included in the controller 130 shown, the processor 134 and the error correction device 13 are related to the reference. Figure 1 The memory controller 12 is a component that is distinguished from the described components. Therefore, in the case of... Figure 7A In the memory system 110 with the structure shown, the error correction device 13 connects to multiple memory devices 1 via a data bus. <a:j>The data transmitted between each of them performs an error correction process.

[0051] According to another embodiment, Figure 7B The memory device shown to be functionally distinct from the controller 130 of the memory system 110 is referenced. Figure 1 Multiple memory devices described 1 <a:j>.Right now, Figure 7B Showing based on reference Figure 1 Multiple memory devices described 1 <a:j>The memory operates under the control of controller 12, and there are multiple memory devices 1. <a:j>Located external to controller 12. Multiple memory devices 1 <a:j>Each of them is a volatile memory device or a non-volatile memory device.

[0052] In this case, Figure 7B Among the components included in the controller 130 shown, the processor 134, the error correction device 13, and the memory interface 142 are consistent with the reference. Figure 1 The memory controller 12 is a component that is distinguished from the described components. Therefore, in the case of... Figure 7B In the memory system 110 with the structure shown, the error correction device 13 operates via a data path between the error correction device 13 and multiple memory devices 1. <a:j>The data transmitted between each of them, that is, the data transmitted through the channel or path, performs an error correction process.

[0053] According to an embodiment, when multiple memory devices 1 <a:j>When each of them is a volatile memory device, Figure 7B The controller 12 shown does not include a volatile memory device 144 internally used as operational memory, or although the controller 12 includes a volatile memory device 144, the controller 12 includes more than a plurality of memory devices 1 <a:j>Volatile memory devices that operate at higher speeds.

[0054] According to another embodiment, when multiple memory devices 1 <a:j>When each of them is a non-volatile memory device, Figure 7B The controller 12 shown includes a volatile memory device 144 that serves internally as operational memory.

[0055] According to yet another embodiment, Figure 7A and Figure 7B The memory system 110 shown is connected to the host 102 via a Computational High-Speed ​​Link (CXL) interface. The CXL interface is a PCIe-based interface designed to enable central processing units (CPUs), graphics processing units (GPUs), and various types of accelerators to utilize memory more efficiently. Figure 7A and Figure 7B The memory system 110 shown is connected to the host 102 via the CXL interface to increase the memory capacity of a computer system such as a data center or server, and to enable the processors within the computer system to share memory.

[0056] More specifically, the controller 130 according to embodiments of the present disclosure includes a host interface 132, a processor 134, a power management unit (PMU) 140, a memory interface 142, and an error correction device 13. The controller 130 further includes a plurality of memory devices 1 <a:j>Alternatively, volatile memory device 144 may be used as internal operating memory.

[0057] Both host 102 and memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, host interface 132 in memory system 110 may include devices capable of sending signals, data, etc. to host 102 or receiving signals, data, etc. from host 102.

[0058] The host interface 132 included in the controller 130 can receive signals, commands (or requests) and / or data input from the host 102 via a bus. For example, the host 102 and the memory system 110 can send and receive data between the host 102 and the memory system 110 using a set of predetermined rules or procedures for data communication or a preset interface.

[0059] Examples of communication standards or interfaces used for sending / receiving data can include various form factors such as 2.5-inch form factor, 1.8-inch form factor, MO-297, MO-300, M.2, and EDSFF (Enterprise and Data Center SSD form factor), as well as various communication standards or interfaces such as USB (Universal Serial Bus), MMC (Multimedia Card), PATA (Parallel Advanced Technology Accessory), SCSI (Small Computer System Interface), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), PCIe (Peripheral Component Interconnect), SAS (Serial Attached SCSI), SATA (Serial Advanced Technology Accessory), and MIPI (Mobile Industry Processor Interface).

[0060] According to an embodiment, host interface 132 is a layer for exchanging data with host 102, and is implemented using or driven by firmware called host interface layer (HIL). According to an embodiment, host interface 132 may include a command queue.

[0061] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and, for example, a cable including 40 wires connected in parallel can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be divided into master memory systems and slave memory systems by utilizing the positions or DIP switches to which the multiple memory systems 110 are connected. The memory system 110 configured as the master memory system can be used as the master memory device. IDE (ATA) can include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0062] The Serial Advanced Technology Accessory (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronics (IDE). The 40 pins of an IDE interface can be reduced to 6 pins in a SATA interface. For example, the 40 parallel signals of IDE can be converted to the 6 serial signals of a SATA interface. The SATA interface is widely used due to its high data transmission and reception rates and its low resource consumption for data transmission and reception within the host 102. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. Furthermore, the SATA interface supports hot-plugging, which allows external devices to be attached to or detached from the host 102 even while data communication is being performed between the host 102 and another device. Therefore, the memory system 110 can be connected or disconnected as an additional device, such as a device supported by Universal Serial Bus (USB), even when the host 102 is powered on. For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102 like an external hard drive.

[0063] Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI can provide high transfer speeds. In SCSI, host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between host 102 and each peripheral device can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from host 102. SCSI can support connections of up to 15 other devices to a single transceiver included in host 102.

[0064] Serial Connected SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed using a serial data communication scheme. SAS supports the connection between the host 102 and peripheral devices via serial cables instead of parallel cables, making it easier to manage devices using SAS and enhancing or improving operational reliability and communication performance. SAS can support connections of up to eight external devices to a single transceiver included in the host 102.

[0065] Non-volatile Memory High-Speed ​​(NVMe) is an interface based at least on Peripheral Component Interconnect High-Speed ​​(PCIe) designed to improve the performance and design flexibility of a host 102, server, computing device, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one line (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB / s or more (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). According to embodiments, PCIe schemes can achieve bandwidths from tens to hundreds of gigabits per second. NVMe can support non-volatile memory systems 110 such as SSDs with faster operating speeds than hard drives.

[0066] According to one embodiment, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be coupled to a single transceiver included in host 102.

[0067] exist Figure 7A In the case of the memory system 110 shown, the error correction device 13 performs error correction not only on the non-volatile memory device 150 disposed outside the controller 130, but also on the multiple memory devices 150 included in the controller 130. <a:j>Perform the error correction process.

[0068] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110, such as the voltage supplied to the controller 130, and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to enable the memory system 110 to perform an emergency backup of its current state when the power supply to the memory system 110 is unstable. According to an embodiment, the PMU 140 may include a device or component capable of accumulating power for use in emergency situations.

[0069] Memory interface 142 can be used for processing between controller 130 and memory device 1 <a:j>An interface for transmitting commands and data between or 150, allowing controller 130 to control memory device 1 in response to commands or requests input from host 102. <a:j>Or 150. In memory device 1 <a:j>In the case where 150 is flash memory, under the control of processor 134, memory interface 142 can generate memory device 1. <a:j>Or 150 control signals, and can process inputs to memory device 1 <a:j>Or 150 or from memory device 1 <a:j>Or the data output by 150.

[0070] For example, when memory device 1 <a:j>When 150 includes NAND flash memory, memory interface 142 includes a NAND flash memory controller (NFC). Memory interface 142 can provide communication between controller 130 and memory device 1. <a:j>Or an interface for commands and data between 150. According to an embodiment, the memory interface 142 may be implemented by firmware called the Flash Interface Layer (FIL) or driven by firmware called the Flash Interface Layer (FIL) for communication with the memory device 1. <a:j>Or exchange data with 150.

[0071] According to an embodiment, the memory interface 142 may support Open NAND Flash Memory Interface (ONFi), switching modes, etc., for use with the memory device 1. <a:j>Alternatively, 150 can be used for data input / output. For example, ONFi can use a data path (e.g., channel, path, etc.) that includes at least one signal line capable of supporting bidirectional transmission and reception in units of 8 bits or 16 bits of data. Controller 130 and memory device 1 <a:j>Data communication between 150 or more can be achieved through at least one interface of Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0072] The controller 130 includes multiple memory devices 1 that serve as operational memory. <a:j>The volatile memory device 144 stores data used to drive the memory system 110 and the controller 130. More specifically, the controller 130 includes multiple memory devices 1 serving as operational memory. <a:j>The volatile memory device 144 stores information when the controller 130 controls the external memory device 150 or 1 in response to a request from the host 102. <a:j>The data required for timely control.

[0073] Processor 134 can control all operations of memory system 110. For example, processor 134 can control memory device 1 in response to write or read requests input from host 102. <a:j>Or 150 programming operations or reading operations.

[0074] According to an embodiment, processor 134 can execute firmware to control programming or reading operations in memory system 110. Here, firmware may be referred to as a flash translation layer (FTL). (See also...) Figure 3 An example of FTL is described in detail in Figure 4. According to the embodiment, the processor 134 may be implemented using a microprocessor, a central processing unit (CPU), etc.

[0075] According to an embodiment, the memory system 110 may be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores that are considered distinct processing regions. For example, when multiple cores in a multi-core processor independently drive or execute multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an embodiment, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0076] Processor 134 controls the entire operation of memory system 110. Specifically, processor 134 controls memory device 1 in response to write or read requests from host 102. <a:j>The processor 134 can perform either programming or reading operations. The processor 134 drives firmware called the Flash Translation Layer (FTL) to control the general operation of the memory system 110. The processor 134 can be implemented by a microprocessor or a central processing unit (CPU).

[0077] For example, controller 130 in memory device 1 <a:j>Alternatively, the controller 130 executes the operation requested from the host 102. That is, the controller 130, via a processor 134 implemented by a microprocessor or central processing unit (CPU), communicates with the memory device 1. <a:j>Alternatively, controller 150 can execute command operations corresponding to commands received from host 102. Controller 130 can execute foreground operations such as command operations corresponding to commands received from host 102. For example, controller 130 can execute programming operations corresponding to write commands, reading operations corresponding to read commands, and erasing operations corresponding to erase commands.

[0078] The controller 130 can also execute the memory device 1 via a processor 134 implemented by a microprocessor or a central processing unit (CPU). <a:j>Or 150 background operations. Memory device 1 <a:j>Or, background operations of 150 may include transferring memory device 1 <a:j>The operation of copying data stored in one storage block to another within a storage block of 150, such as a garbage collection (GC) operation. Background operations can be included in memory device 1. <a:j>Operations that exchange data between one or more of the 150 memory blocks, such as wear leveling (WL) operations, read-reclaim (RR) operations, and media scan operations. Background operations may include storing mapped data retrieved from controller 130 in memory device 1. <a:j>Operations within a memory block of 150, such as a mapping clearing operation. Background operations may include memory device 1. <a:j>Or bad block management operations of 150, which may include operations on memory device 1 <a:j>Or check and process bad blocks among multiple storage blocks in 150.

[0079] The memory module 11 in the figure includes multiple memory devices 1 <a:j>The fact that the number is 10 is merely an example; in reality, fewer or more memory devices can be included as a single memory module 11. However, for convenience, multiple memory devices 1 are used as an example. <a:j>The quantity is 10, and the following description is given.

[0080] Figure 2 This is a diagram illustrating data read from a plurality of memory devices included in a memory system according to embodiments of the present disclosure.

[0081] Reference Figure 2 According to embodiments of the present disclosure, the memory system 110 respectively accesses the first to tenth memory devices 1 <a:j>Read 10 segments of the first data segment DATA1<1:10>.

[0082] Specifically, the first to tenth memory devices 1 <a:j>Each of the data devices 1 is read and output in one go via four data pads (DQ), totaling 64 bits, as a first data segment with a burst length of 16 (i.e., one of the first data segments DATA1<1:10>). That is, the first to tenth memory devices 1 <a:j>Read and output the first data segment DATA1<1:10>, which is a total of 640 bits.

[0083] As can be seen in the figure, the memory devices 1 from the first to the tenth are shown in matrix form. <a:j>The 10 first data segments DATA1<1:10> are read and output. That is, in the figure, each of the 10 first data segments DATA1<1:10> includes 64 bits of data, which are the four columns of 16 bits of data within the dashed lines.

[0084] More specifically, from the first to the tenth memory devices 1 <a:j>The 10 first data segments DATA1<1:10> read and output each include the target data requested to be read and an error correction code. The error correction code is obtained by writing the target data into the first to tenth memory devices 1. <a:j>This is data that is generated through error correction encoding operations and written along with the target data.

[0085] Figure 3 This is a diagram illustrating the error checking operations performed during an error correction process according to an embodiment of the present disclosure.

[0086] Reference Figure 3 Error checking operation 14 is performed during error correction in a memory system according to an embodiment of the present disclosure.

[0087] First, in the above Figure 2 In the middle, in the memory devices 1 from the first to the tenth respectively <a:j>An error bit appeared at an unknown location in any of the 10 first data segments DATA1<1:10> that were read.

[0088] In this case, in order to check whether errors have occurred in the 10 first data segments DATA1<1:10>, the error correction device 13 included in the memory system 110 generates an error sum data segment FS_DATA by performing a parity check operation on the 10 first data segments DATA1<1:10> using an error correction code that is part of the 10 first data segments DATA1<1:10>.

[0089] Specifically, as shown in the figure, an error occurs in bit data 8*2 of the second data pad. Bit data 8*2 is in the first block of DATA1 out of 10 first data segments DATA1<1:10>. <1> The output is in the eighth order with a burst length of 16.

[0090] As shown in the figure, an error occurred in bit data 15*1 of the first data pad. Bit data 15*1 is in the second block of DATA1 out of 10 first data segments DATA1<1:10>. <2> The output is in the fifteenth order of 16 burst length.

[0091] Further, as shown in the figure, errors occur in bit data 3*1 and 9*1 of the first data pad, bit data 5*2 of the second data pad, bit data 1*3 of the third data pad, and bit data 11*4 of the fourth data pad. Bit data 3*1 and 9*1 are in the sixth block of DATA1 out of the 10 first data segments DATA1<1:10>. <6> The data is output in the third and ninth order of 16 burst length, with 5*2 bits of data in the sixth block of DATA1 within the 10 first data segments DATA1<1:10>. <6> The data is output in the fifth order with a burst length of 16, and the 1*3 bits of data are in the sixth block of DATA1 within the 10 first data segments DATA1<1:10>. <6> The data is output in the first sequence with a burst length of 16, and the 11*4 bits of data are in the sixth block of DATA1 within the 10 first data segments DATA1<1:10>. <6> It is output in the eleventh order with a burst length of 16.

[0092] In this way, in the diagram, only the first block of DATA1 out of the 10 first data segments DATA1<1:10> is considered. <1> The second DATA1 <2> And the sixth DATA1 <6> Error bits appeared in one block, but not in the others. Specifically, the error bits were concentrated in the sixth block of DATA1 out of the ten first data segments DATA1<1:10>. <6> In the middle. That is, the error bits are concentrated from the first to the tenth memory devices 1. <a:j>The sixth memory device 1F reads and outputs the first data segment DATA1 <6> This can lead to an SDDC error state.

[0093] On the other hand, the error correction device 13 generates an error sum data segment FS_DATA by adding all the error bits generated from the 10 first data segments DATA1<1:10> through parity checking. That is, the error correction device 13 adds the error bits generated from the first block of DATA1<1:10> of the 10 first data segments DATA1<1:10>. <1> The second DATA1 <2> And the sixth DATA1 <6> The generated error bits are XORed to generate the error sum data segment FS_DATA. Therefore, errors occur in the bit data 3*1, 9*1, and 15*1 of the first data pad, the bit data 5*2 and 8*2 of the second data pad, the bit data 1*3 of the third data pad, and the bit data 11*4 of the fourth data pad. Bit data 3*1, 9*1, and 15*1 are output in the third, ninth, and fifteenth order of 16 burst length within the 64 bits distinguished by the error sum data segment FS_DATA; bit data 5*2 and 8*2 are output in the fifth and eighth order of 16 burst length within the 64 bits distinguished by the error sum data segment FS_DATA; bit data 1*3 is output in the first order of 16 burst length within the 64 bits distinguished by the error sum data segment FS_DATA; and bit data 11*4 is output in the eleventh order of 16 burst length within the 64 bits distinguished by the error sum data segment FS_DATA.

[0094] In this case, only during the parity check operation that generates the error summation data segment FS_DATA can it be determined that all 10 memory devices 1 <a:j>Whether an error occurred and the entire error pattern that occurred, but it is impossible to determine all 10 memory devices 1 <a:j>This includes the number of error bits and their locations.

[0095] Therefore, the error correction device 13 further performs a first initial determination operation on the 10 first data segments DATA1<1:10> separately from the operation of generating the error sum data segment FS_DATA to check how many error bits are included in all 10 first data segments DATA1<1:10> and the position of the generated error bits, and determines whether the error correction process is successful based on the check result. In this case, the error correction device 13 performs an error detection operation on the 10 first data segments DATA1<1:10> using the error correction code, which is part of the 10 first data segments DATA1<1:10>.

[0096] That is, the error correction device 13 performs an error checking operation 14 during the error correction process, and then selectively performs an error detection operation to check all the first to tenth memory devices 1. <a:j>The process includes a first initial determination operation, which determines the number of error bits and the location of the generated error bits. Additionally, based on the result of the first initial determination operation, the error correction device 13 selects whether to perform the remaining operations after the error checking operation 14 during the error correction process, namely, the test preparation operation 15, the error correction operation 16, the judgment operation 17, and the determination operation 18.

[0097] According to an embodiment, when an error detection operation is performed on all first to tenth memory devices 1 <a:j>When the number of error bits generated is less than the set number, and the generated error bits are not concentrated in a specific memory device, the error correction device 13 may not execute the remaining operations in the error correction process after performing the error checking operation 14, namely the test preparation operation 15, error correction operation 16, judgment operation 17, and determination operation 18. That is, the error correction device 13 may determine that the error correction process is successful and output the 10 first data segments DATA1<1:10> as read data as is. In the case shown in the figure, the set number can be three, but this is just an embodiment and can be changed to any other value.

[0098] According to another embodiment, when an error detection operation is performed on all first to tenth memory devices 1 <a:j>When the number of error bits generated is less than the set number, but the positions of the generated error bits are concentrated in a specific memory device, the error correction device 13 performs the remaining operations in the error correction process after performing the error checking operation 14, namely the test preparation operation 15, the error correction operation 16, the judgment operation 17, and the determination operation 18.

[0099] Error detection operations are performed using either Bose-Chaudhuri-Hocquenghem (BCH) codes or Reed-Solomon (RS) codes, as well as cyclic redundancy check (CRC), but error detection operations are not limited to these.

[0100] Figure 4A and Figure 4B This is a diagram illustrating the test preparation operation and error correction operation performed by a memory system according to embodiments of the present disclosure.

[0101] Reference Figure 4A and Figure 4B As can be seen, the test preparation operation 15 and the error correction operation 16 are performed in the error correction process of the memory system according to embodiments of the present disclosure. Specifically, it can be seen that the first to tenth memory devices 1 are selected. <a:j>The first memory device 1A is used as the target memory device and performs test preparation operation 15 and error correction operation 16.

[0102] Specifically, refer to Figure 4A The error correction device 13 reads the first block of DATA1 from 10 first data segments DATA1<1:10> and from the first memory device 1A. <1> It is set as the second data segment DATA2. In addition, the error correction device 13 generates the third data segment DATA3 by performing a parity check operation between the second data segment DATA2 and the error sum data segment FS_DATA.

[0103] First, as referenced Figure 2 and Figure 3 The first block of DATA1, which is derived from 10 first data segments DATA1<1:10> and read from the first memory device 1A and set as the second data segment DATA2, is... <1> The 64 bits may contain errors in bit data 8*2 of the second data pad, which is output in the eighth order of a 16-burst length. Additionally, in the 64-bit data segment FS_DATA, which is classified as the error summation data segment, errors occur in bit data 3*1, 9*1, and 15*1 of the first data pad, bit data 5*2 and 8*2 of the second data pad, bit data 1*3 of the third data pad, and bit data 11*4 of the fourth data pad. Bit data 3*1, 9*1, and 15*1 are output in the third, ninth, and fifteenth order of a 16-burst length; bit data 5*2 and 8*2 are output in the fifth and eighth order of a 16-burst length; bit data 1*3 is output in the first order of a 16-burst length; and bit data 11*4 is output in the eleventh order of a 16-burst length.

[0104] When parity checking is performed between the second data segment DATA2 and the error sum data segment FS_DATA, overlapping error bits are removed, leaving only the other error bits. Therefore, in the 64-bit data set as the third data segment DATA3, errors occur in bits 3*1, 9*1, and 15*1 of the first data pad, bit 5*2 of the second data pad, bit 1*3 of the third data pad, and bit 11*4 of the fourth data pad. Bits 3*1, 9*1, and 15*1 are output in the third, ninth, and fifteenth order of a 16-burst length; bit 5*2 is output in the fifth order of a 16-burst length; bit 1*3 is output in the first order of a 16-burst length; and bit 11*4 is output in the eleventh order of a 16-burst length. That is, the third data segment DATA3 is generated using only the error bits 3*1, 9*1, 15*1, 5*2, 1*3 and 11*4 included in the error sum data segment FS_DATA, excluding the bit data that overlaps with the second data segment DATA2, i.e. the bit data 8*2 of the second data pad. The bit data 8*2 is output in the eighth order with a burst length of 16.

[0105] After generating the third data segment DATA3, the error correction device 13 replaces the first block of DATA1, which is one of the ten first data segments DATA1<1:10>, with the third data segment DATA3. <1> The second data segment DATA2 is used to generate the test data DATA_TAR.

[0106] In summary, the error correction device 13 corrects the first block of DATA1 out of the 10 first data segments DATA1<1:10>. <1> Set as the second data segment DATA2, generate the third data segment DATA3 by performing a parity check operation between the second data segment DATA2 and the error sum data segment FS_DATA, and then replace the first block of DATA1 in the 10 first data segments DATA1<1:10> with the third data segment DATA3. <1> The second data segment DATA2 is used to generate the test data DATA_TAR.

[0107] In this case, the 10 first data segments DATA1<1:10> are 640 bits each, and the first block of DATA1 is set as the second data segment DATA2. <1> The length is 64 bits. Furthermore, the error correction device 13 generates 640-bit test data DATA_TAR by replacing 64 bits of the second data segment DATA2 in the ten 640-bit first data segments DATA1<1:10> with the 64-bit third data segment DATA3. Therefore, when the ten first data segments DATA1<1:10> are compared with the test data DATA_TAR, only the 64-bit data where the second data segment DATA2 is replaced by the third data segment DATA3 is different; the remaining 576 bits are identical.

[0108] After the first memory device 1A is selected as the target memory device, the test data DATA_TAR generated by performing test preparation operation 15 includes all error bits 3*1, 9*1, 15*1, 5*2, 1*3, and 11*4 included in the third data segment DATA3, and error bits 15*1, 3*1, 9*1, 5*2, 1*3, and 11*4 included in the second and sixth blocks DATA1<2,6> of the ten first data segments DATA1<1:10>. That is, after the first memory device 1A is selected as the target memory device, the test data DATA_TAR generated by performing test preparation operation 15 includes 12 error bits, where 12 is a larger number than 7, which is the number of error bits included in the ten first data segments DATA1<1:10> before performing test preparation operation 15.

[0109] Reference Figure 4B After the first memory device 1A is selected as the target memory device, the error correction device 13 performs an error correction operation 16 on the test data DATA_TAR generated by performing the test preparation operation 15. In this case, as shown in the reference... Figure 4A The test data DATA_TAR includes 12 error bits, which may be a larger number than the number used to determine whether the error correction operation was successful or failed. Therefore, in the result of the error correction device 13 performing the error correction operation 16 on the test data DATA_TAR including the 12 error bits, the error correction is determined to have failed. In this way, since the error correction operation 16 has been determined to have failed, the error correction device 13 cannot generate the correction data segment (not shown) that is generated as a result of the error correction operation 16. Therefore, the error correction device 13 may not perform the judgment operation 17, which is the operation performed on the correction data segment during the error correction process.

[0110] Figure 5A and Figure 5B This is a diagram illustrating another test preparation operation and error correction operation performed by a memory system according to an embodiment of the present disclosure.

[0111] Reference Figure 5A and Figure 5B It can be seen that another test preparation operation 15 and error correction operation 16 are performed in the error correction process of the memory system according to an embodiment of the present disclosure. In particular, it can be seen that the first to tenth memory devices 1 are selected. <a:j>The sixth memory device 1F is used as the target memory device and performs test preparation operation 15 and error correction operation 16.

[0112] Specifically, refer to Figure 5A The error correction device 13 will read the sixth block of DATA1 from the 10 first data segments DATA1<1:10> and from the sixth memory device 1F. <6> It is set as the second data segment DATA2. In addition, the error correction device 13 generates the third data segment DATA3 by performing a parity check operation between the second data segment DATA2 and the error sum data segment FS_DATA.

[0113] First, as referenced Figure 2 and Figure 3 The sixth block of DATA1, which is derived from 10 first data segments DATA1<1:10> and read from the sixth memory device 1F and set as the second data segment DATA2, is... <6> The 64 bits may contain errors in bit data 3*1 and 9*1 of the first data pad, bit data 5*2 of the second data pad, bit data 1*3 of the third data pad, and bit data 11*4 of the fourth data pad. Bit data 3*1 and 9*1 are output in the third and ninth order of 16 burst length, bit data 5*2 is output in the fifth order of 16 burst length, bit data 1*3 is output in the first order of 16 burst length, and bit data 11*4 is output in the eleventh order of 16 burst length. Additionally, in the 64-bit data segment FS_DATA, which is classified as the total error data segment, errors occurred in the bit data 3*1, 9*1, and 15*1 of the first data pad, the bit data 5*2 and 8*2 of the second data pad, the bit data 1*3 of the third data pad, and the bit data 11*4 of the fourth data pad. Bit data 3*1, 9*1, and 15*1 were output in the third, ninth, and fifteenth order of the 16-burst length, bit data 5*2 and 8*2 were output in the fifth and eighth order of the 16-burst length, bit data 1*3 was output in the first order of the 16-burst length, and bit data 11*4 was output in the eleventh order of the 16-burst length.

[0114] When parity checking is performed between the second data segment DATA2 and the error sum data segment FS_DATA, overlapping error bits are removed, leaving only the other error bits. Therefore, in the 64-bit data set as the third data segment DATA3, errors occur in bit data 15*1 of the first data pad and bit data 8*2 of the second data pad. Bit data 15*1 is output in the fifteenth order of a 16-burst length, and bit data 8*2 is output in the eighth order of a 16-burst length. That is, the third data segment DATA3 is generated using only the error bits included in the total error data segment FS_DATA, excluding the bit data that overlaps with the second data segment DATA2, namely the bit data 3*1 and 9*1 of the first data pad, the bit data 5*2 of the second data pad, the bit data 1*3 of the third data pad, and the bit data 11*4 of the fourth data pad. The bit data 3*1 and 9*1 are output in the third and ninth order of the 16-burst length, the bit data 5*2 is output in the fifth order of the 16-burst length, the bit data 1*3 is output in the first order of the 16-burst length, and the bit data 11*4 is output in the eleventh order of the 16-burst length.

[0115] After generating the third data segment DATA3, the error correction device 13 replaces the sixth block of DATA1, which is one of the ten first data segments DATA1<1:10>, with the third data segment DATA3. <6> The second data segment DATA2 is generated, and test data DATA_TAR is generated.

[0116] In summary, the error correction device 13 corrects the error in the sixth block of DATA1 out of the ten first data segments DATA1<1:10>. <6> Set as the second data segment DATA2, generate the third data segment DATA3 by performing a parity check operation between the second data segment DATA2 and the error sum data segment FS_DATA, and then replace the sixth block of DATA1 in the 10 first data segments DATA1<1:10> with the third data segment DATA3. <6> The second data segment DATA2 is used to generate the test data DATA_TAR.

[0117] In this case, the 10 first data segments DATA1<1:10> are 640 bits, and the sixth block of DATA1 is set as the second data segment DATA2. <6> The length is 64 bits. Furthermore, the error correction device 13 generates 640-bit test data DATA_TAR by replacing 64 bits of the second data segment DATA2 in the ten 640-bit first data segments DATA1<1:10> with the 64-bit third data segment DATA3. Therefore, when the ten first data segments DATA1<1:10> are compared with the test data DATA_TAR, only the 64-bit data where the second data segment DATA2 is replaced by the third data segment DATA3 is different; the remaining 576 bits are identical.

[0118] After the sixth memory device 1F is selected as the target memory device, the test data DATA_TAR generated by performing test preparation operation 15 includes all error bits 15*1 and 8*2 included in the third data segment DATA3, and error bits 15*1 and 8*2 included in the first and second segments DATA1<1,2> ​​of the ten first data segments DATA1<1:10>. That is, after the sixth memory device 1F is selected as the target memory device, the test data DATA_TAR generated by performing test preparation operation 15 includes 4 error bits, 4 being a number smaller than 7, which is the number of error bits included in the ten first data segments DATA1<1:10> before performing test preparation operation 15.

[0119] Reference Figure 5B After the sixth memory device 1F is selected as the target memory device, the error correction device 13 performs an error correction operation 16 on the test data DATA_TAR generated by performing the test preparation operation 15. In this case, as referred to Figure 5A The test data DATA_TAR includes 4 error bits, where 4 may be a smaller number than the number used to determine whether the error correction operation was successful or failed. Therefore, as a result of the error correction device 13 performing the error correction operation 16 on the test data DATA_TAR including the 4 error bits, the error correction is determined to be successful. In this way, since the error correction operation 16 has been determined to be successful, the error correction device 13 is able to generate a correction data segment (not shown) as a result of the error correction operation 16. Therefore, the error correction device 13 performs a judgment operation 17 as an operation performed on the correction data segment during the error correction process.

[0120] In this case, the determination operation 17 determines whether a miscorrection has occurred in the correction data segment generated by the successful error correction operation 16 on the test data DATA_TAR. That is, although it is confirmed that the error correction operation 16 was performed on the test data DATA_TAR and the error correction was successful, a miscorrection that did not actually correct the error may occur. The error correction apparatus 13 according to an embodiment of the present disclosure can determine whether a miscorrection has occurred by performing the determination operation 17 on the correction data segment.

[0121] More specifically, the error correction device 13 performs a judgment operation 17 on the correction data segment that has been confirmed to have successfully undergone error correction operation 16 in the following order.

[0122] First, the error correction device 13 performs the following first judgment operation: it performs a parity check operation on the correction data segment using the error correction code, and determines that the result of the parity check operation without any error is a success. In this case, when no miscorrection occurs in the error correction operation 16, no error bit should be generated in the result of the parity check operation on the correction data segment.

[0123] In addition, the error correction device 13 performs the following second judgment operation: it determines success if the number of successfully corrected bits in the remaining data of the correction data segment, excluding the data corresponding to the target memory device, is equal to or less than the reference number. For example, in... Figure 5A and Figure 5B In the test data DATA_TAR, there are a total of 4 error bits, and the third data segment DATA3 corresponding to the sixth memory device 1F selected as the target memory device includes 2 error bits. Therefore, the error correction device 13 performs the following operation as a second judgment operation: checking whether the remaining 2 error bits in the data DATA1<1:5,7:10>, excluding the 2 error bits in the third data segment DATA3 corresponding to the target memory device, are equal to or less than a reference number. The reference number can be set to a value corresponding to half of the maximum number of error bits that can be successfully corrected in the error correction operation 16. For example, when the maximum number of error bits that can be successfully corrected in the error correction operation 16 is 10, the reference number can be set to 5.

[0124] When it is determined that both the first judgment operation and the second judgment operation are successful, the error correction device 13 determines that no miscorrection has occurred in the correction data segment.

[0125] When it is determined that either the first judgment operation or the second judgment operation has failed, the error correction device 13 determines that a miscorrection has occurred in the correction data segment.

[0126] The error correction device 13 can simultaneously perform the first judgment operation and the second judgment operation, or perform one operation first and then perform the other operation.

[0127] In summary, as referenced Figure 4A , Figure 4B , Figure 5A and Figure 5B The error correction device 13 selects 10 memory devices 1 <a:j>Each of them serves as the target memory device, performs test preparation operation 15 and error correction operation 16, and selectively performs judgment operation 17 based on the results of test preparation operation 15 and error correction operation 16.

[0128] That is, as referenced Figure 4A and Figure 4B The error correction operation 16 is performed on the test data DATA_TAR generated as a result of the test preparation operation 15. However, if the error correction operation fails because the test data DATA_TAR contains more error bits than the reference number, the error correction device 13 may not perform the judgment operation 17.

[0129] Conversely, as referenced Figure 5A and Figure 5B As a result of performing error correction operation 16 on the test data DATA_TAR generated as a result of test preparation operation 15, when the test data DATA_TAR contains fewer error bits than the reference number and the error correction operation is successful, the error correction device 13 performs judgment operation 17.

[0130] In this case, the error correction device 13 selects 10 memory devices 1 one by one in a predetermined order. <a:j>Each of these is considered as the target memory device, regardless of whether decision operation 17 is performed. Therefore, decision operation 17 can be performed at most ten times, or even not at all.

[0131] That is, the error correction device 13 can perform the following determining operation 18: selecting 10 memory devices one by one in a predetermined order. <a:j>Each of the targets is treated as a target memory device. The test preparation operation 15 and the error correction operation 16 are executed ten times. Based on the results of the ten repetitions of the test preparation operation 15 and the error correction operation 16, the judgment operation 17 is executed from a minimum of zero times to a maximum of ten times. Then, based on the number of times the judgment operation 17 is executed and the result of the executed judgment operation 17 (whether a miscorrection occurred), it is determined whether the error correction process is successful or unsuccessful.

[0132] More specifically, when 10 memory devices 1 <a:j>Each of the selected target memory devices performs at least two judgment operations 17 when the test preparation operation 15 and error correction operation 16 are repeated ten times. If no miscorrection is found in one of the at least two judgment operations 17, the error correction device 13 may perform a determination operation 18 to determine that the error correction process is successful.

[0133] Additionally, when 10 memory devices 1 <a:j>Each of the selected target memory devices performs a judgment operation 17 once when the test preparation operation 15 and error correction operation 16 are repeated ten times. If no miscorrection occurs in the judgment operation 17, the error correction device 13 can perform a determination operation 18 to determine that the error correction process is successful.

[0134] Additionally, when 10 memory devices 1 <a:j>Each of the devices is selected as the target memory device. If the test preparation operation 15 and the error correction operation 16 are repeated ten times, at least two judgment operations 17 are performed. If it is determined that no miscorrection has occurred in all at least two judgment operations 17, the error correction device 13 can perform an operation to compare at least two correction data segments generated in each of the at least two error correction operations 16 corresponding to the at least two judgment operations 17 performed, and determine whether the error correction process is successful or unsuccessful based on the comparison result.

[0135] When, as a result of comparison, at least two correction data segments generated from at least two error correction operations 16, corresponding to at least two judgment operations 17 performed without miscorrection, have the same value, the error correction device 13 may perform a determination operation 18 to determine that the error correction process was successful.

[0136] When, as a result of comparison, at least one of the at least two correction data segments generated from at least two error correction operations 16, which correspond to at least two judgment operations 17 performed without miscorrection, has a different value, the error correction device 13 may perform a determination operation 18 to determine that the error correction process has failed.

[0137] Additionally, when 10 memory devices 1 <a:j>Each of them is selected as the target memory device, and if the test preparation operation 15 and the error correction operation 16 are repeated ten times, and the judgment operation 17 is not executed even once, the error correction device 13 can execute the determination operation 18 to determine that the error correction process has failed.

[0138] Additionally, when 10 memory devices 1 <a:j>Each of the selected target memory devices, when the test preparation operation 15 and error correction operation 16 are repeated ten times, when the judgment operation 17 is executed at least once, and when it is determined that a miscorrection has occurred in the judgment operation 17 executed at least once, the error correction device 13 may execute the determination operation 18 to determine that the error correction process has failed.

[0139] On the other hand, after performing error checking operation 14, in reference Figure 4A , Figure 4B , Figure 5A and Figure 5B The description describes the execution selection of 10 memory devices 1 <a:j>Before selecting 10 memory devices as target memory devices and repeating the test preparation operation 15 and error correction operation 16 ten times, as well as the judgment operation 17 / determination operation 18, the error correction device 13 performs the following steps: <a:j>Each of them is used as a target memory device, and the second initial determination operation, which repeats the test preparation operation 15 and the error detection operation ten times, is used to determine whether the error correction process is successful.

[0140] That is, after performing error checking operation 14 during the error correction process, the error correction device 13 selectively performs the operation by selecting 10 memory devices 1 <a:j>Each of them is used as the target memory device and the test preparation operation 15 and the error detection operation are repeated ten times to determine whether the error correction process is successful in the second initial determination operation.

[0141] Specifically, each time the error correction device 13 selects 10 memory devices 1 <a:j>When each of the target memory devices is used and test preparation operation 15 is performed, error correction device 13 generates test data DATA_TAR, and then performs error detection operation on the generated test data DATA_TAR to check the total number of generated error bits and the position of the generated error bits. In this case, error correction device 13 performs error detection operation on test data DATA_TAR by utilizing error correction codes that are part of test data DATA_TAR.

[0142] That is, the error correction device 13 checks the total number and position of each generated error bit in the 10 test data DATA_TAR through ten test preparation operations 15 and error detection operations.

[0143] Furthermore, when the error correction device 13 performs an error detection operation on each of the 10 test data DATA_TARs, and in at least one of the 10 results checked, the total number of generated error bits is less than a set number and the locations of the generated error bits are not concentrated in a specific memory device, the error correction device 13 may not perform the reference operation. Figure 4A , Figure 4B , Figure 5A and Figure 5B The description selects 10 memory devices 1 <a:j>Each of the data points is used as a target memory device, and the test preparation operation 15 and error correction operation 16 are repeated ten times, along with the judgment operation 17 / determination operation 18. That is, the error correction device 13 can determine that the error correction process is successful, and output any test data DATA_TAR in the 10 test data DATA_TARs where the total number of error bits generated in the error detection operation is less than a set number and the positions of the generated error bits are not concentrated in a specific memory device as read data.

[0144] Additionally, after performing error checking operation 14 during the error correction process, the reference is executed. Figure 4A , Figure 4B , Figure 5A and Figure 5B The description selects 10 memory devices 1 <a:j>Before each of the target memory devices is tested and the preparation operation 15 and error correction operation 16 are repeated ten times, and before the judgment operation 17 / determination operation 18, the error correction device 13 performs the reference... Figure 3 The first initial determination operation is described, and a second initial determination operation is performed if the error correction process is not determined to be successful. Of course, even if the error correction process is not determined to be successful by performing the first initial determination operation, the error correction device 13 may not perform the second initial determination operation. Alternatively, the error correction device 13 may not perform either the first or second initial determination operation.

[0145] Figures 6A to 6D This is a flowchart illustrating the sequence of error correction processes performed by a memory system according to an embodiment of the present disclosure.

[0146] Reference Figures 6A to 6D This illustrates a memory system 110 according to an embodiment of the present disclosure, which includes memory devices 110 from the first to the tenth memory devices 110 respectively. <a:j>The order in which the error correction process is executed on the 10 first data segments DATA1<1:10> read.

[0147] Reference Figure 6A The first to tenth memory devices 1 included in the memory system 110 <a:j>Read 10 first data segments DATA1<1:10> (S10).

[0148] The error sum data segment FS_DATA is generated by performing a parity check operation on the 10 first data segments DATA1<1:10> read in S10 (S20). That is, error checking operation 14 is performed to generate the error sum data segment FS_DATA by performing a parity check operation on the 10 first data segments DATA1<1:10> using the error correction code as part of the 10 first data segments DATA1<1:10> read in S10.

[0149] After generating the error summation data segment FS_DATA in S20, the first initial determination operation (S30) is selectively performed. The specific operation of the first initial determination operation can be referred to... Figure 6C Therefore, it will be described below.

[0150] After generating the error summation data segment FS_DATA in S20 or performing the first initial determination operation in S30, a second initial determination operation (S40) is selectively performed. The specific operation of the second initial determination operation can be referred to... Figure 6D Therefore, it will be described below.

[0151] In S20, an error summation data segment FS_DATA is generated. In S30, a first initial determination operation is performed, or in S40, a second initial determination operation is performed, after which 10 memory devices are selected. <a:j>Each of the targets is treated as a target memory device, and the test preparation operation 15 and the error correction operation 16 are executed ten times. Based on the result of the error correction operation 16, the judgment operation 17 (S50, S61, S62, S63, S70, S80, S90, S100 and S85) are selectively repeated.

[0152] Specifically, it will be used to select 10 memory devices 1 <a:j>One of the variables N, which is the target memory device, is set to 1 (S50). That is, 10 memory devices are selected. <a:j>The first memory device 1A in the memory is used as the target memory device.

[0153] From S50 in the first to tenth memory devices 1 <a:j>The first data DATA1 read from the selected target memory device <n>Set as the second data segment DATA2 (S61). For example, since N is set to 1 in S50, the first data segment DATA1 read from the first memory device 1A can be... <1> Set it to the second data segment DATA2.

[0154] The third data segment DATA3 is generated by performing a parity check operation between the second data segment DATA2 set in S61 and the error summation data segment FS_DATA generated in S20 (S62).

[0155] By replacing the Nth first data DATA1 in the 10 first data segments DATA1<1:10> with the third data segment DATA3 generated in S62. <n>To generate test data DATA_TAR (S63).

[0156] The aforementioned S61 to S63 can correspond to test preparation operation 15.

[0157] Errors in the test data DATA_TAR generated in S63 are corrected using error correction codes (S70). The error correction codes are part of the test data DATA_TAR generated in S63.

[0158] The aforementioned S70 can correspond to error correction operation 16.

[0159] Check whether the error correction operation performed on the test data DATA_TAR in S70 was successful or failed (S80).

[0160] When the error correction operation fails in S80 (no in S80), the value of N is increased by 1 (S85), and the aforementioned S61, S62, S63, S70 and S80 are repeated.

[0161] When the error correction operation in S80 is successful (Yes in S80), judgment operation 17 (S90) is performed on the correction data segment generated by the successful error correction operation in S80. Judgment operation 17 determines whether a miscorrection operation occurred in the correction data segment generated by the successful error correction operation 16 on the test data DATA_TAR. Since judgment operation 17 has already referenced... Figure 5A and Figure 5B It has been described, so its detailed description is omitted.

[0162] Regardless of whether the judgment operation 17 performed in S90 succeeds or fails, the value of N is checked to see if it reaches 10 (S100). The reason for checking if the value of N reaches 10 is because the number of multiple memory devices shown in this disclosure is 10, and the value of N is changed by setting it to 1 in S50 and then incrementing it by 1 in S85. That is, this is because the method of sequentially increasing the value of N from 1 to 10 selects the first to tenth memory devices 1 one by one. <a:j>Each of these is considered a target memory device. In this disclosure, the first to tenth memory devices are selected sequentially using the value of N. <a:j>Each of the methods described above as targeting memory devices is merely an example; in practice, any other method could be used.

[0163] If N does not reach 10 in S100 (no in S100), the value of N can be increased by 1 (S85), and then the above steps S61, S62, S63, S70, S80, S90 and S100 are repeated.

[0164] When N reaches 10 in S100 (is in S100), the test preparation operation 15 and the error correction operation 16 have been repeated ten times through the aforementioned S50, S61, S62, S63, S70, S80, S90 and S100. Then, by checking the number of times the judgment operation 17, which is selectively executed based on the result of the error correction operation 16, has actually been executed and the result of the executed judgment operation 17, the determination operation 18 (S110) is executed to determine whether the error correction process is successful or unsuccessful.

[0165] Reference Figure 6B You can see in Figure 6A In what order are the determined operations 18 performed in S110?

[0166] first, Figure 6A The execution point of S110 can be the point in S50, S61, S62, S63, S70, S80, S90 and S100 where the test preparation operation 15 and error correction operation 16 have been repeated ten times. Then, based on the result of error correction operation 16, it is determined that operation 17 has been executed at least zero times and at most ten times.

[0167] Therefore, in Figure 6B In the process, at the time point of execution S110, it is checked whether the number of times the judgment operation 17 is executed exceeds 1 (S111).

[0168] When the number of times the judgment operation 17 is executed in S111 does not exceed 1, that is, when the judgment operation 17 is executed only once (no in S111), check whether a miscorrection has occurred in the judgment operation 17 that is executed only once (S112).

[0169] If a miscalibration occurs in S112 (S112 is "Yes"), the error calibration process can be determined to have failed (S114). When the error calibration process is determined to have failed, an information indicating the failure of the error calibration process is output instead of reading data.

[0170] If no miscorrection occurs in S112 (no in S112), the error correction process is determined to be successful, and the correction data segment without miscorrection is output as read data (S113).

[0171] When the number of times the judgment operation 17 is executed in S111 exceeds 1, that is, when the judgment operation 17 is executed at least twice (yes in S111), check whether the number of judgment operations 17 that did not have miscorrection among the judgment operations 17 executed at least twice is 1 or less (S115).

[0172] When the number of judgment operations 17 in S115 that do not result in miscorrection is 1 or less (yes in S115), the error correction process is determined to be successful, and the correction data segment corresponding to the judgment operation 17 in which no miscorrection occurred in the at least two judgment operations 17 is executed is output as read data (S116).

[0173] When the number of judgment operations 17 that do not result in miscorrection in at least two judgment operations 17 performed in S115 exceeds 1 (no in S115), check whether the at least two correction data segments corresponding to the at least two judgment operations 17 that did not result in miscorrection are the same (S117).

[0174] When at least two correction data segments corresponding to at least two judgment operations 17 in S117 that did not result in miscorrection are the same (yes in S117), the error correction process is determined to be successful, and one of the at least two correction data segments corresponding to at least two judgment operations 17 in which no miscorrection occurred is output as read data (S118).

[0175] If at least two correction data segments corresponding to at least two judgment operations 17 in S117 that did not result in miscorrection are not the same (no in S117), the error correction process is judged to have failed (S119). When the error correction process is judged to have failed, a message indicating the failure of the error correction process is output instead of reading data.

[0176] Reference Figure 6C It can be seen that when in Figure 6A In S20, the error summation data segment FS_DATA is generated. Then, when the first initial determination operation is performed, in what order are the first initial determination operations executed?

[0177] First, when the first initial determination operation is initiated in S30, it can be compared with... Figure 6A In S20, the error summation data segment FS_DATA is generated, and error detection operations are performed separately on the 10 first data segments DATA1<1:10> (S31). The error detection operation is performed using the error correction code, which is part of the 10 first data segments DATA1<1:10>.

[0178] Check if an error occurred during the error detection operation performed in S31 (S32).

[0179] If no error occurs in S32 (no error in S32), the error correction process is determined to be successful, and the 10 first data segments DATA1<1:10> are output as read data as is (S45).

[0180] If an error occurs in S32 (indicated by "Yes" in S32), the remaining operations of the error correction process continue. That is, the following steps are executed: Figure 6A The S40 follows the S30.

[0181] Reference Figure 6D It can be seen that when the second initial determination operation is performed after the error summation data segment FS_DATA is generated in S20, or when the first initial determination operation is started in S30, the second initial determination operation is performed in what order.

[0182] First, when the second initial determination operation is initiated in S40, it will be used to select 10 memory devices 1 <a:j>One of the variables N, which is the target memory device, is set to 1 (S41). That is, 10 memory devices are selected. <a:j>The first memory device 1A in the memory is used as the target memory device.

[0183] From S41 in the first to tenth memory devices 1 <a:j>The first data DATA1 read from the selected target memory device <n>Set as the second data segment DATA2 (S42). For example, since N is set to 1 in S41, the first data segment DATA1 read from the first memory device 1A can be... <1> Set it to the second data segment DATA2.

[0184] The third data segment DATA3 is generated by performing a parity check operation between the second data segment DATA2 set in S42 and the error summation data segment FS_DATA generated in S20 (S43).

[0185] By replacing the Nth first data DATA1 in the 10 first data segments DATA1<1:10> with the third data segment DATA3 generated in S43. <n>To generate test data DATA_TAR (S44).

[0186] The above S42 to S44 can correspond to test preparation operation 15.

[0187] An error detection operation is performed on the test data DATA_TAR generated in S44 (S45). The error detection operation is performed using the error correction code, which is part of the test data DATA_TAR.

[0188] Regardless of the result of the error detection operation in S45, i.e., regardless of whether an error occurred in the test data DATA_TAR, check whether the value of N reaches 10 (S46).

[0189] When N is not 10 in S46 (it is not in S46), the value of N is increased by 1 (S47), and then the aforementioned S42 to S46 are repeated. The reason for checking whether the value of N reaches 10 is because the number of multiple memory devices shown in this disclosure is 10, and the value of N is changed by setting it to 1 in S41 and then increasing it by 1 in S47. That is, this is because the method of increasing the value of N from 1 to 10 sequentially selects the first to tenth memory devices 1 one by one. <a:j>Each of these is considered a target memory device. In this disclosure, the first to tenth memory devices are selected sequentially using the value of N. <a:j>Each of the methods described above as targeting memory devices is merely an example; in practice, any other method could be used.

[0190] In S46, the case where N is 10 (is in S46) can be considered as having 10 memory devices 1 <a:j>Each of the selected data points is designated as the target memory device, and the test preparation operation 15 and error detection operation have been repeated ten times. That is, it can be in a state where error detection operation has been performed on each of the 10 test data DATA_TARs.

[0191] Based on the result of the error detection operation performed on each of the 10 test data DATA_TARs, check whether there is a test data DATA_TAR without errors (S48). That is, in S48, check whether there is at least one result among the results of the error detection operation performed on each of the 10 test data DATA_TARs where the total number of generated error bits is less than a set number and the positions of the generated error bits are not concentrated in a specific memory device.

[0192] When there is error-free test data DATA_TAR in S48 (yes in S48), the error correction process is determined to be successful, and error-free test data DATA_TAR is output as read data (S49).

[0193] If no error-free test data DATA_TAR exists in S48 (this is not the case in S48), the remaining operations of the error correction process continue. That is, execute... Figure 6A The S50 follows the S40.

[0194] The concepts described above are not limited to the foregoing embodiments and drawings. It will be apparent to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the technical scope of this disclosure. Furthermore, embodiments can be combined to form other embodiments.< / a:j> < / a:j> < / a:j> < / n> < / n> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / n> < / n> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j> < / a:j>

Claims

1. An error correction method for a memory system, the memory system comprising multiple memory devices each storing data and error correction codes, the error correction method comprising: The error checking operation generates an error sum data segment by performing a parity check operation on multiple first data segments read from each memory device using the error correction code; The test preparation operation involves generating a third data segment by performing a parity check operation between the error sum data segment and the second data segment, based on the result of the error checking operation. Test data is then generated by replacing the second data segment with the third data segment, where the second data segment is a data segment read from a target memory device among the plurality of first data segments, and the target memory device is selected from the plurality of memory devices. The error correction operation corrects errors in the test data using the error correction code, generating a correction data segment. The judgment operation determines whether a miscorrection has occurred in the correction data segment when the error correction operation is successful. as well as The determination operation is performed based on the number of times the judgment operation is executed and the result of the judgment operation, which is the result of repeating the test preparation operation, the error correction operation, and the judgment operation on each first data segment, to determine whether the error correction method is successful or unsuccessful.

2. The error correction method according to claim 1, wherein, The determination operation: The error correction method is determined to be successful if no miscorrection occurs in any of the judgment operations performed at least once out of at least two executions, or if no miscorrection occurs in any of the judgment operations performed only once.

3. The error correction method according to claim 2, wherein, The determining operation includes determining that no miscorrection has occurred in all judgment operations performed at least twice: The correction data segments generated in the error correction operations corresponding to at least two executions of the judgment operation are compared; and Based on the results of the comparison, it is determined whether the error correction method is successful or unsuccessful.

4. The error correction method according to claim 3, wherein, The determination operation: When the correction data segments are identical as a result of the comparison, the error correction method is determined to be successful.

5. The error correction method according to claim 3, wherein, The determination operation: When, as a result of the comparison, at least one correction data segment has a value different from the other correction data segments, the error correction method is determined to have failed.

6. The error correction method according to claim 1, wherein, The determination operation: If none of the judgment operations are executed, or if all judgment operations executed at least once result in miscorrection, the error correction method is determined to be a failure.

7. The error correction method according to claim 1, wherein, The judgment operation: When the parity check operation of the correction data segment using the error correction code fails, or when the number of bits in the remaining portion of the correction data segment excluding the third data segment that the error correction operation succeeds is greater than the reference number, it is determined that a miscorrection has occurred in the correction data segment.

8. The error correction method according to claim 1, wherein the error checking operation includes: One or more errors are detected from the plurality of first data segments by utilizing the error correction code; as well as Based on the number of detected errors, determine whether to perform the test preparation operation, the error correction operation, the judgment operation, and the determination operation.

9. The error correction method according to claim 1, wherein, The error checking operation includes: The third data segment is generated by performing a parity check operation between the error sum data segment and the second data segment, so as to generate the test data by replacing the second data segment with the third data segment; One or more errors are detected from the test data using the error correction code; Repeated generation and detection of each first data segment; and Based on the number of errors detected as a result of the repetition, the execution of the test preparation operation, the error correction operation, the judgment operation, and the determination operation is determined.

10. The error correction method according to claim 1, wherein, The error correction code is a product code formed by multiplying together a polynomial generated in response to either the Bose-Chaudhuri-Hocquenghem code (BCH code) or the Reed-Solomon code (RS code), a polynomial generated in response to a parity check code, and a polynomial generated in response to a cyclic redundancy check code (CRC code).

11. A memory system, comprising: Multiple memory devices, each storing data and error correction codes; as well as An error correction device performs an error correction method, the error correction method comprising: The error checking operation generates an error sum data segment by performing a parity check operation on multiple first data segments read from each memory device using the error correction code. The test preparation operation involves generating a third data segment by performing a parity check operation between the error sum data segment and the second data segment, based on the result of the error checking operation. Test data is then generated by replacing the second data segment with this third data segment. The second data segment is a data segment read from a target memory device, selected from the plurality of memory devices. The error correction operation corrects errors in the test data using the error correction code, generating a correction data segment. The judgment operation, when the error correction operation is successful, determines whether a miscorrection occurred in the correction data segment, and The determination operation is performed based on the number of times the judgment operation is executed and the result of the judgment operation, which is the result of repeating the test preparation operation, the error correction operation, and the judgment operation on each first data segment, to determine whether the error correction method is successful or unsuccessful.

12. The memory system according to claim 11, wherein, The error correction device performs the determination operation by determining that the error correction method is successful when it determines that no miscorrection has occurred in only one of the at least two determination operations or in only one determination operation.

13. The memory system according to claim 12, wherein, The determining operation includes determining that no miscorrection has occurred in all judgment operations performed at least twice: The correction data segments generated in the error correction operations corresponding to the judgment operation are compared, and Based on the results of the comparison, it is determined whether the error correction method is successful or unsuccessful.

14. The memory system according to claim 13, wherein, The error correction device performs the determination operation by determining that the error correction method is successful when the correction data segments are identical as a result of the comparison.

15. The memory system according to claim 13, wherein, The error correction device performs the determination operation by determining that the error correction method has failed when, as a result of the comparison, at least one correction data segment has a value different from that of the other correction data segments.

16. The memory system of claim 11, wherein, The error correction device performs the determination operation by determining that the error correction method has failed when all the determination operations are not executed or when all determination operations are executed at least once and a miscorrection is determined to have occurred.

17. The memory system according to claim 11, wherein, The error correction device performs the determination operation by determining that a miscorrection has occurred in the correction data segment when the parity check operation of the correction data segment using the error correction code fails, or when the number of bits in the remaining part of the correction data segment excluding the third data segment that the error correction operation succeeded is greater than a reference number.

18. The memory system according to claim 11, wherein, The error checking operation includes: By utilizing the error correction code, one or more errors are detected from the plurality of first data segments, and Based on the number of detected errors, determine whether to perform the test preparation operation, the error correction operation, the judgment operation, and the determination operation.

19. The memory system according to claim 11, wherein, The error checking operation includes: The third data segment is generated by performing a parity check operation between the error sum data segment and the second data segment, and the test data is generated by replacing the second data segment with the third data segment. One or more errors are detected from the test data using the error correction code. Repeated generation and detection of each first data segment, and Based on the number of errors detected as a result of the repetition, the execution of the test preparation operation, the error correction operation, the judgment operation, and the determination operation is determined.

20. The memory system according to claim 11, wherein, The error correction code is a product code formed by multiplying together a polynomial generated in response to either the Bose-Chaudhuri-Hocquenghem code (BCH code) or the Reed-Solomon code (RS code), a polynomial generated in response to a parity check code, and a polynomial generated in response to a cyclic redundancy check code (CRC code).

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