I2s data dsp short-range storage transmission system and method based on arbitration mechanism
By constructing an autonomous direct storage path between a dedicated hardware bridging module and the DSP's near-field storage, the problem of unpredictable latency in multi-channel I2S data transmission was solved, achieving deterministic, microsecond-level low-latency data transmission, adapting to different application scenarios and improving system efficiency.
Patent Information
- Application Number
- CN202610328096.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-18
- Publication Date
- 2026-05-15
- Estimated Expiration
- 2046-03-18
AI Technical Summary
Existing technologies fail to establish deterministic direct storage paths from multiple I2S interfaces to the nearest memory unit of the DSP core, resulting in unpredictable data transmission delays and additional data copying, making it difficult to meet the microsecond-level, predictable end-to-end latency requirements of high-end real-time processing applications.
By constructing an autonomous direct storage path between a dedicated hardware bridging module and the DSP near-field memory, and combining arbitration mechanisms, autonomous address management, hardware data packaging, and closed-loop synchronous feedback, multi-channel I2S data can be directly written to the DSP near-field memory in an autonomous hardware manner, eliminating the bus arbitration latency and software configuration overhead of the general DMA architecture.
It achieves deterministic, microsecond-level low-latency transmission of multi-channel I2S data, improves the system's scenario adaptability and bus transmission efficiency, reduces software overhead, and meets the latency requirements of high-end real-time processing applications.