I2s data dsp short-range storage transmission system and method based on arbitration mechanism

Abstract

The application discloses an I2S data DSP short-range storage transmission system and method based on an arbitration mechanism, relates to the technical field of embedded audio and real-time signal processing, and aims to solve the technical problems that the prior art cannot construct a multi-channel I2S to DSP short-range storage hardware autonomous deterministic direct storage path, transmission delay is unpredictable, and software overhead is large. The system comprises an I2S interface, a special hardware bridging module, a DSP containing short-range storage, a system bus and a DSP core. The special hardware bridging module is integrated with components such as FIFO, an arbitrator and an address generation unit, and can autonomously complete data caching, arbitration, address management and direct writing operation. The method comprises five steps of system initialization, hardware autonomous direct storage, hardware precise notification, core direct processing and hardware synchronous feedback. The application realizes hardware autonomous deterministic low-delay transmission of I2S data, reduces software overhead, and has good system adaptability and hardware reusability, and is suitable for various embedded audio and real-time signal processing scenes.

Description

Technical Field

[0001] This invention relates to the field of embedded audio and real-time signal processing technology, specifically to an I2S data DSP near-field storage and transmission system and method based on an arbitration mechanism. Background Technology

[0002] In existing embedded audio or real-time signal processing systems, serial audio stream data received via the I2S interface typically needs to be transferred to the system main memory (such as Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) via a Direct Memory Access (DMA) controller before being read and processed by the DSP core. To optimize the latency and efficiency of this process, various improvement schemes have been proposed. For example, some existing technologies aim to reduce CPU utilization and data transfer latency by configuring DMA descriptor chains and utilizing interrupts to coordinate the operation of I2S and DMA. Other existing technologies propose writing audio data directly into the processor's cache to improve data access speed. These technical solutions represent common optimization approaches in this field.

[0003] However, analysis revealed a limitation in the aforementioned and similar existing technologies: they all fail to construct a fully hardware-managed deterministic direct-memory path from multiple I2S interfaces to the nearest memory unit (such as tightly coupled memory or L2 cache) of the DSP core. Specifically, existing solutions either introduce bus arbitration latency and software configuration overhead due to reliance on general-purpose DMA controllers, or fail to achieve automatic, concurrent writing and synchronization of multiple I2S data streams to the fixed DSP near-field memory area due to the lack of a dedicated hardware path. This results in unpredictable delays and additional data copies on the path from the physical interface to the DSP core's real-time computation location, making it difficult to meet the stringent requirements of high-end real-time processing applications for microsecond-level, predictable end-to-end latency.

[0004] Therefore, how to design a dedicated transmission mechanism at the hardware architecture level that can completely avoid general bus arbitration and software intervention, and realize the deterministic and direct writing of multiple I2S data streams into the DSP's local memory, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide an I2S data DSP near-field storage transmission system and method based on an arbitration mechanism. By constructing a dedicated hardware bridging module and an autonomous direct storage path for DSP near-field storage, and combining an arbitration mechanism, autonomous address management, hardware data packaging, and closed-loop synchronous feedback hardware design, it enables the direct, autonomous writing of multiple I2S data streams to DSP near-field storage, completely eliminating the bus arbitration delay and software configuration overhead of general DMA architectures, achieving deterministic, microsecond-level low-latency transmission of I2S data, and improving the system's scenario adaptability.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: On the one hand, an I2S data DSP near-field storage and transmission system and method based on arbitration mechanism, the system comprising: at least one I2S interface, a dedicated hardware bridging module, a DSP containing near-field storage, a system bus, and a DSP core.

[0007] The dedicated hardware bridging module is connected to the I2S interface and the system bus respectively;

[0008] The DSP local storage is connected to the dedicated hardware bridge module via the system bus;

[0009] The dedicated hardware bridging module includes multiple first-in-first-out (FIFO) memories, trigger controllers, arbitrators, address generation units, and bus master interfaces, each corresponding to one of the I2S interfaces.

[0010] The trigger controller monitors the storage status of each FIFO and activates a transmission request when the storage amount of any FIFO reaches a preset trigger condition.

[0011] The arbitrator arbitrates multiple activated transmission requests according to a preset strategy to determine the channel currently executing the transmission.

[0012] The address generation unit pre-stores and independently maintains a base address pointer for each channel, pointing to a dedicated storage window in the DSP's near-field memory. After the channel obtains a transmission authorization, it automatically outputs the current address pointer value as the target address of the system bus transaction. After the transmission is completed, it automatically increments the pointer.

[0013] The bus master interface initiates and completes a direct write transaction to the DSP near-field memory using the FIFO data corresponding to the channel selected by the arbitrator, according to the target address provided by the address generation unit.

[0014] The DSP local storage has a pre-divided, contiguous physical address mapping window in the system bus address space, enabling write transactions initiated by the dedicated hardware bridging module to directly access the physical units of the local storage.

[0015] Furthermore, the system also includes an interrupt generation circuit. After the dedicated hardware bridging module completes a direct write transaction to the DSP local memory, the interrupt generation circuit generates an interrupt signal pointing to the DSP core. In response to the interrupt signal, the DSP core directly reads data from the corresponding address in the DSP local memory for processing, and after processing, feeds back a synchronization signal to the dedicated hardware bridging module.

[0016] The dedicated hardware bridging module also includes a data packer, which is connected between the first-in-first-out (FIFO) memory and the bus master interface. The data packer is used to combine multiple low-bit-width audio data samples from the FIFO memory into a complete data word that matches the system bus bit width, and then submit the complete data word to the bus master interface to initiate a write transaction.

[0017] Furthermore, the dedicated storage window pointed to by the base address pointer maintained by the address generation unit for each channel is continuously and fixedly allocated within the address space of the DSP's near-field storage.

[0018] The address generation unit performs a pointer increment operation after each channel transmission is completed, where the increment step is equal to the byte length of a complete data word output by the data packer, thereby ensuring that continuously written data is sequentially arranged and address-aligned in the dedicated storage window.

[0019] Furthermore, the preset triggering condition monitored by the trigger controller is that the amount of data cached in the first-in-first-out (FIFO) memory reaches or exceeds a preset water level threshold.

[0020] The amount of data corresponding to the water level threshold is at least sufficient to enable the bus master device interface to initiate a complete system bus burst transmission.

[0021] Furthermore, the DSP local storage is a secondary cache or tightly coupled memory of the DSP core;

[0022] The dedicated hardware bridging module can directly access the storage units of the secondary cache or tightly coupled memory through the system bus without going through the system main memory.

[0023] Furthermore, the interrupt generation circuit includes a status flag register corresponding to each transmission channel in the dedicated hardware bridging module;

[0024] After the dedicated hardware bridging module completes writing to the storage window corresponding to a certain channel, it automatically sets the status flag bit corresponding to that channel.

[0025] The setting operation of the status flag directly triggers the generation of a dedicated interrupt signal to the DSP core.

[0026] The DSP core is configured to: after responding to the interrupt signal and reading the processed data, perform a clear operation on the status flag register to reset the corresponding status flag bit;

[0027] The dedicated hardware bridging module is configured to monitor the status flag bit and, after the status flag bit is reset, know that the storage window of the corresponding channel can be written to again.

[0028] Furthermore, the address generation unit also maintains a circular addressing logic for a dedicated storage window for each channel;

[0029] When the base address pointer increments to the end address of the dedicated storage window, the address generation unit automatically resets the base address pointer back to the starting base address of the dedicated storage window, thereby realizing the cyclic overwrite writing of data within a fixed-size buffer.

[0030] Furthermore, the arbitrator's preset arbitration strategy is a configurable static priority strategy or a round-robin scheduling strategy;

[0031] The static priority strategy assigns a fixed priority weight to each I2S transmission channel;

[0032] The polling scheduling strategy responds to the transmission requests of each channel in a fixed order.

[0033] Furthermore, the dedicated hardware bridging module is designed as a parameterizable hardware functional module;

[0034] The parameters include at least the number of supported I2S channels, the FIFO depth, the system bus width, and the base address and size of the DSP near-field memory mapping window.

[0035] By constructing an autonomous "direct storage" path formed by a dedicated hardware bridging module and a local storage bus mapping, the software overhead and arbitration latency in general-purpose DMA architectures can be completely eliminated, enabling deterministic, microsecond-level low-latency data transmission from multiple I2S interfaces to the DSP core. Furthermore, through configurable hardware optimizations in data packaging, address management, arbitration strategies, and IP core design, the system can flexibly adapt to different application scenarios ranging from high real-time performance to multi-channel fair processing, and possesses the ability to be efficiently integrated as a standardized module in different chip designs.

[0036] On the other hand, an I2S data DSP short-range storage and transmission method based on an arbitration mechanism is applicable to an I2S data DSP short-range storage and transmission system based on an arbitration mechanism. The specific steps of this method are as follows:

[0037] Step 1, System Initialization: Configure the parameters of each I2S interface, and allocate and map a dedicated fixed storage window for each I2S channel in the DSP near-field storage. Initialize the address pointers and arbitration strategies of each channel in the dedicated hardware bridging module.

[0038] Step 2, Hardware Autonomous Direct Storage: The I2S interface continuously receives data and stores it in the corresponding FIFO memory. When the trigger controller detects that any FIFO has reached the trigger condition, the arbitrator arbitrates the current transmission channel, the address generation unit outputs the current target address of the channel, and the bus master device interface packages the data of the corresponding FIFO and directly writes it to the corresponding address of the DSP near-field storage.

[0039] Step 3, precise hardware notification: After the direct write transaction is completed, the interrupt generation circuit automatically sets the status flag of the corresponding channel and triggers the DSP core interrupt;

[0040] Step 4, Core Direct Processing: The DSP core responds to the interrupt, directly reads data from the known address in the DSP's local memory, and processes it;

[0041] Step 5, Hardware Synchronization Feedback: After the DSP core completes processing, it clears the status flag. The dedicated hardware bridging module, based on the flag clearing status, knows that the channel storage window can be written to again, thus forming a closed-loop hardware synchronization pipeline.

[0042] By breaking down the transmission process into five distinct steps—initialization, hardware autonomous direct storage, hardware precise notification, core direct processing, and hardware synchronous feedback—a complete, hardware event-driven deterministic processing pipeline can be defined, enabling rigorous analysis and verification of the entire system's behavior. Furthermore, through the clear division of labor between hardware and software—hardware handling automatic data transfer and notification, while software focuses solely on processing and synchronously feeding back ready data—the CPU is completely freed from complex data transfer and management, allowing it to concentrate on core signal processing algorithms and maximizing overall system efficiency.

[0043] Compared with existing technologies, this I2S data DSP short-range storage and transmission system and method based on arbitration mechanism has the following advantages:

[0044] I. This invention constructs a hardware autonomous direct storage path formed by mapping a dedicated hardware bridging module to the DSP local memory bus, eliminating the use of a general-purpose DMA controller. The dedicated hardware bridging module autonomously completes the caching of multiple I2S data, transmission request arbitration, address maintenance, and direct write operations to the DSP local memory. No software involvement in data handling and bus arbitration configuration is required. This enables the construction of a deterministic data transmission path from multiple I2S interfaces to the DSP local memory, eliminating the bus arbitration delay and software configuration overhead caused by the general-purpose DMA architecture. As a result, the end-to-end latency of I2S data transmission is deterministic, significantly reducing the software overhead of data transmission and meeting the technical requirements of high-end real-time processing applications for predictable, low-latency data transmission.

[0045] Second, this invention designs a dedicated hardware bridging module as a parameterizable hardware module, configures a switchable arbitration strategy, designs independent cyclic addressing logic for each I2S channel, and sets a data packetizer to match the bus width. It can flexibly adapt to different I2S channel numbers, system bus widths, and storage mapping requirements. At the same time, it can adapt to different application scenarios with high real-time requirements or multi-channel fair processing. It can also improve the effective transmission efficiency of the system bus and the utilization rate of near-field storage resources. Furthermore, this dedicated hardware bridging module can be integrated as a standardized module into different chip designs, effectively improving the reusability of hardware modules and reducing the hardware development cycle and cost. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0047] Figure 1 This is a schematic diagram of the overall system architecture of the present invention;

[0048] Figure 2 This is a schematic diagram of the internal structure of the dedicated hardware bridging module of the present invention;

[0049] Figure 3 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0050] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below. Example

[0051] The following detailed description, in conjunction with the accompanying drawings, illustrates the specific implementation of the I2S data DSP near-field storage and transmission system and method based on an arbitration mechanism according to the present invention. This embodiment is only used to explain the present invention. The technical solutions described in this embodiment clearly define the specific implementation methods, working principles, and functions of each technical feature. The technical solutions of this embodiment are applicable to the fields of embedded audio, real-time signal processing, and other electrical signal digital processing, and can effectively solve the technical problems of unpredictable latency, large software overhead, and low transmission efficiency in existing multi-channel I2S data transmission, achieving deterministic low-latency transmission of I2S data to DSP near-field storage.

[0052] In this embodiment, the overall architecture of the I2S data DSP near-field storage and transmission system based on the arbitration mechanism of the present invention is as follows: Figure 1 As shown, Figure 1 This is a schematic diagram of the overall system architecture of the present invention. The system includes 8 I2S interfaces, a dedicated hardware bridging module, a DSP containing local storage, a system bus, and a DSP core. The system bus uses an AXI3.0 bus with a 32-bit bit width and a clock frequency of 100MHz. The DSP local storage uses the tightly coupled memory (TCM) of the DSP core, with a total capacity of 512KB and an access speed of 1ns / time. The DSP core uses a floating-point digital signal processor with a clock frequency of 400MHz. The dedicated hardware bridging module is hardware-connected to the 8 I2S interfaces and the system bus. The DSP local storage establishes a data path with the dedicated hardware bridging module through the system bus. The DSP core is directly connected to the DSP local storage, enabling zero-latency access to the local storage.

[0053] Specifically, the DSP's near-field storage is pre-divided into contiguous physical address mapping windows within the system bus address space, ranging from 0x20000000 to 0x2007FFFF. This address range is the dedicated access area for the dedicated hardware bridge module. All write transactions initiated by the dedicated hardware bridge module can directly access the physical memory units within this address range, without going through the system main memory such as DDR SDRAM. This eliminates the latency and bus contention issues caused by accessing the system main memory at the hardware architecture level. All eight I2S interfaces are standard audio serial interfaces, each configured with a sampling rate of 48kHz, a data bit width of 16 bits, a bit clock frequency of 12.288MHz, and a frame synchronization clock frequency of 48kHz, which can meet the signal acquisition requirements of conventional embedded audio systems.

[0054] It is understandable that the dedicated hardware bridging module is the core execution unit of this system, and its internal structure is as follows: Figure 2 As shown, Figure 2This is a schematic diagram of the internal structure of the dedicated hardware bridging module of the present invention. The dedicated hardware bridging module includes eight FIFOs (First-In-First-Out) memories, each corresponding to an I2S interface, a trigger controller, an arbitrator, an address generation unit, a bus master interface, and a data packetizer. The system also includes an independent interrupt generation circuit, which is connected to both the dedicated hardware bridging module and the DSP core to achieve interrupt triggering and synchronous feedback after data transmission is completed. Specifically, the input terminals of the eight FIFOs are connected to the data lines of their corresponding I2S interfaces, and their output terminals are all connected to the input terminals of the data packetizer. The output terminals of the data packetizer are connected to the data source terminal of the bus master interface. The trigger controller is connected to the status terminals of the eight FIFOs, the arbitrator is connected to the output terminal of the trigger controller, the address generation unit is connected to the output terminal of the arbitrator, the bus master interface is connected to the output terminal of the address generation unit and the system bus, and the interrupt generation circuit is connected to the status terminal of the bus master interface, the interrupt input terminal of the DSP core, and the status monitoring terminal of the dedicated hardware bridging module.

[0055] In this embodiment, the eight First-In-First-Out (FIFO) memory units are synchronous FIFOs, all implemented using hardware register arrays. Each FIFO has a uniform depth of 1024 bytes, and its read / write clock is synchronized with the bit clock of the corresponding I2S interface, i.e., 12.288MHz. The write enable signal for each FIFO is jointly controlled by the frame synchronization signal and the bit clock signal of the corresponding I2S interface. When the I2S interface receives valid audio data, the write enable signal is set, and the data is serially stored bit by bit into the FIFO's storage unit, realizing the conversion from I2S serial data to parallel buffered data. The read enable signal for the FIFO is controlled by the internal transmission control logic of a dedicated hardware bridging module. The read enable signal is only set after the corresponding channel obtains transmission authorization, ensuring orderly reading of FIFO data. The core function of the FIFO is to buffer the audio data received in real time by the I2S interface, eliminating the rate difference between the I2S interface data reception rate and the system bus data transmission rate, thus avoiding data loss or transmission congestion.

[0056] Specifically, the trigger controller is implemented using a hardware state machine combined with a counter. The hardware state machine operates at a system bus clock of 100MHz and continuously monitors the storage status of the eight FIFOs in real time. The trigger controller collects the values ​​of the read and write pointers of each FIFO and calculates the difference between the two pointers. This difference represents the current actual amount of data stored in the FIFO. In this embodiment, the preset trigger condition for the trigger controller is that the amount of data stored in the FIFO reaches or exceeds 32 bytes. This 32-byte threshold is a preset water level threshold. This threshold is set to match the burst transmission capability of the system bus. The burst transmission length of the system bus is configured to be 8 bits. Combined with the 32-bit bus width, a complete system bus burst transmission can transmit 32 bits × 8 = 256 bits = 32 bytes of data. Therefore, this water level threshold ensures that each transmission request initiated by the bus master interface can execute a complete system bus burst transmission, avoiding fragmented data transmission and improving bus transmission efficiency. When the trigger controller detects that the amount of stored data in any FIFO has reached 32 bytes, it immediately sets the transmission request flag for that channel and activates the transmission request for that channel to the arbitrator. If multiple FIFOs reach the water level threshold at the same time, the trigger controller will activate the transmission requests for multiple channels simultaneously.

[0057] In this embodiment, the arbitrator is implemented using pure hardware logic circuitry, consisting of logic gates, registers, and multiplexers. The arbitration response time is ≤1 system bus clock cycle, ensuring rapid response to transmission requests. The arbitrator receives a transmission request signal from the trigger controller and, according to a preset arbitration strategy, prioritizes and arbitrates multiple simultaneously active transmission requests to determine the channel for current data transmission. This embodiment supports two configurable arbitration strategies: a static priority strategy and a round-robin scheduling strategy. These two strategies are switched via a hardware configuration register located at address 0x40000020. Writing 0 configures the static priority strategy, while writing 1 configures the round-robin scheduling strategy.

[0058] When configured with a static priority strategy, the arbitrator assigns fixed priority weights to the eight I2S transmission channels, with priorities from highest to lowest: Channel 0, Channel 1, Channel 2, Channel 3, Channel 4, Channel 5, Channel 6, and Channel 7. The arbitrator always prioritizes responding to transmission requests from higher-priority channels, only responding to requests from lower-priority channels when there are no requests from higher-priority channels. This strategy is suitable for applications with higher real-time requirements for some channels. When configured with a round-robin scheduling strategy, the arbitrator responds to transmission requests from each channel in a fixed order from Channel 0 to Channel 7, ensuring each channel has an equal opportunity to transmit. After responding to a transmission request from a channel, the arbitrator automatically switches arbitration rights to the next channel, even if the current channel still has unfinished transmission requests. This strategy is suitable for applications with higher fairness requirements for multi-channel data transmission. After completing arbitration, the arbitrator sends the channel number signal of the selected channel to the address generation unit and the bus master interface to determine the current transmission channel.

[0059] Specifically, the address generation unit is implemented using a hardware register array and adders. It pre-stores and independently maintains a base address pointer for each of the eight transmission channels. Each base address pointer points to the starting address of the dedicated storage window allocated to that channel in the DSP's local memory. In this embodiment, the 512KB physical address mapping window of the DSP's local memory is evenly divided into eight consecutive and fixedly allocated dedicated storage windows. Each storage window has a capacity of 64KB. The base addresses of the dedicated storage windows for the eight channels are configured sequentially as 0x20000000, 0x20010000, 0x20020000, 0x20030000, 0x20040000, 0x20050000, 0x20060000, and 0x20070000. The address ranges of each storage window are continuous and non-overlapping, ensuring that the data storage of each channel is independent and that address conflicts do not occur.

[0060] After receiving the selected channel number signal from the arbitrator, the address generation unit immediately retrieves the base address pointer corresponding to that channel, outputs the current address pointer value as the target address for the system bus transaction, and sends this target address to the bus master interface. Once a data transmission transaction for that channel is completed, the address generation unit performs an automatic increment operation on the current base address pointer using an adder. The increment step is configured to be 4 bytes, which perfectly matches the byte length of a complete data word output by the data packetizer. This ensures that continuously written data is arranged sequentially in address order within the dedicated storage window, achieving data address alignment and preventing system bus transmission errors caused by address misalignment.

[0061] Meanwhile, the address generation unit maintains an independent cyclic addressing logic for each channel's dedicated storage window. This logic is implemented using a comparator and a multiplexer. After incrementing the base address pointer, the address generation unit compares the incremented pointer value with the end address of the channel's dedicated storage window. The end addresses of the eight channels are configured sequentially as 0x2000FFFF, 0x2001FFFF, 0x2002FFFF, 0x2003FFFF, 0x2004FFFF, 0x2005FFFF, 0x2006FFFF, and 0x2007FFFF. When the comparison result shows that the base address pointer has incremented to the end address of the dedicated storage window, the address generation unit automatically resets the base address pointer back to the starting base address of the channel through the multiplexer. This enables cyclic overwriting of data within a fixed-size dedicated storage window, eliminating the need for software-based address management and achieving autonomous address maintenance at the hardware level. Furthermore, the cyclic overwriting method fully utilizes limited local storage resources to meet the needs of continuous data stream transmission.

[0062] In this embodiment, the data packetizer is connected between the FIFO and the bus master interface. It consists of a shift register and data concatenation logic, with a processing latency of 0 system bus clock cycles. Its core function is to combine low-width audio data samples from the FIFO into a complete data word that matches the system bus width. In this embodiment, the audio data width of the I2S interface is 16 bits, and the system bus width is 32 bits. The data packetizer concatenates every two 16-bit audio data samples in big-endian mode. That is, the first 16-bit sample is used as the high 16 bits of the complete data word, and the second 16-bit sample is used as the low 16 bits of the complete data word, combining them into a 32-bit complete data word. This complete data word is then submitted to the bus master interface, ensuring that the data width and system bus width are perfectly matched. This avoids bandwidth waste caused by bus width mismatch and improves the effective data transmission efficiency of the system bus. If the I2S interface data width or system bus width needs to be adjusted in actual applications, the concatenation rules of the data packetizer can be adjusted through the hardware configuration register to adapt to different width combinations.

[0063] Specifically, the bus master interface is a master interface conforming to the AXI 3.0 bus protocol, consisting of a bus protocol controller and data transceiver logic. It serves as the communication interface between the dedicated hardware bridge module and the system bus. The bus master interface receives the selected channel number signal from the arbiter, the target address signal from the address generation unit, and a 32-bit complete data word from the data packetizer. Following the write transaction specifications of the AXI 3.0 bus protocol, it initiates a direct write transaction to the DSP's local memory. In this embodiment, the write transaction initiated by the bus master interface is an incremental burst transfer with a burst length configured to 8 bytes. Each burst transfer writes 32 complete 32-bit data words (128 bytes in total) to the corresponding address in the DSP's local memory. During the transfer, the bus master interface automatically completes bus handshake, data transmission and reception, and response feedback operations without intervention from the DSP core or software, achieving hardware-autonomous direct storage of data. After a burst transfer transaction is completed, the bus master interface sends a transfer completion status signal to the interrupt generation circuit and simultaneously sends a pointer increment trigger signal to the address generation unit, triggering the address generation unit to increment the base address pointer.

[0064] In this embodiment, the interrupt generation circuit consists of status flag registers, interrupt triggering logic, and status monitoring logic. There are eight status flag registers, each corresponding to one of the eight transmission channels. The addresses of the eight status flag registers are configured as 0x40000000, 0x40000004, 0x40000008, 0x4000000C, 0x40000010, 0x40000014, 0x40000018, and 0x4000001C, respectively. Each status flag register has a 1-bit valid bit, and the operation mode is to write 1 to set the flag and write 0 to clear it. When the bus master device interface completes a direct write transaction to the DSP's local memory, it sends a transmission completion status signal to the interrupt generation circuit. The hardware triggering logic of the interrupt generation circuit immediately performs a write 1 operation on the status flag register corresponding to the transmission channel, thus setting the status flag bit. Setting this status flag will directly trigger the external dedicated interrupt line 9 of the DSP core. This interrupt line is configured with the highest priority to ensure that the DSP core can respond quickly to the signal that the data transmission is complete.

[0065] The DSP core is configured to monitor the interrupt triggering of this dedicated interrupt line in real time. Upon detecting an interrupt signal, it immediately enters the interrupt service routine. Based on the channel number carried by the interrupt signal, it directly reads data from the known address of the dedicated storage window for that channel in the DSP's near-field memory and performs signal processing, such as audio filtering, equalization, and noise reduction. After the DSP core completes the processing of this batch of data, it performs a write operation to the status flag register corresponding to that channel, clearing the status flag bit. The status monitoring logic of the interrupt generation circuit continuously monitors the status of eight status flag registers at a clock frequency of 100MHz. When it detects that the status flag bit of a certain channel has been cleared, it immediately sends a signal to the dedicated hardware bridge module indicating that the storage window of that channel is writable again. Upon receiving this signal, the dedicated hardware bridge module removes the transmission restriction on that channel, allowing the channel to be triggered again by the controller to activate the transmission request.

[0066] In this embodiment, the dedicated hardware bridging module of the present invention is designed as a parameterizable hardware functional module. Core parameters can be flexibly configured via a hardware configuration register. The address range of the configuration register is 0x40000020-0x4000003F. It supports power-on initialization configuration and online dynamic configuration without requiring redesign of the hardware circuit, thus improving the module's adaptability and reusability. Configurable parameters include at least the number of supported I2S channels, FIFO depth, system bus width, and the base address and size of the DSP near-field memory mapping window. The number of I2S channels can be configured to 1-16, the FIFO depth can be configured to 256-4096 bytes, the system bus width can be configured to 16bit, 32bit, or 64bit, the base address of the DSP near-field memory mapping window can be configured in the address range of 0x20000000-0x20FFFFFF, and the size of the mapping window can be configured to 64KB-1MB. The configuration values ​​of each parameter are implemented by writing to the corresponding configuration register. After configuration, the dedicated hardware bridging module will automatically adjust its internal logic according to the configuration parameters to adapt to different application scenarios and hardware platforms.

[0067] This invention also provides an I2S data DSP short-range storage and transmission method based on an arbitration mechanism. This method is applicable to the aforementioned I2S data DSP short-range storage and transmission system based on an arbitration mechanism. The method flow is as follows: Figure 3 As shown, Figure 3 This is a schematic diagram of the method flow of the present invention. This method implements a closed-loop pipeline for data transmission and processing through hardware event-driven mechanisms. No software intervention is required for data handling and address management throughout the process; only software is needed to complete system initialization and data processing. This effectively reduces the resource occupancy of the DSP core and improves the real-time performance and determinism of the system. The specific steps of this method are as follows:

[0068] Step 1: System Initialization. After the system powers on, the DSP core software program completes the parameter configuration and status initialization of the entire system. First, the core parameters of the 8 I2S interfaces are configured, including a sampling rate of 48kHz, a data bit width of 16bit, a bit clock frequency of 12.288MHz, and a frame synchronization clock frequency of 48kHz, putting the I2S interfaces in a ready state to receive external serial audio data. Next, within the 512KB physical address mapping window of the DSP's local storage, dedicated fixed storage windows are allocated and mapped for each of the 8 I2S channels. Each storage window has a capacity of 64KB, and the base addresses are configured sequentially from 0x20000000 to 0x20070000, ensuring that the storage addresses of each channel are independent and continuous. Then, the core parameters of the dedicated hardware bridging module are initialized. The depth of the eight FIFOs is configured to 1024 bytes, the waterline threshold of the trigger controller is configured to 32 bytes, the arbitration strategy of the arbitrator is configured to a static priority strategy, the initial value of the base address pointers of the eight channels in the address generation unit is configured to the starting base address of the dedicated storage window of each channel, the concatenation rule of the data packetizer is configured to concatenate two 16-bit samples into one 32-bit complete data word, and the burst transmission length of the bus master interface is configured to 8. Finally, the interrupt priority of the interrupt generation circuit is configured to the highest level, the initial values ​​of the eight status flag registers are set to 0, and the initialization of the entire system is completed, putting the system into a standby state.

[0069] Step two, hardware autonomous direct storage. After system initialization, the eight I2S interfaces continuously receive external serial audio data and store the received audio data bit by bit into the corresponding FIFO, realizing real-time data caching. The trigger controller continuously monitors the amount of stored data in the eight FIFOs at a clock frequency of 100MHz. When the amount of stored data in any FIFO reaches the 32-byte threshold, the transmission request for that channel is immediately activated. If multiple FIFOs reach the threshold simultaneously, the arbitrator will arbitrate the multiple transmission requests according to a preset static priority strategy to determine the current transmission channel. After arbitration, the address generation unit retrieves the current base address pointer of the channel and outputs the target address to the bus master interface. Simultaneously, the data packetizer concatenates the 16-bit audio data samples in the channel's FIFO into a complete 32-bit data word. The bus master interface, according to the target address and the AXI3.0 bus protocol, initiates a burst write transaction to the DSP's local memory, directly writing the concatenated complete data word into the corresponding dedicated storage window of the DSP's local memory. After each burst transfer, the address generation unit automatically increments the base address pointer by 4 bytes, preparing the address for the next transfer. The entire hardware autonomous direct storage process is independently completed by a dedicated hardware bridging module, requiring no intervention from the DSP core or software.

[0070] Step 3, Precise Hardware Notification. Once the bus master interface completes a direct write transaction to the DSP's local memory, it immediately sends a transmission completion signal to the interrupt generation circuit. Upon receiving this signal, the interrupt generation circuit automatically sets the status flag register corresponding to the transmission channel. Setting the status flag directly triggers a dedicated interrupt signal from the DSP core. This interrupt signal carries the channel number information, enabling the DSP core to quickly determine the memory channel where the data is located, thus achieving precise hardware notification upon completion of data transmission. The notification delay is ≤1 system bus clock cycle.

[0071] Step four, core direct processing. The DSP core monitors dedicated interrupt signals in real time. Upon detecting an interrupt trigger, it immediately responds to the interrupt and enters the corresponding interrupt service routine. Based on the channel number in the interrupt signal, it directly reads data from the known address of the dedicated storage window for that channel in the DSP's local memory. Since the DSP's local memory is a tightly coupled memory, the DSP core's access to it has zero latency, allowing for rapid data acquisition and subsequent signal processing operations. In this embodiment, the DSP core's processing time for 32 complete 32-bit data words in a single burst transmission is ≤10μs, far lower than the processing time for reading data from the system's main memory in existing technologies.

[0072] Step 5, Hardware Synchronization Feedback. After the DSP core completes the processing of the batch of data, it clears the status flag register corresponding to the channel. The interrupt generation circuit continuously monitors the status flag register. When it detects that the status flag bit of the channel has been cleared, it immediately sends a synchronization signal to the dedicated hardware bridging module indicating that the channel's storage window can be rewritten. Upon receiving the synchronization signal, the dedicated hardware bridging module removes the transmission restriction on the channel, allowing the channel's FIFO to be triggered again by the controller to monitor and activate the transmission request. This forms a closed-loop hardware synchronization pipeline, enabling continuous, stable, and low-latency transmission and processing of I2S data.

[0073] In related technologies, the transmission of I2S data in embedded audio or real-time signal processing systems often relies on general-purpose DMA controllers. This requires software configuration of the DMA descriptor chain and coordination of bus arbitration, which not only introduces significant software overhead but also leads to uncertain transmission delays. Furthermore, data must first be written to the system's main memory, resulting in substantial access delays when the DSP core reads the data, making it difficult to meet the demands of high-end real-time processing applications. The system and method of this invention, by constructing a dedicated hardware bridging module and a direct storage path for DSP local storage, achieves autonomous transmission of multiple I2S data streams at the hardware level. This completely eliminates the bus arbitration delay and software configuration overhead caused by general-purpose DMA controllers. Simultaneously, the direct access characteristics of DSP local storage significantly improve the data read speed of the DSP core, ensuring that the end-to-end delay from the I2S interface to the DSP core's computational location is ≤10μs, achieving microsecond-level deterministic low-latency transmission.

[0074] The beneficial effects of this invention are as follows: First, it achieves autonomous direct storage of I2S data to the DSP's local memory through a dedicated hardware bridging module, eliminating the need for software intervention in data transfer and address management, effectively reducing the resource occupancy of the DSP core and allowing it to focus on signal processing algorithm execution. Second, the direct access design of the DSP's local memory eliminates the access latency of the system's main memory, improving the efficiency of data reading and processing. Simultaneously, the dedicated address mapping window of the local memory avoids address conflicts and bus contention with other bus devices. Third, through configurable arbitration strategies, circular addressing logic, and... The data packaging mechanism enhances the system's adaptability to different application scenarios and hardware platforms, while ensuring bus transmission efficiency and storage resource utilization. Fourth, through a closed-loop hardware synchronous pipeline, efficient collaboration between data transmission and processing is achieved. The triggering, arbitration, writing, notification, processing, and feedback of transmission requests are all completed by hardware, making the system's transmission latency deterministic and meeting the stringent latency requirements of real-time signal processing. Fifth, the parameterizable design of the dedicated hardware bridging module improves the module's reusability and allows it to be integrated as a standardized hardware module into different chip designs, reducing hardware development cycles and costs.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An I2S data DSP short-range storage and transmission system based on an arbitration mechanism, characterized in that, The system consists of: at least one I2S interface, a dedicated hardware bridging module, a DSP with local storage, a system bus, and a DSP core. The dedicated hardware bridging module is connected to the I2S interface and the system bus respectively; The DSP local storage is connected to the dedicated hardware bridge module via the system bus; The dedicated hardware bridging module includes multiple first-in-first-out (FIFO) memories, trigger controllers, arbitrators, address generation units, and bus master interfaces, each corresponding to one of the I2S interfaces. The trigger controller monitors the storage status of each FIFO and activates a transmission request when the storage amount of any FIFO reaches a preset trigger condition. The arbitrator arbitrates multiple activated transmission requests according to a preset strategy to determine the channel currently executing the transmission. The address generation unit pre-stores and independently maintains a base address pointer for each channel, pointing to a dedicated storage window in the DSP's near-field memory. After the channel obtains a transmission authorization, it automatically outputs the current address pointer value as the target address of the system bus transaction. After the transmission is completed, it automatically increments the pointer. The bus master interface initiates and completes a direct write transaction to the DSP near-field memory using the FIFO data corresponding to the channel selected by the arbitrator, according to the target address provided by the address generation unit. The DSP local storage has a pre-divided, contiguous physical address mapping window in the system bus address space, enabling write transactions initiated by the dedicated hardware bridging module to directly access the physical units of the local storage.

2. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The system also includes an interrupt generation circuit. After the dedicated hardware bridging module completes a direct write transaction to the DSP local memory, the interrupt generation circuit generates an interrupt signal pointing to the DSP core. In response to the interrupt signal, the DSP core directly reads data from the corresponding address in the DSP local memory for processing, and after processing, feeds back a synchronization signal to the dedicated hardware bridging module. The dedicated hardware bridging module also includes a data packer, which is connected between the first-in-first-out (FIFO) memory and the bus master interface. The data packer is used to combine multiple low-bit-width audio data samples from the FIFO memory into a complete data word that matches the system bus bit width, and then submit the complete data word to the bus master interface to initiate a write transaction.

3. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The address generation unit maintains a dedicated storage window for each channel, pointed to by a base address pointer. This window is continuously and fixedly allocated within the address space of the DSP's near-field storage. The address generation unit performs a pointer increment operation after each channel transmission is completed, where the increment step is equal to the byte length of a complete data word output by the data packer, thereby ensuring that continuously written data is sequentially arranged and address-aligned in the dedicated storage window.

4. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The preset triggering condition monitored by the trigger controller is that the amount of data cached in the first-in-first-out (FIFO) memory reaches or exceeds a preset water level threshold. The amount of data corresponding to the water level threshold is at least sufficient to enable the bus master device interface to initiate a complete system bus burst transmission.

5. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The DSP local storage is a secondary cache or tightly coupled memory of the DSP core; The dedicated hardware bridging module can directly access the storage units of the secondary cache or tightly coupled memory through the system bus without going through the system main memory.

6. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 2, characterized in that, The interrupt generation circuit includes a status flag register corresponding to each transmission channel in the dedicated hardware bridging module. After the dedicated hardware bridging module completes writing to the storage window corresponding to a certain channel, it automatically sets the status flag bit corresponding to that channel. The setting operation of the status flag directly triggers the generation of a dedicated interrupt signal to the DSP core. The DSP core is configured to: after responding to the interrupt signal and reading the processed data, perform a clear operation on the status flag register to reset the corresponding status flag bit; The dedicated hardware bridging module is configured to monitor the status flag bit and, after the status flag bit is reset, know that the storage window of the corresponding channel can be written to again.

7. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The address generation unit also maintains a circular addressing logic for a dedicated storage window for each channel; When the base address pointer increments to the end address of the dedicated storage window, the address generation unit automatically resets the base address pointer back to the starting base address of the dedicated storage window, thereby realizing the cyclic overwrite writing of data within a fixed-size buffer.

8. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The arbitrator's preset arbitration strategy is either a configurable static priority strategy or a round-robin scheduling strategy. The static priority strategy assigns a fixed priority weight to each I2S transmission channel; The polling scheduling strategy responds to the transmission requests of each channel in a fixed order.

9. The I2S data DSP near-field storage and transmission system based on arbitration mechanism according to claim 1, characterized in that, The dedicated hardware bridging module is designed as a parameterizable hardware functional module. The parameters include at least the number of supported I2S channels, the FIFO depth, the system bus width, and the base address and size of the DSP near-field memory mapping window.

10. An I2S data DSP local storage and transmission method based on an arbitration mechanism, applicable to any one of claims 2 to 9, characterized in that, The specific steps of this method are as follows: Step 1, System Initialization: Configure the parameters of each I2S interface, and allocate and map a dedicated fixed storage window for each I2S channel in the DSP near-field storage. Initialize the address pointers and arbitration strategies of each channel in the dedicated hardware bridging module. Step 2, Hardware Autonomous Direct Storage: The I2S interface continuously receives data and stores it in the corresponding FIFO memory. When the trigger controller detects that any FIFO has reached the trigger condition, the arbitrator arbitrates the current transmission channel, the address generation unit outputs the current target address of the channel, and the bus master device interface packages the data of the corresponding FIFO and directly writes it to the corresponding address of the DSP near-field storage. Step 3, precise hardware notification: After the direct write transaction is completed, the interrupt generation circuit automatically sets the status flag of the corresponding channel and triggers the DSP core interrupt; Step 4, Core Direct Processing: The DSP core responds to the interrupt, directly reads data from the known address in the DSP's local memory, and processes it; Step 5, Hardware Synchronization Feedback: After the DSP core completes processing, it clears the status flag. The dedicated hardware bridging module, based on the flag clearing status, knows that the channel storage window can be written to again, thus forming a closed-loop hardware synchronization pipeline.

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