Memory controller, control method of memory controller, and computer device
By introducing a shared SRAM physical array into the memory controller and dynamically configuring the mode according to workload characteristics, the problems of low resource utilization and long data paths in the DDR memory controller and last-level cache separation architecture are solved, achieving efficient utilization of storage resources and performance improvement.
CN121880263BActive Publication Date: 2026-07-10MOXIN ARTIFICIAL INTELLIGENCE TECH (SHENZHEN) CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MOXIN ARTIFICIAL INTELLIGENCE TECH (SHENZHEN) CO LTD
- Filing Date
- 2026-03-09
- Publication Date
- 2026-07-10
AI Technical Summary
Technical Problem
The existing system-on-chip architecture with separate DDR memory controller and last-level cache leads to problems such as low hardware resource utilization, long data paths, and increased power consumption and latency.
Method used
By introducing a shared SRAM physical array into the memory controller, and dynamically configuring it as a read reordering buffer, last-level cache, or hybrid mode according to runtime workload characteristics, efficient utilization and flexible adaptation of storage resources can be achieved.
Benefits of technology
It significantly reduces chip area, avoids resource waste, reduces data movement power consumption, improves data reading performance, and is adaptable to various application scenarios.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN121880263B_ABST
Abstract
The disclosure provides a memory controller, a control method of the memory controller and a computer device, and relates to the technical field of integrated circuits.The memory controller comprises an on-chip interconnection interface, a DRAM interface, a shared storage unit and a control unit configured to monitor a runtime workload characteristic of a memory access request received through the on-chip interconnection interface, configure the memory controller into a read-only reorder buffer mode in response to determining that the workload characteristic meets a first condition, configure the memory controller into a last-level cache-only mode in response to determining that the workload characteristic meets a second condition, and divide the shared storage unit into a first logical area serving as a read-only reorder buffer and a second logical area serving as a last-level cache in response to determining that the workload characteristic meets a third condition. Efficient utilization and flexible adaptation of on-chip storage resources in the memory controller are achieved.
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