Three-layer merging element transport sub-qubits

Abstract

A quantum circuit and related manufacturing method are disclosed. The quantum circuit includes a vertical Josephson junction (1001) formed by a bottom electrode (810) in the first superconducting material layer, a tunnel barrier (830), and a top electrode (820) in the second superconducting material layer. A contact portion (811) and a coupling portion (812) of the bottom electrode are respectively located inside and outside the Josephson junction. The transport sub-qubit of the quantum circuit comprises a Josephson junction (101) and a shunt capacitor formed from contacts of a top electrode and a bottom electrode as shunt capacitor plates. The readout circuit is capacitively coupled to the bottom electrode through the coupling and includes a coupling head (861). The coupling portion is fitted into the recess of the coupling head. The top electrode is configured as a floating electrode and is not resistance-coupled to the first superconducting material layer.

Description

Technical Field

[0001] This invention relates to the field of superconducting quantum circuits, and more specifically to three-layer merged-element transmon qubit devices. Background Technology

[0002] By cleverly utilizing quantum superposition, interference, and entanglement, quantum computers promise to solve complex computational problems more efficiently than today's most powerful classical computers. Various scalable qubit implementations for precise quantum computing are currently being explored, but these require significant effort and are technically challenging. One widely pursued and promising approach for qubit implementations in quantum computing applications is the use of superconducting circuits, including Josephson junctions.

[0003] A transporter is a type of superconducting qubit in which a Josephson junction is electrically connected in parallel with a shunt capacitor, the capacitance of which is larger than the stray capacitance of the Josephson junction. This results in a significantly reduced sensitivity of the superconducting qubit to charge noise, while maintaining a sufficient degree of anharmonicity in each quantum state. Material defects and imperfections, primarily located on the surface and interfaces, have a significant detrimental effect on the quantum coherence properties of transporter qubits, which are crucial for high-fidelity quantum computing applications. To minimize their impact, the shunt capacitor of the transporter is typically implemented as a large coplanar device. Unfortunately, this approach results in a device footprint of transporter qubits approaching square millimeters, which lacks the compactness required to scale to high areal density qubit processors.

[0004] Zhao Ruichen et al., in “Merged-element transmon”, Physical Review Applied, Vol. 14, No. 6, 2020, described a merged-element transmon qubit with a reduced device size. In this transmon, a large external shunt capacitor was replaced by the self-capacitance of the Josephson junction. The merged-element transmon qubit structure was etched into a sputtered Nb / a-Si / Nb trilayer, and an Nb air bridge was formed over the qubit device to electrically connect the top electrode of the qubit to ground. However, forming the Nb air bridge requires applying a protective amorphous dielectric filler to the transmon qubit and then removing it. This process introduces new material defects and imperfections within and around the Josephson junction region, resulting in poor performance of the qubit device in terms of achievable coherence time.

[0005] A compact transporter qubit circuit system with improved coherence characteristics is needed. Summary of the Invention

[0006] The objective of this invention is to provide a transport subqubit with improved coherence characteristics. This objective is achieved by a quantum circuit comprising a vertically coupled array of transport subqubits according to the claims and a related method of fabrication.

[0007] In one aspect, the present invention relates to a quantum circuit comprising a vertical Josephson junction and a transport qubit. The vertical Josephson junction is formed on a substrate and includes a bottom electrode, a tunnel barrier, and a top electrode. A contact portion of the bottom electrode is located inside the vertical Josephson junction, while a coupling portion of the bottom electrode is located outside the vertical Josephson junction. The bottom electrode is formed in a first superconducting material layer, while the top electrode is formed in a second superconducting material layer. The transport qubit includes the vertical Josephson junction and a shunt capacitor formed by the overlapping portion of the top and bottom electrodes within the vertical Josephson junction. A readout circuit including a coupling head is capacitively coupled to the bottom electrode via the coupling portion. The coupling portion of the bottom electrode is fitted into / engaged to a recess in the coupling head of the readout circuit. This means that an interlock between the coupling portion of the bottom electrode and the coupling head of the readout circuit can be established non-contactly, allowing capacitive coupling between the bottom electrode and the readout circuit for qubit state measurement. The top electrode of the vertical Josephson junction is configured as a floating electrode, non-resistively coupled to the first superconducting material layer.

[0008] In various embodiments, the vertical direction can be defined by a vertical Josephson junction, i.e., the contact portion of the bottom electrode, the tunnel barrier, and the top electrode are disposed in different material layers stacked vertically.

[0009] In various embodiments, the contacts of the top and bottom electrodes act as the relative capacitor plates of the shunt capacitor for transmitting the subqubit. This allows for reduction or elimination of charge noise and eliminates the need for an additional shunt capacitor outside the Josephson junction.

[0010] In various embodiments, the coupling portion of the bottom electrode acts as a coupling capacitor relative to the coupling head portion of the readout circuit. In various embodiments, the recess in the coupling head of the readout circuit can be formed as a receiving slot relative to the coupling portion of the bottom electrode. This optimizes capacitive coupling. The advantage of providing a dedicated coupling portion for the bottom electrode outside the Josephson junction is that the coupling between the Josephson junction and the readout circuit can be designed almost independently, with fewer constraints and greater design freedom. This also allows for improved capacitive coupling between the bottom electrode and the readout circuit to obtain a stronger readout signal and reduced parasitic capacitive coupling between the top electrode and the readout circuit.

[0011] In various embodiments, the readout circuit can be configured to perform dispersion readout of the qubit state (e.g., configured to induce and detect dispersion shifts with the resonant frequency of the readout resonator coupled to the transport qubit). Furthermore, the readout circuit may include a readout resonator. The readout resonator can be provided as a coplanar waveguide, which is easy to implement, has a high quality factor, low dispersion, good broadband operation, is unaffected by uncontrolled stray inductance or capacitance, and has a characteristic impedance value that can be precisely controlled. The quality factor of the readout resonator is Q ≥ 30000, and a normalized dispersion shift |X| / k > 1.0 can be obtained (where X represents the dispersion shift and k is the linewidth of the readout resonator). For example, transport qubit state-dependent readout resonator dispersion shifts on the order of 100 kHz can be achieved, which is compatible with readout resonator linewidths up to 100 kHz. The readout resonator can be formed in a first superconducting material layer. The impedance value of the readout resonator can be at least 100 ohms. In various embodiments, the readout circuit may also include a transmission line electrically (e.g., capacitively) coupled to the readout resonator. To simplify circuit fabrication, the transmission line may also be formed in a first superconducting material layer.

[0012] In various embodiments, the readout circuit may be formed in the first superconducting material layer to achieve coplanar capacitive coupling with the bottom electrode through the coupling head portion of the readout circuit and the coupling portion of the bottom electrode.

[0013] In various embodiments, the readout circuit may, for example, act as a drive circuit relative to the transport subqubit, to drive the transport subqubit. This means that the transitions between the quantum states of the transport subqubit and / or the fabrication of the transport subqubit in a specific quantum state (which may be a quantum superposition of the ground state and the first excited state) can be driven or induced by applying a corresponding electrical pulse or pulse sequence to the readout circuit. In alternative embodiments, a separate drive line may be provided in addition to the readout circuit. This drive line may be arranged to pass through or have an end close to the transport subqubit. In this alternative embodiment, the bottom electrode may be configured to extend out of the Josephson junction region at more than one location along the junction periphery, thereby connecting the contact to the coupling portion (as described above) and further to the drive portion. Similar to the coupling portion, the drive portion may include finger-like, strip-like, or multi-finger structures to allow strong capacitive coupling with the additional drive line. The drive line may include terminal segments of complementary shapes for receiving the drive portion, such as resulting in an interlocked, contactless configuration of the drive line and the drive portion of the bottom electrode, similar to the interlocked, contactless configuration of the readout circuit coupling head and the coupling portion of the bottom electrode. Furthermore, the drive section can be connected to the contact section of the bottom electrode via a tapered segment. The drive section and the coupling section can be connected and extend from opposite sides of the contact section of the bottom electrode, or they can be connected and extend from the contact section of the bottom electrode at an angle (e.g., a right angle).

[0014] In various embodiments, the bottom electrode coupling portion and the readout circuit coupling head may have complementary interlocking profiles, wherein the interlocking is loose and non-contact, but includes a space between the two interlocking portions. The bottom electrode coupling portion may include or be formed as a fork, finger, or tongue, while the readout circuit coupling head may have a recess, slot, or slit for receiving a corresponding fork, finger, or tongue of the bottom electrode coupling portion, for example in a flat or planar version of the mortise (cut) and tenon (tongue) interlocking profile.

[0015] In various embodiments, the quantum circuit may further include a ground contact region arranged for capacitive coupling with the contact portion of the bottom electrode. The ground contact region may be arranged adjacent to but separate from the vertical Josephson junction.

[0016] In various embodiments, a ground contact region may be formed in the first superconducting material layer. The ground contact region may be configured as a ground plane adjacent to the contact portion of the bottom electrode. In various embodiments, the ground contact region (e.g., a ground plane) is useful for providing shielding and voltage reference.

[0017] In various embodiments, the grounding contact area and the bottom electrode can be a coplanar structure of the first superconducting material.

[0018] In various embodiments, the ground contact region and the bottom electrode can be separated from each other by gaps in each lateral direction perpendicular to the vertical direction defined by the vertical Josephson junction. The size of the gap can vary along the perimeter of the bottom electrode. The size of the gap can be smaller along the edge of the contact portion of the bottom electrode compared to the edge of the coupling portion. The size of the gap can increase between the contact portion and the coupling portion of the bottom electrode. The size of the gap can be constant along the perimeter of the contact portion of the bottom electrode, except for the connection end of the contact portion that engages with the coupling portion of the bottom electrode. Furthermore, if the ground contact region is disposed in a material layer different from the first superconducting material layer, a vertical gap can separate the ground contact region and the bottom electrode along the vertical direction.

[0019] In various embodiments, the ground contact area is arranged away from the bottom electrode. This means that the ground contact area does not directly contact or adjoin the contact portion of the bottom electrode. A gap may be formed in the plane of the first superconducting material layer, separating the ground contact area from the bottom electrode. In various embodiments, the coupling portion of the bottom electrode is preferably arranged further away from the ground contact area than the contact portion of the bottom electrode. The gap in the plane of the first superconducting material layer that separates the ground contact area from the bottom electrode may be wider along the boundary or periphery of the contact portion of the bottom electrode than along the boundary or periphery of the coupling portion of the bottom electrode.

[0020] In other embodiments, a ground contact region may be formed in a third superconducting material layer above or on top of the second superconducting material layer. In other words, the third superconducting material layer may be in contact with / adjacent to / attached to the second superconducting material layer, or it may be separated from the second superconducting material layer by one or more intermediate layers. The second superconducting material layer may be disposed between the first and third superconducting material layers. The ground contact region may be formed in the third superconducting material layer adjacent to the top electrode, but not adjacent to or adjacent to the top electrode. The ground contact region may be vertically (i.e., along the vertical direction of the Josephson junction) separated from the top electrode by a height distance between the third and second superconducting material layers, and the ground contact region may be laterally offset relative to the top electrode (i.e., in a direction perpendicular to the vertical direction of the Josephson junction). The offset in each lateral direction may be large enough to obtain a non-overlapping ground contact region that does not overlap with the top electrode in the second superconducting material layer below the third superconducting material layer. The ground contact region may be configured as a ground plane of the third superconducting material layer.

[0021] The advantage of having a gap between the ground contact region and the periphery of the Josephson junction is that the different components of the quantum circuit (transmitter, ground contact, readout / drive) can be defined by (photolithography) patterning and selective material removal (e.g., etching) from different material layers of a prefabricated multilayer material stack or wafer. No additional functional layers for quantum circuit operation need to be deposited or grown, which might require further processing or temperature treatment. This limits the introduction or propagation of surface defects, thereby improving the coherence characteristics of the quantum circuit. Furthermore, the gap size can be optimized to achieve strong capacitive coupling between the top electrode of the Josephson junction and the electrical ground, thus improving readout coupling strength.

[0022] Furthermore, the gap between the ground contact region and the outer periphery of the Josephson junction can extend through the interface between the bottom electrode and the substrate and partially into the substrate. A recess can be defined on the upper surface of the substrate, which coincides with the gapped region across the entire surface of the planar quantum circuit. Partial removal of substrate material in the gapped region results in the bottom electrode, coupling head, and readout resonator structure being formed on and supported by a base of substrate material. This has the advantage that a larger volume of the electric edge field exists in a vacuum rather than in the substrate dielectric, which can further reduce dielectric losses.

[0023] In various embodiments, the contact portion of the bottom electrode may correspond to the junction-forming portion of the bottom electrode located inside the Josephson junction.

[0024] In various embodiments, the top electrode of the Josephson junction may completely overlap with the contact portion of the bottom electrode disposed below the top electrode.

[0025] In various embodiments, the contacts of the top electrode, tunnel barrier, and bottom electrode of the vertical Josephson junction may have the same shape or profile.

[0026] In various embodiments, the vertical projections of the top electrode of the vertical Josephson junction and the respective perimeters (outer edges) of the tunnel barrier onto a common plane are preferably aligned or coincident.

[0027] In various embodiments, the vertical projections of the respective perimeters (outer edges) of the contacts of the top electrode, tunnel barrier, and bottom electrode of the vertical Josephson junction onto a common plane may coincide.

[0028] In various embodiments, the top electrode of the vertical Josephson junction and the adjacent sidewalls of the tunnel barrier (e.g., walls whose surface normals are substantially perpendicular to the vertical direction of the Josephson junction) may be adjacent to each other.

[0029] In various embodiments, the outer walls of adjacent portions of the contacts of the top electrode, tunnel barrier, and bottom electrode of the vertical Josephson junction (e.g., walls whose surface normals are substantially perpendicular to the vertical direction of the Josephson junction) may be adjacent to each other.

[0030] In various embodiments, the outer sidewalls of the contacts of the top electrode, tunnel barrier, and bottom electrode can be vertical sidewalls, i.e., straight sidewalls that rise at a 90-degree angle relative to the upper flat surface of the lower substrate. Nevertheless, the outer sidewalls of the contacts of the top electrode, tunnel barrier, and bottom electrode can be slightly inclined, for example, oriented at a direction of 90°+ / -20° relative to the upper flat surface of the lower substrate.

[0031] In various embodiments, a tunneling barrier may be disposed between the contact portion of the bottom electrode and the top electrode. The top electrode may be formed on top of the bottom electrode and the tunneling barrier.

[0032] In various embodiments, the contact portion of the bottom electrode can be covered by a tunnel barrier.

[0033] In various embodiments, the tunnel barrier may be covered by the top electrode.

[0034] In various embodiments, the bottom electrode may be in direct contact with the substrate or supported by the substrate.

[0035] In various embodiments, the bottom electrode can be formed as a single interconnected structure, wherein the contact portion and the coupling portion are disposed at opposite ends.

[0036] In various embodiments, the contact portion of the bottom electrode can be directly connected to the coupling portion of the bottom electrode. In other embodiments, the contact portion and the coupling portion of the bottom electrode can be connected via an intermediate connecting portion (such as a tapered connecting portion of the bottom electrode).

[0037] In various embodiments, the bottom electrode may include a middle portion for connecting the contact portion of the bottom electrode to the coupling portion of the bottom electrode. The middle portion of the bottom electrode may be located outside the vertical Josephson junction. The middle portion of the bottom electrode may be tapered.

[0038] In various embodiments, the shape or outline of the coupling portion of the bottom electrode can resemble fingers, tongues, forks, or strips in the first superconducting material layer.

[0039] In various embodiments, the coupling portion of the bottom electrode may correspond to an elongated strip or a single-finger coupling structure of the first superconducting material. In other embodiments, the coupling portion of the bottom electrode may correspond to a cross-finger coupling structure of the first superconducting material.

[0040] In various embodiments, the coupling portion of the bottom electrode may extend along a preferred direction within the first superconducting material layer, for example, it may be shaped into a long and narrow section of the first superconducting material, whereby the width of the coupling portion is less than the length of the coupling portion. Preferably, the width of the coupling portion is greater than the width of the contact portion at its closest point to the tip of the coupling portion (the tip).

[0041] In various embodiments, in a top view of the quantum circuit, the inner edge of the ground contact region can—without contacting or intersecting—define, surround, or enclose the outer edge of the contact portion of the bottom electrode. Similarly, the vertical projection of the boundary (perimeter, edge) of the ground contact region onto the plane of the first superconducting material layer can—without contacting or intersecting—define, surround, or enclose the boundary (perimeter, edge) of the contact portion of the bottom electrode.

[0042] In various embodiments, in a top view of the quantum circuit, the inner edge of the ground contact region may—without contacting or intersecting—define, surround, or enclose the outer edge of the top electrode, except at the end of the top electrode where the contact portion of the underlying bottom electrode is transitioning toward or adjacent to the coupling portion of the bottom electrode. Similarly, the vertical projection of the boundary (perimeter, edge) of the ground contact region onto the plane of the second superconducting material layer may—without contacting or intersecting—define, surround, or enclose the boundary (perimeter, edge) of the top electrode, except at the end of the top electrode where the contact portion of the underlying bottom electrode is transitioning toward or adjacent to the coupling portion of the bottom electrode.

[0043] In various embodiments, in a top view of the quantum circuit, the inner edge of the ground contact area may—without contacting or intersecting—limit, surround, or enclose the outer edge or sidewall of the Josephson junction, except at the end of the Josephson junction, where the contact portion of the bottom electrode is transitioning toward or adjacent to the coupling portion of the bottom electrode.

[0044] In various embodiments, in a top view of the quantum circuit, the inner edge of the ground contact region may—without contacting or intersecting—define, surround, or enclose the outer edge or sidewall of the tunnel barrier, except at the end of the tunnel barrier where the contact portion of the bottom electrode is transitioning toward or adjacent to the coupling portion of the bottom electrode. Similarly, the vertical projection of the boundary (perimeter, edge) of the ground contact region onto the plane containing the tunnel barrier may—without contacting or intersecting—define, surround, or enclose the boundary (perimeter, edge) of the tunnel barrier, except at the end of the tunnel barrier where the contact portion of the underlying bottom electrode is transitioning toward or adjacent to the coupling portion of the bottom electrode.

[0045] In various embodiments, the sidewalls or outer surface of the tunnel barrier of the Josephson junction may be bonded to air, a vacuum, or an inert gas.

[0046] In various embodiments, the sidewalls or outer surfaces of the contact portion of the bottom electrode may be bonded to air, a vacuum, or an inert gas.

[0047] In various embodiments, the sidewalls or outer surfaces of the bottom electrode may be bonded to air, a vacuum, or an inert gas.

[0048] In various embodiments, the sidewalls or outer surfaces of the top electrode may be bonded to air, a vacuum, or an inert gas.

[0049] In transport subqubits of combined elements, the electric field is confined within the junction region. Using air, vacuum, or an inert gas instead of dielectric filler or substrate material as the surrounding medium for bonding with the sidewalls of a vertical Josephson junction has the advantage of avoiding dielectric losses, which would lead to a reduction in the coherence time of the transport subqubit.

[0050] In various embodiments, the vertical Josephson knot can be a three-layer knot.

[0051] In various embodiments, a tunneling barrier can be formed within a barrier layer. The first superconducting material layer, the barrier layer, and the second superconducting material layer can be patterned layers of a three-layer material stack. The three-layer material stack can be prefabricated under optimized growth conditions for the different material layers, thereby producing high-quality and flat material layers even at the wafer scale.

[0052] In various embodiments, the barrier layer can be provided as an insulating material layer, such as a dielectric layer. The dielectric layer can be a non-amorphous dielectric layer, such as a crystalline dielectric layer. Non-amorphous tunneling barriers advantageously reduce losses and improve the coherence characteristics of qubits.

[0053] In various embodiments, the top electrode may be without resistive electrical contacts. The contactless top electrode may be provided in its original state. The original state of the top electrode may include an outwardly facing upper surface opposite the tunnel barrier, which is continuous and smooth and not interrupted by any outwardly projecting structures. The upper surface may not have any deposited metallic structures. Providing a top electrode without any resistive contacts has the advantage of avoiding the introduction of material defects and imperfections during contact formation.

[0054] In various embodiments, the top electrode may have a smooth and continuous upper surface facing away from the tunnel barrier and a lower surface facing the tunnel barrier. The upper surface of the top electrode may be a flat surface. The upper surface of the top electrode may be bonded to a vacuum, air, or a protective dielectric layer over its entire surface area.

[0055] In embodiments of the invention, the capacitance of the shunt capacitor of the transport subqubit corresponds to the self-capacitance of the vertical Josephson junction. This means that the transport subqubit is of the combined element type. Combined element transport subqubits are advantageous in terms of improved compactness and reduced footprint because they do not require electrical connections to large external capacitors.

[0056] In various embodiments, the vertical Josephson junction may have a junction length along a first direction parallel to the substrate and a junction width along a second direction parallel to the substrate, the second direction being perpendicular to the first direction, and the ratio of the junction width to the junction length may be at most 0.02.

[0057] In various embodiments, the vertical Josephson knot may have a knot area of ​​size "A" and a knot perimeter of length "P", such that .

[0058] In various embodiments, the vertical Josephson junction can have a rectangular shape with a width of "w" and an area of ​​"A", and the gap separating the grounding contact area and the vertical Josephson junction can have a gap width of "G", such that... .

[0059] In various embodiments, one or both of the first and second superconducting material layers may include aluminum.

[0060] In various embodiments, the tunnel barrier can be formed in a dielectric layer, preferably comprising aluminum oxide. Aluminum is a commonly used superconductor and is readily oxidized to form a high-quality tunnel barrier. High-purity aluminum can be obtained at the wafer scale using well-known epitaxial growth processes.

[0061] In various embodiments, the vertical sidewalls of the vertical Josephson junction may be free of deposited dielectric residues.

[0062] In another aspect, the present invention relates to a method for manufacturing the aforementioned quantum circuit. The method includes the following steps:

[0063] A multilayer material stack comprising a first superconducting material, a dielectric layer, and a second superconducting material is provided on a substrate.

[0064] A bottom electrode is formed in a first superconducting material. The bottom electrode includes a contact portion and a coupling portion.

[0065] A top electrode is formed in the second superconducting material, and the top electrode is configured as a floating electrode that is not resistively coupled to the first superconducting material layer.

[0066] A transport qubit is formed comprising a vertical Josephson junction and a shunt capacitor, wherein the vertical Josephson junction includes a contact portion of the bottom electrode, a tunnel barrier formed in the dielectric layer, and a top electrode, and the shunt capacitor includes the contact portion of the top electrode and the bottom electrode serving as a shunt capacitor plate.

[0067] The readout circuit capacitor is coupled to the bottom electrode, including interlocking without the coupling portion of the bottom electrode coming into contact with the recess formed in the coupling head of the readout circuit.

[0068] In various embodiments, the method may further include the step of forming a ground contact region in a third superconducting material layer on top of the first or second superconducting material layer. The ground contact region is formed adjacent to a vertical Josephson junction. The ground contact region may have a ground plane structure.

[0069] In various embodiments, providing a multilayer material stack may include depositing a first superconducting material layer, a dielectric layer, and a second superconducting material layer on a substrate. For example, additional material layers, such as a third superconducting material layer, a buffer layer, or a seed layer, may be deposited on the second superconducting material layer or between the substrate and the first superconducting material layer. The first superconducting material layer, the second superconducting material layer, the tunnel barrier layer, and other optional layers may be provided as a multilayer stacked film, such as an epitaxially stacked thin film.

[0070] In various embodiments, depositing the first superconducting material layer, the second superconducting material layer, and / or the tunnel barrier layer may include epitaxially growing these layers or depositing them using sputtering, vapor deposition, or atomic layer deposition techniques. Depositing the dielectric layer for the tunnel barrier may include depositing and subsequently oxidizing a metal or semiconductor layer, which may correspond to a portion of the thickness of the first superconducting material layer.

[0071] In various embodiments, forming the top electrode may include patterning (e.g., photolithography through the resist) and selectively removing material from the second superconducting material layer. Material from the dielectric layer may be selectively removed simultaneously with (e.g., in the same removal process step) or immediately after the selective removal of material from the second superconducting material layer. If material from the dielectric layer is selectively removed together with material from the second superconducting material layer, the same pattern definition or patterned structure can be used. That is, a thickness portion of the dielectric layer, which may include the full thickness of the dielectric layer, can be etched together with the second superconducting material layer. This has the advantage that structures such as Josephson junction profiles are aligned with both the second superconducting material layer and the dielectric layer. This avoids additional photolithographic alignment steps.

[0072] In various embodiments, the method may further include the step of forming a tunnel barrier. This may include patterning (e.g., photolithography through a resist) and selectively removing material from the dielectric layer.

[0073] In various embodiments, forming the bottom electrode may include patterning (e.g., photolithography through the resist) and selectively removing material from the first superconducting material layer. Material from the underlying substrate may be selectively removed simultaneously with (e.g., in the same removal process step) or immediately after the selective removal of material from the first superconducting material layer. If material from the substrate is selectively removed together with material from the first superconducting material layer, the same pattern definition or patterned structure can be used. In other words, the thicker portions of the substrate may be etched together with the first superconducting material layer.

[0074] In other embodiments, forming the bottom electrode may include patterning (e.g., photolithography through a resist) and selectively removing material from the second superconducting material layer. The resulting pattern of the bottom electrode in the second superconducting material layer is then transferred to the first superconducting material. This may include etching through the layer thickness associated with the second superconducting material layer and etching into a material layer beneath the second superconducting material layer, such as etching into an insulating barrier layer and further into the first superconducting material layer. The top electrode can then be formed by selectively removing excess material in the second superconducting material layer that does not contribute to or belong to the top electrode structure.

[0075] In various embodiments, patterning the first superconducting material layer, the dielectric layer, and / or the second material layer may include the following steps: depositing a resist layer, exposing the resist to optical or electron beam irradiation to define an area to be etched according to a photolithographic pattern (e.g., a mask pattern), and developing the resist to define an opening in the resist corresponding to the area to be etched.

[0076] In various embodiments, selective removal of material from the first superconducting material layer, the dielectric layer, and / or the second material layer may include, for example, etching away the material of these layers in areas not protected by the resist layer.

[0077] One advantage of this invention is that the floating three-layer merged transport element can be fabricated from any superconductor-insulator-superconductor three-layer stack with only two patterning steps and no further material addition, thereby potentially reducing introduced material defects and improving qubit coherence. The Josephson junction can be maintained in its original state, which improves the quality of the tunnel barrier.

[0078] One advantage of this invention is that the quantum circuit can serve as a vehicle for testing transmitted qubits. The increased barrier sensitivity and area insensitivity of the transmitted qubits can be utilized to identify and characterize better-performing Josephson junction material combinations (e.g., three-layer stacks) and to develop methods to reduce fabrication variability.

[0079] Another advantage of this invention is that non-oxide insulators can be used as tunnel barriers and tested.

[0080] Another advantage of this invention is that quantum circuits can be fabricated at a high quantum bit density on a wafer scale and in a CMOS-compatible manner. Angled shading evaporation of the Josephson junction material is not required. Furthermore, protective dielectric fillers or spacers are not required during circuit fabrication, as these materials could introduce additional interface defects along the Josephson junction sidewalls or be difficult to remove later without damaging the junction.

[0081] Another advantage of this invention is that the coupling between the transport qubit and the readout circuit can be achieved through a compact coupling structure, thereby avoiding the use of an extended and narrow antenna-like coupling structure.

[0082] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features of the dependent claims may be suitably combined with features of the independent and other dependent claims, not merely those expressly set forth in the claims.

[0083] For the purpose of summarizing the invention and its advantages over the prior art, certain objects and advantages of the invention have been described above. It should be understood, of course, that not all such objects or advantages may be achieved according to any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention can be embodied or practiced in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0084] The above and other aspects of the invention will be apparent from the embodiments described below and will be illustrated with reference to the embodiments. Attached Figure Description

[0085] The invention will now be further described by way of example with reference to the accompanying drawings, in which:

[0086] Figure 1 This is a top view showing a portion of a quantum circuit according to a first embodiment of the present invention.

[0087] Figure 2 yes Figure 1 A magnified perspective view of the quantum circuit in the image.

[0088] Figure 3 yes Figure 1 A cross-sectional view of a Josephson junction in a quantum circuit.

[0089] Figure 4 An equivalent circuit diagram of the quantum circuit according to the first embodiment is shown.

[0090] Figure 5 The frequency-junction barrier thickness relationship of the combined element transport subqubits according to an embodiment of the present invention is shown.

[0091] Figure 6 The combined effect of the circumferential gap width and the aspect ratio of the Josephson junction area on the coupling capacitance between the junction top electrode and the ground contact area, according to an embodiment of the present invention, is illustrated.

[0092] Figure 7 The combined effect of the circumferential gap width and the Josephson junction area aspect ratio on readout contrast is shown in an embodiment of the present invention.

[0093] Figure 8 This is a top view showing a portion of a quantum circuit according to a second embodiment of the present invention.

[0094] Figure 9 yes Figure 8 An enlarged view of the transport qubit in a quantum circuit.

[0095] Figure 10 yes Figure 8 A cross-sectional view of a portion of the quantum circuit shown.

[0096] Figure 11 The steps of a method for manufacturing a quantum circuit according to an embodiment of the present invention are shown.

[0097] These figures are illustrative only and are not restrictive. No reference numerals in the claims should be construed as limiting the scope. In different figures, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0098] The invention will be described with reference to specific embodiments and accompanying drawings, but the invention is defined only by the claims.

[0099] It should be noted that the term "comprising" as used in the claims should not be construed as limiting itself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the features, integers, steps, or components stated as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the scope of the expression "device comprising means A and B" should not be limited to a device consisting solely of components A and B. It means that for the present invention, the only relevant components of the device are A and B.

[0100] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in an embodiment" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner, as will be apparent to those skilled in the art from this disclosure.

[0101] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this approach of the disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, the inventive aspect lies in fewer features than all the features of a single foregoing disclosed embodiment. Thus, the claims appended to the Detailed Description are thereby expressly incorporated into this Detailed Description, wherein each claim itself represents a separate embodiment of the invention.

[0102] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention can be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0103] In the following text, as is generally understood in the art, a "three-layer" transport qubit refers to a transport qubit whose Josephson junction is etched into a prefabricated three-layer material stack. This means that the three-layer stack is first deposited and then etched into shape. A three-layer transport qubit differs from a transport qubit with an overlapping Josephson junction, where the bottom electrode is first patterned, then a barrier layer and a top electrode layer are deposited, and then the top electrode structure is etched. Furthermore, a three-layer transport qubit also differs from a transport qubit with a "shadow-evaporated" Josephson junction, where the bottom electrode is first deposited at one angle using a resist shadow mask, then partially oxidized to form a barrier layer, and finally covered by a top electrode structure deposited at another angle (all of which are deposited in situ using the same resist pattern).

[0104] Figure 1 This is a top view illustrating a portion of a quantum circuit according to a first embodiment of the present invention. The quantum circuit 100 includes a transport qubit structure having a cross-shaped, vertically oriented Josephson junction 101. Here, vertical orientation means that the Josephson junction is established along a vertical axis (e.g., the Z-axis), and different junction material layers are stacked along this vertical axis. Furthermore, the interfaces between adjacent materials of the Josephson junction and the resulting Josephson junction region extend in a plane perpendicular to the vertical axis (e.g., the XY plane). The bottom electrode structure 110 of the quantum circuit has a contact portion 111 located inside the Josephson junction 101 and a coupling portion 112 located outside the Josephson junction 101. Thus, a portion of the bottom electrode 110 extends beyond the junction region and outside the junction region. The coupling portion 112 of the bottom electrode 110 is fitted and extends into a corresponding recess 162 of a coupling head 161. A readout resonator structure 163, such as a coplanar waveguide structure, includes the coupling head 161 as an end, for example, terminated by the coupling head 161 or having one end connected to the coupling head 161. Both the readout resonator structure 162 and the coupling head 161 form part of a larger readout circuit 160. Although not shown, additional components of the readout circuit 160 may exist in the quantum circuit, such as a Purcell filter, transmission line, or feeder capacitively coupled to the readout resonator 163.

[0105] As shown, the recess 162 can be formed as a receiving slot for the coupling portion 112. The latter has corresponding fingers, forks, or strip segments that are appropriately interlocked with the receiving slot in a non-contact manner. Here, non-contact interlocking means that the edges of the coupling portion and the recess do not physically contact each other, thus avoiding resistive connections, and are instead separated by narrow insulating spaces or gaps. This achieves good capacitive coupling between the coupling portion 112 and the coupling head 161, and between the bottom electrode 110 and the readout resonator 163. For the transport qubit resonant frequency in the range of 4 GHz to 10 GHz, the associated qubit-readout circuit coupling constant (coupling strength g / 2π) can be about 3-10 MHz or greater, for example, 3-50 MHz. If a larger Josephson junction area with a thicker tunnel barrier is desired (which tends to achieve a greater coupling strength), atomic layer deposition of the tunnel barrier layer is superior to sputter deposition. In various embodiments, the recess and the coupling portion can be shaped and arranged in various other ways to interlock (but not contact each other) and provide good capacitive coupling.

[0106] The bottom electrode 110 preferably also includes a tapered segment 113 that connects the coupling portion 112 outside the Josephson junction 101 and the contact area 111 inside the Josephson junction 102. Alternatively, the coupling portion 112 may include a tapered segment 113 that connects the contact portion to the coupling portion of the bottom electrode. The tapered segment 113 ensures that the width of the bottom electrode (measured along the X-axis) smoothly transitions from the narrower contact portion inside the Josephson junction 101 to the wider coupling portion outside the Josephson junction 102 and inside the recess 162. The wider coupling portion of the bottom electrode outside the Josephson junction has the advantage of increasing the electrode surface area outside the Josephson junction region, thereby achieving stronger capacitive coupling between the bottom electrode and the readout circuitry without excessively increasing the capacitive coupling between the bottom electrode and the ground contact area. The smooth transition eliminates unwanted parasitic inductance or capacitance.

[0107] A ground contact region 150, separated from the readout circuit 160, provides a reference voltage, such as a ground (GND) signal, to the readout resonator 163 and the coupling head 161. The ground contact region 150, which can be implemented as a ground plane, extends from both sides of the readout resonator 163 and the coupling head 161 toward the Josephson junction 101 and wraps around the perimeter of the Josephson junction to surround it by following its outer perimeter (i.e., the perimeter). The opposing electrodes (top and bottom) perpendicular to the Josephson junction are capacitively coupled to the ground plane 150. By making the ground contact region almost completely surround or encircle the Josephson junction region, good capacitive coupling is achieved between the top electrode of the Josephson junction 101 and the ground contact region 150, except for the narrow space at the tip of the Josephson junction 101 (where the contact 111 of the bottom electrode 110 connects to the coupling 112).

[0108] An insulating space 102 (preferably an air gap or vacuum gap) extends and separates the ground contact region 150 and the vertical Josephson junction 101 on one hand, and extends and separates the ground contact region 150 and the readout circuitry 160 on the other. In the gap region of the quantum circuitry 100, the bare substrate 140 can be exposed. Furthermore, the orientation and / or width dimension 'G' of the gap 102 can be approximately constant locally, but varies globally in the XY plane. For example, the gap region between the edge of the Josephson junction 101 and the ground plane 150 is narrower (smaller) than the gap region between the coupling head 161 and the ground plane 150. The gap width also increases along the cone 113 from or near the tip of the Josephson junction. The gap width can be measured in the direction perpendicular to the sidewall forming the gap (i.e., the surface normal direction), and the gap orientation can be defined by the intersection curve between the plane of the substrate 140 and the transverse sidewall of the ground contact area 150 that is in contact with the gap, or by the intersection curve between the plane of the substrate 140 and the transverse sidewall of the gap that is opposite to the sidewall of the ground contact area, or by a combination or average of the two.

[0109] As shown in the figure, the inner or outer edge of the grounding contact area 150 and the outer edge or outer periphery of the Josephson junction 101 have complementary shapes, such that the Josephson junction 102 is received or surrounded by the cavity-like planar recess of the grounding plane 150. The opposing sidewalls of the grounding contact area 150 and the perpendicular Josephson junction face each other and are separated by a gap 102 having a constant width "G" along the periphery of the Josephson junction 101.

[0110] The shape of the Josephson node region, extending in the XY plane, is not limited to a cross-shaped profile. The Josephson node region can be rectangular, rounded rectangular, elongated, polygonal, elliptical, comb-like, double-comb-like, or star-shaped. The shape of the Josephson node region can be defined by a linear, possibly curved path in the XY plane, or can include different branches. In some embodiments, the Josephson node can be rectangular, linear, or formed as a thin and narrow structure, preferably extending along a specific axis, such as a longitudinal axis parallel to one of the X and Y axes, or a longitudinal axis oriented at an angle relative to the Y axis. Furthermore, the shape of the Josephson node region can be convex and / or concave.

[0111] Figure 2This is an enlarged perspective view of the tip of the Josephson junction 101 pointing towards the coupling portion 112. The different vertical stacked layers from the vertical Josephson junction 101 can be clearly distinguished. More specifically, the vertical Josephson junction 101 includes a contact portion 111 of a bottom electrode 110, a tunnel barrier 130 located above the contact portion 111, and a top electrode 120 located above the tunnel barrier. The contact portion 111 of the bottom electrode 110 is located inside the Josephson junction 101, and the shape of the top electrode 120 defines and delineates the Josephson junction region.

[0112] In this example, the contact portion 111, tunnel barrier 130, and top electrode 120 have substantially the same planar shape and are horizontally aligned. This means that the vertical projections of the corresponding edges of the contact portion 111, tunnel barrier 130, and top electrode 120 onto a common plane (e.g., the (bottom) plane of the substrate) almost everywhere coincide, except for possible deviations at the nose or tip of the Josephson junction where the contact portion 111 of the bottom electrode 110 connects to the coupling portion 112. Possible deviations may be less than 5% of the total perimeter of the Josephson junction, for example, less than 2% of the junction perimeter, or for example, less than 1% of the junction perimeter. Therefore, the adjacent vertically extending sidewalls of the contact portion 111, tunnel barrier 130, and top electrode 120 are preferably adjacent to each other, except for deviations at the nose or tip of the Josephson junction where the contact portion 111 of the bottom electrode 110 connects to the coupling portion 112.

[0113] The quantum circuit 100 includes a transport qubit of the merging element type. This means that the inherent self-capacitance of the vertical Josephson junction 101 acts as a shunt capacitor for the transport qubit. In this case, it is not necessary to implement an external shunt capacitor and connect it to the vertical Josephson junction. This makes it possible to reduce the footprint of the qubit device and fabricate a higher area density quantum circuit containing a transport qubit of the merging element. In this embodiment, the contact 111 of the top electrode 120 and the bottom electrode 110 forms two opposing capacitor plates of the shunt capacitor for the transport qubit. To achieve good charge noise suppression behavior and typical anharmonicity of the transport qubit, the capacitor plates provided by the top electrode 120 and the contact 111, and the resulting Josephson junction area, are chosen to have a larger area than conventional superconducting qubit devices. For example, the area of ​​the top electrode and the corresponding Josephson junction can be at least about 1 µm². Furthermore, the top electrode may not have any sharp edges along its perimeter, for example, rounded edges are formed at changes in direction or turns at the perimeter of the top electrode. This advantageously reduces coupling to potential local defects via excessively high electric fields.

[0114] A gap 102, including, for example, air or vacuum, separates the vertical Josephson junction 101 from the adjacent ground contact area 150. The narrow gap 102 allows capacitive coupling between the contact portion 111 of the bottom electrode 110 and the ground plane 150, and between the top electrode 120 and the ground plane 150, while preventing resistive short circuits. As shown, the sidewalls of the ground plane 150 forming the gap can open at the tip of the Josephson junction toward the tapered portion 113 of the bottom electrode 110 to gradually increase the width of the gap 102 away from the Josephson junction. Furthermore, the lower portion of the gap 102 can be formed within the underlying substrate 140. That is, the gap 102 can extend through the interface between the bottom electrode 110 and the substrate 140 and partially enter the substrate 140. For example, the bottom wall of the gap 102 and the lower portion 141 of the vertical wall defining the gap 102 can be formed in the substrate 140. In this configuration, the lower, vertically extending wall portion 141 defines a recess on the upper surface of the substrate 140, which may coincide with a gap region across the entire surface of the planar quantum circuit 100. Partial removal of substrate material in the gap region 102 results in the bottom electrode 110, coupling head 161, and readout resonator structure 163 being formed on and supported by a base of substrate material. This has the advantage that a larger volume portion of the electric edge field exists in a vacuum rather than in the substrate dielectric, which can further reduce dielectric losses. However, in other embodiments of the invention, the bottom wall of the gap 102 may correspond to the top surface of the substrate 140, i.e., at the interface between the bottom electrode layer and the substrate below it.

[0115] Figure 3 It is along Figure 1 The figure shows a cross-sectional view of the Josephson junction 101 taken by line AA'. As shown, a three-layer Josephson junction 101 is formed on the substrate 140 and is surrounded on both sides by ground contact regions 150. The vertical sidewalls of the Josephson junction 101 and the ground contact regions 150 are separated by gaps 102. In this embodiment, the bottom electrode 110 with contact portion 111 and the ground contact regions 150 can be separate coplanar structures formed in the same material layer. In this case, the top surfaces of the ground contact regions 150 and the bottom electrode 110 can be located at the same vertical height (e.g., measured along the Z-axis).

[0116] In this embodiment, the width of the vertical Josephson junction 101 in the X direction can be about 100 nm or less. The gap 102 can have a width dimension of about 40 nm or less in the X direction. The height or thickness of the bottom electrode 110 and the top electrode 120 in the Z direction can be about 50 nm and 150 nm, respectively. The height or thickness of the tunnel barrier 130 in the Z direction can be in the range of several nanometers, for example, 0.5-5.0 nm, such as between 1.2-4.5 nm. For a 4 nm thick ALD AlOx barrier, the example values ​​for the Josephson junction area and the associated shunt capacitance are 5.5 µm² and 125 fF, respectively; for a 1.2 nm thick sputtered AlOx tunnel barrier, the example values ​​for the Josephson junction area and the associated shunt capacitance are 1.7 µm² and 128 fF, respectively. The superconducting bottom and top electrodes can each comprise one of Al, TiN, Nb, Ta, Mo, Pb, NbN, and NbTiN. The tunnel barrier layer may include one of AlOx, TaOx, Teflon, Si, GaN, SiC, SrTiO3, and LaAlO3. The transport qubit according to the first embodiment can achieve an energy ratio E... J / E C > 50, resonant frequencies in the 2-8 GHz range and anharmonic values ​​above 100 MHz (α / 2π).

[0117] Furthermore, the resonant frequency of the transport subqubit in the floating merging element, i.e., the qubit state transition frequency, is independent of the Josephson junction area. For example, the resonant frequency of the transport subqubit can be expressed by the expression... It is directly proportional, where "d" is the thickness of the tunnel barrier. Figure 5 The graph illustrates the dependence of the merged element transporter (MET) qubit (resonant) frequency on the junction barrier thickness. It clearly shows that for different deposited alumina (AlOx) barrier materials, namely sputtering deposition and atomic layer deposition (ALD), the MET qubit frequency decays rapidly and exponentially with increasing barrier thickness. This highlights the extreme sensitivity of the MET qubit frequency to barrier thickness and the barrier deposition or formation method, which is beneficial for testing and characterizing different Josephson junction material combinations and fabrication techniques. The rectangular windows represent typical MET qubit frequencies in the 2–8 GHz range.

[0118] In this embodiment, the bottom electrode 110, including contact portion 111 and coupling portion 112, the ground contact area 150, and the readout circuit 160, including coupling head 161 and resonator structure 163, are coplanar structures and are typically formed in a first superconducting material layer on substrate 140. A tunnel barrier 130 is formed in an insulating barrier layer, such as a dielectric material layer, between the first and second superconducting material layers. A top electrode 120 is formed in the second superconducting material layer, on top of the barrier layer.

[0119] The first and second superconducting material layers may have the same composition and include the same superconducting material, such as aluminum. The barrier layer may include a non-amorphous dielectric material, such as non-amorphous alumina. Alternatively, the first and second superconducting material layers may each include one of TiN, Nb, Ta, Mo, Pb, NbN, and NbTiN. Other material choices for the tunnel barrier layer include one of tantalum oxide, Teflon, Si, GaN, SiC, SrTiO3, and LaAlO3. A tunnel barrier layer may be provided comprising or composed of an oxide of the superconducting metal of the first superconducting material layer. Suitable substrate materials may be silicon, such as wafer-grade high-resistivity silicon or sapphire.

[0120] Embodiments of the present invention are not limited to superconducting material layers with the same composition. For example, the first superconducting material layer may include one of TiN, Nb, Ta, Mo, Pb, NbN, NbTiN, and Al, while the second superconducting material layer may include another of TiN, Nb, Ta, Mo, Pb, NbN, NbTiN, and Al.

[0121] Figure 4 The equivalent circuit diagram 400 of the quantum circuit of the first embodiment and its simplified version 410 are shown. The readout resonator (RES), consisting of capacitors (Cr) and inductors (Lr), is coupled to the electrodes on one side of the Josephson junction (JJ) (bottom electrode BE, top electrode TE) via capacitors C13 and C23, and to the feed line (F-LINE) on the other side via capacitor C34. The ground plane (GND) provides a reference potential to the circuit. The top electrode (TE) and bottom electrode (BE) are also capacitively connected to the ground plane (GND) via their respective capacitors C01 and C02. The shunt capacitor inherent to the transport qubit is represented by capacitor C12. Assuming the capacitive coupling between the top electrode (TE) and the readout resonator (RES) is sufficiently small, i.e., capacitor C23 approaches zero, the equivalent capacitance of the simplified circuit 410 is:

[0122] ,

[0123] ,and

[0124] .

[0125] Typically, CA << Cr and CB << C12. Representing the coupling strength between the transmission sub-qubit and the readout circuit, a large coupling capacitance “CC” is preferred.

[0126] By providing the contact portion and the coupling portion to the bottom electrode as separate but connected parts, the capacitive coupling between the top electrode (TE) and the readout resonator (RES) can indeed be reduced to a negligible amount while maintaining a strong capacitive coupling between the bottom electrode (TE) and the readout resonator cavity (RES). The coupling head for receiving the coupling portion of the bottom electrode further increases the capacitive coupling between the bottom electrode (TE) and the readout resonator (RES). In addition, compared with the compactly designed junction, the top electrode (TE) has a long perimeter, is proportionally thick, and is separated from the ground contact area by a relatively narrow gap (e.g., narrower than the Josephson junction width), thereby achieving a stronger capacitive coupling with the ground contact area / ground plane. Therefore, according to an embodiment of the present invention, a good coupling capacitance “CC” and the corresponding coupling strength between the transmission sub-qubit and the readout circuit can be achieved in a quantum circuit.

[0127] In an embodiment of the present invention, by forming an elongated or rectangular Josephson junction (e.g., strip-shaped, finger-shaped or oval-shaped junction area) having a small aspect ratio AR = w / L << 1.0, where “w” refers to the characteristic junction width (e.g., along the X-axis), and “L” refers to the characteristic junction length (e.g., measured along the Y-axis), the perimeter of the top electrode of the vertical Josephson junction can be advantageously increased. For example, the aspect ratio can be limited to AR ≤ 0.02. Despite the aspect ratio criterion, different area shapes of the Josephson junction can be allowed, such as non-rectangular, but a long perimeter of the top electrode can still be obtained. Another design criterion for the vertical Josephson junction can be , where “A” represents the junction area, and “P” represents the junction perimeter or circumference. In addition, for the gap 102 around the Josephson junction, a good coupling strength between the transmission sub-qubit and the readout circuit can be achieved, and the gap follows the inequality Where “G” represents the characteristic gap width. For a given tunnel barrier thickness (or the qubit frequency determined therefrom), there is a trade-off between the Josephson junction area and the anharmonicity of the transport qubits. This means that the good selectivity of transitions between qubit states (e.g., between the ground state, the first excited state, and the second excited state) sets a practical limit on the size of the Josephson junction area. Different tunnel barrier materials can exhibit different exponential scaling behaviors of the resistance-area product with respect to barrier thickness. Materials that benefit from less pronounced thickness scaling in the resistance-area product may be preferred, as this opens the door to designing larger Josephson junction regions. The above design criteria are useful for the design of quantum circuits according to embodiments of the present invention, but are not required. Other design criteria can be developed and adhered to.

[0128] Figure 6 and Figure 7 The combined effects of the width of the circumferential gap around the vertical Josephson junction and the aspect ratio of the Josephson junction area on the coupling capacitance CO2 between the junction top electrode and the ground contact area, as well as the readout contrast |X| / k, are illustrated. Here, a vertically oriented Josephson junction with a sputtered-deposited 1.2 nm thick AlOx tunnel barrier and a rounded rectangular shape is assumed. The readout contrast indicates the qubit state-related dispersion shift at the readout resonator frequency. As can be understood from the figures, a small circumferential gap width / spacing of less than 100 nm, e.g., less than 60 nm, such as less than 40 nm, and a small aspect ratio of less than 0.02 are preferred.

[0129] refer to Figures 8 to 10 The quantum circuit according to the second embodiment of the present invention will now be described. Figure 8 This is a top view of a portion of a quantum circuit 800, which includes a transport qubit 801 with a vertical Josephson junction coupled to a readout circuit 860. The bottom electrode of the transport qubit 801 includes a coupling portion 812 that extends out of the Josephson junction region and into a complementary-shaped recess of the coupling head 861. The planar readout circuit 860 includes a readout resonator structure 863, such as a coplanar waveguide, terminated by the coupling head 861. Compared to the quantum circuit of the first embodiment, Figure 8 The figure shows a larger portion of the readout resonator 863 within the quantum circuit 800. As shown, the ground contact region 850 corresponds to the large-area ground plane shared by the readout resonator 863 and the transport qubit 801. The ground contact region 850, the readout resonator 863 with a coupling head 861, and the bottom electrode with a coupling portion 812 can be formed as a coplanar structure having the same layer (e.g., a first superconductor layer).

[0130] Figure 9An enlarged view of the transport qubit 801 of the quantum circuit 800 is shown. A gap region 802 of the planar quantum circuit 800 defines a ground plane 850 and separates it from both the readout circuit 860 and the transport qubit 801. Around the transport qubit 801, such as adjacent to the perimeter or outer wall of a vertical Josephson junction, the gap region 802 forms a narrow circumferential space or non-conductive channel. This narrow circumferential space widens into a wider channel at the end of the Josephson junction, where the contact 811 of the bottom electrode 810 abuts the coupling portion 812. The associated gap dimensions (e.g., gap width along the X-axis) increase from G3 to G1. For example, a second narrow circumferential space with an associated gap dimension G2 provides a corridor connecting to a wide trench in the gap region extending from either side of the coupling portion 812, which is not located within the coupling head recess 862. The second narrow circumferential space runs along the edge of the coupling head recess 862 and can be wider than the first narrow circumferential space bordering the vertical Josephson junction sidewall, i.e., G1>>G2>G1. This reduces the capacitive coupling strength between the bottom electrode 810 and the ground contact region 850, but strengthens the capacitive coupling between the bottom electrode 810 and the readout resonator 863 (by interlocking the coupling portion 812 and the coupling head 861) and between the top electrode 820 of the transport qubit and the ground contact region 850. In the gap region 802, the top surface of the lower substrate 140 can be exposed. Figure 10 This is a cross-sectional view taken along line BB', showing different connection portions 811 and 812 of the bottom electrode 810 located inside and outside the vertical Josephson junction region 1001, respectively, and gap spaces of dimensions G2 and G3, which separate the bottom electrode 810 from the coupling head 861 and the ground contact region 850 at their respective ends. Compared with the quantum circuit of the first embodiment, the quantum circuit 800 according to the second embodiment does not show substrate material removal across the gap region 802. This means that no vertical sidewalls are formed in the underlying substrate 140, and it is not exposed to the gap filling medium (e.g., air, vacuum, or inert gas). Furthermore, the bottom electrode 810, the coupling head 861, and the readout resonator structure 863 are not formed on and supported by the substrate material 140.

[0131] Figure 11Steps (a) to (f) of a method for fabricating a quantum circuit according to an embodiment of the present invention are shown. In the first step (a), a multilayer stack is provided, comprising at least a first superconductor formed or covered in a first layer 1101 on a substrate 1140, an insulator formed or covered in a second layer 1102 (e.g., formed directly on and in physical contact with the first layer 1101) on the first layer 1101, and a second superconductor formed or covered in a third layer 1103 (e.g., formed directly on and in physical contact with the second layer 1102) on a second layer 1104. The first and second superconductors may be made of the same material or composition, for example, both comprising or composed of one of Al, Ta, TiN, and Nb. Alternatively, the first and second superconductors may have different compositions. The insulator may be a dielectric material, for example comprising or composed of AlOx, Teflon, or TaOx. The substrate may comprise silicon, for example, high-resistivity silicon. The multilayer stack may be disposed on a wafer, for example, using a wafer-level fabrication method. Providing a multilayer stack may include the following prior steps: depositing or covering a first layer (e.g., a thin film) comprising a first superconductor on a substrate; depositing, covering, or forming a second layer (e.g., a thin film) comprising an insulator on the first layer; and depositing or covering a third layer (e.g., a thin film) comprising a second superconductor on the second layer. The multilayer stack may be provided as an epitaxial stack. In various embodiments, depositing the first and third layers comprising the first and second superconductors respectively may include layer deposition using sputtering techniques, atomic layer deposition (ALD), or suitable epitaxial stack growth techniques. Forming the second layer comprising an insulator may include, for example, partially oxidizing the upper portion of the first layer in a controlled atmosphere.

[0132] In step (b), photoresist 1110 is applied to the material layer stack, and in step (c), it is photolithographically patterned to define the structure of the top electrode of the transport qubit. Photolithographic patterning may include exposing the photoresist layer 1110 to irradiation through an exposure mask or a series of masks, or exposing the photoresist layer 1110 to focused irradiation scanned through the photoresist layer. The photoresist is sensitive to the irradiation used for exposure, which may be optical or electron beam radiation. The choice of resist hue and corresponding mask design (inverted or non-inverted) is not limiting, but in embodiments using electron beam writing techniques for photolithography, a negative resist may be preferred, thereby reducing write / exposure time. Photolithographic patterning may also include developing the photoresist after exposure and selectively removing unexposed portions of the photoresist. This creates openings in the stack for etching the layers below, but protects the structures to be transferred to the layers below, such as the top electrode structures to be transferred to the third layer 1103, which includes the second superconductor, and optionally further to the second layer 1102, which includes the insulator.

[0133] Subsequently, in step (d), for example by a selective etching step or a sequence of etching steps, portions of the third layer 1103 and the second layer 1102 not protected by the remaining resist 1110 are removed. This transfers the top electrode structure to the third layer 1103 and further to the second layer 1102. The advantage of combining the selective removal of material from the third layer 1103 and the second layer 1102 is that an aligned structure of the top electrode and tunnel barrier of the vertical Josephson junction can be obtained through a single photolithographic alignment step. In various embodiments, the same or different etchants can be used to selectively remove material from the third layer 1103 first, and then continue selectively removing material from the second layer 1102. The choice of etchant or the order of etchants typically depends on the material selection of the second superconductor and insulator in both layers.

[0134] In steps (e) to (f), the remaining portion of the first resist 1110 is stripped, and a second photoresist layer 1111 is applied to the stack and photolithographically patterned to define the structure of the first layer 1101. The bottom electrode and the readout resonator with a coupling head are structures that need to be formed in the first layer 1101, which includes the first superconductor. It may also be advantageous to define other portions of the readout circuitry concurrently with the resonator. In embodiments where the ground contact area (e.g., the ground plane) is coplanar with the bottom electrode, the ground plane structure is also defined by photolithography in steps (e) to (f). The photolithographic patterning of the second resist layer 1111 can be performed similarly to the previous step (c). The first resist 1110 and the second resist 1111 can have the same or different compositions. In embodiments using electron beam writing technology, a positive-tone resist may be preferred to reduce writing time.

[0135] Next, in step (g), for example by a selective etching step or a sequence of etching steps, the first superconducting portion of the first layer 1101 not protected by the remaining resist 1111 is selectively removed. This transfers the bottom electrode structure, ground plane structure, and readout circuit structure (including the readout resonator and coupling head structure) to the first layer 1101. The remaining resist 1111 is stripped from the fabricated multilayer stack to obtain, as shown... Figure 10 The quantum circuit shown in the cross-section.

[0136] The advantage of this invention is that the quantum circuit according to the embodiment of the invention can be obtained simply by removing material without adding any material. Furthermore, it requires as few as two photolithographic patterning and alignment steps. Pre-fabricated multilayer material stacks with precisely deposited / formed layers and few or no obvious surface and / or interface defects can be used.

[0137] In step (g), it is possible to over-etch the first layer 1101, i.e., to continue etching through the top surface and into the underlying substrate 1140, such that the structure of the first layer 1101 is also partially transferred into the substrate 1140. This allows for the formation of a corresponding pedestal in the substrate that supports and superelevates the structure of the first layer 1101 relative to the exposed upper surface of the underlying substrate (e.g., the bottom wall of the gap region 102 in the quantum circuit 100 of the first embodiment). The advantage of combining selective removal of the material of the first layer 1101 with selective partial removal of the substrate material is that aligned structures can be obtained in these layers with only a single photolithographic alignment step. In various embodiments, the same or different etchants can be used to selectively remove material from the first layer 1101 first, and then continue selectively removing material from the substrate 1140. The choice of etchant or the order of etchants generally depends on the material selection of the second superconductor and insulator in both layers.

[0138] In a variation of the manufacturing method, the structure of the first layer 1101, such as the bottom electrode, ground contact area, and readout circuit structure, is defined in the first resist 1110 and subsequently transferred to the first layer 1101 by selectively removing (e.g., etching away) the corresponding materials in the aforementioned layers 1102 and 1103. Then, a second photolithographic patterning step associated with the second resist 1111 can be used to define and protect the structures of the top electrode and tunnel barrier in the third and second layers, respectively. This removes excess material in the third layer 1103 and the second layer 1102 that does not belong to the top electrode and tunnel barrier structures, exposing the coupling portions, ground plane, and readout circuit within the first layer 1101.

[0139] Although the invention has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration are intended to be illustrative or exemplary, and not restrictive. By studying the drawings, this disclosure, and the appended claims, those skilled in the art will understand and practice other variations of the disclosed embodiments in the practice of the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plural. No reference numerals in the claims should be construed as limiting the scope.

Claims

1. A quantum circuit (100), comprising: A bottom electrode (110) is formed in a first superconducting material layer, the bottom electrode including a contact portion (111) and a coupling portion (112). The top electrode (120) is formed in the second superconducting material layer. A vertical Josephson junction (101) is formed on a substrate (140), the Josephson junction including the contact portion of the bottom electrode, a tunnel barrier (130) and the top electrode. The transport sub-qubit includes the vertical Josephson junction (101) and a shunt capacitor formed by the contact portion of the top electrode and the bottom electrode, which serve as a shunt capacitor plate. A readout circuit (160) is capacitively coupled to the bottom electrode via the coupling portion. The readout circuit includes a coupling head (161), and the coupling portion of the bottom electrode is fitted into a recess (162) formed in the coupling head. The top electrode of the vertical Josephson junction is configured as a floating electrode, which is not resistively coupled to the first superconducting material layer.

2. The quantum circuit (100) according to claim 1, characterized in that, The readout circuit (160) includes a readout resonator (163) such as a coplanar waveguide, the end of which includes the coupling head (161) of the readout circuit.

3. The quantum circuit (100) according to claim 2, characterized in that, At least one of the readout resonators of the readout circuit is formed in the first superconducting material layer.

4. The quantum circuit (100) according to any one of the preceding claims, characterized in that, It also includes a ground contact region (150) adjacent to the vertical Josephson junction (101), the ground contact region being formed in the first superconducting material layer or in a third superconducting material layer on top of the second superconducting material layer.

5. The quantum circuit (100) according to claim 4, characterized in that, A gap (102) separates the grounding contact area (150) from the sidewall of the vertical Josephson junction, the gap having a width of up to 100 nm in the normal direction of the sidewall.

6. The quantum circuit (100) according to any one of the preceding claims, characterized in that, The recess (162) in the coupling head (161) is formed as a receiving groove relative to the coupling portion of the bottom electrode.

7. The quantum circuit (100) according to any one of the preceding claims, characterized in that, The vertical Josephson junction (101) has a characteristic junction length (L) along a first direction parallel to the substrate (140) and a characteristic junction width (w) along a second direction parallel to the substrate, the second direction being perpendicular to the first direction, and wherein the ratio of the characteristic junction width to the characteristic junction length is at most 0.

02. Or, the vertical Josephson knot (101) described therein has a knot area of ​​size "A" and a knot perimeter of length "P", such that... .

8. The quantum circuit (100) according to any one of the preceding claims, characterized in that, It also includes a grounding contact area (150) adjacent to the vertical Josephson junction (101), the vertical Josephson junction having a rectangular shape with a width of "w" and an area of ​​"A", and a gap (102) separating the grounding contact area from the sidewall of the vertical Josephson junction, the gap having a gap width of "G", such that .

9. The quantum circuit (100) according to any one of the preceding claims, characterized in that, The first superconducting material layer and the second superconducting material layer comprise aluminum, and / or the tunnel barrier (130) is formed in a dielectric layer preferably comprising aluminum oxide.

10. The quantum circuit (100) according to any one of the preceding claims, characterized in that, It also includes a ground contact area (150) adjacent to the vertical Josephson junction (101), the ground contact area surrounding the contact portion (111) of the bottom electrode (110).

11. The quantum circuit (100) according to any one of the preceding claims, characterized in that, No dielectric residue was deposited on the sidewalls of the vertical Josephson junction.

12. The quantum circuit (100) according to any one of the preceding claims, characterized in that, The sidewalls of the tunnel barrier are in contact with air or a vacuum.

13. A method for manufacturing a quantum circuit, comprising: A multilayer material stack comprising a first superconducting material, a dielectric layer, and a second superconducting material is provided on a substrate. A bottom electrode is formed in the first superconducting material, the bottom electrode including a contact portion and a coupling portion. A top electrode is formed in the second superconducting material. A transport qubit is formed comprising a vertical Josephson junction and a shunt capacitor. The vertical Josephson junction includes a contact portion of the bottom electrode, a tunnel barrier formed in the dielectric layer, and a top electrode. The shunt capacitor is formed by the contact portion of the top electrode and the bottom electrode, which serve as a shunt capacitor plate. Coupling the readout circuit capacitor to the bottom electrode includes fitting the coupling portion of the bottom electrode into a recess formed in the coupling head of the readout circuit. The top electrode of the vertical Josephson junction is configured as a floating electrode, which is not resistively coupled to the first superconducting material layer.

14. The method according to claim 13, characterized in that, Also includes: Adjacent to the vertical Josephson junction, a grounding contact area is formed in the third superconducting material layer on top of the first superconducting material layer or the second superconducting material layer.

15. The method according to claim 13 or 14, characterized in that, The steps for forming the top electrode include: Patterning and selectively removing material from the second superconducting material layer and optionally also from the dielectric layer; The step of forming the bottom electrode includes: The material is patterned and selectively removed from the first superconducting material layer and optionally also from the substrate.

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