Word Line driving circuit of NorFlash memory and NorFlash memory
By employing a Word Line drive circuit composed of PMOS and NMOS transistors in the NorFlash memory, and utilizing the NMOS transistors to assist the PMOS transistors in transmitting the word line voltage, the problem of the large area ratio of the drive circuit in the prior art is solved. This achieves an effective technical solution, addresses the unresolved technical problem in the prior art, and improves the flexibility and efficiency of the NorFlash memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
- Filing Date
- 2025-11-25
- Publication Date
- 2026-04-17
AI Technical Summary
The Word Line drive circuit in NorFlash memory occupies a large area, resulting in an increase in the overall area of the memory.
A Word Line driving circuit composed of a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor is adopted. The first NMOS transistor assists the first PMOS transistor in transmitting the positive voltage signal of the word line, thereby reducing the size of the PMOS transistor. Low-voltage driving is achieved by turning the NMOS transistor on and off under different actions.
It effectively reduces the area of the Word Line driving circuit and improves the flexibility and efficiency of the word line driving voltage.
Smart Images
Figure CN121884906A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of storage technology, specifically to a Word Line driving circuit for a NorFlash memory and the NorFlash memory itself. Background Technology
[0002] NorFlash is a type of non-volatile memory. The majority of the area in this memory is used to store bit cells. In addition, it also includes power systems, word line (WL) drivers, sensitive amplifiers, control logic and other circuits. Among these, the WL drivers account for a large proportion of the area due to their numerous repetitions. Summary of the Invention
[0003] This invention provides a Word Line driving circuit for NorFlash memory and NorFlash memory to solve the problem of the large proportion of WL driving area in NorFlash memory.
[0004] In a first aspect, the present invention provides a Word Line driving circuit for a NorFlash memory, comprising: a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The source of the first PMOS transistor is connected to the first signal, the gate is connected to the second signal, and the drain is connected to the target word line; The source of the second NMOS transistor is connected to the third signal, the gate is connected to the second signal, and the drain is connected to the target word line; The source of the first NMOS transistor is connected to the first signal, the gate is connected to the fourth signal, and the drain is connected to the target word line; The first signal, the second signal, the third signal, and the fourth signal are used to determine whether the target word line is selected and the action to be performed.
[0005] In a second aspect, the present invention provides a NorFlash memory, including the Word Line driving circuit of any of the NorFlash memories described in the first aspect above.
[0006] In the Word Line driving circuit for NorFlash memory provided in this embodiment, the last stage of the Word Line driving circuit consists of three MOS transistors: a first PMOS transistor P5, a first NMOS transistor N6, and a second NMOS transistor N5. The positive voltage signal driving the word line (when the first signal PS is either the first positive voltage signal or the second positive voltage signal) is jointly transmitted by the first NMOS transistor N6 and the first PMOS transistor P5. Therefore, the size of the first PMOS transistor P5 can be smaller, thereby effectively reducing the area of the Word Line driving circuit. In addition, due to the presence of the first NMOS transistor N6, the voltage of the positive voltage signal driving the word line can be lower. Attached Figure Description
[0007] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0008] Figure 1 This is a schematic diagram of a Word Line driving circuit for a NorFlash memory according to an embodiment of the present invention. Figure 2 This is a schematic diagram of voltage transmission when a target word line is selected to perform a read / write operation according to an embodiment of the present invention; Figure 3 This is a schematic diagram of voltage transmission when a target word line is not selected for reading / writing operations according to an embodiment of the present invention; Figure 4 This is a schematic diagram of voltage transmission when the target sector to which the target word line belongs is not selected for read / write operations according to an embodiment of the present invention; Figure 5 This is a schematic diagram of voltage transmission when the target sector to which the target word line belongs is selected and an erasure operation is performed according to an embodiment of the present invention; Figure 6 This is a schematic diagram of voltage transmission when the target sector to which the target word line belongs is not selected and an erasure operation is performed according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a sector driving circuit in a Word Line driving circuit according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the overall layout of the Word Line driving circuit of the NorFlash memory according to an embodiment of the present invention. Figure 9This is a schematic diagram of a decoding circuit in a Word Line driving circuit according to an embodiment of the present invention. Detailed Implementation
[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0010] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.
[0011] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0012] This embodiment provides a Word Line driving circuit for a NorFlash memory, such as... Figure 1 As shown, the driving circuit includes: a first PMOS transistor P5, a first NMOS transistor N6, and a second NMOS transistor N5; The source of the first PMOS transistor is connected to the first signal PS, the gate is connected to the second signal SC, and the drain is connected to the target word line; The source of the second NMOS transistor N5 is connected to the third signal VN, the gate is connected to the second signal SC, and the drain is connected to the target word line; The source of the first NMOS transistor N6 is connected to the first signal PS, the gate is connected to the fourth signal SC_N, and the drain is connected to the target word line; The first signal PS, the second signal SC, the third signal VN, and the fourth signal SC_N are used to determine whether the target word line is selected and the action to be performed.
[0013] In the Word Line driving circuit for NorFlash memory provided in this embodiment, the last stage of the Word Line driving circuit consists of three MOS transistors: a first PMOS transistor P5, a first NMOS transistor N6, and a second NMOS transistor N5. The positive voltage signal driving the word line (when the first signal PS is either the first positive voltage signal or the second positive voltage signal) is jointly transmitted by the first NMOS transistor N6 and the first PMOS transistor P5. Therefore, the size of the first PMOS transistor P5 can be smaller, thereby effectively reducing the area of the Word Line driving circuit. In addition, due to the presence of the first NMOS transistor N6, the voltage of the positive voltage signal driving the word line can be lower.
[0014] In some optional embodiments, the second signal SC and the fourth signal SC_N are output by the driving circuit of the target sector to which the target word line belongs.
[0015] In some alternative implementations, such as Figure 2 and Figure 3 As shown, when the target sector is selected to perform a read or write operation, the second signal SC is a zero voltage signal, the fourth signal SC_N is a third positive voltage (positive high voltage) signal, the first PMOS transistor P5 and the first NMOS transistor N6 are turned on, and the second NMOS transistor N5 is turned off; at this time, the driving voltage of the target word line is provided by the first signal PS, specifically, the first signal PS drives the target word line through the first PMOS transistor P5 and the first NMOS transistor N6.
[0016] like Figure 2 As shown, when the first signal PS is a first positive voltage signal, the target word line is selected to perform a read or write operation. Due to the presence of the first NMOS transistor N6, the first signal PS can be a positive voltage signal of any magnitude. Specifically, the voltage of the first signal PS can be greater than the threshold voltage of the PMOS transistor, equal to the threshold voltage of the PMOS transistor, or less than the threshold voltage of the PMOS transistor, which improves the flexibility of the word line driving voltage.
[0017] like Figure 3 As shown, when the first signal PS is a zero voltage signal, the target word line is not selected to perform a read or write operation.
[0018] In some alternative implementations, such as Figure 4As shown, when the target sector is not selected for a read or write operation, the second signal SC is a fifth positive voltage (high positive voltage) signal, the fourth signal SC_N is a zero voltage signal, the first PMOS transistor P5 and the first NMOS transistor N6 are turned off, and the second NMOS transistor N5 is turned on. At this time, the driving voltage of the target word line is provided by the third signal VN. Specifically, the third signal VN drives the target word line through the second NMOS transistor N5. The third signal VN is a zero voltage signal, and the driving voltage of the target word line is also zero voltage. The target word line is not selected for a read or write operation.
[0019] In some alternative implementations, such as Figure 5 As shown, when the target sector is selected and the erasure operation is performed, the second signal SC is the sixth positive voltage (low positive voltage) signal, the fourth signal SC_N is the negative voltage signal, the third signal VN is the negative voltage signal, the first PMOS transistor P5 and the first NMOS transistor N6 are turned off, the second NMOS transistor N5 is turned on, and the third signal VN drives the target word line through the second NMOS transistor N5. That is, at this time, the driving voltage of the target word line is provided by the third signal VN, which is a negative voltage.
[0020] In some alternative implementations, such as Figure 6 As shown, when the target sector is not selected for the erase operation, the second signal SC is a negative voltage signal, the fourth signal SC_N is a fourth positive voltage (low positive voltage) signal, the first PMOS transistor P5 and the first NMOS transistor N6 are turned on, and the second NMOS transistor N5 is turned off; the first signal PS is a second positive voltage signal, and the first signal PS drives the target word line through the first PMOS transistor P5 and the first NMOS transistor N6. That is, at this time, the driving voltage of the target word line is provided by the first signal PS, which is the second positive voltage signal. The voltage of the second positive voltage signal can be less than that of the first positive voltage signal.
[0021] In addition, due to the presence of the first NMOS transistor N6, the first signal PS can be a positive voltage signal of any magnitude. Specifically, the voltage of the first signal PS can be greater than the threshold voltage of the PMOS transistor, equal to the threshold voltage of the PMOS transistor, or less than the threshold voltage of the PMOS transistor, which improves the flexibility of the word line driving voltage.
[0022] Some optional implementations, such as Figure 7 As shown, the Word Line driving circuit of the NorFlash memory also includes: a sector driving circuit; one sector corresponds to multiple word lines; The sector driving circuit includes a second PMOS transistor P1, a third PMOS transistor P2, a fourth PMOS transistor P3, a fifth PMOS transistor P4, a third NMOS transistor N1, a fourth NMOS transistor N2, a fifth NMOS transistor N3, and a sixth NMOS transistor N4; The source of the second PMOS transistor P1 is connected to the fifth signal VP, the gate is connected to the sixth signal XB2, and the drain is connected to the source of the third PMOS transistor P2 and the fourth PMOS transistor P3, respectively. The source of the third PMOS transistor P2 is connected to the drain of the second PMOS transistor P1, the gate is connected to the seventh signal XA, and the drain is used to output the second signal SC. The source of the fourth PMOS transistor P3 is connected to the drain of the second PMOS transistor P1, the gate is connected to the eighth signal XB1, and the drain is used to output the second signal SC. The source of the fifth PMOS transistor P4 is connected to the fifth signal VP, the gate is connected to the second signal SC, and the drain is used to output the fourth signal SC_N; The source of the third NMOS transistor N1 is connected to the third signal VN, the gate is connected to the eighth signal XB1, and the drain is connected to the source of the fourth NMOS transistor N2. The source of the fourth NMOS transistor N2 is connected to the drain of the third NMOS transistor N1, the gate is connected to the seventh signal XA, and the drain is used to output the second signal SC; The source of the fifth NMOS transistor N3 is connected to the third signal VN, the gate is connected to the sixth signal XB2, and the drain is used to output the second signal SC; The source of the sixth NMOS transistor N4 is connected to the third signal VN, the gate is connected to the second signal SC, and the drain is used to output the fourth signal SC_N.
[0023] In this embodiment, the preceding stage of the Word Line driving circuit (i.e., the sector driving circuit) includes a second PMOS transistor P1, a third PMOS transistor P2, a fourth PMOS transistor P3, a fifth PMOS transistor P4, a third NMOS transistor N1, a fourth NMOS transistor N2, a fifth NMOS transistor N3, and a sixth NMOS transistor N4.
[0024] In some optional implementations, when performing a read or write operation, the fifth signal VP is a seventh positive voltage (high positive voltage) signal, the third signal VN is a zero voltage signal; the sixth signal XB2 is a zero voltage signal, the second PMOS transistor P1 is turned on, the fifth NMOS transistor N3 is turned off, and the third PMOS transistor P2, the fourth PMOS transistor P3, the fourth NMOS transistor N2, and the third NMOS transistor N1 constitute a NAND gate; when the seventh signal XA is a ninth positive voltage (high positive voltage) signal and the eighth signal XB1 is an eleventh positive voltage (high positive voltage) signal... When the target sector corresponding to the sector driving circuit is selected to perform read / write operations, the second signal SC is a zero voltage signal and the fourth signal SC_N is a third positive voltage (high positive voltage, basically equal to the voltage of the fifth signal VP, that is, equal to the voltage of the seventh positive voltage signal); when the seventh signal XA or the eighth signal XB1 is a zero voltage signal, the target sector corresponding to the sector driving circuit is not selected to perform read / write operations, and the second signal SC is a fifth positive voltage (high positive voltage, basically equal to the voltage of the fifth signal VP, that is, equal to the voltage of the seventh positive voltage signal) and the fourth signal SC_N is a zero voltage signal.
[0025] In some optional implementations, when performing the erase operation, the fifth signal VP is the eighth positive voltage (low positive voltage) signal, the third signal VN is the negative voltage signal, and the eighth signal XB1 is the twelfth positive voltage (low positive voltage) signal; the third NMOS transistor N1 is turned on, the fourth PMOS transistor P3 is completely turned off, and the second PMOS transistor P1, the third PMOS transistor P2, the fourth NMOS transistor N2, and the fifth NMOS transistor N3 form a NOR gate. When the seventh signal XA and the sixth signal XB2 are negative voltage signals, the target sector corresponding to the sector driving circuit is selected to perform the erase operation, and the second signal SC is... When the sixth positive voltage (low positive voltage, basically equal to the voltage of the fifth signal VP, that is, equal to the voltage of the eighth positive voltage signal) and the fourth signal SC_N is the negative voltage (voltage basically equal to the voltage of the third signal VN); when the seventh signal XA is the tenth positive voltage (low positive voltage) or the sixth signal XB2 is the fourteenth positive voltage (low positive voltage) signal, the target sector corresponding to the sector driving circuit is not selected to perform the erasure operation, the second signal SC is the negative voltage (voltage basically equal to the voltage of the third signal VN) signal, and the fourth signal SC_N is the fourth positive voltage (low positive voltage, basically equal to the voltage of the fifth signal VP, that is, equal to the voltage of the eighth positive voltage signal) signal.
[0026] The sector driving circuit provided in this embodiment can effectively save area by multiplexing P2, P3, P4, N3, N4, and N5 under different operations (read, write, erase), thereby further reducing the area of the Word Line drive in the NorFlash memory. In this embodiment, by designing the two-stage circuit of the Word Line drive circuit separately and reducing the area of each stage, the area of the Word Line drive in the NorFlash memory can be greatly reduced.
[0027] like Figure 8 The diagram shows an overall layout of a NorFlash memory Word Line (WL) driver circuit, illustrating a driver layout of 1024 WLs. This layout consists of 256 sector drivers and 1024 WL drivers. Each sector driver circuit drives four WL drivers, and these four WL drivers correspond to the PS (Power Supply). <0> To PS <3> In this embodiment, the second signal SC and the fourth signal SC_N are used to select a sector, and the first signal PS is used to select the WL in the selected sector.
[0028] In some optional embodiments, the Word Line driving circuit of the NorFlash memory further includes a decoding circuit, which is used to generate the first signal PS, the seventh signal XA, the sixth signal XB2, and the eighth signal XB1.
[0029] Specifically, such as Figure 9 As shown, the decoding circuit may include three decoders, which are used to decode the low-order, middle-order, and high-order bits of the address, respectively. The low-order address decoding generates the first signal PS, the middle-order address decoding generates the seventh signal XA, and the high-order address decoding generates the sixth signal XB2 and the eighth signal XB1.
[0030] During read / write decoding, the first signal PS corresponding to the selected target word line is a high positive voltage signal (i.e., the first positive voltage signal), and the first signal PS corresponding to the unselected target word line is a zero voltage signal. During erase decoding, all first signals PS are uniformly set to low positive voltage (i.e., the second positive voltage signal).
[0031] During read / write decoding, when the target sector containing the target word line is selected, the corresponding seventh signal XA is a ninth positive voltage signal (high positive voltage signal); when the target sector containing the target word line is not selected, the corresponding seventh signal XA is a zero voltage signal. During erase decoding, when the target sector containing the target word line is selected, the corresponding seventh signal XA is a negative voltage signal; when the target sector containing the target word line is not selected, the corresponding seventh signal XA is a negative voltage signal.
[0032] During read / write decoding, when the target sector to which the target word line belongs is selected, the corresponding eighth signal XB1 is the eleventh positive voltage (high positive voltage) signal; when the target sector to which the target word line belongs is not selected, the corresponding eighth signal XB1 is the zero voltage signal, and the sixth signal XB2 is uniformly the zero voltage signal.
[0033] During the erase decoding process, when the target sector to which the target word line belongs is selected, the sixth signal XB2 is a negative voltage signal; when the target sector to which the target word line belongs is not selected, the corresponding XB2 is the fourteenth positive voltage (low positive voltage) signal, while the eighth signal XB1 is uniformly the twelfth positive voltage (low positive voltage) signal.
[0034] In the above embodiments, the voltages of the high positive voltage signals can be the same or different, and the voltages of the low positive voltage signals can also be the same or different. The voltage of the high positive voltage signal is generally greater than the voltage of the low positive voltage signal.
[0035] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.
Claims
1. A word line drive circuit for a NorFlash memory, characterized by, include: First PMOS transistor (P5), first NMOS transistor (N6), and second NMOS transistor (N5); The source of the first PMOS transistor is connected to the first signal (PS), the gate is connected to the second signal (SC), and the drain is connected to the target word line; The source of the second NMOS transistor (N5) is connected to the third signal (VN), the gate is connected to the second signal (SC), and the drain is connected to the target word line; The source of the first NMOS transistor (N6) is connected to the first signal (PS), the gate is connected to the fourth signal (SC_N), and the drain is connected to the target word line; The first signal (PS), the second signal (SC), the third signal (VN), and the fourth signal (SC_N) are used to determine whether the target word line is selected and the action to be performed.
2. The Word Line driving circuit of a NorFlash memory according to claim 1, characterized in that, The second signal (SC) and the fourth signal (SC_N) are output by the driving circuit of the target sector to which the target word line belongs; When the target sector is selected to perform a read or write operation, the second signal (SC) is a zero voltage signal, the fourth signal (SC_N) is a third positive voltage signal, the first PMOS transistor (P5) and the first NMOS transistor (N6) are turned on, and the second NMOS transistor (N5) is turned off; when the first signal (PS) is a first positive voltage signal, the target word line is selected to perform a read or write operation; when the first signal (PS) is a zero voltage signal, the target word line is not selected to perform a read or write operation.
3. The Word Line driving circuit of a NorFlash memory according to claim 2, characterized in that, When the target sector is not selected for a read or write operation, the second signal (SC) is a fifth positive voltage signal, the fourth signal (SC_N) is a zero voltage signal, the first PMOS transistor (P5) and the first NMOS transistor (N6) are turned off, the second NMOS transistor (N5) is turned on, the third signal (VN) is a zero voltage signal, and the target word line is not selected for a read or write operation.
4. The Word Line driving circuit of the NorFlash memory according to claim 3, characterized in that, When the target sector is selected and the wiping operation is performed, the second signal (SC) is the sixth positive voltage signal, the fourth signal (SC_N) is the negative voltage signal, the third signal (VN) is the negative voltage signal, the first PMOS transistor (P5) and the first NMOS transistor (N6) are turned off, and the second NMOS transistor (N5) is turned on.
5. The Word Line driving circuit of the NorFlash memory according to claim 4, characterized in that, When the target sector is not selected for the wiping operation, the second signal (SC) is a negative voltage signal, the fourth signal (SC_N) is a fourth positive voltage signal, the first PMOS transistor (P5) and the first NMOS transistor (N6) are turned on, and the second NMOS transistor (N5) is turned off; the first signal (PS) is a second positive voltage signal.
6. The Word Line driving circuit of the NorFlash memory according to any one of claims 1-5, characterized in that, When the first signal (PS) is a positive voltage signal, the voltage is greater than, equal to, or less than the threshold voltage of the PMOS transistor.
7. The Word Line driving circuit of the NorFlash memory according to any one of claims 1-5, characterized in that, It also includes: sector drive circuitry; one sector corresponds to multiple word lines; The sector driving circuit includes a second PMOS transistor (P1), a third PMOS transistor (P2), a fourth PMOS transistor (P3), a fifth PMOS transistor (P4), a third NMOS transistor (N1), a fourth NMOS transistor (N2), a fifth NMOS transistor (N3), and a sixth NMOS transistor (N4). The source of the second PMOS transistor (P1) is connected to the fifth signal (VP), the gate is connected to the sixth signal (XB2), and the drain is connected to the source of the third PMOS transistor (P2) and the fourth PMOS transistor (P3), respectively. The source of the third PMOS transistor (P2) is connected to the drain of the second PMOS transistor (P1), the gate is connected to the seventh signal (XA), and the drain is used to output the second signal (SC). The source of the fourth PMOS transistor (P3) is connected to the drain of the second PMOS transistor (P1), the gate is connected to the eighth signal (XB1), and the drain is used to output the second signal (SC). The source of the fifth PMOS transistor (P4) is connected to the fifth signal (VP), the gate is connected to the second signal (SC), and the drain is used to output the fourth signal (SC_N). The source of the third NMOS transistor (N1) is connected to the third signal (VN), the gate is connected to the eighth signal (XB1), and the drain is connected to the source of the fourth NMOS transistor (N2). The source of the fourth NMOS transistor (N2) is connected to the drain of the third NMOS transistor (N1), the gate is connected to the seventh signal (XA), and the drain is used to output the second signal (SC). The source of the fifth NMOS transistor (N3) is connected to the third signal (VN), the gate is connected to the sixth signal (XB2), and the drain is used to output the second signal (SC). The source of the sixth NMOS transistor (N4) is connected to the third signal (VN), the gate is connected to the second signal (SC), and the drain is used to output the fourth signal (SC_N).
8. The Word Line driving circuit of the NorFlash memory according to claim 7, characterized in that, When performing a read or write operation, the fifth signal (VP) is the seventh positive voltage signal and the third signal (VN) is a zero voltage signal; the sixth signal (XB2) is a zero voltage signal, the second PMOS transistor (P1) is turned on, the fifth NMOS transistor (N3) is turned off, and the third PMOS transistor (P2), the fourth PMOS transistor (P3), the fourth NMOS transistor (N2), and the third NMOS transistor (N1) form a NAND gate; when the seventh signal (XA) is the ninth positive voltage signal and the eighth signal (XB1) is the eleventh positive voltage signal, the target sector corresponding to the sector driving circuit is selected to perform a read or write operation, the second signal (SC) is a zero voltage signal, and the fourth signal (SC_N) is a third positive voltage signal; when the seventh signal (XA) or the eighth signal (XB1) is a zero voltage signal, the target sector corresponding to the sector driving circuit is not selected to perform a read or write operation, the second signal (SC) is the fifth positive voltage signal, and the fourth signal (SC_N) is a zero voltage signal.
9. The Word Line driving circuit of the NorFlash memory according to claim 8, characterized in that, When performing the erase operation, the fifth signal (VP) is the eighth positive voltage signal, the third signal (VN) is the negative voltage signal, and the eighth signal (XB1) is the twelfth positive voltage signal; the third NMOS transistor (N1) is turned on, and all fourth PMOS transistors (P3) are turned off. The second PMOS transistor (P1), the third PMOS transistor (P2), the fourth NMOS transistor (N2), and the fifth NMOS transistor (N3) form a NOR gate. When the seventh signal (XA) and the sixth signal (XB2) are negative voltage signals, the target sector corresponding to the sector driving circuit is selected to perform the erase operation. The second signal (SC) is the sixth positive voltage signal, and the fourth signal (SC_N) is the negative voltage signal. When the seventh signal (XA) is the tenth positive voltage signal or the sixth signal (XB2) is the fourteenth positive voltage signal, the target sector corresponding to the sector driving circuit is not selected to perform the erase operation. The second signal (SC) is the negative voltage signal, and the fourth signal (SC_N) is the fourth positive voltage signal.
10. The Word Line driving circuit of the NorFlash memory according to claim 7, characterized in that, Also includes: A decoding circuit is used to generate the first signal (PS), the seventh signal (XA), the sixth signal (XB2), and the eighth signal (XB1).
11. A NorFlash memory, characterized in that, The Word Line driving circuit of the NorFlash memory included in any one of claims 1-10.