Reading method of flash memory device and reading command format thereof

Abstract

The invention provides a reading method and a reading command format of a flash memory device. The reading method comprises the following steps: judging whether a to-be-read block is an open block or not based on a special code in a reading command; the open block has a written area and an unwritten area. When it is determined that the block is not an open block and the selected word line of the block is read, a first read pass bias group is applied to the non-selected word line in the block. When the block is judged to be an open block and the selected word line of the block is read, a second read-through bias group is applied to the non-selected word line in the written area, and a third read-through bias group is applied to the non-selected word line in the non-written area. The method is suitable for the 3D NAND flash memory, and has high capacity and high performance.

Description

Technical Field

[0001] This disclosure relates to memory operation, and more particularly to a method for reading flash memory and its read command format. Background Technology

[0002] Generally, 3D memories, such as non-volatile flash memory, have a multi-layered structure (e.g., word line layers). Therefore, when reading from a 3D memory, detailed layer compensation is required for the read window. Furthermore, operating a 3D memory typically involves programming it first. Programming usually proceeds sequentially, working one word line (layer) at a time within a block. After programming each word line's memory cell, the data written to that cell needs to be verified—this is known as program verification. During verification, a verification voltage is applied to the word line, while a verification pass voltage Vpass_pv is applied to other word lines. The corresponding bit lines are also subject to their respective bit line verification voltages Vblc_pv. This verifies whether the memory cell has been correctly programmed. Unprogrammed memory cells are presented with a low threshold voltage.

[0003] Subsequently, when reading a memory block that has already been written to, a read voltage is applied to the word line and bit line to be read. Furthermore, because the memory block already contains written data, each memory cell may be in a low threshold voltage state or a high threshold voltage state. Therefore, when applying the first word line read pass voltage Vpass_rd to a word line that is not yet to be read, a relatively large voltage is required to enable the memory cell that is not yet to be read.

[0004] As mentioned above, the verification pass voltage Vpass_pv used during programming and the first word line read pass voltage Vpass_rd used during reading are different. That is, the bias settings for the word line / bit line pass voltages used during programming and reading are different. However, applying excessive voltage will change the threshold voltage of the memory cell.

[0005] Therefore, when a memory block is an open block, because a portion of the open block has not been written to, and those memory cells that have not been written to are in a low threshold voltage state, if the normal read bias setting is still used in this situation, such as still using the first word line read through voltage Vpass_rd to apply to the unselected word line, it may cause data read errors and generate additional read interference.

[0006] Therefore, how to avoid read errors and read interference when reading open blocks is a research topic. Summary of the Invention

[0007] In view of the above description, according to an embodiment of the present disclosure, a method for reading a flash memory device is provided. The reading method includes a method for reading a flash memory device comprising a plurality of blocks, the reading method comprising: receiving a read command for reading at least one block of the plurality of blocks, the read command being appended with a special code and a final write word line address; determining, based on the special code of the read command, whether the at least one block is an open block, the open block having a written area and an unwritten area; if the at least one block is determined not to be an open block, when reading the at least one block, applying a first read-through bias group to a plurality of non-selected word lines in the at least one block; and if the at least one block is determined to be an open block, and when reading the at least one block, applying a second read-through bias group to a plurality of non-selected word lines in the written area of ​​the at least one block, and applying a third read-through bias group to a plurality of non-selected word lines in the unwritten area.

[0008] According to another embodiment of this disclosure, a read command format for a flash memory device is provided. The read command format includes: a special code for specifying whether each of a plurality of blocks in the flash memory device is an open block; a final write word line address for specifying the address of the last written word line in each of the plurality of blocks; and a read command specification, which, to conform to the standard format of the flash memory device, further includes a read command, a row address, a column address, and a read confirmation command in sequence.

[0009] Based on the above, when reading open blocks of flash memory, setting the word line read voltage applied to unselected word lines in areas that have not been written to be different from the word line read voltage applied to unselected word lines in areas that have already been written to can reduce false reads and read interference. Furthermore, the bit line read voltage can be adjusted accordingly based on the final position of the written word line, which can further reduce false reads and read interference. Attached Figure Description

[0010] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings.

[0011] Figure 1 The diagram illustrates an open block of flash memory.

[0012] Figure 2 A schematic diagram illustrating a reading method flow according to an embodiment of the present disclosure is shown.

[0013] Figure 3Aand Figure 3B A schematic diagram illustrating a flash memory reading method according to an embodiment of the present disclosure is shown.

[0014] Figures 4A to 4C The schematic illustration shows the existing flash memory read command format.

[0015] Figures 5A to 5D The schematic illustration shows a flash memory read command format according to an embodiment of the present disclosure.

[0016] Figure 6 A flowchart illustrating the determination of bit line readout voltage according to an embodiment of the present disclosure is shown schematically.

[0017] Figure 7 The diagram schematically illustrates a block diagram for determining the bit line read voltage according to an embodiment of the present disclosure.

[0018] Explanation of reference numerals in the attached figures:

[0019] 100: Block (Open Block)

[0020] 100A: Block (Non-open block)

[0021] 102: Area already written

[0022] 104: Area Not Written

[0023] WL j Select word lines

[0024] WL1~WL j-1 WL j+1 ~WL PA WL PA+1 ~WL n No text lines selected

[0025] BL1~BL m BL: Bitline

[0026] WL PA : Final write word line

[0027] Vpass_rd: First word line reads the voltage passed through.

[0028] Vblc_rd: The first line reads the voltage passing through it.

[0029] Vpass_x, Vpass_y: The second word line reads the voltage passed through.

[0030] Vpass_z: The third word line reads the voltage passed through.

[0031] Vblc_xx: Second bit line reads the voltage passing through.

[0032] VBL_1~VBL_N: Bit line read voltage

[0033] Vpass_pv: Pass voltage for verification

[0034] Vblc_pv: Bit line verification voltage

[0035] S100~S104: Steps

[0036] S200~S218: Steps to determine the voltage passed through the bit line read

[0037] V_rd: Word line read voltage

[0038] IO[7:0]: Input / output terminals

[0039] PRX: Precursor

[0040] CA, C1, C2: Row address

[0041] RA, R1, R2, R3: Column addresses

[0042] RD, 00h: Read command code

[0043] RDC, 30h: Read confirmation command

[0044] R / B#: Ready signal

[0045] CEB: Chip Enable Signal

[0046] 01h, 02h, 03h, A2h: Code

[0047] B0h: Special Code

[0048] PA: Final word line address

[0049] FEh: Setting Feature Command

[0050] FA: Eigenvalue. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0052] Figure 1 This diagram illustrates the open blocks of a flash memory. Flash memory is composed of memory arrays. A memory array contains multiple blocks, and each block can have multiple word lines (WL1~WL in this example). n (where n is an integer) and bit lines (BL1~BL2) m (where m is an integer) is used for addressing. For example... Figure 1The diagram illustrates an open block, where an open block refers to a block 100 where, during programming, not all data is written to it; only a portion remains unwritten. In this case, block 100 is called an open block. In the following description, without affecting understanding, the label 100 may refer to a block, specifically an open block.

[0053] like Figure 1 As shown, open block 100 includes a written area 102 and an unwritten area 104. This is because programming block 100 of the flash memory is performed on word lines WL1~WL. n The process is performed sequentially, for example, in a 3D stacked flash memory, this order can be from top to bottom or from bottom to top. Therefore, unwritten area 104 generally follows immediately after written area 102. Furthermore, Figure 1 The symbol PA in the text represents the final write word line WL. PA The address, which is the final word line address PA, means that this open block 100 only writes from word line WL1 to this word line WL. PA The storage unit on the device.

[0054] Furthermore, the memory cells in the written region 102 have all been programmed, so they contain random data; that is, the memory cells may be in a low threshold voltage state, a high threshold voltage state, or multiple threshold voltage states. Conversely, the memory cells in the unwritten region 104 have not yet been programmed, and therefore are all in a low threshold voltage state. In the following examples, the word line WL will be used for reading. j Taking the data in the storage unit as an example, that is, the select word line WL j As the object of the read operation. The other word lines WL1~WL j-1 WL j+1 ~WL PA and WL PA+1 ~WL n Then it is not a read object, that is, a non-select word line.

[0055] Figure 2 This is a schematic flowchart illustrating the reading method according to an embodiment of the present disclosure. Figure 3A and Figure 3B This is a schematic diagram illustrating a flash memory reading method according to an embodiment of this disclosure. The following is in conjunction with... Figure 2 as well as Figure 3A , 3B This invention describes a method for reading open blocks in flash memory according to an embodiment of the present disclosure.

[0056] According to embodiments of this disclosure, such as Figure 2As shown, in step S100, when a certain block of the flash memory array needs to be read, the flash memory controller sends a read command to the memory array to select at least one of the multiple word lines of the block (e.g., Figure 3A Or the word line WL shown in 3B j The selected word line is the one specified in the original text, while the other word lines are non-selected word lines. Furthermore, according to embodiments of this disclosure, the read command has a specific read command format, which will be described in detail later. This read command format adds a special code and the final write word line address PA to the read command specification. The read command specification conforms to current flash memory standard specifications. The final write word line is used to indicate the final write word line address PA of a block (e.g., ...). Figure 3B (As shown).

[0057] Next, in step S102, based on the special code of this read command, it is determined whether the block to be read is an open block. Therefore, upon receiving this read command, the special code indicates that the block has not been completely written, thus classifying it as an open block. Furthermore, by using the final written word line address PA, it can be determined from which word line the unwritten area 104 of the open block 100 begins. In this case, assuming the programming order is top-down (or vice versa), then... Figure 3B The open block 100 shown is in word line WL PA and the part before it (i.e., the corresponding character lines WL1~WL) PA This refers to area 102, where all memory cells have been programmed. Therefore, the state of these memory cells may be either a low threshold voltage state or a high threshold voltage state, indicating random data. Furthermore, Figure 3B The open block 100 shown is in word line WL PA The following part (and the corresponding letter WL) PA+1 ~WL n This refers to the unwritten region 104, where none of the memory cells have been programmed, so all memory cells are in a low threshold voltage state.

[0058] Next, in step S102, when it is determined that the block to be read is as follows... Figure 3A When the non-open block 100A is shown, step S104 is executed. In step S104, all storage units of the block are programmed, so existing read methods can be used to select word line WL. j Perform the reading. Specifically, select the word line WL. j A word line read voltage V_rd and an appropriate bit line read voltage Vbl are applied to the selected bit lines for reading. Simultaneously, the non-selected word lines WL1~WL in block 100A are read. j-1 and WL j+1 ~WL nA first read-through bias group is applied. The first read-through bias group includes the first word line read-through voltage Vpass_rd and the first bit line read-through voltage Vblc_rd, as follows: Figure 3A As shown. This allows the storage units for characters that were not selected to be online to be enabled.

[0059] Furthermore, in step S102, when it is determined that the block to be read is as follows... Figure 3B When the open block 100 is shown, step S106 is executed. As described above, at the final write word line WL of the open block 100... PA The preceding area is the written region 102, while the final write word line WL in open block 100... PA The next area is the unwritten region 104. According to this embodiment of the disclosure, when reading the select word line WL... j When writing to unselected word lines WL1~WL in area 102 j-1 WL j+1 ~WL PA The reading is achieved by setting the voltage and by selecting the unselected word line WL in the unwritten area 104. PA+1 ~WL n The readings are obtained by adjusting the voltage settings.

[0060] In other words, when reading open block 100, the method of applying the read voltage for the select word line is the same as the existing method, that is, applying the voltage to the select word line WL. j Apply a word line read voltage V_rd and an appropriate bit line read voltage Vbl to the selected bit lines. However, the method for setting the read voltage for non-selected word lines differs from the existing method.

[0061] like Figure 3B As shown, for the non-select word lines WL1~WL in the written area 102 of open block 100 j-1 WL j+1 ~WL PA A second read-through bias group is applied. According to one embodiment of this disclosure, the second read-through bias group may include a second word line read-through voltage Vpass_x and a second bit line read-through voltage Vblc_xx. Furthermore, the non-selected word line WL in the unwritten region 104 of block 100 is also biased. PA+1 ~WL n A third read-through bias group is applied. Here, the third read-through bias group may include the third word line read-through voltage Vpass_z and the second bit line read-through voltage Vblc_xx.

[0062] According to embodiments of this disclosure, the third word line read voltage Vpass_z of the third read through bias group is different from the second word line read voltage Vpass_x of the second read through bias group. As an example, because the memory cells in the unwritten region 104 are all in a low threshold voltage state, the voltage applied to the unselected word line WL... PA+1 ~WL n The third word line read via voltage Vpass_z can be set to be less than that applied to unselected word lines WL1~WL j-1 WL j+1 ~WL PA The second word line is read through voltage Vpass_x.

[0063] Furthermore, in the example above, when reading the select word line WLj, the non-select word lines WL1~WL in the written area 102 of open block 100 are also read. j-1 WL j+1 ~WL PA The same second read through the bias group is applied to all of them, but this disclosure is not limited thereto. As an example, the non-select word lines WL1~WL in the written area 102 are... j-1 WL j+1 ~WL PA The applied word line reading voltage can be adjusted appropriately according to the word line's position (number). For example, in Figure 3B In the example, non-select word lines WL1~WL can be selected. j-1 Apply voltage Vpass_x to the word line for reading, but not to the non-selected word line WL. j+1 ~WL PA Apply the word line read voltage Vpass_y. Furthermore, in this example, the non-selected word lines WL1~WL1 already written to region 102 are... j-1 WL j+1 ~WL PA They are all divided into two zones, with different word line read voltages Vpass_x and Vpass_y applied to each zone. However, it is also possible to further divide the non-selected word lines WL1~WL j-1 WL j+1 ~WL PA They are all divided into more zones to apply different word lines for reading through voltage.

[0064] Furthermore, according to one embodiment of this disclosure, non-select word lines WL1~WL are applied to the written area 102. j-1 WL j+1 ~WL PAThe second read voltage via the second word line of the bias group, Vpass_x (and / or Vpass_y), can be set in the same existing manner as the first word line read voltage, Vpass_rd. Alternatively, the second word line read voltage, Vpass_x (and / or Vpass_y), can be set differently from the first word line read voltage, Vpass_rd.

[0065] In summary, when reading open block 100, for the unselected word line WL of the unwritten region 104... PA+1 ~WL n The applied third word line read pass voltage Vpass_z is different from the unselected word lines WL1~WL of the written region 102. j-1 WL j+1 ~WL PA The applied second word line read pass voltage Vpass_x (and / or Vpass_y) allows for finer adjustments to the word line read pass voltage when reading the selected word line WL. j This can further prevent data misreading and reading interference.

[0066] Figures 4A to 4C This illustrates the existing flash memory read command format. For example... Figure 4A As shown, the existing flash memory read command format includes a preamble PRX, read command code RD, address CA, RA, and read confirmation command RDC. After the chip enable signal CEB goes low, the command is sent to the input / output terminals IO[7:0]. According to the flash memory datasheet, the read command code RD is, for example, 00h, and the read confirmation command RDC is, for example, 30h, indicating that the transmission of the read command code RD and its read addresses CA and RA has been completed. After the ready signal R / B# goes low, the flash memory will send out the data according to the read command. The address can include the row address CA and the column address RA. Figure 4B In this code, the preamble PRX of the read command format can be set to 01h02h03h, indicating that the memory cell to be read is a third-order cellular storage (TLC). After the read command code 00h is sent, the row addresses C1 and C2 and the column addresses R1, R2, and R3 of the memory cell to be read are immediately sent. Figure 4C In this context, setting the preceding PRX to A2h indicates that the memory cell to be read is a single-level storage cell (SLC). The preceding PRX can be used to set different memory configurations, etc.

[0067] According to embodiments of this disclosure, a read command format is provided, which can determine whether the block to be read is an open block. Figures 5A to 5DThese are various read command formats illustrated according to embodiments of this disclosure. The basic concept of this read command format design is to incorporate the aforementioned special code (e.g., B0h) and the final write word line address PA into the read command specification, as follows: Figure 4A The read command format shown includes the preamble PRX, read command code RD, address CA, RA, and read confirmation command RDC. The special code and the final write word line address PA can be discussed and finalized with the customer. Several feasible methods are listed below.

[0068] like Figure 5A As shown, the simplest way is to append the special code (e.g., B0h, though other values ​​can also be used) and the final write word line address PA before the read command specification. That is, the special code B0h is added before the final write word line address PA, followed by the entire read command code RD (e.g., 00h). Alternatively, a prefix PRX can be added before the special code B0h.

[0069] exist Figure 5B In the example shown, since reading a block is typically a whole page read, the row address CA is rarely used. Therefore, the final write word line address PA can replace the row address CA in the standard read command specification. Furthermore, the special code B0h precedes the read command code RD (e.g., 00h). Additionally, a preceding PRX can be added before the special code B0h.

[0070] exist Figure 5C The example shown represents the command format for a multiplane block. In this example, the read command format consists of a first part and a second part. The first part includes, in sequence, the preamble PRX, read command code 00h, row address CA, final write word line address PA, and special code B0h. The second part includes, in sequence, the read command code 00h, row address CA, column address RA, and read confirmation command 30h, which is the standard read command specification described above.

[0071] The example above simply appends the special code B0h and the final write word line address PA to the standard read command specification. The example below will further utilize another command from flash memory. The standard flash memory specification also includes some customizable features. Using the so-called set feature command in the standard specification, it is possible to extend the specification to implement custom features. Therefore, this embodiment utilizes the set feature command to define an open block.

[0072] exist Figure 5DIn the example, the read command format further includes a feature value setting section (left side of the figure) and a read command specification (right side of the figure). The feature value setting section includes, in sequence, the feature setting command FEh, the feature value FA, and the final write word line address PA. Similarly, the read command specification includes, in sequence, the read command code 00h, the row address CA, the column address RA, and the special code B0h. That is, Figure 5C The read confirmation command 30h in the read command specification (i.e., the second part) is replaced with the special code B0h.

[0073] In addition, when there is more than one block to be read, the read command format can include multiple sets of feature values / final write bit line addresses, such as B0h / PA0, B1h / PA1, etc., to distinguish whether different blocks are open blocks and their respective final write word line addresses.

[0074] Figure 6 This is a flowchart illustrating the determination of bit line reading through voltage according to an embodiment of the present disclosure. Figure 7 This is a block diagram illustrating the determination of the bit line reading through voltage according to an embodiment of this disclosure. For example... Figure 7 As shown, the architecture example of open block 100 here is similar to the one described above. Figure 3B Since the same parts are the same, the same parts can be referred to the above description, and the repeated parts are omitted here. Here, the open block 100 can be further divided into multiple sections, such as section 1, section 2, ..., section N, where N is an integer. In addition, the final write word line address PA can be any of the sections 1, 2, ..., N. When reading the select word line WLj, the word line read voltage V_rd is applied to the select word line WLj, and the unselected word lines WL1~WL in the written area 102 are read. j-1 WL j+1 ~WL PA Apply a second word line read pass voltage Vpass_x (and / or Vpass_y, as detailed above) to the unselected word line WL in the unwritten region 104. PA+1 ~WL n Then apply the third word line to read the voltage Vpass_z.

[0075] For unselected word lines WL1~WL j-1 WL j+1 ~WL PA and WL PA+1 ~WL n The corresponding bit line is then subjected to any one of the bit line read pass voltages VBLx (x = 1~N, where N is an integer). That is, the bit line read pass voltage VBLx is determined based on the final write word line WL. PA It depends on which segment from segment 1 to N it is in. The following will refer to... Figure 6Let me explain in detail.

[0076] like Figure 6 As shown, in step S200, a read command is received, which includes a special code (such as B0h) and the final write word line address PA. In step S202, it is determined whether the block to be read is an open block based on the special code attached to the read command.

[0077] Next, in step S202, if it is determined that the block to be read is not an open block, then step S204 is executed. In step S204, the selection word line WL is... j A word line read voltage V_rd is applied, and an appropriate bit line read voltage Vbl is applied to the selected bit lines to perform the read operation. Simultaneously, the non-selected word lines WL1~WL in this block are read. j-1 and WL j+1 ~WL n Apply a first read pass bias group, which includes the first word line read pass voltage Vpass_rd and the first bit line read pass voltage Vblc_rd.

[0078] Furthermore, in step S202, if it is determined that the block to be read is open block 100, then step S206 is executed to further determine the final write word line WL. PA Is it in section 1? If it is eventually written to word line WL PA In section 1, step S208 is executed. In step S208, the selection word line WL is read. j At that time, for the unselected word lines WL1~WL in the already written area 102 j-1 WL j+1 ~WL PA Apply the second word line read pass voltage Vpass_x (and / or Vpass_y) and apply it to the unselected word line WL of the unwritten region 104. PA+1 ~WL n Apply a third word line read pass voltage Vpass_z. Additionally, apply a bit line read pass voltage VBL_1 to the bit lines corresponding to the unselected word lines.

[0079] In step S206, if it is determined that the final write word line WL PA If not in section 1, proceed to step S210. In step S210, further determine the final write word line WL. PA Is it in section 2? If it is eventually written to word line WL PA In section 2, step S212 is executed. In step S212, the selection word line WL is read. j At that time, for the unselected word lines WL1~WL in the already written area 102 j-1 WL j+1 ~WL PAApply the second word line read pass voltage Vpass_x (and / or Vpass_y) and pass the unselected word line WL of the unwritten region 104. PA+1 ~WL n Apply a third word line read pass voltage Vpass_z. Additionally, apply a bit line read pass voltage VBL_2 to the bit lines corresponding to the unselected word lines.

[0080] Determine the final write word line WL PA The procedure for determining which segment is in will continue until it is determined whether the segment is in segment N. For example, in step S210, if it is determined that the final write word line WL will be written... PA If not in section 2, proceed to step S214. In step S214, further determine the final write word line WL. PA Is it in section N? If it is eventually written to word line WL PA In section N, step S216 is executed. In step S216, the select word line WL is read. j At that time, for the unselected word lines WL1~WL in the already written area 102 j-1 WL j+1 ~WL PA Apply the second word line read pass voltage Vpass_x (and / or Vpass_y) and apply it to the unselected word line WL of the unwritten region 104. PA+1 ~WL n Apply a third word line read pass voltage Vpass_z. Additionally, apply a bit line read pass voltage VBL_N to the bit lines corresponding to the unselected word lines.

[0081] In step S214, if it is determined that the final write word line WL PA If not in section N, proceed to step S218. In step S218, read the selection word line WL. j At that time, for the non-select word lines WL1~WL in this block j-1 and WL j+1 ~WL n Apply the first word line read pass voltage Vpass_rd and the first bit line read pass voltage Vblc_rd.

[0082] When reading an open block, because the resistance of the memory cells in the low-threshold voltage state of the unwritten region 104 is different from that of the memory cells in the high-threshold voltage state, the quantity of memory cells in the low-threshold voltage state of the unwritten region 104 can be determined by the final write word line address PA. Therefore, the quantity can be further determined based on the final write word line WL. PA The bit line read voltage VBL_N applied to the bit line is adjusted according to the corresponding section. This further reduces false reads and read interference.

[0083] Based on the above method, when reading open blocks of flash memory, setting the word line read voltage applied to unselected word lines in areas that have not been written to be different from the word line read voltage applied to unselected word lines in areas that have already been written to can reduce false reads and read interference. Furthermore, the bit line read voltage can be adjusted accordingly based on the final position of the written word line, which can further reduce false reads and read interference.

[0084] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for reading a flash memory device, the flash memory device comprising a plurality of blocks, the method comprising: Receive a read command to read at least one of the plurality of blocks, the read command being appended with a special code and the final write word line address; Based on the special code of the read command, it is determined whether the at least one block is an open block, and the open block has a written area and an unwritten area; In the case where it is determined that the at least one block is not an open block, when reading the at least one block, a first read pass bias group is applied to a plurality of non-select word lines in the at least one block; as well as When it is determined that the at least one block is an open block, and when reading the at least one block, a second read pass bias group is applied to a plurality of non-select word lines in the written area of ​​the at least one block, and a third read pass bias group is applied to a plurality of non-select word lines in the unwritten area.

2. The read method of a flash memory device according to claim 1, wherein, The first read-through bias group includes the first word line read-through voltage and the first bit line read-through voltage, and The second read-through bias group includes the second word line read-through voltage and the second bit line read-through voltage.

3. The method for reading a flash memory device according to claim 1, wherein... The second read operation via the bias group includes the second word line read voltage and the second bit line read voltage. The third read-through bias group includes the third word line read-through voltage and the second bit line read-through voltage, and The voltage through which the third word line is read is different from the voltage through which the second word line is read.

4. The method for reading a flash memory device according to claim 2, wherein the second word line read pass voltage of the second read pass bias group is determined based on the position of the plurality of non-selected word lines in the written region.

5. The method for reading a flash memory device according to claim 1, wherein the open block further comprises a plurality of nodes. The second and third read pass voltages in the bias group are determined based on which of the plurality of segments the final write word line address is located in.

6. The method for reading a flash memory device according to claim 1, wherein the read command has a read command format, the read command format being the read command specification plus the special code and the final write word line address, and the read command specification sequentially including a read command code, a row address, a column address, and a read confirmation command.

7. The method for reading a flash memory device according to claim 6, wherein the special code and the final write word line address are appended before the read command specification.

8. The method for reading a flash memory device according to claim 7, wherein the read command format further includes a preamble, the preamble being arranged before the special code.

9. The method for reading a flash memory device according to claim 6, wherein the special code is arranged before the read command code in the read command specification, and the final write word line address replaces the row address.

10. The method for reading a flash memory device according to claim 9, wherein the read command format further includes a preamble, the preamble being arranged before the special code.

11. The method for reading a flash memory device according to claim 1, wherein the read command has a read command format, and the read command format further includes a first part and a second part. The first part sequentially includes a preamble, a read command code, a line address, the final write word line address, and the special code, and The second part includes, in sequence, the read command code, the row address, the column address, and the read confirmation command.

12. The method for reading a flash memory device according to claim 1, wherein the read command has a read command format, and the read command format further includes a setting feature value portion and a read command specification. The set feature value section sequentially includes a set feature command, a feature value, and the final write word line address, and The read command specification includes, in sequence, the read command code, the row address, the column address, and the special code.

13. The reading method of the flash memory device according to claim 1, the reading method further comprising applying a read voltage to a select word line and applying a bit line voltage to a select bit line for reading.

14. A read command format for a flash memory device, including... A special code is used to specify whether each of the plurality of blocks in the flash memory device is an open block; Finally, the word line address is written to specify the address of the last word line written in each of the plurality of blocks; as well as The read command specification, in order to conform to the standard format of the flash memory device, further includes the read command code, row address, column address, and read confirmation command in sequence.

15. The read command format for a flash memory device according to claim 14, wherein the special code and the final write word line address are appended before the read command specification.

16. The read command format for a flash memory device according to claim 14, wherein the special code is arranged before the read command code in the read command specification, and the final write word line address replaces the row address.

17. The read command format for a flash memory device according to claim 14, wherein the read command format further comprises a first part and a second part. The first part sequentially includes a preamble, the read command code, the line address, the final write word line address, and the special code, and The second part is the read command specification.

18. The read command format for a flash memory device according to claim 14, wherein the read command format further includes a setting feature value portion. The set feature value section includes, in sequence, a set feature command, a feature value, and the final write word line address.

19. The read command format for the flash memory device according to claim 14, further comprising a preamble, the preamble being arranged before the special code.

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