High signal-to-noise ratio sensing readout circuit for simulating silicon photomultiplier

Abstract

The invention discloses a high signal-to-noise ratio sensing readout circuit for simulating a silicon photomultiplier. The high signal-to-noise ratio sensing readout circuit comprises a correlation event calculation circuit and a fully differential current buffer circuit. The input end of the correlation event calculation circuit is connected with the output end of the pulse compression circuit in the macro pixel of the analog silicon photomultiplier, and the output end of the correlation event calculation circuit is connected with the current generation circuit in the macro pixel. The input end of the fully-differential current buffer circuit is connected with the output end of the current generating circuit, and the output end of the fully-differential current buffer circuit is connected with a subsequent fully-differential trans-impedance amplifier circuit. The correlation event calculation circuit adopts a simulation scheme based on a sequencer, background light noise can be effectively filtered out through calculation, and the signal-to-noise ratio of the circuit is improved; the fully differential current buffer circuit isolates the subsequent fully differential transimpedance amplifier circuit from the output capacitor of the macro pixel, so that the overall circuit bandwidth is improved. All circuits adopt a fully differential form, so that common-mode noise introduced by macro pixels is weakened, and interference on leading-edge moment identification of a subsequent comparator is avoided.

Description

Technical Field

[0001] This invention belongs to the field of laser radar optical signal receiving technology, specifically relating to a high signal-to-noise ratio sensing readout circuit for simulating silicon photomultiplier tubes. Background Technology

[0002] In recent years, with the development of laser technology and integrated circuits, lidar has been applied in more fields that are closely related to the public.

[0003] LiDAR based on the Time-of-Flight (ToF) principle directly or indirectly measures the delay between the emitted laser and the received reflected light to obtain depth images, offering advantages such as strong anti-interference capability, low cost, and high detection accuracy. Among these, direct Time-of-Flight (dToF) lidar has attracted significant attention due to its simple measurement principle, high sensitivity of the front-end detection device, and long measurement range. A typical DToF lidar system usually consists of three parts: laser emission, front-end reception, and back-end signal processing. The front-end reception module is often the main factor limiting the performance of the lidar system. Silicon photomultipliers (SiPMs), fabricated using silicon-based processes, consist of multiple single-photon avalanche photodiodes (SPADs) operating in Geiger mode in parallel. With their advantages such as single-photon level detection sensitivity and compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes, they are increasingly being applied in the lidar field.

[0004] However, due to the extremely high sensitivity of SPAD, background light noise can easily trigger the SiPM response, resulting in the output of false ToF information. Furthermore, the large parasitic capacitance at the SiPM pixel end severely attenuates the bandwidth of the traditional transimpedance amplifier (TIA), increasing the walking error and thus reducing the detection accuracy of the lidar system. In addition, common-mode noise introduced by the front-end circuitry significantly affects the accuracy of subsequent time-phase discrimination decisions. Summary of the Invention In order to solve the above-mentioned problems in the prior art, the present invention provides a high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a high signal-to-noise ratio sensing readout circuit for simulating silicon photomultiplier tubes, comprising: M related event calculation circuits and a fully differential current buffer circuit; The input terminal of the i-th relevant event calculation circuit is connected to the output terminals of N pulse compression circuits in the i-th macropixel of the analog silicon photomultiplier tube. The output terminal of the i-th relevant event calculation circuit is connected to the input terminals of N current generation circuits in the i-th macropixel. Here, M is a positive integer greater than 1, N is a positive integer greater than or equal to 4, and i ranges from 1 to M. The analog silicon photomultiplier tube has a pixel array composed of M macropixels. Each macropixel is composed of N pixel units. Each pixel unit includes a single-photon avalanche diode, the pulse compression circuit, and the current generation circuit. The output terminal of the current generation circuit in the M macropixels is connected to the input terminal of the fully differential current buffer circuit. The output terminal of the fully differential current buffer circuit is connected to the fully differential transimpedance amplifier circuit. The i-th related event calculation circuit is used to determine that the i-th macro-pixel is triggered when the number of single-photon avalanche diode responses in the i-th macro-pixel is greater than a threshold within the time window; The fully differential current buffer circuit is based on a modulated cascode type and is used to isolate the output capacitor of the pixel array from the fully differential transimpedance amplifier circuit, as well as to eliminate common-mode noise interference.

[0005] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) In this invention, each macropixel in the simulated silicon photomultiplier tube is connected to a related event calculation circuit. The related event calculation circuit adopts a sequencer-based simulation scheme. It determines that the macropixel is effectively triggered only when the number of single-photon avalanche diode responses in the connected macropixel is greater than a set threshold within a time window. This effectively enhances the lidar's ability to suppress background light noise and achieves a high signal-to-noise ratio. 2) The fully differential current buffer circuit in this invention is based on a modulated common-source cascode fully differential current buffer. The input terminal of the buffer circuit is connected to the output terminal of the current generation circuit in each macropixel of the analog silicon photomultiplier tube, while the output terminal is connected to the fully differential transimpedance amplifier circuit following the analog silicon photomultiplier tube. This isolates the fully differential transimpedance amplifier circuit from the output capacitor of the pixel array in the analog silicon photomultiplier tube, thereby improving the overall circuit bandwidth and thus improving the ranging accuracy of the system. Furthermore, the differential architecture of the buffer circuit reduces the common-mode noise introduced by the front-end circuit and improves the decision accuracy of subsequent time-phase discrimination.

[0006] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0007] Figure 1 This is an internal circuit topology diagram of each pixel unit provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the circuit structure of a high signal-to-noise ratio sensing readout circuit for simulating a silicon photomultiplier tube, provided in an embodiment of the present invention. Figure 3 This is a circuit topology diagram of the related event calculation circuit provided in an embodiment of the present invention; Figure 4 This is a circuit topology diagram of a fully differential current buffer circuit provided in an embodiment of the present invention. Detailed Implementation

[0008] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0009] This invention provides a high signal-to-noise ratio inductive readout circuit for simulating a silicon photomultiplier tube, comprising: M correlation event calculation circuits and a fully differential current buffer circuit; wherein, the input terminal of the i-th correlation event calculation circuit is connected to the output terminals of N pulse compression circuits in the i-th macropixel of the simulated silicon photomultiplier tube, and the output terminal of the i-th correlation event calculation circuit is connected to the input terminals of N current generation circuits in the i-th macropixel, wherein M is a positive integer greater than 1, N is a positive integer greater than or equal to 4, and i takes the value from 1 to M; the simulated silicon photomultiplier tube has a pixel array composed of M macropixels, each macropixel is composed of N pixel units, and each pixel unit includes a single-photon avalanche diode, a pulse compression circuit, and a current generation circuit; the output terminals of the current generation circuits in the M macropixels are connected to the input terminals of the fully differential current buffer circuit, and the output terminals of the fully differential current buffer circuit are connected to a fully differential transimpedance amplifier circuit. The i-th related event calculation circuit determines that the i-th macropixel is triggered when the number of single-photon avalanche diode responses in the i-th macropixel exceeds a threshold within the time window. The fully differential current buffer circuit is based on a modulated cascode common-source current buffer, used to isolate the output capacitor of the pixel array from the fully differential transimpedance amplifier circuit, and to eliminate common-mode noise interference. It should be noted that the signal pulses output by the N pulse compression circuits constitute an N-bit pulse signal IN, and the aforementioned threshold is the threshold of the i-th related event calculation circuit.

[0010] Each pixel unit includes: a single-photon avalanche diode, a quenching reset circuit, a pulse compression circuit, a first delay unit, and a current generation circuit connected in sequence, and the first delay unit and the current generation circuit are connected via a first analog switch. For example, Figure 1 This is a diagram of the internal circuit topology of each pixel unit. For example... Figure 1 As shown, the cathode of this single-photon avalanche diode is connected to voltage HV, the anode is connected to the input of the quenching and reset circuit, the output of the quenching and reset circuit is connected to the input of the pulse compression circuit, the output of the pulse compression circuit is connected to the input of the first delay unit, the output of the first delay unit is connected to one end of the first analog switch, and the other end of the first analog switch is connected to the input of the current generation circuit. It should be noted that the quenching and reset circuit, pulse compression circuit, first delay unit, and current generation circuit are all existing circuits; therefore, the structure of these circuits will not be described in detail in this invention.

[0011] For example, Figure 2 This is a schematic diagram of the high signal-to-noise ratio sensing readout circuit for simulating silicon photomultiplier tubes provided by the present invention. Figure 2 This diagram illustrates the circuit connections between a macropixel in an analog silicon photomultiplier tube, a related event calculation circuit, and a fully differential current buffer circuit when N is 4. Figure 2 As shown, IN<0:3> represents the 4-bit pulse signal IN composed of the signal pulses output by the four pulse compression circuits in the four pixel units constituting this macro-pixel, TRIG represents the trigger signal generated by the correlation event calculation circuit based on the input IN<0:3>, and I IP and I IN I represents the differential current signal output by the four current generation circuits of this macropixel. OUTP and I OUTN This represents the differential current signal output by the fully differential current buffer circuit.

[0012] In this invention, each relevant event calculation circuit includes: an N-bit sequencer, N second analog switches, and a trigger signal generation and reset module. It should be noted that both the first and second analog switches refer to analog switches; the use of "first" and "second" in this invention is to distinguish analog switches located in different circuits. The input terminal of the N-bit sequencer is used to connect IN<0:N-1>, and the N output terminals of the N-bit sequencer are connected one-to-one with one end of each of the N second analog switches. The control terminals of the N second analog switches are used to connect to an externally input threshold signal N. TH (i.e. N) TH <0:N-1>); The other ends of the N second analog switches are all connected to the input terminal of the trigger signal generation and reset module, and the output terminal of the trigger signal generation and reset module is connected to the control terminal of the first analog switch. The trigger signal TRIG generated by the trigger signal generation and reset module is used to control the on and off of the first analog switch. N TH <0:N-1> is an N-bit signal used to control the threshold change of the relevant event calculation circuit, where N THA single signal value of <0:N-1> controls a second analog switch, when N TH When the signal values ​​of the least significant bit to the most significant bit of <0:N-1> are sequentially 1, the threshold of the related event calculation circuit changes sequentially from 1 to N. For example, when N is 4, and N TH When the low-order signal value of <0:3> is 1, the threshold of the correlation event calculation circuit is 1, and when N TH When the signal value of the second least significant bit of <0:3> is 1, the threshold of the correlation event calculation circuit is 2, when N TH When the signal value of the second most significant bit of <0:3> is 1, the threshold of the correlation event calculation circuit is 3. When N TH When the signal value of the high bit of <0:3> is 1, the threshold of the relevant event calculation circuit is 4.

[0013] Here, the N-bit sequencer is constructed using multiple 2-bit sequencers. The trigger signal generation and reset module includes multiple inverters, multiple MOSFETs, and a second delay unit. The input of this second delay unit is used to input the trigger signal TRIG, and the output is used to output the reset signal R. ST It should be noted that both the first delay unit and the second delay unit refer to delay units. The use of "first" and "second" in this invention is to distinguish delay units located in different circuits. For example, when N is 4, the N-bit sorter is a 4-bit sorter, and the 4-bit sorter is composed of five 2-bit sorters. For example, Figure 3 This is a circuit topology diagram of a correlated event calculation circuit, illustrating how five 2-bit sorters can be combined to form a 4-bit sorter. Specifically, as shown... Figure 3As shown, each 2-bit sorter consists of an AND gate and a NOT gate. Both inputs of the first and second 2-bit sorters are connected to the pulse signal IN<0:3>. One output of the first 2-bit sorter is connected to one input of the third 2-bit sorter, and another output of the first 2-bit sorter is connected to one input of the fourth 2-bit sorter. One output of the second 2-bit sorter is connected to the other input of the third 2-bit sorter, and the other output of the second 2-bit sorter is connected to the other input of the fourth 2-bit sorter. One output of the third 2-bit sorter is connected to one end of the first second analog switch, and the other output of the third 2-bit sorter is connected to one input of the fifth 2-bit sorter. The two outputs of the fifth 2-bit sorter are connected to one end of the second and third second analog switches, respectively. One output of the fourth 2-bit sorter is connected to the other input of the fifth 2-bit sorter, and the other output of the fourth 2-bit sorter is connected to one end of the fourth second analog switch. This sorter has a simple structure and a small circuit area.

[0014] For example, when N is 5, the truth table of the 5-bit sorter is shown in Table 1; when N is 6, the truth table of the 6-bit sorter is shown in Table 2.

[0015] Table 1

[0016] Table 2

[0017] Here, the trigger signal generation and reset module includes: inverter T1, inverter T2, inverter T3, MOSFETs M1~M6, and a second delay unit. As described above. Figure 3 As shown, the input terminal of inverter T1 is simultaneously connected to the other ends of N second analog switches and the gate of MOSFET M1. The output terminal of inverter T1 is connected to the gate of MOSFET M2. The source of MOSFET M1 is connected to the drain of MOSFET M5. The sources of MOSFET M5 and MOSFET M6 are both used to connect to the power supply voltage V. DDThe gate of MOSFET M5 is connected to the gate of MOSFET M3 and the output of inverter T2. The drain of MOSFET M1 is connected to the drain of MOSFET M2, the drain of MOSFET M6, the input of inverter T2, and the input of inverter T3. The source of MOSFET M2 is connected to the drain of MOSFET M3. The source of MOSFET M3 is connected to the drain of MOSFET M4. The source of MOSFET M4 is grounded. The gate of MOSFET M4 is connected to the gate of MOSFET M6 and the output of the second delay unit. The input of the second delay unit is connected to the output of inverter T3. The output of inverter T3 is connected to the control terminal of the first analog switch. The output of inverter T3 is used to output the trigger signal TRIG.

[0018] Combination Figure 2 and Figure 3 IN<0:3> is a single SPAD trigger signal, entering the 4-bit sequencer. NTH<0:3> controls the output of the 4-bit sequencer, with only one bit being 1. When NTH<0:3> is 1 from low to high bits, it represents a threshold of 1 to 4 for the relevant event calculation circuit. When the number of pulses of IN<0:3> is greater than or equal to the threshold of the relevant event calculation circuit at a certain moment, node A is at a high level; otherwise, node A is always at a low level. The trigger signal generation and reset module outputs the potential of point A as a TRIG signal and resets it. When the TRIG signal is high, it indicates that the macro-pixel connected to the relevant event calculation circuit is triggered, and thus the analog switch in the macro-pixel (i.e., the first analog switch mentioned above) is turned on, thereby controlling the current generation circuit of the triggered pixel unit in the four pixel units inside the macro-pixel to generate differential current. The second delay unit in the trigger signal generation and reset module widens the voltage pulse width of node A, opening a time window for the output of subsequent circuits, ensuring that the TRIG signal normally controls the output of the current generation circuit inside the macro-pixel. It should be noted that the width of the time window can be set according to actual needs, and the present invention does not limit the width of the time window.

[0019] In this invention, the fully differential current buffer circuit includes: a pair of differential input common gates, and a two-stage differential internal active feedback stage connected to the pair of differential input common gates; wherein, the differential input terminals of the pair of differential input common gates are connected to the output terminals of the current generation circuits in M ​​macro pixels, and the differential output terminals of the pair of differential input common gates serve as the output terminals of the fully differential current buffer circuit, and the pair of differential input common gates are also used to respectively connect to a first bias voltage V. BP Second bias voltage V BN and power supply voltage V DDThe two-stage differential internal active feedback stage includes: two input terminals, a common drain, a load module, and a bias current supply module; wherein, the common drain and each input terminal are connected to a pair of differential input common gates, and each input terminal is connected to the common drain, the load module, and the bias current supply module, respectively. The bias current supply module and the common drain stage are also used to connect the power supply voltage VDD and the first bias voltage V. BP The load module is also grounded.

[0020] In some embodiments, one of the pair of differential input common gates includes a MOSFET M. P1 MOSFET M 01 MOSFET M N1 The other common gate in a pair of differential input common gates includes a MOSFET M. P2 MOSFET M 02 MOSFET M N2 Furthermore, the MOSFET M N1 and MOSFET M N2 The drains of the MOSFETs form a pair of differential input terminals. P1 and MOSFET M P2 The drains of M form a pair of differential output terminals. It should be noted that M... 01 and M 02 All are NMOS transistors. NMOS transistor M 01 M 02 As a common-gate amplifier transistor, in order to provide a suitable voltage margin to ensure that each MOSFET operates in the saturation region, M 01 M 02 Using deep N-well transistors eliminates the effects of bulk effects and reduces the threshold voltage of both. Deep N-well transistors are transistors fabricated using deep N-well technology. Deep N-well (DNW) is a key technology in semiconductor manufacturing used for isolating and controlling device performance, widely applied in the manufacture of CMOS integrated circuits and high-voltage devices. MOS transistors M... P1 and M P2 and MOSFET M N1 and M N2 For a simple common-source current mirror, the two transistors are M and M respectively. 01 MOSFET M 02 Provide bias current.

[0021] In some embodiments, the two-stage differential internal active feedback stage includes: a MOSFET M P3 MOSFET M P4 MOSFET M P5 MOSFET M 03 MOSFET M 04 MOSFET M05 MOSFET M 06 MOSFET M 07 MOSFET M 08 MOSFET M 09 MOSFET M 10 Among them, MOS transistor M 03 and MOSFET M 05 This forms an input stage, MOSFET M 04 and MOSFET M 06 This forms another input stage, the MOSFET M 07 and MOSFET M 08 The load module consists of MOSFET M. 09 MOSFET M 10 MOSFET M P3 and MOSFET M P5 Forming a common drain, MOSFET M P4 It is a bias current supply module, M 09 and M 10 Both use a source-substrate short-circuit method, which improves the linearity of the circuit.

[0022] For example, Figure 4 This is a circuit topology diagram of a fully differential current buffer circuit. For example... Figure 4 As shown, M P1 M P2 M P3 M P4 M P5 The source is connected to V. DD M P1 M P2 M P3 M P4 M P5 The gates of all are connected to V BP M N1 M N2 The gates of all are connected to V BN M N1 M 05 M 06 M 07 M 08 M N2 The sources of M are all grounded. 09 M 10 The drains of M are all grounded. P1 The drain and M 01 The drain connection, M 01 The source pole is simultaneously with M N1 Drain, M 03 gate, M 05 gate connection, M 03 The drain of M is simultaneously05 Drain, M 07 gate, M 07 Drain, M 09 gate connection, M 09 The source pole is simultaneously with M 01 gate, M P3 The drain connection, M P4 The drain of M is simultaneously 03 The source, M 04 The source connection, M 04 The drain of M is simultaneously 10 gate, M 08 gate, M 08 Drain, M 06 The drain connection, M 06 The gate of M is simultaneously 04 gate, M 02 The source, M N2 The drain connection, M 02 The drain and M P2 The drain connection; and M N1 and M N2 The drains of the two electrodes form a pair of differential input terminals, used to connect the differential current signal I output from the current generation circuits in all macro pixels. IP and I IN M P1 and M P2 The drains of the two electrodes form a pair of differential output terminals, used to output the differential current signal I. OUTP and I OUTN .like Figure 4 As shown, the two-stage differential internal active feedback stage reduces the overall circuit's input resistance, and this internal active feedback stage does not require an additional common-mode feedback circuit. M P4 This provides a bias current for the internal active feedback stage. M 03 ~ M 06 This is the input stage for the internal active feedback stage. M 07 M 08 This is the load for the internal active feedback stage. M 09 M 10 M P3 M P5 The constructed source follower can guarantee M 03 M 04 M operates stably in the saturation region. 09 and M 10 Both use source-substrate short-circuiting, which improves the linearity of the circuit.

[0023] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0025] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0026] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes, characterized in that, include: M related event calculation circuits and a fully differential current buffer circuit; The input terminal of the i-th relevant event calculation circuit is connected to the output terminals of N pulse compression circuits in the i-th macropixel of the analog silicon photomultiplier tube. The output terminal of the i-th relevant event calculation circuit is connected to the input terminals of N current generation circuits in the i-th macropixel. Here, M is a positive integer greater than 1, N is a positive integer greater than or equal to 4, and i ranges from 1 to M. The analog silicon photomultiplier tube has a pixel array composed of M macropixels. Each macropixel is composed of N pixel units. Each pixel unit includes a single-photon avalanche diode, the pulse compression circuit, and the current generation circuit. The output terminal of the current generation circuit in the M macropixels is connected to the input terminal of the fully differential current buffer circuit. The output terminal of the fully differential current buffer circuit is connected to the fully differential transimpedance amplifier circuit. The i-th related event calculation circuit is used to determine that the i-th macro-pixel is triggered when the number of single-photon avalanche diode responses in the i-th macro-pixel is greater than a threshold within the time window; The fully differential current buffer circuit is based on a modulated cascode type and is used to isolate the output capacitor of the pixel array from the fully differential transimpedance amplifier circuit, as well as to eliminate common-mode noise interference.

2. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 1, characterized in that, Each pixel unit includes: a single-photon avalanche diode, a quenching reset circuit, a pulse compression circuit, a first delay unit, and a current generation circuit connected in sequence, and the first delay unit and the current generation circuit are connected through a first analog switch; the signal pulses output by the N pulse compression circuits constitute an N-bit pulse signal IN; the i-th related event calculation circuit includes: an N-bit sorter, N second analog switches, and a trigger signal generation and reset module; The input terminal of the N-bit sequencer is used to receive the pulse signal IN. The N output terminals of the N-bit sequencer are connected one-to-one with one end of each of the N second analog switches. The control terminals of the N second analog switches are used to receive an externally input threshold signal N. TH The other end of each of the N second analog switches is connected to the input terminal of the trigger signal generation and reset module, and the output terminal of the trigger signal generation and reset module is connected to the control terminal of the first analog switch. The trigger signal TRIG generated by the trigger signal generation and reset module is used to control the on and off of the first analog switch.

3. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 2, characterized in that, The threshold signal N TH It is an N-bit signal used to control the change of the threshold, wherein the threshold signal N TH A single signal value controls a second analog switch when the threshold signal N TH When the signal values ​​from the low bit to the high bit are 1 in sequence, the threshold of the i-th related event calculation circuit changes from 1 to N in sequence.

4. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 2, characterized in that, The N-bit sorter is composed of multiple 2-bit sorters; the trigger signal generation and reset module includes multiple inverters, multiple MOS transistors, and a second delay unit, wherein the input terminal of the second delay unit is used to input the trigger signal TRIG, and the output terminal is used to output the reset signal R. ST .

5. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 4, characterized in that, The trigger signal generation and reset module includes: inverter T1, inverter T2, inverter T3, MOSFETs M1~M6, and the second delay unit; The input terminal of inverter T1 is simultaneously connected to the other terminals of the N second analog switches and the gate of MOSFET M1. The output terminal of inverter T1 is connected to the gate of MOSFET M2. The source of MOSFET M1 is connected to the drain of MOSFET M5. The sources of MOSFET M5 and MOSFET M6 are both used to connect to the power supply voltage V. DD The gate of MOSFET M5 is connected to the gate of MOSFET M3 and the output of inverter T2. The drain of MOSFET M1 is connected to the drain of MOSFET M2, the drain of MOSFET M6, the input of inverter T2, and the input of inverter T3. The source of MOSFET M2 is connected to the drain of MOSFET M3. The source of MOSFET M3 is connected to the drain of MOSFET M4. The source of MOSFET M4 is grounded. The gate of MOSFET M4 is connected to the gate of MOSFET M6 and the output of the second delay unit. The input of the second delay unit is connected to the output of inverter T3. The output of inverter T3 is connected to the control terminal of the first analog switch. The output of inverter T3 is used to output the trigger signal TRIG.

6. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 4, characterized in that, When N is 4, the N-bit sorter is a 4-bit sorter, and the 4-bit sorter is composed of 5 2-bit sorters.

7. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 1, characterized in that, The fully differential current buffer circuit includes: a pair of differential input common gates, and a two-stage differential internal active feedback stage connected to the pair of differential input common gates; wherein, the differential input terminals of the pair of differential input common gates are connected to the output terminals of the current generation circuits in the M macro pixels, and the differential output terminals of the pair of differential input common gates serve as the output terminals of the fully differential current buffer circuit, and the pair of differential input common gates are also used to respectively connect to a first bias voltage V. BP Second bias voltage V BN and power supply voltage V DD .

8. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 7, characterized in that, The two-stage differential internal active feedback stage includes: two input terminals, one common drain terminal, one load module, and one bias current supply module; The common drain and each input terminal are connected to the pair of differential input common gates. Each input terminal is connected to the common drain, the load module, and the bias current supply module, respectively. The bias current supply module and the common drain are also used to connect to the power supply voltage V. DD and the first bias voltage V BP The load module is also grounded.

9. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 8, characterized in that, One of the differential input common gates includes a MOSFET M. P1 MOSFET M 01 MOSFET M N1 The other common gate of the pair of differential input common gates includes a MOSFET M. P2 MOSFET M 02 MOSFET M N2 Among them, MOS transistor M N1 and MOSFET M N2 The drains of the MOSFETs form a pair of differential input terminals. P1 and MOSFET M P2 The drains of the two electrodes form a pair of differential output terminals.

10. The high signal-to-noise ratio inductive readout circuit for simulating silicon photomultiplier tubes according to claim 9, characterized in that, The two-stage differential internal active feedback stage includes: MOSFET M P3 MOSFET M P4 MOSFET M P5 MOSFET M 03 MOSFET M 04 MOSFET M 05 MOSFET M 06 MOSFET M 07 MOSFET M 08 MOSFET M 09 MOSFET M 10 ; Among them, MOS transistor M 03 and MOSFET M 05 This forms an input stage, MOSFET M 04 and MOSFET M 06 This forms another input stage, the MOSFET M 07 and MOSFET M 08 The load module is composed of MOS transistor M 09 MOSFET M 10 MOSFET M P3 and MOSFET M P5 The common drain MOSFET M is formed P4 It is the bias current providing module.

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