An impedance-invariant vector synthesis phase shifter, array element, phased array

Abstract

The application discloses an impedance-invariant vector synthesis phase shifter, an array element and a phased array, and relates to the technical field of phased array design. The application provides the impedance-invariant vector synthesis phase shifter, two capacitive compensation branches are arranged in each Gilbert cell of a variable gain amplifier, and the capacitive compensation branches are only connected to the circuit when the bit is turned off, so that the output impedance of the cell remains unchanged when the bit is turned on and turned off, the phase shifting precision of the phase shifter is effectively improved, the root mean square phase error of the phase shifter is reduced to the acceptable range in the engineering field, the phase shifting is directly carried out according to the most ideal condition based on the IQ quadrature signal, the complicated calibration work is avoided, and the calibration problem of the vector synthesis phase shifter is solved. The application further provides the array element, which adopts the impedance-invariant vector synthesis phase shifter, a continuous time linear equalizer and a current mode attenuator, and has the advantage of convenient deployment.

Description

Technical Field

[0001] This invention relates to the field of phased array design technology, and more specifically, to: 1. an impedance-invariant vector synthesizing phase shifter; 2. a conveniently deployable array element constructed using the vector synthesizing phase shifter; 3. a conveniently deployable phased array constructed using the array element. Background Technology

[0002] Phased array technology is a technique that controls the phase of each antenna element to achieve beam pointing, and it has great application prospects. Currently, the phased array industry faces the following problems:

[0003] I. As one of the most important components in a phased array, the phase shifter's phase shifting accuracy directly corresponds to the beam pointing accuracy of the phased array. Currently, vector synthesis phase shifters achieve the smallest phase shift step and the highest accuracy among various phase shifter types. However, their internal variable gain amplifier (VGA) has many factors affecting phase shifting accuracy: ① gain control linearity; ② parasitic capacitance imbalance caused by increasing bit size during different bit switching processes; ③ undesirable incidental phase errors introduced by amplitude modulation; ④ the IQ signals generated by the previous stage's quadrature signal generation network are not perfectly orthogonal. These factors can all lead to excessive root mean square phase error (RMS Phase Error) in the phase shifter, necessitating calibration. The calibration problem of vector synthesis phase shifters has long been a major pain point in the industry. Currently, the industry's conventional solution to this problem is "code selection"—that is, first testing to know all the amplitude and phase states of the phase shifter, and then "carefully selecting" the code value combination with good phase shifting state from these many states. The advantage of this solution is that it utilizes the application potential of codes in different states of the phase shifter, but its disadvantages are also obvious: First, the total number of code value combinations for a single phase shifter is extremely large—a common 6-bit phase shifter corresponds to at least 256 state combinations (if implemented using a 4-bit VGA), and considering the phase shift redundancy bits in the calibration design (adding 2 calibration bits on top of the 4-bit VGA, for a total of 6-bit VGA), this number is often 4096; Second, different phase shifters correspond to different mismatches, so if there are N phase shifters in the phased array, then N corresponding calibrations should be performed, which will result in a huge workload and severely limit the large-scale deployment of phased array technology.

[0004] II. Multi-beam phased arrays have attracted much attention because they can simultaneously meet the communication needs of multiple users. However, the increase in the number of phased array beams directly leads to an increase in the number of array elements required for the phased array, which will cause a proportional increase in chip area; and a larger area means higher cost, which will also affect its large-scale deployment.

[0005] Third, the existing array elements output power signals, which requires power matching of each channel to synthesize the power signals. However, this is a very complex task, and the difficulty of matching is directly proportional to the number of array elements. Summary of the Invention

[0006] Therefore, it is necessary to provide an impedance-invariant vector synthesis phase shifter, array element, and phased array to address the problems of the phase shifting accuracy of existing vector synthesis phase shifters being greatly affected by the internal VGA and the large amount of calibration work.

[0007] This invention is achieved using the following technical solution:

[0008] In a first aspect, the present invention provides an impedance-invariant vector synthesis phase shifter, comprising: one quadrature signal generator PPF and two identical variable gain amplifiers VGA1 to VGA2.

[0009] In each Gilbert cell of VGA1 and VGA2, two capacitive compensation branches are set up. The capacitive compensation branch includes a compensation capacitor and an NMOS transistor connected in parallel. One end is grounded and the other end is connected to the sub-stage phase shift signal of the corresponding bit through a switching transistor. When the bit is turned on, the switching transistor is turned off and the capacitive compensation branch is not connected to the circuit. When the bit is turned off, the switching transistor is turned on and the capacitive compensation branch is connected to the circuit to compensate for the real and imaginary parts of the impedance and keep the output impedance of the cell constant.

[0010] The implementation of this impedance-invariant vector synthesis phase shifter is based on the method or process of an embodiment of this disclosure.

[0011] Secondly, the present invention discloses a conveniently deployable array element, including: a low-noise transconductance amplifier (LNTA), a matching network (MN), a vector synthesis phase shifter (VMPS), a continuous-time linear equalizer (CTLE), a current-mode attenuator (CM-ATT), and three DC isolators.

[0012] LNTA is used for: processing radio frequency input differential signals RF IN + RF IN - Low-noise amplification is performed to obtain the differential amplified signal P1. + P1 - .

[0013] MN is used for: P1 based on Zs and Zl + P1 - Impedance matching is performed to obtain the differential matching signal P2. + P2 - Where Zs is the output source impedance of the LNTA and Zl is the input load impedance of the VMPS.

[0014] The first DC isolator is used to separate the DC input of the VMPS from the DC output of the LNTA.

[0015] VMPS is an impedance-invariant vector synthesizer phase shifter as disclosed in the first aspect, which is used to: perform multi-bit vector synthesis phase shifting on the output signal of the first DC isolator to obtain a differential phase-shifted signal I3. + I3 - The output signal of the first DC isolator serves as the input signal of the PPF.

[0016] The second DC isolator is used to separate the input DC of CLTE from the output DC of VMPS.

[0017] CLTE is used to: introduce corresponding zeros to compensate for the main poles of the circuit to achieve bandwidth enhancement, thereby obtaining the differential boosted signal I4, corresponding to high and low frequencies. + I4 - .

[0018] CM-ATT is used for: I4 + I4 - Shunt attenuation is performed to achieve swing amplitude control, thereby obtaining the differential amplitude modulation signal I5. + I5 - .

[0019] The third DC isolator is used to isolate the DC output from the VMPS, thus obtaining the RF output differential signal. OUT + RF OUT - .

[0020] The implementation of such array elements is based on the methods or processes of embodiments of this disclosure.

[0021] Thirdly, the present invention discloses a conveniently deployable phased array, comprising: a plurality of conveniently deployable array elements as disclosed in the second aspect, connected in parallel.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. This invention provides an impedance-invariant vector synthesis phase shifter, which sets two capacitive compensation branches in each Gilbert unit of a variable gain amplifier, and connects the capacitive compensation branches to the circuit only when the bit is off, ensuring that the unit output impedance remains unchanged when the bit is on and off, effectively improving the phase shifting accuracy of the phase shifter, reducing the root mean square phase error of the phase shifter to an acceptable range in the engineering field, realizing phase shifting directly according to the ideal situation based on IQ quadrature signals, avoiding tedious calibration work, and solving the calibration problem of vector synthesis phase shifters.

[0024] 2. The capacitive compensation branch of this invention includes a compensation capacitor and an NMOS transistor connected in parallel. One end is grounded, and the other end is connected to the sub-stage phase-shift signal of the corresponding bit through a switching transistor. The switching transistor is controlled according to the bit switching state to realize that the capacitive compensation branch is turned off when the bit is on to avoid interference and turned on when the bit is off to compensate for impedance. Furthermore, this invention supports further optimization of linearity by controlling the capacitance value of the compensation capacitor.

[0025] 3. This invention provides a conveniently deployable array element. On the one hand, it adopts an impedance-invariant vector synthesis phase shifter, which improves the phase shifting accuracy of the phase shifter. On the other hand, it utilizes the linear equalization function of a continuous-time linear equalizer to introduce corresponding zeros at high and low frequencies in the system to compensate for the main poles of the circuit, thereby achieving bandwidth enhancement. This replaces the power matching network composed of a large area of ​​inductors, reducing the area occupied. Furthermore, it converts the power signal into a current signal and performs signal amplitude modulation by shunting through a current-mode attenuator, avoiding multi-path power matching and power synthesis, and facilitating the scale expansion of the phased array.

[0026] 4. This invention provides a conveniently deployable phased array, which is constructed by connecting several conveniently deployable array elements in parallel, and has significant engineering application value and promotion prospects. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A circuit architecture diagram of a conveniently deployable array element provided in an embodiment of the present invention;

[0029] Figure 2 for Figure 1 Circuit architecture diagram of variable gain amplifiers VGA1~VGA2;

[0030] Figure 3 for Figure 2 The circuit structure diagram of the Gilbert cell corresponding to the nth bit in VGA1;

[0031] Figure 4 for Figure 2 The circuit structure diagram of the Gilbert cell corresponding to the nth bit in VGA2;

[0032] Figure 5 for Figure 1 Circuit diagram of the continuous-time linear equalizer (CTLE);

[0033] Figure 6 for Figure 1 Circuit diagram of the medium current mode attenuator CM-ATT. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0037] Example

[0038] See Figure 1 This diagram illustrates the architecture of a conveniently deployable array element provided in this embodiment, which includes: a low-noise transconductance amplifier (LNTA, which has an output source impedance Zs), a matching network (MN), a vector synthesis phase shifter (VMPS, which has an input load impedance Zl), a continuous-time linear equalizer (CTLE), a current-mode attenuator (CM-ATT), and three DC isolators.

[0039] From a functional perspective:

[0040] I. LNTA is used for: processing radio frequency input differential signals RF IN + RF IN - Low-noise amplification is performed to obtain the differential amplified signal P1. + P1 - .

[0041] Among them, RF IN + Indicates positive radio frequency input signal, RF IN - This indicates a negative radio frequency input signal; both are power signals. P1 + Indicates positive amplification signal, P1 - This indicates a negative amplified signal; both are power signals.

[0042] As Figure 1 As shown, the two inputs of the LNTA are connected to RF respectively. IN + RF IN - The two output terminals are used to output P1 respectively. + P1 - .

[0043] II. MN is used for: P1 based on Zs and Zl. + P1 - Impedance matching is performed to obtain the differential matching signal P2. + P2 - .

[0044] Among them, P2 + Indicates positive matching signal, P2 - This indicates a negative matched signal; both are power signals.

[0045] As Figure 1 As shown, MN actually achieves impedance matching from LNTA to VMPS through a series inductor and a parallel capacitor.

[0046] Specifically, MN includes: two inductors L1~L2 and two capacitors C1~C2. One end of L1 is connected to P1. + The other end is connected to the upper plate of C1 and used for output P2. + One end of L2 is connected to P1. - The other end is connected to the upper plate of C2 and used for output P2. - The lower plates of C1 and C2 are grounded.

[0047] 3. The first DC isolator is used to: separate the DC input of the VMPS from the DC output of the LNTA.

[0048] As Figure 1 As shown, the first DC isolator can be designed using capacitors, including two capacitors C3 and C4. The upper plate of C3 is connected to P2. + The lower plate serves as the output terminal of the first DC isolator; the upper plate of C4 is connected to P2. - The lower electrode plate serves as the output terminal of the first DC isolator.

[0049] IV. VMPS is used to: perform multi-bit vector synthesis and phase shifting on the output signal of the first DC isolator to obtain the differential phase-shifted signal I3. + I3 - .

[0050] Among them, I3 + Indicates the total positive phase shift signal, I3 - This indicates a total negative phase-shift signal; both are current signals.

[0051] As Figure 1 As shown, VMPS is actually a vector synthesis phase shifter based on active frequency response shaping. It performs multi-bit vector synthesis phase shifting through the cooperation of a first-stage quadrature signal generator (PPF) and two parallel-connected variable gain amplifiers (VGA).

[0052] Specifically, VMPS includes: one quadrature signal generator PPF and two variable gain amplifiers VGA1~VGA2.

[0053] 401, PPF is used to: generate an IQ quadrature signal VI based on its input signal. + VI - VQ + VQ - Among them, VI + Indicates a positive signal in the I-channel; VI - Indicates a negative signal in the I channel; VQ + VQ represents the positive signal of the Q channel; - This indicates a negative signal in the Q channel.

[0054] See Figure 1 The input signal to the PPF is still a differential signal—that is, the output signal of the first DC isolator. Specifically, the two input terminals of the PPF are connected one-to-one to the two output terminals of the first DC isolator, and the four output terminals output VI respectively. + VI - VQ + VQ - .

[0055] In other words, VI + VI - The phase difference is 180°; VQ + VQ - The phase difference is 180°; VI + VQ + The phase difference is 90°; VI - VQ - The phase difference is 90°.

[0056] It should be noted that the IQ quadrature signal generated by the PPF may still exhibit IQ mismatch (i.e., the issue described in ④ in the background section), affecting the root mean square phase error of the phase shifter. However, the design improvements to VGA1~VGA2 in the following sections address ①, ②, and ③ in the background section, reducing the root mean square phase error of the phase shifter to an acceptable range in engineering practice (less than or equal to half the phase shift step). This avoids tedious calibration work and allows for direct phase shifting based on the most ideal conditions.

[0057] 402, see Figure 2 VGA1 is used to: provide an impedance that remains constant as the bit switches, to achieve VI-based... + VI - I phase-shifted signals are obtained by directly performing phase shifting according to the most ideal situation. out + I out - ;

[0058] Among them, I out + Indicates the I-channel positive phase shift signal; I out - This indicates the negative phase-shifting signal of channel I.

[0059] VGA2 is used to: provide an impedance that remains constant as the bits switch, to achieve VQ-based... + VQ - The Q-channel phase-shifted signal Q is obtained by directly performing phase shifting according to the most ideal situation. out + Q out - ;

[0060] Among them, Q out + Indicates the positive phase-shifting signal of the Q-channel; Q out - This indicates the Q-channel negative phase-shift signal.

[0061] It is important to note that I out + Q out + The superposition forms the total positive phase shift signal I3 + ;I out - Q out - The superposition forms the total negative phase-shifted signal I3 - .

[0062] In general, VGA1 and VGA2 have the same circuit structure, with the only difference being their input and output.

[0063] It should be noted that, as Figure 2 As shown, VGA1~VGA2 follow the conventional architecture of multi-bit vector synthesis phase shifters, which are designed according to the required number of phase shifts N, and improve the structure of the Gilbert cell.

[0064] I. Taking VGA1 as an example, it includes: N bits of Gilbert units connected in parallel.

[0065] It should be noted that the number of parallel connections of the Gilbert unit corresponding to the nth bit is 2. n-1 ; n∈[1,N]. That is to say, if VGA1 is considered a hierarchical design, then it includes N parallel layers, with the nth layer corresponding to the nth bit, including 2... n-1 A parallel Gilbert unit.

[0066] For easier understanding, please refer to Figure 2 Unit 1,1 This means that the number of Gilbert cells corresponding to the first bit in VGA1 is only set to 1; as the level increases, the number of bits also increases accordingly, and the number of Gilbert cells connected in parallel also increases accordingly.

[0067] In VGA1: For the Gilbert cell corresponding to the nth bit, it is based on the control signal group ICTRL. n VI + VI - Perform the nth phase shift to obtain the corresponding bit's sub-stage phase shift signal I. out,n + I out,n - So, I out,1 + ~I out,N + Superposition to form I out + ;I out,1 - ~I out,N - Superposition to form I out - .

[0068] Among them, ICTRL n Includes: 3 control signals CTRL_I n S_I n + S_I n - .

[0069] See Figure 3It demonstrates the specific circuit design of the Gilbert cell corresponding to the nth bit in VGA1—including: 2 PMOS transistors UM1~UM2 and 10 NMOS transistors UM3~UM4. 12 Two compensation capacitors, Cc1 and Cc2.

[0070] Specifically, in the Gilbert cell corresponding to the nth bit in VGA1:

[0071] The sources of UM1 and UM2 are connected to the power supply VDD; the gates of UM1 and UM2 are connected to the bias voltage V. BP The drain of UM1 is connected to the drains of UM3, UM4, and UM6 to output I. out,n + The drain of UM2 is connected to the drains of UM5, UM7, and UM8 to output I. out,n - The gate of UM3 is connected to CTRL_I. n The source is connected to the drain of UM9 and the upper plate of Cc1; the gate of UM4 is connected to S_I. n + The source is connected to the source of UM5 and the drain of UM9; the gates of UM5 and UM6 are connected to S_I. n - ; The gate of UM7 is connected to S_I n + The source is connected to the source of UM6, UM 11 The drain of UM8; the gate of UM8 is connected to CTRL_I. n UM source connection 12 The drain of Cc2, the upper plate of Cc2; UM9, UM 12 Gate connection bias voltage V BN ; UM9 source, Cc1 lower electrode, UM 10 The source pole, UM 11 The source pole, UM 12 The source electrode and the lower electrode of Cc2 are both connected to ground.

[0072] It should be noted that:

[0073] UM1, UM2, UM9, UM 12 Operating in the saturation region; UM3~UM8 operate in the linear region; UM3 and UM8 act as switching transistors; Cc1 and UM9 form the first capacitive compensation branch that is activated when the bit is turned off (i.e., the two are connected in parallel, one end is grounded, and the other end is connected to I through UM3). out,n + ), Cc2, UM 12 This forms a second capacitive compensation branch that is activated when the bit is turned off (i.e., the two are connected in parallel, with one end grounded and the other end connected to I via UM8).out,n - ).

[0074] For the Gilbert cell corresponding to the nth bit in VGA1, the following control logic was designed:

[0075] ①. When S_I n + S_I n - CTRL_I n When all values ​​are 0, UM3~UM8 are all turned off, the Gilbert cell is closed and its state is useless.

[0076] ②. When S_I n + S_I n - All are 0, CTRL_I n When the value is 1, UM4~UM7 are all off, UM3 and UM8 are on, and the two capacitive compensation branches are connected to the circuit, compensating for the real and imaginary parts of the impedance. It is important to note that this is a bit-off condition, VI. + VI - with I out,n + I out,n - Separated, I out,n + Grounding via UM3 and the first capacitive compensation branch results in no output, I out,n - Grounding via UM8 and the second capacitive compensation branch results in no output.

[0077] ③. When S_I n + =0, S_I n - 1, CTRL_I n When the value is 0, the Gilbert cell is inverted and turned on (UM5 and UM6 are on, UM4 and UM7 are off), UM3 and UM8 are off, and the two capacitive compensation branches are not connected to the circuit. It should be noted that this situation is called bit inversion turn-on, VI + VI - Corresponding control UM 10 UM 11 Switch to make output I out,n + I out,n - The phase difference is +180°.

[0078] It is important to note that when S_I n + =0, S_In - 1, CTRL_I n When the value is 1, the Gilbert cell will also be turned on in reverse, but this state is useless.

[0079] ④. When S_I n + 1, S_I n - 0, CTRL_I n When the value is 0, the Gilbert cells are in-phase enabled (UM4 and UM7 are on, UM5 and UM6 are off), UM3 and UM8 are off, and the two capacitive compensation branches are not connected to the circuit. It should be noted that this situation also constitutes in-phase bit enable, VI + VI - Corresponding control UM 10 UM 11 Switch to make output I out,n + I out,n - The phase difference is -180°.

[0080] It is important to note that when S_I n + 1, S_I n - 0, CTRL_I n When the value is 1, the Gilbert cell will also be turned on in phase, but this state is useless.

[0081] ⑤. When S_I n + 1, S_I n - When it is 1, regardless of CTRL_I n Whether it is 1 or 0, I will be turned on because UM4~UM7 are all conducting. out,n + I out,n - Direct connection results in no output, meaning the state is useless.

[0082] In summary, each Gilbert cell in VGA1 has two capacitive compensation branches. These branches consist of a parallel compensation capacitor and an NMOS transistor, with one end grounded and the other connected to the corresponding bit's sub-phase shift signal via a switching transistor. When the bit is on, UM3 and UM8 are off, and the capacitive compensation branch is not connected to the circuit to avoid interference, resulting in a normal Gilbert cell. When the bit is off, UM3 and UM8 switch to conduct, and the capacitive compensation branch is connected to the circuit to compensate for the real and imaginary parts of the impedance, thus keeping the cell's output impedance constant.

[0083] In other words, the capacitive compensation branch is only connected to the circuit when the bit is off, ensuring that the unit's output impedance remains constant when the bit is on and off, thus solving problems ①, ②, and ③ mentioned in the background technology. This is because: when the transistor is on, the impedance seen from its drain can be mainly equivalent to the on-resistance; when the transistor is off, the impedance seen from its drain can be equivalent to the drain-source parasitic capacitance, i.e., the off-resistance capacitance. That is to say, the impedance seen from the output terminal is different when the transistor is on and off, so the change in the number of transistors on and off will also cause impedance fluctuations, thus degrading the linearity of the Gilbert cell; however, the introduced capacitive compensation branch can be turned off when the bit is on to avoid interference and turned on when the bit is off to compensate for impedance, and can also optimize linearity by further finely adjusting the capacitance values ​​of Cc1~Cc2.

[0084] II. Similar to VGA1, VGA2 includes: N-bit Gilbert cells connected in parallel; wherein the number of parallel Gilbert cells corresponding to the nth bit is 2. n-1 ;n∈[1,N].

[0085] For easier understanding, please refer to Figure 2 Unit 2,1 This means that the number of Gilbert cells corresponding to the first bit in VGA2 is only set to 1; as the level increases, the number of bits also increases accordingly, and the number of parallel Gilbert cells also increases accordingly.

[0086] Similar to VGA1, in VGA2: for the Gilbert cell corresponding to the nth bit, it is based on the control signal group QCTRL. n VQ + VQ - Perform the nth phase shift to obtain the bit sub-level phase shift signal Q. out,n + Q out,n - ; n∈[1,N]. Then, Q out,1 + ~Q out,N + Superposition to form Q out + Q out,1 - ~Q out,N - Superposition to form Q out - .

[0087] Among them, QCTRL n Includes: 3 control signals CTRL_Q n S_Q n +S_Q n - .

[0088] So, see Figure 4 The Gilbert cell corresponding to the nth bit in VGA2 has the same structure as the Gilbert cell corresponding to the nth bit in VGA1, and also includes: 2 NMOS transistors UM1~UM2 and 10 PMOS transistors UM3~UM4. 12 Two compensation capacitors, Cc1 and Cc2. The difference lies in: VI in the circuit... + Switch to VQ + VI - Switch to VQ - CTRL_I n Change to CTRL_Q n S_I n + Replace with S_Q n + S_I n - Replace with S_Q n - I out,n + Change to Q out,n + I out,n - Change to Q out,n - The control logic is also inherited from the Gilbert unit corresponding to the nth bit in VGA1.

[0089] Then, in the Gilbert cell corresponding to the nth bit in VGA2:

[0090] The sources of UM1 and UM2 are connected to the power supply VDD; the gates of UM1 and UM2 are connected to the bias voltage V. BP The drain of UM1 is connected to the drains of UM3, UM4, and UM6 to output Q. out,n + The drain of UM2 is connected to the drains of UM5, UM7, and UM8 to output Q. out,n - The gate of UM3 is connected to CTRL_Q. n The source is connected to the drain of UM9 and the upper plate of Cc1; the gate of UM4 is connected to S_Q. n + The source is connected to the source of UM5 and the drain of UM9; the gates of UM5 and UM6 are connected to S_Q. n - The gate of UM7 is connected to S_Q. n +The source is connected to the source of UM6, UM 11 The drain of UM8; the gate of UM8 is connected to CTRL_Q. n UM source connection 12 The drain of Cc2, the upper plate of Cc2; UM9, UM 12 Gate connection bias voltage V BN ; UM9 source, Cc1 lower electrode, UM 10 The source pole, UM 11 The source pole, UM 12 The source electrode and the lower electrode of Cc2 are both connected to ground;

[0091] Similarly, UM1, UM2, UM9, UM 12 Operating in the saturation region; UM3~UM8 operate in the linear region; UM3 and UM8 act as switches; Cc1 and UM9 form the first capacitive compensation branch that is activated when the bit is turned off; Cc2 and UM 12 This forms the second capacitive compensation branch that is activated when the bit is turned off.

[0092] Similarly, for the Gilbert cell corresponding to the nth bit in VGA2, the following control logic was designed:

[0093] ① When S_Q n + S_Q n - CTRL_Q n When all values ​​are 0, UM3~UM8 are all turned off, the Gilbert cell is closed and its state is useless.

[0094] ② When S_Q n + S_Q n - All are 0, CTRL_Q n When the value is 1, UM4~UM7 are all off, UM3 and UM8 are on, and the two capacitive compensation branches are connected to the circuit, compensating for the real and imaginary parts of the impedance. It is important to note that this is a bit-off condition, VQ + VQ - With Q out,n + Q out,n - Separated, Q out,n + Grounding via UM3 and the first capacitive compensation branch results in no output, Q out,n - Grounding via UM8 and the second capacitive compensation branch results in no output.

[0095] ③ When S_Q n+ =0, S_Q n - 1, CTRL_Q n When the value is 0, the Gilbert cell is inverted and turned on (UM5 and UM6 are on, UM4 and UM7 are off), UM3 and UM8 are off, and the two capacitive compensation branches are not connected to the circuit. It is important to note that this situation is known as bit inversion activation, VQ + VQ - Corresponding control UM 10 UM 11 Switch to make output Q out,n + Q out,n - The phase difference is +180°.

[0096] It is important to note that when S_Q n + =0, S_Q n - 1, CTRL_Q n When the value is 1, the Gilbert cell will also be turned on in reverse, but this state is useless.

[0097] ④ When S_Q n + 1, S_Q n - 0, CTRL_Q n When the value is 0, the Gilbert cells are in-phase enabled (UM4 and UM7 are on, UM5 and UM6 are off), UM3 and UM8 are off, and the two capacitive compensation branches are not connected to the circuit. It should be noted that this situation also results in in-phase bit enable, VQ + VQ - Corresponding control UM 10 UM 11 Switch to make output Q out,n + Q out,n - The phase difference is -180°.

[0098] It is important to note that when S_Q n + 1, S_Q n - 0, CTRL_Q n When the value is 1, the Gilbert cell will also be turned on in phase, but this state is useless.

[0099] ⑤ When S_Q n + 1, S_Q n - When it is 1, regardless of CTRL_Qn A value of 1 or 0 will cause Q to be active because UM4~UM7 are all conducting. out,n + Q out,n - Direct connection results in no output, meaning the state is useless.

[0100] In other words, VGA2 has the same design as VGA1, so it can also ensure that the unit output impedance remains unchanged when the bit is on and off.

[0101] In summary, VGA1~VGA2 effectively improve the phase shifting accuracy of the phase shifters by ensuring that the output impedance remains constant when the bits are on and off. Therefore, the code selection for the phase shifters can be directly performed according to the ideal situation (which can be obtained immediately by simple mathematical calculations), without having to measure all the states of each phase shifter individually and then "carefully select" them "personally," avoiding tedious calibration work and solving the calibration problem of vector synthesis phase shifters.

[0102] In this embodiment, N is recommended to be 6, which enables 7-bit bit vector synthesis phase shifting of the output signal of the first DC isolator within the range of 0~360°. It should be noted that N of 6 refers to the number of bits of VGA1~VGA2, while 7 bits refers to the number of bits of VMPS: VGA1 and VGA2 each support 6-bit 64-state amplitude modulation, together forming a 64*64 dot matrix (4096 dots) in the first quadrant of the IQ plane, and a 128*128 dot matrix (16384 dots) in the entire IQ plane. Then, by selecting 128 dots arranged on the circumference from these 16384 dots, 7-bit phase shifting can be functionally achieved.

[0103] 5. The second DC isolator is used to separate the DC input of CLTE from the DC output of VMPS.

[0104] As Figure 1 As shown, the second DC isolator can also be designed using capacitors, including two capacitors C5 and C6. The upper plate of C5 is connected to I3. + The lower plate serves as the output terminal of the second DC isolator; the upper plate of C6 is connected to I3. - The lower electrode plate serves as the output terminal of the second DC isolator.

[0105] VI. CLTE is used to: introduce corresponding zeros to compensate the main poles of the circuit for high and low frequencies to achieve bandwidth enhancement, resulting in a differential boosted signal I4. + I4 - .

[0106] See Figure 5CLTE can be designed to include: 6 resistors CR1~CR6 and 12 inverters INV1~INV 12 Four additional capacitors YC1~YC4.

[0107] INV1~INV4 are connected in series; one end of CR1 is connected to the input terminal of INV1 and the first output terminal of the second DC isolator, and the other end is connected to the output terminal of INV1; INV5~INV8 are connected in series; one end of CR2 is connected to the input terminal of INV5 and the second output terminal of the second DC isolator, and the other end is connected to the output terminal of INV5; one end of CR3 is connected to the output terminal of INV2, the input terminal of INV9, and the upper plate of YC2, and the other end is connected to the output terminal of INV9 and the upper plate of YC1; one end of CR4 is connected to INV... 11 The input terminal of YC1, the lower plate of YC1, the output terminal of INV6, and the other end is connected to INV. 11 The output terminal of YC2 and the lower electrode plate of YC2; one end of CR5 is connected to the output terminal of INV3 and INV. 10 The input terminal is connected to the upper plate of YC4, and the other end is connected to INV. 10 The output terminal of YC3 and the upper plate of YC3; one end of CR6 is connected to INV. 12 The input terminal of YC3, the lower electrode of YC3, the output terminal of INV7, and the other end is connected to INV. 12 The output terminal of YC4 and the lower electrode of YC4; the output terminal of INV4 is used to output I4. + The output of INV8 is used to output I4. - .

[0108] In other words, INV9, INV 11 CR3, CR4, YC1, and YC2 constitute a continuous-time linear equalizer to introduce a zero at high frequencies (the position of this zero is adjusted by controlling the values ​​of CR3, CR4, YC1, and YC2: the larger the value, the closer the zero is to the origin, and the earlier the bandwidth is raised in the frequency domain; conversely, the bandwidth is raised later in the frequency domain); INV 10 INV 12 CR5, CR6, YC3, and YC4 constitute another continuous-time linear equalizer (similarly, the zero position is adjusted by controlling the values ​​of CR5, CR6, YC3, and YC4: the larger the value, the closer the zero is to the origin, and the bandwidth will be raised earlier in the frequency domain; conversely, the bandwidth will be raised later in the frequency domain) to introduce a zero at low frequencies; this can compensate for the circuit's dominant pole, resulting in a significant improvement in the circuit's operating bandwidth on a macroscopic scale.

[0109] Moreover, since CTLE is an active circuit with a very small footprint, the array element area is reduced by about 50%, which doubles the number of array elements that can be accommodated in the same area. This allows for the realization of higher precision and more numerous beams on a single chip without additional cost.

[0110] In this embodiment, CLTE is recommended to be configured to increase the 3dB bandwidth of the system transmission function H(s) to meet the operating requirements of the C-band (3~5GHz).

[0111] VII. CM-ATT is used for: I4 + I4 - Shunt attenuation is performed to achieve swing amplitude control, thereby obtaining the differential amplitude modulation signal I5. + I5 - .

[0112] CLTE can be equivalently represented as a current source, with an output I4. + I4 - It refers to current, not power. Therefore, CM-ATT is able to target I4. + I4 - Amplitude modulation of the signal is achieved by splitting the current.

[0113] See Figure 6 The CM-ATT can be designed to include 14 NMOS transistors M1~M2. 14 14 resistors R1~R 14 8 capacitors TC1~TC8.

[0114] M1 gate connection control code D <0> Drain connection I4 + The source electrode is connected to the upper plate of TC1 and one end of R1; the lower plate of TC1 and the other end of R1 are connected to I4. - ;

[0115] M2 gate connection control code D <1> Drain connection I4 + The source electrode is connected to the upper plate of TC2 and one end of R2; the lower plate of TC2 and the other end of R2 are connected to I4. - ;

[0116] Gate connection control code D for M3 and M4 <2> M3's drain is connected to I4. + The source electrode is connected to the upper plate of TC3 and one end of R4; the lower plate of TC3 is connected to the other end of R4 and M. 12 The drain of M4 is connected to I4. - The source is connected to the upper plate of TC4 and one end of R5; the lower plate of TC4 is connected to the other end of R5 and the drain of M9.

[0117] M9, M 12Gate connection control code D* <2> The source of M9 is connected to the drain of M3 and one end of R3, and the drain is connected to the other end of R3; M 12 The source is connected to the drain of M4 and one end of R6, and the drain is connected to the other end of R6;

[0118] Gate connection control code D for M5 and M6 <3> The drain of M5 is connected to the drain of M9, and the source is connected to the upper plate of TC5 and one end of R8; the lower plate of TC5 is connected to the other end of R8, M... 13 The drain of M6; the drain of M6 is connected to M 12 The drain and source of TC6 are connected to the upper plate of TC6 and one end of R9; the lower plate of TC6 is connected to the other end of R9 and M. 10 The drain electrode;

[0119] M 10 M 13 Gate connection control code D* <3> M 10 The source of M5 is connected to the drain of M5 and one end of R7, and the drain is connected to the other end of R7; M 13 The source is connected to the drain of M6, R 10 One end, the drain is connected to R 10 The other end;

[0120] Gate connection control code D for M7 and M8 <4> The drain of M7 is connected to M. 10 The drain and source are connected to the upper plate of TC7 and R. 12 One end; the lower electrode of TC7 is connected to R. 12 The other end, M 14 The drain is used to output I5. - M8's drain connection M 13 The drain and source are connected to the upper plate of TC8 and R. 13 One end; the lower electrode of TC8 is connected to R. 13 The other end, M 11 The drain is used to output I5. + ;

[0121] M 11 M 14 Gate connection control code D* <4> M 11 The source is connected to the drain of M7, R 11 One end, the drain is connected to R 11 The other end; M 14 The source is connected to the drain of M8, R 14 One end, the drain is connected to R 14 The other end.

[0122] It should be noted that D <2> D* <2> For the opposite signal; D <3> D* <3> For the opposite signal; D <4> D* <4> This is the opposite signal.

[0123] When CM-ATT has no attenuation, D <0> ~D <4> Both values ​​should be 0 to turn off the corresponding MOSFET, D* <2> ~D* <4> If both are set to 1 to turn on the corresponding MOSFET, the current flowing from the CM-ATT input will not pass through any other branch and will flow directly to the output without current attenuation; if D is set to 1... <0> Set to 1, D <1> ~D <4> If the value is still 0, then M1 is turned on. The current flowing into the CM-ATT input terminal will pass through a current branch passing through M1 in addition to the branch at the output terminal. That is, a portion of the current is "diverted" by this branch, so the current flowing out of the output terminal will show a corresponding current attenuation. And so on, if D <0> ~D <4> Setting more values ​​to 1 will create more shunt branches, resulting in greater current attenuation. Specifically, D... <0> D <1> Used for fine-tuning bits; D <2> D <3> D <4> Used for coarse adjustment bit; from D <0> To D <4> It is a binary relation.

[0124] It should be noted that the output interconnection of multiple array elements can be directly achieved through current lines, eliminating the complex multi-path power matching problem and further facilitating the scalability expansion of phased arrays.

[0125] 8. The third DC isolator is used to: isolate the DC output of the VMPS to obtain the RF output differential signal. OUT + RF OUT - .

[0126] As Figure 1 As shown, the third DC isolator can also be designed using capacitors, including two capacitors C7 and C8. The upper plate of C7 is connected to I5. + The lower electrode is used for RF output. OUT + The upper plate of C8 is connected to I5. - The lower electrode is used for RF output. OUT - .

[0127] Based on the array elements designed above, selecting several of these array elements and connecting them in parallel will construct a phased array, which has the following advantages:

[0128] 1. This invention supports simultaneous communication by multiple users and achieves precise beam control through the vector synthesis phase shifter provided above, which can improve the communication capacity and service flexibility of satellites.

[0129] 2. This invention provides reliable signal amplitude and phase control capabilities, making array beamforming more stable and significantly improving signal quality, thus meeting the needs of radar detection and broadband wireless transmission.

[0130] 3. The present invention combines the design of a continuous-time linear equalizer and a current-mode attenuator, which greatly reduces the area of ​​a single array element, allowing more array elements to be arranged within a limited chip area, thereby supporting the generation of more beams and higher resolution beam scanning capabilities.

[0131] 4. This invention utilizes the synthesis characteristics of current-mode output signals and employs a continuous-time linear equalizer, which eliminates the need for complex power matching processing for signal interconnection between multiple array elements. This greatly simplifies the system design of large-scale arrays and reduces the difficulty and cost of system deployment.

[0132] In summary, this invention is applicable not only to high-performance satellite communication phased arrays, but also to various scenarios with strict requirements for beam pointing accuracy, large-scale array deployment capabilities, and high-bandwidth communication performance, such as ground-based high-density phased arrays, broadband radar systems, and future large-scale MIMO communication platforms. It has significant engineering application value and promising prospects for promotion.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An impedance-invariant vector synthesis phase shifter, comprising: One quadrature signal generator (PPF) and two identical variable gain amplifiers (VGA1~VGA2) are characterized by: PPF is used to: generate an IQ quadrature signal VI based on its input signal. + VI - VQ + VQ - ; In each Gilbert cell of VGA1 and VGA2, two capacitive compensation branches are set up. The capacitive compensation branch includes a compensation capacitor and an NMOS transistor connected in parallel. One end is grounded and the other end is connected to the sub-stage phase shift signal of the corresponding bit through a switching transistor. When the bit is turned on, the switching transistor is turned off and the capacitive compensation branch is not connected to the circuit. When the bit is turned off, the switching transistor is turned on and the capacitive compensation branch is connected to the circuit to compensate for the real and imaginary parts of the impedance and keep the output impedance of the cell constant. VGA1 is used to: provide an impedance that remains constant as the bit switches, to achieve VI-based... + VI - I phase-shifted signals are obtained by directly performing phase shifting according to the most ideal situation. out + I out - ; VGA1 includes: N-bit Gilbert cells connected in parallel; wherein the number of parallel Gilbert cells corresponding to the nth bit is 2. n-1 n∈[1,N]; In VGA1: The Gilbert cell corresponding to the nth bit is based on the control signal group ICTRL n VI + VI - Perform the nth phase shift to obtain the nth bit sub-stage phase shift signal I. out,n + I out,n - ;I out,1 + ~I out,N + Superposition to form I out + ;I out,1 - ~I out,N - Superposition to form I out - ;ICTRL n Includes: 3 control signals CTRL_I n S_I n + S_I n - The Gilbert cell corresponding to the nth bit includes: 2 PMOS transistors UM1~UM2 and 10 NMOS transistors UM3~UM4. 12 Two compensation capacitors Cc1 and Cc2; the sources of UM1 and UM2 are connected to the power supply VDD; the gates of UM1 and UM2 are connected to the bias voltage V. BP The drain of UM1 is connected to the drains of UM3, UM4, and UM6 to output I. out,n + The drain of UM2 is connected to the drains of UM5, UM7, and UM8 to output I. out,n - The gate of UM3 is connected to CTRL_I. n The source is connected to the drain of UM9 and the upper plate of Cc1; the gate of UM4 is connected to S_I. n + The source is connected to the source of UM5, UM 10 The drain of UM5 and UM6; the gates of UM5 and UM6 are connected to S_I. n - ; The gate of UM7 is connected to S_I n + The source is connected to the source of UM6, UM 11 The drain of UM8; the gate of UM8 is connected to CTRL_I. n UM source connection 12 The drain of Cc2, the upper plate of Cc2; UM9, UM 12 Gate connection bias voltage V BN ; UM9 source, Cc1 lower electrode, UM 10 The source pole, UM 11 The source pole, UM 12 The source electrode and the lower electrode of Cc2 are both connected to ground; Among them, UM1, UM2, UM9, UM 12 Operating in the saturation region; UM3~UM8 operate in the linear region; UM3 and UM8 act as switches; Cc1 and UM9 form the first capacitive compensation branch that is activated when the bit is turned off; Cc2 and UM 12 This forms a second capacitive compensation branch that is activated when the bit is turned off; When S_I n + S_I n - All are 0, CTRL_I n When the value is 1, the bit is off, UM3 and UM8 are on, and the two capacitive compensation branches are connected to the circuit. When S_I n + =0, S_I n - 1, CTRL_I n When the value is 0, the bit is inverted and turned on, UM3 and UM8 are turned off, and the two capacitive compensation branches are not connected to the circuit. When S_I n + 1, S_I n - 0, CTRL_I n When the value is 0, the bits are in phase and turned on, UM3 and UM8 are turned off, and the two capacitive compensation branches are not connected to the circuit.

2. The impedance-invariant vector synthesis phase shifter according to claim 1, characterized in that, The input signal of the PPF is a differential signal; VI + VI - The phase difference is 180°; VQ + VQ - The phase difference is 180°; VI + VQ + The phase difference is 90°; VI - VQ - The phase difference is 90°.

3. The impedance-invariant vector synthesis phase shifter according to claim 1, characterized in that, VGA2 is used to: provide an impedance that remains constant as the bits switch, to achieve VQ-based... + VQ - The Q-channel phase-shifted signal Q is obtained by directly performing phase shifting according to the most ideal situation. out + Q out - ; VGA2 consists of N-bit Gilbert cells connected in parallel; wherein the number of parallel Gilbert cells corresponding to the nth bit is 2. n-1 n∈[1,N]; In VGA2: The Gilbert cell corresponding to the nth bit is based on the control signal group QCTRL n VQ + VQ - Perform the nth phase shift to obtain the bit sub-level phase shift signal Q. out,n + Q out,n - Q out,1 + ~Q out,N + Superposition to form Q out + Q out,1 - ~Q out,N - Superposition to form Q out - ;QCTRL n Includes: 3 control signals CTRL_Q n S_Q n + S_Q n - The Gilbert cell corresponding to the nth bit includes: 2 NMOS transistors UM1~UM2 and 10 PMOS transistors UM3~UM4. 12 Two compensation capacitors Cc1 and Cc2; the sources of UM1 and UM2 are connected to the power supply VDD; the gates of UM1 and UM2 are connected to the bias voltage V. BP The drain of UM1 is connected to the drains of UM3, UM4, and UM6 to output Q. out,n + The drain of UM2 is connected to the drains of UM5, UM7, and UM8 to output Q. out,n - The gate of UM3 is connected to CTRL_Q. n The source is connected to the drain of UM9 and the upper plate of Cc1; the gate of UM4 is connected to S_Q. n + The source is connected to the source of UM5 and the drain of UM9; the gates of UM5 and UM6 are connected to S_Q. n - The gate of UM7 is connected to S_Q. n + The source is connected to the source of UM6, UM 11 The drain of UM8; the gate of UM8 is connected to CTRL_Q. n UM source connection 12 The drain of Cc2, the upper plate of Cc2; UM9, UM 12 Gate connection bias voltage V BN ; UM9 source, Cc1 lower electrode, UM 10 The source pole, UM 11 The source pole, UM 12 The source electrode and the lower electrode of Cc2 are both connected to ground; Among them, UM1, UM2, UM9, UM 12 Operating in the saturation region; UM3~UM8 operate in the linear region; UM3 and UM8 act as switches; Cc1 and UM9 form the first capacitive compensation branch that is activated when the bit is turned off; Cc2 and UM 12 This forms the second capacitive compensation branch that is activated when the bit is turned off.

4. The impedance-invariant vector synthesis phase shifter according to claim 3, characterized in that, When S_Q n + S_Q n - All are 0, CTRL_Q n When the value is 1, the bit is off, UM3 and UM8 are on, and the two capacitive compensation branches are connected to the circuit. When S_Q n + =0, S_Q n - 1, CTRL_Q n When the value is 0, the bit is inverted and turned on, UM3 and UM8 are turned off, and the two capacitive compensation branches are not connected to the circuit. When S_Q n + 1, S_Q n - 0, CTRL_Q n When the value is 0, the bits are in phase and turned on, UM3 and UM8 are turned off, and the two capacitive compensation branches are not connected to the circuit.

5. A conveniently deployable array element, characterized in that, include: Low-noise transconductance amplifier (LNTA), matching network (MN), vector synthesis phase shifter (VMPS), continuous-time linear equalizer (CTLE), current-mode attenuator (CM-ATT), and three DC isolators. LNTA is used for: processing radio frequency input differential signals RF IN + RF IN - Low-noise amplification is performed to obtain the differential amplified signal P1. + P1 - ; MN is used for: P1 based on Zs and Zl + P1 - Impedance matching is performed to obtain the differential matching signal P2. + P2 - Where Zs is the output source impedance of the LNTA; Zl is the input load impedance of the VMPS. The first DC isolator is used to: separate the DC input of the VMPS from the DC output of the LNTA; VMPS is an impedance-invariant vector synthesis phase shifter as described in any one of claims 1-4, used to: perform multi-bit vector synthesis phase shifting on the output signal of the first DC isolator to obtain a differential phase-shifted signal I3. + I3 - The output signal of the first DC isolator serves as the input signal of the PPF. The second DC isolator is used to separate the input DC of CLTE from the output DC of VMPS; CLTE is used to: introduce corresponding zeros to compensate for the main poles of the circuit to achieve bandwidth enhancement, thereby obtaining the differential boosted signal I4, corresponding to high and low frequencies. + I4 - ; CM-ATT is used for: I4 + I4 - Shunt attenuation is performed to achieve swing amplitude control, thereby obtaining the differential amplitude modulation signal I5. + I5 - ; The third DC isolator is used to isolate the DC output from the VMPS, thus obtaining the RF output differential signal. OUT + RF OUT - .

6. The conveniently deployable array element according to claim 5, characterized in that MN Includes: 2 inductors L1~L2, 2 capacitors C1~C2; one end of L1 is connected to P1. + The other end is connected to the upper plate of C1 and used for output P2. + One end of L2 is connected to P1. - The other end is connected to the upper plate of C2 and used for output P2. - The lower plates of C1 and C2 are grounded; Or / and, CLTE includes: 6 resistors CR1~CR6, 12 inverters INV1~INV 12 Four additional capacitors YC1~YC4; INV1~INV4 are connected in series; one end of CR1 is connected to the input terminal of INV1 and the first output terminal of the second DC isolator, and the other end is connected to the output terminal of INV1; INV5~INV8 are connected in series; one end of CR2 is connected to the input terminal of INV5 and the second output terminal of the second DC isolator, and the other end is connected to the output terminal of INV5; one end of CR3 is connected to the output terminal of INV2, the input terminal of INV9, and the upper plate of YC2, and the other end is connected to the output terminal of INV9 and the upper plate of YC1; one end of CR4 is connected to INV1... 11 The input terminal of YC1, the lower plate of YC1, the output terminal of INV6, and the other end is connected to INV. 11 The output terminal of YC2 and the lower electrode plate of YC2; one end of CR5 is connected to the output terminal of INV3 and INV. 10 The input terminal is connected to the upper plate of YC4, and the other end is connected to INV. 10 The output terminal of YC3 and the upper plate of YC3; one end of CR6 is connected to INV. 12 The input terminal of YC3, the lower electrode of YC3, the output terminal of INV7, and the other end is connected to INV. 12 The output terminal of YC4 and the lower electrode of YC4; the output terminal of INV4 is used to output I4. + The output of INV8 is used to output I4. - Among them, INV9 and INV 11 CR3, CR4, YC1, and YC2 constitute a continuous-time linear equalizer to introduce a zero at high frequencies; INV 10 INV 12 CR5, CR6, YC3, and YC4 form another continuous-time linear equalizer to introduce a zero at low frequencies; Or / and, CM-ATT includes: 14 NMOS transistors M1~M 14 14 resistors R1~R 14 8 capacitors TC1~TC8; gate connection control code D for M1 <0> Drain connection I4 + The source electrode is connected to the upper plate of TC1 and one end of R1; the lower plate of TC1 and the other end of R1 are connected to I4. - Gate connection control code D of M2 <1> Drain connection I4 + The source electrode is connected to the upper plate of TC2 and one end of R2; the lower plate of TC2 and the other end of R2 are connected to I4. - Gate connection control code D for M3 and M4 <2> M3's drain is connected to I4. + The source electrode is connected to the upper plate of TC3 and one end of R4; the lower plate of TC3 is connected to the other end of R4 and M. 12 The drain of M4 is connected to I4. - The source is connected to the upper plate of TC4 and one end of R5; the lower plate of TC4 is connected to the other end of R5 and the drain of M9; M9, M 12 Gate connection control code D* <2> The source of M9 is connected to the drain of M3 and one end of R3, and the drain is connected to the other end of R3; M 12 The source of M4 is connected to the drain of M4 and one end of R6, and the drain is connected to the other end of R6; the gates of M5 and M6 are connected to control code D. <3> The drain of M5 is connected to the drain of M9, and the source is connected to the upper plate of TC5 and one end of R8; the lower plate of TC5 is connected to the other end of R8, M... 13 The drain of M6; the drain of M6 is connected to M 12 The drain and source of TC6 are connected to the upper plate of TC6 and one end of R9; the lower plate of TC6 is connected to the other end of R9 and M. 10 Drain; M 10 M 13 Gate connection control code D* <3> M 10 The source of M5 is connected to the drain of M5 and one end of R7, and the drain is connected to the other end of R7; M 13 The source is connected to the drain of M6, R 10 One end, the drain is connected to R 10 The other end; gate connection control code D for M7 and M8 <4> The drain of M7 is connected to M. 10 The drain and source are connected to the upper plate of TC7 and R. 12 One end; the lower electrode of TC7 is connected to R. 12 The other end, M 14 The drain is used to output I5. - M8's drain connection M 13 The drain and source are connected to the upper plate of TC8 and R. 13 One end; the lower electrode of TC8 is connected to R. 13 The other end, M 11 The drain is used to output I5. + M 11 M 14 Gate connection control code D* <4> M 11 The source is connected to the drain of M7, R 11 One end, the drain is connected to R 11 The other end; M 14 The source is connected to the drain of M8, R 14 One end, the drain is connected to R 14 The other end; D <2> D* <2> For the opposite signal; D <3> D* <3> For the opposite signal; D <4> D* <4> This is the opposite signal.

7. The conveniently deployable array element according to claim 5, characterized in that, The first DC isolator includes: two capacitors C3 and C4; the upper plate of C3 is connected to P2. + The lower plate serves as the output terminal of the first DC isolator; the upper plate of C4 is connected to P2. - The lower electrode plate serves as the output terminal of the first DC isolator. Or / and, the second DC isolator includes: two capacitors C5~C6; the upper plate of C5 is connected to I3. + The lower plate serves as the output terminal of the second DC isolator; the upper plate of C6 is connected to I3. - The lower electrode plate serves as the output terminal of the second DC isolator. Or / and, the third DC isolator includes: two capacitors C7~C8; the upper plate of C7 is connected to I5. + The lower electrode is used for RF output. OUT + The upper plate of C8 is connected to I5. - The lower electrode is used for RF output. OUT - .

8. A conveniently deployable phased array, characterized in that, include: A number of conveniently deployable array elements connected in parallel as described in any one of claims 5-7.

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