A gain control circuit, a gain control method, and an infrared receiver

Abstract

The application provides a gain control circuit, a gain control method and an infrared receiver. The gain control circuit comprises a signal identification module, an add-subtract counter and a digital-to-analog converter. The signal identification module identifies the duration of the level of a first electrical signal output by a first shaping circuit to obtain a first control signal. The add-subtract counter adjusts a count value under the control of the first control signal to obtain a target digital signal representing the adjusted count value. The digital-to-analog converter performs a digital-to-analog conversion operation on the target digital signal to obtain a gain control signal. The variable gain amplifier adjusts the gain value of the variable gain amplifier under the control of the gain control signal. Since the circuit is digitally controlled and the gain control signal used to control the gain value can be adjusted according to the first electrical signal, the gain control circuit is suitable for on-chip integration while flexibly adjusting the gain value of the variable gain amplifier, thereby improving the area utilization and on-chip integration of the chip.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a gain control circuit, a gain control method, and an infrared receiver. Background Technology

[0002] An infrared receiver is typically a device that receives and processes infrared remote control signals from an infrared transmitter. In addition to the infrared remote control signal, the input signal received by the infrared receiver usually includes various ambient light noise signals, such as those generated by sunlight, incandescent lamps, and fluorescent lamps. The presence of these noise signals can cause signal reception errors, thereby reducing the performance of the infrared receiver. To ensure the reliability of the infrared receiver, it is necessary to filter out or appropriately suppress these noise signals.

[0003] Since the ratio of high-level duration to low-level duration in infrared remote control signals is less than 50%, while the ratio of high-level duration to low-level duration in noise signals is greater than 50%, the ratio of high-level duration to low-level duration in the input signal is usually used to determine whether the current input signal is an infrared remote control signal or a noise signal. Then, based on the type of the current input signal, the gain value of the variable gain amplifier is adjusted through a gain control circuit to suppress noise signals and improve receiving sensitivity.

[0004] In related technologies, capacitor charging and discharging is typically used to change the gain control signal output by the gain control circuit, thereby adjusting the gain value of the variable gain amplifier. Specifically, the gain control signal output by the gain control circuit is adjusted by increasing or decreasing the capacitor voltage, and the gain value of the variable gain amplifier is adjusted accordingly. However, to improve the sensitivity of the infrared receiver, the charging and discharging speed of the capacitor in the gain control circuit should not be too fast, resulting in a large capacitor footprint, making it unsuitable for on-chip integration. Summary of the Invention

[0005] This invention provides a gain control circuit, a gain control method, and an infrared receiver to solve the problem that the gain control circuit in the prior art occupies a large area and is not suitable for on-chip integration.

[0006] In a first aspect, embodiments of the present invention provide a gain control circuit applied to an infrared receiver, comprising a signal recognition module, an up / down counter, and a digital-to-analog converter, wherein:

[0007] The signal recognition module, the up / down counter, and the digital-to-analog converter are electrically connected in sequence.

[0008] The signal recognition module is used to identify the level and duration of the first electrical signal output by the first shaping circuit to obtain the first control signal;

[0009] The up-down counter is used to adjust the count value under the control of the first control signal to obtain a target digital signal representing the adjusted count value.

[0010] The digital-to-analog converter is used to perform digital-to-analog conversion on the target digital signal to obtain a gain control signal, so that the variable gain amplifier can adjust the gain value of the variable gain amplifier under the control of the gain control signal.

[0011] The count value of the up-down counter is proportional to the gain value.

[0012] This invention provides a gain control circuit, including a signal identification module, an up / down counter, and a digital-to-analog converter. The signal identification module identifies the level and duration of a first electrical signal output by a first shaping circuit to obtain a first control signal. Under the control of the first control signal, the up / down counter adjusts its count value to obtain a target digital signal representing the adjusted count value. The digital-to-analog converter performs a digital-to-analog conversion operation on the target digital signal to obtain a gain control signal, so that the variable gain amplifier adjusts its gain value under the control of the gain control signal. Since the up / down counter adjusts its own count value under the control of the first control signal output by the signal identification module, and thus adjusts the gain control signal used to control the variable gain amplifier, this gain control circuit can flexibly adjust the gain value of the variable gain amplifier while also being suitable for on-chip integration, improving chip area utilization and on-chip integration density.

[0013] In one optional embodiment, the signal recognition module includes a signal recognition unit, a signal processing unit, and a signal output unit, wherein:

[0014] The signal recognition unit is electrically connected to the signal processing unit and the signal output unit respectively, and the signal processing unit is electrically connected to the signal output unit;

[0015] The signal recognition unit is used to recognize the high-level duration in the first electrical signal and output a second electrical signal representing that the high-level duration is greater than a first preset duration based on the first recognition result; or to recognize the low-level duration in the first electrical signal and output a third electrical signal representing that the low-level duration is greater than a second preset duration based on the second recognition result; or to recognize the low-level duration in the first signal and output a fourth electrical signal representing that the low-level duration is greater than a third preset duration based on the third recognition result.

[0016] The signal processing unit is configured to output a fifth electrical signal representing the arrival of a fourth preset time period based on the second electrical signal or the third electrical signal.

[0017] The signal output unit is configured to output a first control sub-signal to control the up-down counter to perform a down operation based on the second electrical signal and the fifth electrical signal, or based on the third electrical signal and the fifth electrical signal, or to output a second control sub-signal to control the up-down counter to perform an up operation based on the fourth electrical signal.

[0018] The circuit described above includes a signal recognition module comprising a signal recognition unit, a signal processing unit, and a signal output unit. The signal recognition unit identifies the level and duration of the first electrical signal output by the first shaping circuit and outputs a second or third electrical signal to the signal processing unit based on the recognition result, or outputs a fourth electrical signal to the signal output unit based on the recognition result. The signal output unit uses the fourth electrical signal as a second control sub-signal to control the up / down counter to perform an increment operation. The signal processing unit outputs a fifth electrical signal to the signal output unit based on the second or third electrical signal. The signal output unit then outputs a first control sub-signal to control the up / down counter to perform a decrement operation based on the fifth electrical signal and the second or third electrical signal. By recognizing the first electrical signal output by the first shaping circuit through the signal recognition module, and subsequently generating the first or second control sub-signal to control the up / down counter, precise adjustment of the gain control signal is achieved.

[0019] In one optional embodiment, the signal recognition unit includes a first signal recognition branch, a second signal recognition branch, and a third signal recognition branch;

[0020] The first signal identification branch includes a first AND gate, a first preset number of first frequency dividers, a first NOR gate, and a first D flip-flop, wherein:

[0021] The first input terminal of the first AND gate is used to input the first electrical signal, the second input terminal of the first AND gate is used to input the reset pulse signal, and the output terminal of the first AND gate is electrically connected to the control terminal of each first frequency divider, the reset terminal of the first D flip-flop, and the input terminal of the first D flip-flop, respectively, to output the first enable signal;

[0022] The input terminal of the first-stage first frequency divider is used to input the clock signal. For each other-stage first frequency divider, the input terminal of the other-stage first frequency divider is electrically connected to the output terminal of the adjacent previous-stage first frequency divider. The output terminal of the first frequency divider at the first preset position is also electrically connected to different input terminals of the first NOR gate.

[0023] The output terminal of the first NOR gate is electrically connected to the clock terminal of the first D flip-flop to output a first intermediate signal, and the output terminal of the first D flip-flop is used to output the second electrical signal.

[0024] The first preset quantity and the first preset position are determined based on the first preset duration and the period of the clock signal.

[0025] The circuit described above includes a signal recognition unit comprising a first signal recognition branch, a second signal recognition branch, and a third signal recognition branch. The first signal recognition branch enables a first frequency divider and a first D flip-flop based on a first electrical signal and a reset pulse signal. The first frequency divider performs frequency division processing on the clock signal and sets a first preset duration by setting the first frequency divider and a first NOR gate at a first preset position. During the process of recognizing the high-level duration of the first electrical signal, if the high-level duration of the first electrical signal reaches the first preset duration, the first frequency divider and the first D flip-flop are continuously enabled within the first preset duration. At this time, the first intermediate signal output by the first NOR gate becomes a high-level signal, making the second electrical signal output by the first D flip-flop also a high-level signal. Therefore, when the second electrical signal output by the first signal recognition branch is a high-level signal, it indicates that the high-level duration of the first electrical signal is greater than the first preset duration. In this case, the first electrical signal is determined to be a noise signal.

[0026] In one optional embodiment, the second signal identification branch includes a first inverter, a second AND gate, a second preset number of second frequency dividers, a second NOR gate, and a second D flip-flop, wherein:

[0027] The input terminal of the first inverter is used to input the first electrical signal. The output terminal of the first inverter is electrically connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to input a reset pulse signal. The output terminal of the second AND gate is electrically connected to the control terminal of each second frequency divider, the reset terminal of the second D flip-flop, and the input terminal of the second D flip-flop, respectively, and is used to output a second enable signal.

[0028] The input terminal of the first-stage second frequency divider is used to input the clock signal. For each other-stage second frequency divider, the input terminal of the other-stage second frequency divider is electrically connected to the output terminal of the adjacent previous-stage second frequency divider. The output terminal of the second frequency divider at the second preset position is also electrically connected to different input terminals of the second NOR gate.

[0029] The output of the second NOR gate is electrically connected to the clock terminal of the second D flip-flop to output the second intermediate signal, and the output of the second D flip-flop is used to output the third electrical signal.

[0030] The second preset quantity and the second preset position are determined based on the second preset duration and the period of the clock signal.

[0031] In the above circuit, the second signal recognition branch enables the second frequency divider and the second D flip-flop based on the first electrical signal and the reset pulse signal. The second frequency divider performs frequency division processing on the clock signal, and sets the second preset duration by setting the second frequency divider and the second NOR gate at the second preset position. During the process of recognizing the low-level duration of the first electrical signal, if the low-level duration of the first electrical signal reaches the second preset duration, the second frequency divider and the second D flip-flop are continuously enabled within the second preset duration. At this time, the second intermediate signal output by the second NOR gate becomes a high-level signal, making the third electrical signal output by the second D flip-flop also a high-level signal. Therefore, when the third electrical signal output by the second signal recognition branch is a high-level signal, it indicates that the low-level duration of the first electrical signal is longer than the second preset duration. At this time, the first electrical signal is determined to be a noise signal.

[0032] In an optional embodiment, the third signal identification branch includes a third preset number of third frequency dividers, third NOR gates, and third D flip-flops, wherein:

[0033] The output terminal of the first inverter is also electrically connected to the control terminal of each third frequency divider, the reset terminal of the third D flip-flop, and the input terminal of the third D flip-flop, respectively, for outputting a third enable signal;

[0034] The input terminal of the first-stage third frequency divider is used to input the clock signal. For each other-stage third frequency divider, the input terminal of the other-stage third frequency divider is electrically connected to the output terminal of the adjacent previous-stage third frequency divider. The output terminal of the third frequency divider at the third preset position is also electrically connected to different input terminals of the third NOR gate.

[0035] The output of the third NOR gate is electrically connected to the clock terminal of the third D flip-flop to output a third intermediate signal. The output of the third D flip-flop is used to output the fourth electrical signal, wherein the fourth electrical signal is used as the second control sub-signal.

[0036] The third preset quantity and the third preset position are determined based on the third preset duration and the period of the clock signal.

[0037] In the circuit described above, the third signal recognition branch enables the third frequency divider and the third D flip-flop based on the first electrical signal. The third frequency divider performs frequency division processing on the clock signal and sets the third preset duration by setting the third frequency divider and the third NOR gate at the third preset position. During the process of recognizing the low-level duration of the first electrical signal, if the low-level duration of the first electrical signal reaches the third preset duration, the third frequency divider and the third D flip-flop are continuously enabled within the third preset duration. At this time, the third intermediate signal output by the third NOR gate becomes a high-level signal, making the fourth electrical signal output by the third D flip-flop also a high-level signal. Therefore, when the fourth electrical signal output by the third signal recognition branch is a high-level signal, it indicates that the low-level duration of the first electrical signal is longer than the third preset duration. At this time, the first electrical signal is determined to be a remote control signal.

[0038] In one optional embodiment, the signal processing unit includes a first OR gate, a third AND gate, a fourth frequency divider of a predetermined number, a fourth NOR gate, and a fourth D flip-flop, wherein:

[0039] The first input terminal of the first OR gate is used to input the second electrical signal, the second input terminal of the first OR gate is used to input the third electrical signal, and the output terminal of the first OR gate is electrically connected to the first input terminal of the third AND gate.

[0040] The second input terminal of the third AND gate is used to input the reset pulse signal, and the output terminal of the third AND gate is electrically connected to the control terminal of each fourth frequency divider, the input terminal of the fourth D flip-flop, and the reset terminal of the fourth D flip-flop, respectively, to output the fourth enable signal;

[0041] The input terminal of the first-stage fourth frequency divider is used to input the clock signal. For each other-stage fourth frequency divider, the input terminal of the other-stage fourth frequency divider is electrically connected to the output terminal of the adjacent previous-stage fourth frequency divider. The output terminal of the fourth frequency divider at the fourth preset position is also electrically connected to different input terminals of the fourth NOR gate.

[0042] The output of the fourth NOR gate is electrically connected to the clock terminal of the fourth D flip-flop to output the fourth intermediate signal, and the output of the fourth D flip-flop is used to output the fifth electrical signal.

[0043] In the circuit described above, the signal processing unit enables the fourth frequency divider and the fourth D flip-flop based on the reset pulse signal and the second or third electrical signal. The fourth frequency divider performs frequency division processing on the clock signal, and sets the fourth preset duration by setting the fourth frequency divider and the fourth NOR gate at the fourth preset position. During the process of identifying the high-level duration of the second or third electrical signal, if the high-level duration of the second or third electrical signal reaches the fourth preset duration, the fourth frequency divider and the fourth D flip-flop are continuously enabled within the fourth preset duration. At this time, the fourth intermediate signal output by the fourth NOR gate generates a high-level pulse, causing the fifth electrical signal output by the fourth D flip-flop to also generate a high-level pulse, triggering the reset pulse signal to generate a low-level pulse, resetting the entire signal identification module, thereby achieving the purpose of adjusting the count value of the up / down counter within the fourth preset duration.

[0044] In an optional embodiment, the signal output unit includes a second OR gate, a second inverter, and a fourth AND gate, wherein:

[0045] The input terminal of the second inverter is used to input the fifth electrical signal, and the output terminal of the second inverter is electrically connected to the first input terminal of the fourth AND gate;

[0046] The first input terminal of the second OR gate is used to input the second electrical signal, the second input terminal of the second OR gate is used to input the third electrical signal, and the output terminal of the second OR gate is electrically connected to the second input terminal of the fourth AND gate.

[0047] The output of the fourth AND gate is used to output the first control sub-signal.

[0048] In the circuit described above, the signal output unit outputs a first control sub-signal based on the fifth electrical signal and the second or third electrical signal to control the up-down counter to perform an up operation, or uses the fourth electrical signal as the second control sub-signal to control the up-down counter to perform a down operation, thereby adjusting the gain control signal used to control the gain value, and realizing the gain control circuit's adjustment of the gain value.

[0049] In a second aspect, embodiments of the present invention provide a gain control method applied to a gain control circuit as described in any embodiment of the first aspect, the method comprising:

[0050] The duration of the first electrical signal output by the first shaping circuit is identified, and the count value of the up and down counter is adjusted according to the identification result to obtain the target digital signal representing the adjusted count value.

[0051] The target digital signal is subjected to a digital-to-analog conversion operation to obtain a gain control signal, so that the variable gain amplifier adjusts its own gain value under the control of the gain control signal.

[0052] In one optional embodiment, identifying the duration of the first electrical signal output by the first shaping circuit and adjusting the count value of the up / down counter based on the identification result includes:

[0053] If the high-level duration of the first electrical signal is greater than the first preset duration, or the low-level duration of the first electrical signal is greater than the second preset duration, then the up-down counter is decremented.

[0054] If the low-level duration of the first electrical signal is greater than the third preset duration, then the increment / decrement counter is incremented.

[0055] Thirdly, embodiments of the present invention provide an infrared receiver, including a gain control circuit as described in any embodiment of the first aspect.

[0056] For the technical effects that the gain control method disclosed in the second aspect and the infrared receiver disclosed in the third aspect may achieve, please refer to the above description of the technical effects that can be achieved for the first aspect or various possible solutions in the first aspect, and will not be repeated here. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 A schematic diagram of the circuit structure of a gain control circuit provided in related technologies;

[0059] Figure 2 This is a schematic diagram of a gain control circuit provided in an embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram of the structure of an infrared receiver provided in an embodiment of the present invention;

[0061] Figure 4 This is a schematic diagram of the structure of a signal recognition module provided in an embodiment of the present invention;

[0062] Figure 5 This is a schematic diagram of the circuit structure of a signal recognition unit provided in an embodiment of the present invention;

[0063] Figure 6This is a schematic diagram of a frequency divider provided in an embodiment of the present invention;

[0064] Figure 7 This is a waveform diagram of a signal recognition module provided in an embodiment of the present invention;

[0065] Figure 8 A schematic diagram of the circuit structure of a signal processing unit provided in an embodiment of the present invention;

[0066] Figure 9 A schematic diagram of the circuit structure of a signal output unit provided in an embodiment of the present invention;

[0067] Figure 10 This is a schematic diagram of another gain control circuit provided in an embodiment of the present invention;

[0068] Figure 11 A flowchart illustrating the operation of a gain control method provided in an embodiment of the present invention;

[0069] Figure 12 A waveform diagram of a gain control circuit provided in an embodiment of the present invention;

[0070] Figure 13 The waveform diagram of the output signal of a bandpass filter provided in an embodiment of the present invention. Detailed Implementation

[0071] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0072] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0073] In related technologies, capacitor charging and discharging are typically used to change the gain control signal output by the gain control circuit, thereby adjusting the gain value of the variable gain amplifier. Figure 1The diagram shows a schematic of the gain control circuit in the related technology. The gain control circuit includes a capacitor C0, a first current source Ich, a second current source Idis, a first switch Charge_en, and a second switch Discharge_en. The input terminal of the first current source Ich is electrically connected to the power supply voltage terminal VCC. The output terminal of the first current source Ich is electrically connected to one end of the first switch Charge_en. The other end of the first switch Charge_en is electrically connected to one end of the capacitor C0 and one end of the second switch Discharge_en. The other end of the second switch Discharge_en is electrically connected to the input terminal of the second current source Idis. The other end of the capacitor C0 and the output terminal of the second current source Idis are both grounded.

[0074] Specifically, the first current source Ich serves as the charging current source, and the second current source Idis serves as the discharging current source. When the first switch Charge_en is closed, the second switch Discharge_en is open, and the first current source Ich charges capacitor C0. When the second switch Discharge_en is closed, the first switch Charge_en is open, and capacitor C0 uses its stored energy to power the second current source Idis, i.e., capacitor C0 discharges. A gain control signal is output based on the voltage difference across capacitor C0, and the gain value of the variable gain amplifier is adjusted according to the gain control signal.

[0075] Since the gain control circuit is used in the infrared receiver, the charging and discharging speed of capacitor C0 should not be too fast in order to improve the receiving sensitivity of the infrared receiver. Typically, the charging and discharging voltage difference of capacitor C0 per millisecond is about tens of mV. For example, if the current provided by the first current source Ich is Ich = 1 μA, and the current provided by the second current source Idis is Idis = 1 μA, and the charging voltage difference of capacitor C0 within 1 ms is ΔV = 20 mV, then according to the capacitor charging and discharging formula: I × t = C × ΔV, it can be seen that the amount of charge added to capacitor C0 within the time t = 1 ms, that is, the capacitance value of capacitor C0, is:

[0076] C0=(Ich×t) / ΔV=(1μA×1ms) / 20mV=50nF

[0077] Where Ich is the current value provided by the first current source Ich, t is the charging time of capacitor C0, ΔV is the charging voltage difference of capacitor C0 within 1ms, and C0 is the amount of charge added to capacitor C0 within t=1ms, that is, the capacitance value of capacitor C0.

[0078] However, for on-chip integrated capacitors, their unit capacitance is typically (0.5~5) fF / um. 2Therefore, a capacitor with a capacitance value of C0 = 50nF occupies a very large area, making it unsuitable for on-chip integration. For example, a capacitor with a unit capacitance value of 5fF / µm... 2 That is, the area of ​​the on-chip integrated capacitor with a capacitance of 5fF is 1µm. 2 Therefore, the capacitance value is 50nF = 5 × 10 7 The area of ​​the on-chip integrated capacitor of fF is 1×10 7 um 2 =10mm 2 Its footprint is very large, making it unsuitable for on-chip integration.

[0079] If a capacitor with a small capacitance value is used to meet the requirements of on-chip integration, the charging and discharging current of this capacitor will be very small in order to ensure the receiving sensitivity of the infrared receiver. Current technology cannot achieve precise adjustment of this small charging and discharging current. For example, if the capacitance value of capacitor C0 is set to C0 = 10pF, and the charging time for capacitor C0 is t = 1ms, and the charging voltage difference of capacitor C0 within 1ms is ΔV = 20mV, then according to the capacitor charging and discharging formula: I × t = C × ΔV, the charging current corresponding to capacitor C0 is:

[0080] Ich=(C0×ΔV) / t=(20mV×10pF) / 1ms=200pA

[0081] Where C0 is the capacitance of capacitor C0, ΔV is the charging voltage difference of capacitor C0 within 1ms, t is the charging time of capacitor C0, and Ich is the current provided by the first current source Ich to capacitor C0.

[0082] However, with current technology, the leakage current of transistors alone reaches several hundred pA. Therefore, it is difficult to accurately achieve a charging and discharging current of Ich = 200 pA in actual circuits, and thus it is impossible to accurately adjust the gain value of the variable gain amplifier.

[0083] In summary, the gain control circuits in related technologies cannot achieve precise gain adjustment and on-chip integration compatibility.

[0084] To address the aforementioned problems, embodiments of the present invention provide a gain control circuit, a gain control method, and an infrared receiver to achieve precise gain adjustment of the gain control circuit and on-chip integration compatibility.

[0085] Example 1

[0086] The following specific embodiments illustrate a gain control circuit provided by the present invention. Figure 2The diagram shows the structure of the gain control circuit 20, which is applied to the infrared receiver. The gain control circuit 20 includes a signal recognition module 21, an up / down counter 22, and a digital-to-analog converter (DAC) 23.

[0087] The signal recognition module 21, the up / down counter 22, and the digital-to-analog converter 23 are electrically connected in sequence;

[0088] The signal recognition module 21 is used to identify the level and duration of the first electrical signal output by the first shaping circuit 24 to obtain the first control signal;

[0089] The up / down counter 22 is used to adjust the count value under the control of the first control signal to obtain the target digital signal D[n:0] representing the adjusted count value;

[0090] The digital-to-analog converter 23 is used to perform digital-to-analog conversion on the target digital signal D[n:0] to obtain a gain control signal Vagc, so that the variable gain amplifier 25 can adjust the gain value of the variable gain amplifier 25 under the control of the gain control signal Vagc.

[0091] The count value of the up / down counter 22 is proportional to the gain value.

[0092] This invention provides a gain control circuit 20, including a signal identification module 21, an up / down counter 22, and a digital-to-analog converter 23. The signal identification module 21 identifies the level and duration of a first electrical signal output by a first shaping circuit 24 to obtain a first control signal. Under the control of the first control signal, the up / down counter 22 adjusts its count value to obtain a target digital signal D[n:0] representing the adjusted count value. The digital-to-analog converter 23 performs a digital-to-analog conversion operation on the target digital signal D[n:0] to obtain a gain control signal Vagc, so that the variable gain amplifier 25 adjusts its gain value under the control of the gain control signal Vagc. Since the up / down counter 22 adjusts its own count value under the control of the first control signal output by the signal identification module 21, and thus adjusts the gain control signal Vagc used to control the variable gain amplifier 25, this gain control circuit 20 can flexibly adjust the gain value of the variable gain amplifier 25 while also being suitable for on-chip integration, improving the chip area utilization and on-chip integration density.

[0093] like Figure 3The diagram shows the structure of an infrared receiver 30. The infrared receiver 30 includes a photodiode 31, a preamplifier 32, a variable gain amplifier 25, a limiting amplifier 33, a bandpass filter 34, a first comparator 35, a first demodulator 36, a first shaping circuit 24, a gain control circuit 20, a second comparator 37, a second demodulator 38, a second shaping circuit 39, and an output unit 310. The photodiode 31, preamplifier 32, variable gain amplifier 25, limiting amplifier 33, and bandpass filter 34 are electrically connected in sequence. The output terminal of the bandpass filter 34... The first input terminal of the first comparator 35 and the first input terminal of the second comparator 37 are electrically connected respectively. The second comparator 37, the second demodulator 38, the second shaping circuit 39 and the output unit 310 are electrically connected in sequence. The second input terminal of the second comparator 37 is used to input the remote control signal threshold Vth2. The second input terminal of the first comparator 35 is used to input the noise signal threshold Vth1. The first comparator 35, the first demodulator 36, the first shaping circuit 24 and the gain control circuit 20 are electrically connected in sequence. The output terminal of the gain control circuit 20 is electrically connected to the control terminal of the variable gain amplifier 25.

[0094] In a specific implementation, the infrared transmitter sends an infrared light signal to the photodiode 31. Upon receiving the infrared light signal, the photodiode 31 converts it into an input electrical signal and transmits it to the preamplifier 32. This input electrical signal is amplified by the preamplifier 32 and then output to the variable gain amplifier 25. The variable gain amplifier 25 processes the amplified input signal according to its gain value and transmits the processed electrical signal to the bandpass filter 34 via the limiting amplifier 33 for filtering. Specifically, the center frequency of the bandpass filter 34 is adjusted to match the carrier frequency of the infrared light signal to filter out out-of-band noise. The electrical signal output from the bandpass filter is transmitted to the first comparator 35 and the second comparator 37. The first comparator 35 compares the electrical signal output from the bandpass filter with the noise signal threshold Vth1 and... The comparison result is output to the first shaping circuit 24 via the first demodulator 36. The first shaping circuit 24 shapes the input electrical signal to obtain the first electrical signal and transmits it to the gain control circuit 20. The gain control circuit 20 generates a gain control signal Vagc based on the first electrical signal and outputs the gain control signal Vagc to the control terminal of the variable gain amplifier 25 to control the variable gain amplifier 25 to adjust its gain value according to the gain control signal Vagc, thereby suppressing noise signals and amplifying remote control signals. The remote control signal amplified by the variable gain amplifier 25 is processed sequentially by the limiting amplifier 33, the bandpass filter 34, the second comparator 37, the second demodulator 38, and the second shaping circuit 39 before being sent to the output unit 310 and output to the outside of the infrared receiver 30 via the output unit 310.

[0095] It should be noted that, in this embodiment of the invention, both the noise signal threshold Vth1 and the remote control signal threshold Vth2 can be adjusted by a programmable fuse, thereby enhancing the flexibility of the infrared receiver application.

[0096] In one alternative embodiment, such as Figure 4 As shown, the signal recognition module 21 includes a signal recognition unit 211, a signal processing unit 212, and a signal output unit 213, wherein:

[0097] The signal recognition unit 211 is electrically connected to the signal processing unit 212 and the signal output unit 213 respectively, and the signal processing unit 212 is electrically connected to the signal output unit 213.

[0098] The signal recognition unit 211 is used to recognize the high-level duration in the first electrical signal and output a second electrical signal representing a high-level duration greater than a first preset duration T1 based on the first recognition result; or to recognize the low-level duration in the first electrical signal and output a third electrical signal representing a low-level duration greater than a second preset duration T2 based on the second recognition result; or to recognize the low-level duration in the first signal and output a fourth electrical signal representing a low-level duration greater than a third preset duration T3 based on the third recognition result.

[0099] Signal processing unit 212 is used to output a fifth electrical signal representing the arrival of a fourth preset duration T4 based on the second electrical signal or the third electrical signal;

[0100] The signal output unit 213 is used to output a first control sub-signal EN_C1 for controlling the up-down counter 22 to perform a down operation based on the second electrical signal and the fifth electrical signal, or based on the third electrical signal and the fifth electrical signal, or to output a second control sub-signal EN_C2 for controlling the up-down counter 22 to perform an up operation based on the fourth electrical signal.

[0101] In a specific implementation, the first shaping circuit 24 inputs a first electrical signal to the gain control circuit 20. After receiving the first electrical signal, the signal recognition unit 211 identifies the high-level duration of the first electrical signal. If the duration of the high-level duration of the first electrical signal is greater than or equal to the first preset duration T1, the first electrical signal is identified as a noise signal. At this time, the second electrical signal is output to the signal processing unit 212. The signal processing unit 212 outputs a fifth electrical signal to the signal output unit 213 based on the second electrical signal, so that the signal output unit 213 outputs a first control sub-signal EN_C1 to control the up-down counter 22 to perform a down operation based on the fifth electrical signal and the second electrical signal, thereby reducing the gain control voltage Vagc output by the digital-to-analog converter 23. This causes the variable gain amplifier 25 to adjust its own gain value accordingly based on the reduced gain control voltage Vagc to suppress the noise signal. If the duration of the high-level duration of the first electrical signal is less than the first preset duration T1, the first electrical signal is identified as a remote control signal, and the gain control voltage Vagc is not adjusted.

[0102] In specific implementation, the signal recognition unit 211 identifies the low-level duration of the first electrical signal. If the duration of the low-level duration of the first electrical signal is greater than or equal to the second preset duration T2, the first electrical signal is identified as a noise signal. At this time, a third electrical signal is output to the signal processing unit 212. The signal processing unit 212 outputs a fifth electrical signal to the signal output unit 213 based on the third electrical signal. This causes the signal output unit 213 to output a first control sub-signal EN_C1 that controls the up-down counter 22 to perform a down operation based on the fifth and third electrical signals. This reduces the gain control voltage Vagc output by the digital-to-analog converter 23, thereby causing the variable gain amplifier 25 to adjust its gain value accordingly based on the reduced gain control voltage Vagc to suppress the noise signal. If the duration of the low-level duration of the first electrical signal is less than the second preset duration T2, the first electrical signal is identified as a remote control signal, and the gain control voltage Vagc is not adjusted.

[0103] In a specific implementation, the signal recognition unit 211 identifies the low-level duration of the first electrical signal. If the duration of the low-level duration of the first electrical signal is greater than or equal to the third preset duration T3, the first electrical signal is identified as a remote control signal. At this time, a fourth electrical signal is output to the signal output unit 213, so that the signal output unit 213 outputs a second control sub-signal EN_C2 to control the up-down counter 22 to perform an up operation according to the fourth electrical signal. This increases the gain control voltage Vagc output by the digital-to-analog converter 23, thereby causing the variable gain amplifier 25 to adjust its own gain value accordingly based on the increased gain control voltage Vagc, so as to increase the receiving sensitivity of the remote control signal.

[0104] It should be noted that the noise signal generated by fluorescent lamps is an accented noise signal, which is a periodic signal with a period of 8ms to 10ms. The period of the infrared remote control signal is similar to that of the accented noise signal. However, in the infrared remote control signal, except for the first cycle where the high-level and low-level durations are relatively long, the high-level and low-level durations of the remaining cycles are relatively short. Therefore, the difference in the high-level or low-level durations of the accented noise signal and the infrared remote control signal can be used to determine the signal type, that is, to determine whether the current signal is an accented noise signal or an infrared remote control signal.

[0105] Specifically, for most suppressed noise signals, the high-level duration is relatively long, typically greater than 2ms. Therefore, the first preset duration T1 is set to 1.9ms to suppress such suppressed noise signals. For a small portion of suppressed noise signals, the high-level duration is shorter, typically in the range of 1.2ms to 1.6ms. Therefore, the first preset duration T1 is set to 1ms to suppress such suppressed noise signals. In summary, setting the first preset duration T1 to two adjustable modes can suppress various types of suppressed noise signals, thus broadening the application range of the infrared receiver.

[0106] Specifically, since the duration of the low level of the noise suppression signal is longer than its duration of the high level, the duration of the low level of the noise suppression signal is longer than half of its period length. Taking the period of the noise suppression signal as 8ms as a reference, half of the period length is taken as the second preset duration T2. ​​Therefore, the second preset duration T2 = 4ms is set. If the duration of the low level of the current signal is longer than the second preset duration T2 = 4ms, the current signal is identified as a noise signal. The gain control circuit 20 controls the gain value of the variable gain amplifier 25 to decrease through the gain control signal Vac to suppress the current signal.

[0107] Specifically, after the noise signal is suppressed, the gain value of the variable gain amplifier 25 needs to be restored to its maximum gain value to improve the sensitivity of the infrared receiver 30 in receiving the infrared remote control signal. Since the period of the ambient light noise signal is less than or equal to 10ms, and the duration of no input signal for the infrared remote control signal is generally greater than 15ms, a third preset duration T3 = 11ms is set. If the duration of the low level of the current signal is greater than T3 = 11ms, the noise signal can be considered to have disappeared, and the current signal is the infrared remote control signal. Then, the gain value of the variable gain amplifier 25 is restored to its maximum gain value to improve the sensitivity of the infrared receiver 30.

[0108] Specifically, since the signal processing unit 212 performs gain control signal adjustment within the fourth preset duration T4, the fourth preset duration T4 is set to 2ms.

[0109] It should be noted that, in this embodiment of the invention, the values ​​of the first preset duration T1, the second preset duration T2, the third preset duration T3, and the fourth preset duration T4 can be appropriately adjusted according to the actual situation, and this embodiment of the invention does not impose any restrictions on this.

[0110] In the aforementioned circuit, the signal recognition module 21 includes a signal recognition unit 211, a signal processing unit 212, and a signal output unit 213. The signal recognition unit 211 identifies the level and duration of the first electrical signal output by the first shaping circuit 24, and outputs a second or third electrical signal to the signal processing unit 212, or a fourth electrical signal to the signal output unit 213, based on the recognition result. The signal output unit 213 uses the fourth electrical signal as a second control sub-signal EN_C2 to control the up / down counter to perform an increment operation. The signal processing unit 212 outputs a fifth electrical signal to the signal output unit 213 based on the second or third electrical signal. The signal output unit 213 outputs a first control sub-signal EN_C1 to control the up / down counter to perform a decrement operation based on the fifth electrical signal and the second or third electrical signal. By recognizing the first electrical signal output by the first shaping circuit 24 through the signal recognition module 211, a first control sub-signal EN_C1 or a second control sub-signal EN_C2 to control the up / down counter is generated, thereby achieving precise adjustment of the gain control signal Vagc.

[0111] In one alternative embodiment, such as Figure 5 As shown, the signal recognition unit 211 includes a first signal recognition branch 2111, a second signal recognition branch 2112, and a third signal recognition branch 2113;

[0112] The first signal identification branch 2111 includes a first AND gate AND1, a first preset number of first frequency dividers (FD11, FD12, ..., FD1(n1)), a first NOR gate NOR1, and a first D flip-flop DFF1, wherein:

[0113] The first input terminal of the first AND gate AND1 is used to input the first electrical signal SEN1, the second input terminal of the first AND gate AND1 is used to input the reset pulse signal RB, and the output terminal of the first AND gate AND1 is electrically connected to the control terminal of each first frequency divider (FD11, FD12, ..., FD1(n1)), the reset terminal of the first D flip-flop DFF1, and the input terminal of the first D flip-flop DFF1, respectively, to output the first enable signal EN1;

[0114] The input terminal of the first-stage first frequency divider FD11 is used to input the clock signal CLK. For each other-stage first frequency divider (FD12, ..., FD1(n1)), the input terminal of the other-stage first frequency divider (FD12, ..., FD1(n1)) is electrically connected to the output terminal of the adjacent previous-stage first frequency divider (FD11, FD12, ..., FD1(n1-1)). The output terminal of the first frequency divider (FD11, FD12, ..., FD1(n1)) at the first preset position is also electrically connected to different input terminals of the first NOR gate NOR1.

[0115] The output of the first NOR gate NOR1 is electrically connected to the clock terminal of the first D flip-flop DFF1 to output the first intermediate signal ST1. The output of the first D flip-flop DFF1 is used to output the second electrical signal Q1.

[0116] The first preset quantity and the first preset position are determined based on the first preset duration T1 and the period of the clock signal CLK.

[0117] It should be noted that in the embodiments of the present invention, the first frequency divider (FD11, FD12, ..., FD1(n1)) can be a frequency divider of two, a frequency divider of four, or a frequency divider of K, where K is any positive integer, and the embodiments of the present invention do not impose any restrictions on it.

[0118] The following example illustrates this using the first frequency divider (FD11, FD12, ..., FD1(n1)) as a 2-divider:

[0119] Optional, such as Figure 6 The diagram shows the circuit structure of the first frequency divider FD11. The first frequency divider FD11 includes a fourth D flip-flop DFF51. The clock terminal of the fourth D flip-flop DFF51 serves as the input terminal of the first frequency divider FD11, used to input the clock signal CLK. The reset terminal of the fourth D flip-flop DFF51 serves as the control terminal of the first frequency divider FD11, used to input the first enable signal EN1. The input terminal of the fourth D flip-flop DFF51 is electrically connected to the inverted output terminal of the fourth D flip-flop DFF51, and the inverted output terminal of the fourth D flip-flop DFF51 serves as the output terminal of the first frequency divider FD11. If the period of the clock signal CLK input to the first frequency divider FD11 is Tclk = 100μs, then the period of the clock signal output by the first frequency divider FD11 is: Tc2 = Tclk × 2 = 100μs × 2 = 200μs. Similarly, the period of the clock signal output by the first frequency divider FD12 is: Tc4 = Tclk × 4 = 100μs × 4 = 400μs.

[0120] In specific implementation, the first preset duration T1 is set to 1ms, the period Tclk of the clock signal CLK is 100μs, and the first electrical signal SEN1 is the signal output by the first shaping circuit 24. In order to continuously identify the high level duration of the first electrical signal SEN1 within the first preset duration T1 = 1ms, according to the first preset duration T1 = 1ms and the period Tclk of the clock signal CLK = 100μs, the first preset quantity is set to 4, and the first preset position is the second-stage first frequency divider and the fourth-stage first frequency divider. That is to say, the first signal identification branch 2111 contains 4 cascaded first frequency dividers (FD11, FD12, FD13, FD14), i.e., n1 = 4. The first NOR gate NOR1 is a two-input NOR gate. The output terminals of the first frequency divider FD12 and the first frequency divider FD14 are electrically connected to the two input terminals of the first NOR gate NOR1, respectively.

[0121] Specifically, the clock signal CLK is divided by four after passing through the first frequency divider FD11 and the first frequency divider FD12. Therefore, the period of the clock signal output by the first frequency divider FD12 is four times the period Tclk of the clock signal CLK, that is, Tc4 = Tclk × 4 = 100μs × 4 = 400μs; similarly, the period of the clock signal output by the first frequency divider FD14 is 16 times the period Tclk of the clock signal CLK, that is, Tc4 = Tclk × 4 = 100μs × 4 = 400μs. c16 = Tclk × 16 = 100μs × 16 = 1600μs; After the first NOR gate NOR1 is input to the clock signal output from the first frequency divider FD12 and the clock signal output from the first frequency divider FD14, the period of the first intermediate signal ST1 is Tst1 = 1600μs, where the low level duration is: (Tc4 + Tc16) / 2 = (400μs + 1600μs) / 2 = 1ms, which is the first preset duration T1.

[0122] like Figure 7As shown, since the first frequency divider (FD11, FD12, FD13, FD14) is enabled at a high level, the reset pulse signal RB is also high. When the first electrical signal SEN1 is high, the first enable signal EN1 becomes high, enabling the first frequency divider (FD11, FD12, FD13, FD14) and the first D flip-flop DFF1. The first frequency divider (FD11, FD12, FD13, FD14) then begins to divide the clock signal CLK. If the first electrical signal SEN1 continues to enable the first frequency divider (FD11, FD12, FD13, FD14), the clock signal CLK will continue to be divided. 12, FD13, FD14) reach the first preset duration T1, that is, the high level duration of the first electrical signal SEN1 is maintained for the first preset duration T1. At this time, the first intermediate signal ST1 output by the first NOR gate NOR1 becomes high level. Under the control of the first enable signal EN1 and the first intermediate signal ST1, the second electrical signal Q1 output by the first D flip-flop DFF1 also becomes high level. Therefore, the second electrical signal Q1 is used to characterize that the high level duration of the first electrical signal SEN1 is greater than the first preset duration T1. At this time, the first electrical signal SEN1 is determined to be a noise signal.

[0123] The above circuit's signal recognition unit includes a first signal recognition branch 2111, a second signal recognition branch 2112, and a third signal recognition branch 2113. The first signal recognition branch 2111 enables the first frequency divider (FD11, FD12, ..., FD1(n1)) and the first D flip-flop DFF1 based on the first electrical signal SEN1 and the reset pulse signal RB. The first frequency divider (FD11, FD12, ..., FD1(n1)) performs frequency division processing on the clock signal CLK. By setting the first frequency divider (FD11, FD12, ..., FD1(n1)) and the first NOR gate NOR1 to a first preset position, the first preset duration T1 is set. The first electrical signal SEN1... During the high-level duration identification process, if the high-level duration of the first electrical signal SEN1 reaches the first preset duration T1, the first frequency divider (FD11, FD12, ..., FD1(n1)) and the first D flip-flop DFF1 are continuously enabled within the first preset duration T1. At this time, the first intermediate signal ST1 output by the first NOR gate NOR1 becomes a high-level signal, making the second electrical signal Q1 output by the first D flip-flop DFF1 also a high-level signal. Therefore, when the second electrical signal Q1 output by the first signal identification branch 2111 is a high-level signal, it indicates that the high-level duration of the first electrical signal SEN1 is greater than the first preset duration T1. At this time, the first electrical signal SEN1 is determined to be a noise signal.

[0124] In one alternative embodiment, such as Figure 5As shown, the second signal identification branch 2112 includes a first inverter INV1, a second AND gate AND2, a second preset number of second frequency dividers (FD21, FD22, ..., FD2(n2)), a second NOR gate NOR2, and a second D flip-flop DFF2, wherein:

[0125] The input terminal of the first inverter INV1 is used to input the first electrical signal SEN1. The output terminal of the first inverter INV1 is electrically connected to the first input terminal of the second AND gate AND2. The second input terminal of the second AND gate AND2 is used to input the reset pulse signal RB. The output terminal of the second AND gate AND2 is electrically connected to the control terminal of each second frequency divider (FD21, FD22, ..., FD2(n2)), the reset terminal of the second D flip-flop DFF2, and the input terminal of the second D flip-flop DFF2, respectively, and is used to output the second enable signal EN2.

[0126] The input terminal of the first-stage second frequency divider FD21 is used to input the clock signal. For each other-stage second frequency divider (FD22, ..., FD2(n2)), the input terminal of the other-stage second frequency divider (FD22, ..., FD2(n2)) is electrically connected to the output terminal of the adjacent previous-stage second frequency divider (FD21, ..., FD2(n2-1)). The output terminal of the second frequency divider (FD21, FD22, ..., FD2(n2)) at the second preset position is also electrically connected to different input terminals of the second NOR gate NOR2.

[0127] The output of the second NOR gate NOR2 is electrically connected to the clock terminal of the second D flip-flop DFF2 to output the second intermediate signal ST2. The output of the second D flip-flop DFF2 is used to output the third electrical signal Q2.

[0128] The second preset quantity and the second preset position are determined based on the second preset duration T2 and the period of the clock signal CLK.

[0129] It should be noted that in the embodiments of the present invention, the second frequency divider (FD21, FD22, ..., FD2(n2)) can be a frequency divider of two, a frequency divider of four, or a frequency divider of K, where K is any positive integer, and the embodiments of the present invention do not impose any restrictions on it.

[0130] The following example illustrates this using two dividers (FD21, FD22, ..., FD2(n2)).

[0131] In the specific implementation, the second preset duration T2 is set to 4ms, the period Tclk of the clock signal CLK is 100μs, and the first electrical signal SEN1 is the signal output by the first shaping circuit 24. In order to continuously identify the low level duration of the first electrical signal SEN1 within the second preset duration T2 = 4ms, according to the second preset duration T2 = 4ms and the period Tclk of the clock signal CLK = 100μs, the second preset quantity is set to 6, and the second preset position is the fourth-level second frequency divider and the sixth-level second frequency divider. That is to say, the second signal identification branch 2112 contains 6 cascaded second frequency dividers (FD21, FD22, ..., FD26), i.e., n2 = 6. The second NOR gate NOR2 is a two-input NOR gate. The output terminal of the second frequency divider FD24 and the output terminal of the second frequency divider FD26 are electrically connected to the two input terminals of the second NOR gate NOR2, respectively.

[0132] Specifically, the clock signal CLK is divided by 16 after passing through the second frequency divider (FD21, FD22, FD23, FD24). Therefore, the period of the clock signal output by the second frequency divider FD24 is 16 times the period Tclk of the clock signal CLK, that is, Tc16 = Tclk × 16 = 100μs × 16 = 1600μs; similarly, the period of the clock signal output by the second frequency divider FD26 is 64 times the period Tclk of the clock signal CLK. The period of the second intermediate signal ST2 is Tst2 = 6400μs, which is Tc64 = Tclk × 64 = 100μs × 64 = 6400μs. After the clock signal output from the second frequency divider FD24 and the clock signal output from the second frequency divider FD26 are input to the second NOR gate NOR2, the period of the output second intermediate signal ST2 is Tst2 = 6400μs. The low level duration is (Tc16 + Tc64) / 2 = (1600μs + 6400μs) / 2 = 4ms, which is the second preset duration T2.

[0133] Since the second frequency divider (FD21, FD22, ..., FD26) is enabled at a high level, when the first electrical signal SEN1 is low, the output signal of the first inverter INV1 is a high-level signal, and the reset pulse signal RB is also high. Therefore, the second enable signal EN2 output from the second AND gate AND2 is high, enabling the second frequency divider (FD21, FD22, ..., FD26) and the second D flip-flop DFF2. The second frequency divider (FD21, FD22, ..., FD26) then begins to divide the clock signal CLK. If the first electrical signal SEN1 is enabled... The second frequency divider (FD21, FD22, ..., FD26) is continuously enabled until the second preset duration T2 is reached. That is, the low level duration of the first electrical signal SEN1 is maintained for the second preset duration T2. ​​At this time, the second intermediate signal ST2 output by the second NOR gate NOR2 becomes high. Under the control of the second enable signal EN2 and the second intermediate signal ST2, the third electrical signal Q2 output by the second D flip-flop DFF2 also becomes high. Therefore, the third electrical signal Q2 is used to characterize that the low level duration of the first electrical signal SEN1 is greater than the second preset duration T2. ​​At this time, the first electrical signal SEN1 is determined to be a noise signal.

[0134] In the above circuit, the second signal recognition branch 2112 enables the second frequency divider (FD21, FD22, ..., FD2(n2)) and the second D flip-flop DFF2 based on the first electrical signal SEN1 and the reset pulse signal RB. The second frequency divider (FD21, FD22, ..., FD2(n2)) performs frequency division processing on the clock signal CLK, and sets the second preset duration T2 by using the second frequency divider (FD21, FD22, ..., FD2(n2)) and the second NOR gate NOR2 to set the second preset position. During the process of recognizing the low level duration of the first electrical signal SEN1, if the first electrical signal SEN1... When the low-level duration of N1 reaches the second preset duration T2, the second frequency divider (FD21, FD22, ..., FD2(n2)) and the second D flip-flop DFF2 are continuously enabled within the second preset duration T2. ​​At this time, the second intermediate signal ST2 output by the second NOR gate NOR2 becomes a high-level signal, making the third electrical signal Q2 output by the second D flip-flop DFF2 also a high-level signal. Therefore, when the third electrical signal Q2 output by the second signal recognition branch 2112 is a high-level signal, it indicates that the low-level duration of the first electrical signal SEN1 is greater than the second preset duration T2. ​​At this time, the first electrical signal SEN1 is determined to be a noise signal.

[0135] In one alternative embodiment, such as Figure 5As shown, the third signal identification branch 2113 includes a third preset number of third frequency dividers (FD31, FD32, ..., FD3(n3)), a third NOR gate, and a third D flip-flop, DFF3, wherein:

[0136] The output terminal of the first inverter INV1 is also electrically connected to the control terminal of each third frequency divider (FD31, FD32, ..., FD3(n3)), the reset terminal of the third D flip-flop DFF3, and the input terminal of the third D flip-flop DFF3, respectively, for outputting the third enable signal EN3;

[0137] The input terminal of the first-stage third frequency divider FD31 is used to input the clock signal CLK. For each other-stage third frequency divider (FD32, ..., FD3(n3)), the input terminal of the other-stage third frequency divider (FD32, ..., FD3(n3)) is electrically connected to the output terminal of the adjacent previous-stage third frequency divider (FD31, ..., FD3(n3-1)). The output terminal of the third frequency divider (FD31, FD32, ..., FD3(n3)) at the third preset position is also electrically connected to different input terminals of the third NOR gate NOR3.

[0138] The output of the third NOR gate NOR3 is electrically connected to the clock terminal of the third D flip-flop DFF3 to output the third intermediate signal ST3. The output of the third D flip-flop DFF3 is used to output the fourth electrical signal Q3, wherein the fourth electrical signal Q3 is used as the second control sub-signal EN_C2.

[0139] The third preset quantity and the third preset position are determined based on the third preset duration T3 and the period of the clock signal CLK.

[0140] It should be noted that in the embodiments of the present invention, the third frequency divider (FD31, FD32, ..., FD3(n3)) can be a frequency divider of two, a frequency divider of four, or a frequency divider of K, where K is any positive integer, and the embodiments of the present invention do not impose any restrictions on it.

[0141] The following example illustrates this using the third frequency divider (FD31, FD32, ..., FD3(n3)) as a 2-divider:

[0142] In specific implementation, the third preset duration T3 is set to 11ms, the period Tclk of the clock signal CLK is 100μs, and the first electrical signal SEN1 is the signal output by the first shaping circuit 24. In order to continuously identify the low level duration of the first electrical signal SEN1 within the third preset duration T3 = 11ms, based on the third preset duration T3 = 11ms and the period Tclk of the clock signal CLK = 100μs, the third preset quantity is set to 7, and the third preset position is the second-stage third frequency divider, the third-stage third frequency divider, and the fourth... The third signal identification branch 2113 contains seven cascaded third frequency dividers (FD31, FD32, ..., FD37), i.e., n3 = 7. The third NOR gate NOR3 is a five-input NOR gate. The outputs of the third frequency dividers FD32, FD33, FD34, FD36, and FD37 are electrically connected to the five inputs of the third NOR gate NOR3, respectively.

[0143] Specifically, the clock signal CLK is divided by four after passing through the third frequency divider (FD31, FD32). Therefore, the period of the clock signal output by the third frequency divider FD32 is 4 times the period Tclk of the clock signal CLK, i.e., Tc4 = Tclk × 4 = 100μs × 4 = 400μs. Similarly, the period of the clock signal output by the third frequency divider FD33 is 8 times the period Tclk of the clock signal CLK, i.e., Tc8 = Tclk × 8 = 100μs × 8 = 800μs. The period of the clock signal output by the third frequency divider FD34 is 16 times the period Tclk of the clock signal CLK, i.e., Tc16 = Tclk × 16 = 100μs × 16 = 1600μs. The period of the clock signal output by the third frequency divider FD36 is 64 times the period Tclk of the clock signal CLK, i.e., Tc64 = Tclk × 64 = 100μs. s×64=6400μs, the period of the clock signal output by the third frequency divider FD37 is 128 times the period Tclk of the clock signal CLK, that is, Tc128=Tclk×128=100μs×128=12800μs; the third NOR gate NOR3 inputs the clock signal output by the third frequency divider FD32, the clock signal output by the third frequency divider FD33, the clock signal output by the third frequency divider FD34, and the third frequency divider... After the clock signal output by frequency divider FD36 and the clock signal output by third frequency divider FD37, the period of the third intermediate signal ST3 is Tst3 = 12800μs. The low level duration is: (Tc4 + Tc8 + Tc16 + Tc64 + T128) / 2 = (400μs + 800μs + 1600μs + 6400μs + 12800μs) / 2 = 11ms, which is the third preset duration T3.

[0144] When the first electrical signal SEN1 goes low, the third enable signal EN3 output from the output terminal of the first inverter INV1 goes high. The third signal recognition branch 2113 and the second signal recognition branch 2112 are simultaneously enabled. That is, the third frequency divider (FD31, FD32, ..., FD3(n3)) and the third D flip-flop DFF3 are enabled. The third frequency divider (FD31, FD32, ..., FD3(n3)) begins to divide the clock signal CLK. If the first electrical signal SEN1 can be continuously enabled... When the third frequency divider (FD31, FD32, ..., FD3(n3)) reaches the third preset duration T3, the third intermediate signal ST3 output by the third NOR gate becomes high. Under the control of the third enable signal EN3 and the third intermediate signal ST3, the fourth electrical signal Q3 output by the third D flip-flop DFF3 also becomes high. Therefore, the fourth electrical signal Q3 is used to characterize that the low-level duration of the first electrical signal SEN1 is greater than the third preset duration T3. At this time, the first electrical signal SEN1 is determined to be a remote control signal.

[0145] In the above circuit, the third signal recognition branch 2113 enables the third frequency divider (FD31, FD32, ..., FD3(n3)) and the third D flip-flop DFF3 based on the first electrical signal SEN1 and the reset pulse signal RB. The third frequency divider (FD31, FD32, ..., FD3(n3)) performs frequency division processing on the clock signal CLK, and sets the third preset duration T3 by setting the third frequency divider (FD31, FD32, ..., FD3(n3)) and the third NOR gate NOR3 at the third preset position. During the process of recognizing the low level duration of the first electrical signal SEN1, if the first electrical signal SEN1... When the low-level duration of N1 reaches the third preset duration T3, the third frequency divider (FD31, FD32, ..., FD3(n3)) and the third D flip-flop DFF3 are continuously enabled within the third preset duration T3. At this time, the third intermediate signal ST3 output by the third NOR gate NOR3 becomes a high-level signal, making the fourth electrical signal Q3 output by the third D flip-flop DFF3 also a high-level signal. Therefore, when the fourth electrical signal Q3 output by the third signal recognition branch 2113 is a high-level signal, it indicates that the low-level duration of the first electrical signal SEN1 is greater than the third preset duration T3. At this time, the first electrical signal SEN1 is determined to be a remote control signal.

[0146] In one alternative embodiment, such as Figure 8 As shown, the signal processing unit 212 includes a first OR gate OR1, a third AND gate AND3, a fourth frequency divider (FD41, FD42, ..., FD4(n4)) of a preset number, a fourth NOR gate NOR4, and a fourth D flip-flop DFF4, wherein:

[0147] The first input terminal of the first OR gate OR1 is used to input the second electrical signal Q1, the second input terminal of the first OR gate OR1 is used to input the third electrical signal Q2, and the output terminal of the first OR gate OR1 is electrically connected to the first input terminal of the third AND gate AND3.

[0148] The second input terminal of the third AND gate AND3 is used to input the reset pulse signal RB. The output terminal of the third AND gate AND3 is electrically connected to the control terminal of each fourth frequency divider (FD41, FD42, ..., FD4(n4)), the input terminal of the fourth D flip-flop DFF4, and the reset terminal of the fourth D flip-flop DFF4, respectively, and is used to output the fourth enable signal EN4.

[0149] The input terminal of the first-stage fourth frequency divider FD41 is used to input the clock signal CLK. For each other-stage fourth frequency divider (FD42, ..., FD4(n4)), the input terminal of the other-stage fourth frequency divider (FD42, ..., FD4(n4)) is electrically connected to the output terminal of the adjacent previous-stage fourth frequency divider (FD41, ..., FD4(n4-1)). The output terminal of the fourth preset position fourth frequency divider (FD41, FD42, ..., FD4(n4)) is also electrically connected to different input terminals of the fourth NOR gate NOR4.

[0150] The output of the fourth NOR gate NOR4 is electrically connected to the clock terminal of the fourth D flip-flop DFF4 to output the fourth intermediate signal ST4. The output of the fourth D flip-flop DFF4 is used to output the fifth electrical signal Q4.

[0151] It should be noted that in the embodiments of the present invention, the fourth frequency divider (FD41, FD42, ..., FD4(n4)) can be a frequency divider of two, a frequency divider of four, or a frequency divider of K, where K is any positive integer, and the embodiments of the present invention do not impose any restrictions on it.

[0152] The following example illustrates this using the fourth frequency divider (FD41, FD42, ..., FD4(n4)) as a 2-divider:

[0153] In specific implementation, the fourth preset duration T4 is set to 2ms, the period Tclk of the clock signal CLK is 100μs, the second electrical signal Q1 is the signal output by the first signal recognition branch 2111, and the third electrical signal Q2 is the signal output by the second signal recognition branch 2112. In order to adjust the gain control signal Vagc within the fourth preset duration T4 = 2ms, according to the fourth preset duration T4 = 2ms and the period Tclk of the clock signal CLK = 100μs, the fourth preset quantity is set to 5, and the fourth preset position is the third-stage fourth frequency divider and the fifth-stage fourth frequency divider. That is to say, the signal processing unit 212 contains 5 cascaded fourth frequency dividers (FD41, FD42, ..., FD45), i.e., n4 = 5. The fourth NOR gate NOR4 is a two-input NOR gate. The output terminals of the fourth frequency divider FD43 and the fourth frequency divider FD45 are electrically connected to the two input terminals of the fourth NOR gate NOR4, respectively.

[0154] Specifically, the clock signal CLK is divided by the fourth frequency divider (FD41, FD42, ..., FD45). The clock signals output from the fourth frequency divider FD43 and the fourth frequency divider FD45 are then subjected to a logical OR operation through the fourth NOR gate NOR4. The period of the output fourth intermediate signal ST4 is Tst4 = 3200μs, where the low level duration is: (Tc8 + Tc32) / 2 = (800μs + 3200μs) / 2 = 2ms, which is the fourth preset duration T4.

[0155] like Figure 7 As shown, when the second electrical signal Q1 becomes high, after the second electrical signal Q1 and the reset pulse signal RB are logically ANDed, the resulting fourth enable signal EN4 also becomes high. The fourth frequency divider (FD41, FD42, ..., FD4(n4)) and the fourth D flip-flop DFF4 are both enabled. The fourth frequency divider (FD41, FD42, ..., FD4(n4)) begins to divide the clock signal CLK. After the second electrical signal Q1 continuously enables the fourth frequency divider (FD41, FD42, ..., FD4(n4)) for the fourth preset duration T4, the fourth intermediate signal ST4 output by the fourth NOR gate becomes high, so that the fifth electrical signal Q4 output by the fourth D flip-flop DFF4 generates a high-level pulse accordingly. Therefore, the fifth electrical signal Q4 is used to characterize the arrival of the fourth preset duration T4. At this time, the adjustment of the gain control signal Vagc is stopped.

[0156] In the above circuit, the signal processing unit 212 enables the fourth frequency divider (FD41, FD42, ..., FD4(n4)) and the fourth D flip-flop DFF4 based on the reset pulse signal RB and the second electrical signal Q1 or the third electrical signal Q3. The fourth frequency divider (FD41, FD42, ..., FD4(n4)) performs frequency division processing on the clock signal CLK, and sets the fourth preset duration T4 by setting the fourth frequency divider (FD41, FD42, ..., FD4(n4)) and the fourth NOR gate NOR4 at the fourth preset position. During the process of identifying the high level duration of the second electrical signal Q1 or the high level duration of the third electrical signal Q2, If the high-level duration of the second electrical signal Q1 or the high-level duration of the third electrical signal Q2 reaches the fourth preset duration T4, then the fourth frequency divider (FD41, FD42, ..., FD4(n4)) and the fourth D flip-flop DFF4 are continuously enabled within the fourth preset duration T4. At this time, the fourth intermediate signal ST4 output by the fourth NOR gate NOR4 generates a high-level pulse, which causes the fifth electrical signal Q4 output by the fourth D flip-flop DFF4 to also generate a high-level pulse, triggering the reset pulse signal RB to generate a low-level pulse, resetting the entire signal recognition module 21, thereby achieving the purpose of adjusting the count value of the up-down counter 22 within the fourth preset duration T4.

[0157] In one alternative embodiment, such as Figure 9 As shown, the signal output unit 213 includes a second OR gate OR2, a second inverter INV2, and a fourth AND gate AND4, wherein:

[0158] The input terminal of the second inverter INV2 is used to input the fifth electrical signal Q4, and the output terminal of the second inverter INV2 is electrically connected to the first input terminal of the fourth AND gate AND4.

[0159] The first input terminal of the second OR gate OR2 is used to input the second electrical signal Q1, the second input terminal of the second OR gate OR2 is used to input the third electrical signal Q2, and the output terminal of the second OR gate OR2 is electrically connected to the second input terminal of the fourth AND gate AND4.

[0160] The output of the fourth AND gate AND4 is used to output the first control sub-signal EN_C1.

[0161] In practical implementation, after the fifth electrical signal Q4 passes through the second inverter INV2, the output signal is the inverted signal of the fifth electrical signal Q4, namely the sixth electrical signal Q4B. For example... Figure 7As shown, if the signal recognition unit 211 identifies the first electrical signal SEN1 as a noise signal, then the second electrical signal Q1 output by the first signal recognition branch 2111 is at a high level, the fifth electrical signal Q4 is at a low level, and the sixth electrical signal Q4B is at a high level. The fourth AND gate AND4 performs a logical AND operation on the second electrical signal Q1 and the sixth electrical signal Q4B, and the output signal is at a high level, that is, the first control sub-signal EN_C1 is at a high level. After receiving the first control sub-signal EN_C1, the up-down counter 22 decrements its own count value by 1, so that the target digital signal D[n:0] output by it is decremented by 1. This causes the digital-to-analog converter 23 to perform digital-to-analog conversion on the target digital signal D[n:0] after the decrement operation, and the resulting gain control signal Vagc is reduced by one step, thereby controlling the gain value of the variable gain amplifier to also be reduced by one step, so as to achieve the purpose of suppressing noise signals.

[0162] When the signal processing unit 212 outputs the fifth electrical signal Q4, which characterizes the arrival of the fourth preset duration T4, the fifth electrical signal Q4 becomes high. At this time, the sixth electrical signal Q4B becomes low, causing the first control sub-signal EN_C1 to also become low, generating a falling edge. The falling edge of the first control sub-signal EN_C1 triggers the reset pulse RB to generate a low-level pulse, thereby resetting the entire signal recognition module 21. This resets both the second electrical signal Q1 and the fifth electrical signal Q4 to low levels, and the second detection of the first electrical signal SEN1 begins. The above method achieves the purpose of adjusting the gain control signal Vagc during the fourth preset duration T4.

[0163] In a specific implementation, if the signal recognition unit 211 recognizes the first electrical signal SEN1 as a remote control signal, then the fourth electrical signal Q3 output by the third signal recognition branch 21131 is at a high level. The signal output unit 213 uses the fourth electrical signal Q3 as the second control sub-signal EN_C2. After receiving the second control sub-signal EN_C2, the up-down counter 22 increments its own count value by 1, causing the target digital signal D[n:0] it outputs to also increment by 1. This causes the digital-to-analog converter 23 to perform digital-to-analog conversion on the target digital signal D[n:0] after the increment operation, and the resulting gain control signal Vagc increases by one step, thereby controlling the gain value of the variable gain amplifier to also increase by one step, until the count value of the up-down counter 22 increases to the maximum count value, so as to improve the receiving sensitivity of the remote control signal.

[0164] In the circuit described above, the signal output unit 213 outputs a first control sub-signal EN_C1 based on the fifth electrical signal Q4 and the second electrical signal Q1 or the third electrical signal Q2 to control the up-down counter 22 to perform an up operation, or uses the fourth electrical signal Q3 as the second control sub-signal EN_C2 to control the up-down counter 22 to perform a down operation, thereby adjusting the gain control signal Vagc used to control the gain value, so as to realize the gain control circuit 20's adjustment of the gain value.

[0165] In practical implementation, the initial count value of the up / down counter 22 is set to the maximum count value in the initial state, and correspondingly, the gain value of the variable gain amplifier 25 is also set to the maximum gain value. For example... Figure 10 As shown, the signal recognition module 21 identifies the first electrical signal SEN1 output by the first shaping circuit 24. If the first electrical signal SEN1 is identified as a noise signal, the first control sub-signal EN_C1 output by the signal recognition module 21 becomes high, i.e., EN_C1 = '1'. Under the control of the first control sub-signal EN_C1, the up / down counter 22 decrements its own count value by 1, so that the target digital signal D[n:0] output by the up / down counter 22 is also decremented by 1 accordingly. For example, before the up / down counter 22 decrements its count value by 1, the target digital signal D[n:0] output by the up / down counter 22... If the target digital signal D[n:0] = 10011, then after the up-down counter 22 decrements the count value by 1, the target digital signal D[n:0] is also decremented by 1 accordingly. At this time, the target digital signal D[n:0] output by the up-down counter 22 is 10010. The target digital signal D[n:0] is converted into a gain control voltage Vagc by the digital-to-analog converter (DAC) 23, and the gain control voltage Vagc is sent to the variable gain amplifier 25 so that the variable gain amplifier 25 adjusts its gain value according to the gain control voltage Vagc.

[0166] Optionally, the target digital signal D[n:0] is decremented by 1, and the gain control voltage Vagc decreases by one step accordingly. The gain value of the variable gain amplifier 25 also decreases by one step. Specifically, the step size is set to 2ms, and the full-scale output voltage of the digital-to-analog converter 23 is taken as VCC. Therefore, the adjustment voltage for one step is VCC / 2. n+1 For example, if n = 6 and VCC = 3.3 in the target digital signal D[n:0], then one adjustment step size is 25.8mV. That is, if the count value of the up / down counter 22 is reduced by 1, the corresponding gain control voltage Vagc output by the digital-to-analog converter 23 decreases by 25.8mV. Furthermore, the larger the number of bits n in the target digital signal D[n:0], the finer the adjustment of the gain control voltage Vagc. By changing different n values, different gain adjustment step sizes can be obtained, thereby improving the flexibility of gain adjustment.

[0167] Example 2

[0168] Based on the same concept, this embodiment of the invention provides a gain control method. Since this method is the same as the method applied in the circuit of this embodiment of the invention, and the principle of solving the problem by this method is similar to that of the circuit, the implementation of this method can be referred to the implementation of the circuit, and the repeated parts will not be described again.

[0169] like Figure 11 As shown, the gain control method includes the following steps:

[0170] Step 1101: Identify the duration of the first electrical signal output by the first shaping circuit, and adjust the count value of the up-down counter according to the identification result to obtain the target digital signal representing the adjusted count value;

[0171] Step 1102: Perform a digital-to-analog conversion on the target digital signal to obtain a gain control signal, so that the variable gain amplifier can adjust its own gain value under the control of the gain control signal.

[0172] In one optional embodiment, the duration of the first electrical signal output by the first shaping circuit is identified, and the count value of the up / down counter is adjusted according to the identification result, including:

[0173] If the high-level duration of the first electrical signal is greater than the first preset duration, or the low-level duration of the first electrical signal is greater than the second preset duration, then the up-down counter is decremented.

[0174] If the low-level duration of the first electrical signal is longer than the third preset duration, then the up / down counter is incremented.

[0175] In specific implementation, such as Figure 12 As shown, if the high-level duration of the first electrical signal SEN1 output by the first shaping circuit is longer than the first preset duration T1, then the first electrical signal SEN1 is identified as a noise signal. At this time, within the fourth preset duration T4, the first control sub-signal EN_C1 is set to a high level to control the up-down counter to decrement the count value by 1, thereby controlling the gain control signal Vagc to decrease by one step. The variable gain amplifier also reduces its own gain value accordingly based on the gain control signal Vagc to suppress the noise signal.

[0176] In specific implementation, such as Figure 12As shown, if the low-level duration of the first electrical signal SEN1 output by the first shaping circuit is longer than the second preset duration T2, then the first electrical signal SEN1 is identified as a noise signal. At this time, within the fourth preset duration T4, the first control sub-signal EN_C1 is set to a high level to control the up-down counter to decrement the count value by 1, thereby controlling the gain control signal Vagc to decrease by one step. The variable gain amplifier also reduces its own gain value accordingly based on the gain control signal Vagc to suppress the noise signal.

[0177] In specific implementation, such as Figure 12 As shown, if the low-level duration of the first electrical signal SEN1 output by the first shaping circuit is greater than the third preset duration T3, then the first electrical signal SEN1 is identified as a remote control signal. At this time, the second control sub-signal EN_C2 is set to a high level to control the up-down counter to increment the count value by 1, thereby controlling the gain control signal Vagc to increase by one step. The variable gain amplifier also increases its own gain value according to the gain control signal Vagc, until the up-down counter reaches the maximum count value, so as to improve the receiving sensitivity of the remote control signal.

[0178] Specifically, such as Figure 13 As shown, as the gain control signal Vagc decreases, the gain value of the variable gain amplifier also decreases accordingly, and the lower envelope output signal of the bandpass filter gradually increases. When the lower envelope output signal of the bandpass filter is higher than the noise signal threshold Vth1, it indicates that the noise signal has been suppressed and the gain adjustment process ends. At this time, the signal output by the bandpass filter is the remote control signal.

[0179] Example 3

[0180] Based on the same concept, embodiments of the present invention provide an infrared receiver, such as... Figure 3 As shown, it includes the gain control circuit in any embodiment of the present invention.

[0181] The principle of solving the problem with the infrared receiver in this embodiment can be referred to the principle of solving the problem with the gain control circuit in any of the above embodiments, and will not be repeated here.

[0182] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0183] Those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims and their equivalents, this invention is also intended to include these modifications and variations.

Claims

1. A gain control circuit, characterized in that, Applied to infrared receivers, it includes a signal recognition module, an up / down counter, and a digital-to-analog converter, wherein: The signal recognition module, the up / down counter, and the digital-to-analog converter are electrically connected in sequence. The signal recognition module is used to quantitatively determine the high-level duration and low-level duration of the first electrical signal output by the first shaping circuit to obtain the first control signal. The up-down counter is used to adjust the count value in steps under the control of the first control signal to obtain a target digital signal representing the adjusted count value. The digital-to-analog converter is used to perform digital-to-analog conversion on the target digital signal to obtain a gain control signal, so that the variable gain amplifier adjusts the gain value of the variable gain amplifier under the control of the gain control signal, wherein the count value of the up-down counter is positively correlated with the gain value; Wherein, the first control signal includes a first control sub-signal and a second control sub-signal, and the signal recognition module is further used for: When the high-level duration is greater than a first preset duration, or when the low-level duration is greater than a second preset duration, the first control sub-signal controlling the up-down counter to perform a down operation is output; when the low-level duration is greater than a third preset duration, the second control sub-signal controlling the up-down counter to perform an up operation is output.

2. The circuit as described in claim 1, characterized in that, The signal recognition module includes a signal recognition unit, a signal processing unit, and a signal output unit, wherein: The signal recognition unit is electrically connected to the signal processing unit and the signal output unit respectively, and the signal processing unit is electrically connected to the signal output unit; The signal recognition unit is configured to output a second electrical signal when the high-level duration is longer than the first preset duration, or output a third electrical signal when the low-level duration is longer than the second preset duration, or output a fourth electrical signal when the low-level duration is longer than the third preset duration. The signal processing unit is configured to output a fifth electrical signal representing the arrival of a fourth preset time period based on the second electrical signal, or to output the fifth electrical signal based on the third electrical signal. The signal output unit is configured to output the first control sub-signal based on the second electrical signal and the fifth electrical signal, or output the first control sub-signal based on the third electrical signal and the fifth electrical signal, or output the second control sub-signal based on the fourth electrical signal.

3. The circuit as described in claim 2, characterized in that, The signal recognition unit includes a first signal recognition branch, a second signal recognition branch, and a third signal recognition branch; The first signal identification branch includes a first AND gate, a first preset number of first frequency dividers, a first NOR gate, and a first D flip-flop, wherein: The first input terminal of the first AND gate is used to input the first electrical signal, the second input terminal of the first AND gate is used to input the reset pulse signal, and the output terminal of the first AND gate is electrically connected to the control terminal of each first frequency divider, the reset terminal of the first D flip-flop, and the input terminal of the first D flip-flop, respectively, to output the first enable signal; The input terminal of the first-stage first frequency divider is used to input the clock signal. For each other-stage first frequency divider, the input terminal of the other-stage first frequency divider is electrically connected to the output terminal of the adjacent previous-stage first frequency divider. The output terminal of the first frequency divider at the first preset position is also electrically connected to different input terminals of the first NOR gate. The output terminal of the first NOR gate is electrically connected to the clock terminal of the first D flip-flop to output a first intermediate signal, and the output terminal of the first D flip-flop is used to output the second electrical signal. The first preset quantity and the first preset position are determined based on the first preset duration and the period of the clock signal.

4. The circuit as described in claim 3, characterized in that, The second signal identification branch includes a first inverter, a second AND gate, a second preset number of second frequency dividers, a second NOR gate, and a second D flip-flop, wherein: The input terminal of the first inverter is used to input the first electrical signal. The output terminal of the first inverter is electrically connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to input a reset pulse signal. The output terminal of the second AND gate is electrically connected to the control terminal of each second frequency divider, the reset terminal of the second D flip-flop, and the input terminal of the second D flip-flop, respectively, and is used to output a second enable signal. The input terminal of the first-stage second frequency divider is used to input the clock signal. For each other-stage second frequency divider, the input terminal of the other-stage second frequency divider is electrically connected to the output terminal of the adjacent previous-stage second frequency divider. The output terminal of the second frequency divider at the second preset position is also electrically connected to different input terminals of the second NOR gate. The output of the second NOR gate is electrically connected to the clock terminal of the second D flip-flop to output the second intermediate signal, and the output of the second D flip-flop is used to output the third electrical signal. The second preset quantity and the second preset position are determined based on the second preset duration and the period of the clock signal.

5. The circuit as described in claim 4, characterized in that, The third signal identification branch includes a third preset number of third frequency dividers, third NOR gates, and third D flip-flops, wherein: The output terminal of the first inverter is also electrically connected to the control terminal of each third frequency divider, the reset terminal of the third D flip-flop, and the input terminal of the third D flip-flop, respectively, for outputting a third enable signal; The input terminal of the first-stage third frequency divider is used to input the clock signal. For each other-stage third frequency divider, the input terminal of the other-stage third frequency divider is electrically connected to the output terminal of the adjacent previous-stage third frequency divider. The output terminal of the third frequency divider at the third preset position is also electrically connected to different input terminals of the third NOR gate. The output of the third NOR gate is electrically connected to the clock terminal of the third D flip-flop to output a third intermediate signal. The output of the third D flip-flop is used to output the fourth electrical signal, wherein the fourth electrical signal is used as the second control sub-signal. The third preset quantity and the third preset position are determined based on the third preset duration and the period of the clock signal.

6. The circuit as described in claim 3, characterized in that, The signal processing unit includes a first OR gate, a third AND gate, a fourth frequency divider (a predetermined number of such dividers), a fourth NOR gate, and a fourth D flip-flop, wherein: The first input terminal of the first OR gate is used to input the second electrical signal, the second input terminal of the first OR gate is used to input the third electrical signal, and the output terminal of the first OR gate is electrically connected to the first input terminal of the third AND gate. The second input terminal of the third AND gate is used to input the reset pulse signal, and the output terminal of the third AND gate is electrically connected to the control terminal of each fourth frequency divider, the input terminal of the fourth D flip-flop, and the reset terminal of the fourth D flip-flop, respectively, to output the fourth enable signal; The input terminal of the first-stage fourth frequency divider is used to input the clock signal. For each other-stage fourth frequency divider, the input terminal of the other-stage fourth frequency divider is electrically connected to the output terminal of the adjacent previous-stage fourth frequency divider. The output terminal of the fourth frequency divider at the fourth preset position is also electrically connected to different input terminals of the fourth NOR gate. The output of the fourth NOR gate is electrically connected to the clock terminal of the fourth D flip-flop to output the fourth intermediate signal, and the output of the fourth D flip-flop is used to output the fifth electrical signal.

7. The circuit as described in claim 2, characterized in that, The signal output unit includes a second OR gate, a second inverter, and a fourth AND gate, wherein: The input terminal of the second inverter is used to input the fifth electrical signal, and the output terminal of the second inverter is electrically connected to the first input terminal of the fourth AND gate; The first input terminal of the second OR gate is used to input the second electrical signal, the second input terminal of the second OR gate is used to input the third electrical signal, and the output terminal of the second OR gate is electrically connected to the second input terminal of the fourth AND gate. The output of the fourth AND gate is used to output the first control sub-signal.

8. A gain control method, characterized in that, Applied to the gain control circuit as described in any one of claims 1 to 7, the method includes: The high-level duration and low-level duration of the first electrical signal output by the first shaping circuit are quantitatively determined, and the count value of the up-down counter is adjusted in steps according to the determination result to obtain the target digital signal representing the adjusted count value. The target digital signal is subjected to a digital-to-analog conversion operation to obtain a gain control signal, so that the variable gain amplifier adjusts its own gain value under the control of the gain control signal, wherein the count value of the up-down counter is positively correlated with the gain value; The step of quantitatively determining the high-level duration and low-level duration of the first electrical signal output by the first shaping circuit, and then adjusting the count value of the up / down counter in steps according to the determination results, includes: If the duration of the high level is greater than a first preset duration, or if the duration of the low level is greater than a second preset duration, the counter is controlled to perform a decrement operation. When the duration of the low level exceeds a third preset duration, the increment / decrement counter is controlled to perform an increment operation.

9. An infrared receiver, characterized in that, Includes the gain control circuit as described in any one of claims 1 to 7.

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