Distributed closed loop power control with VGA gain update

Abstract

A closed-loop power control (CLPC) system is disclosed, including a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes a first power amplifier, a first output power detector configured to detect a first output power level of the first power amplifier, and a first processor configured to determine a first analog gain of a first controller and a first gain of a first digital-to-analog converter based on a first cumulative error between the first output power level and the effective isotropic radiated power of a target. The second processor is configured to set a first variable gain of a first variable gain amplifier coupled to the input of the first power amplifier. The CLPC can be configured to control the gain of the first signal path individually or as a single signal path.

Description

Technical Field

[0001] The subject matter disclosed herein relates to wireless communication systems. More specifically, the subject matter disclosed herein relates to closed-loop power control (CLPC) systems that can be used to provide thermal compensation to the output stage of a transmitter. Background Technology

[0002] At fixed gain settings, heat generation can adversely affect millimeter-wave phased array integrated circuits by causing a reduction in effective isotropically radiated power (EIRP). Existing single-stage CLPC systems provide temperature compensation by adjusting the gain (dGain) of the digital-to-analog converter (DAC). The dGain range of the DAC is limited, and single-stage CLPC systems may fail to meet the target EIRP when the system temperature rises rapidly. Summary of the Invention

[0003] An example embodiment provides a closed-loop power control system, which may include a first power amplifier, a first output power detector, a first processor, and a second processor. The first output power detector may be configured to detect a first output power level P of the first power amplifier. det The first processor can be configured to determine the first analog gain G of the first controller. req The first gain dGain of the first digital-to-analog converter can be based on the first output power level P. det The first accumulated error between the effective isotropic radiated power of the target and the first accumulated error between the target and the target's effective isotropic radiated power. The second processor can be configured to set the first variable gain GC of the first variable gain amplifier coupled to the input of the first power amplifier. req In one embodiment, the first processor may also be configured to increase the first analog gain G. req The signal is transmitted to the first controller. In another embodiment, the first processor may also be configured to determine the first analog gain G. req And the first gain dGain, which can be based on the first output power level P det The first weighted cumulative error between the target EIRP and the target EIRP. In yet another embodiment, the first processor may also be configured to determine the first variable gain GC of the first VGA. req and the first variable gain GC req The data is transmitted to the first controller. In yet another embodiment, the second processor may also be configured to determine the first variable gain GC. req In one embodiment, the second processor can determine the first variable gain GC. reqIt can be based on the first output power level P det The second accumulated error between the target EIRP and the target EIRP. In another embodiment, the second processor can determine the first variable gain GC. req It can be based on the first output power level P det A second weighted cumulative error between the target EIRP and the target EIRP. In another embodiment, the system may include a first signal path for a first polarization and a second signal path for a second polarization, wherein the first signal path may include a first power amplifier, a first output power detector, a first processor, a first DAC, a first controller, and a second processor, and wherein the second signal path may include: a second power amplifier; and a second output power detector configured to detect a second output power level P of the second power amplifier. det The third processor can be configured to determine the second analog gain G of the second controller. req The second gain dGain of the second DAC can be based on the second output power level P. det The second accumulated error between the second VGA and the EIRP; and the fourth processor, which can be configured to set the second variable gain GC of the second VGA coupled to the input of the second power amplifier. req In another embodiment, the system may include a first signal path for a first polarization and a second signal path for a second polarization, wherein the first signal path may include a first power amplifier, a first output power detector, a first processor, a first controller, and a second processor, wherein the second signal path may include a second controller, a third processor, a second VGA, and a second power amplifier, and wherein the first processor may also be configured to increase the first analog gain G. req The data is transmitted to the second controller, and the third processor can also be configured to set the first variable gain GC of the second VGA coupled to the input of the second power amplifier. req In one embodiment, the first processor may also be configured to use a first variable-gain GC. req The signal is transmitted to a first controller and a second controller. In another embodiment, the system may include a first signal path for a first polarization and a second signal path for a second polarization, wherein the first signal path may include a first power amplifier, a first output power detector, a first processor, a first DAC, a first controller, and a second processor, wherein the second signal path may include a second DAC, a second controller, a third processor, a second VGA, and a second power amplifier, wherein the first analog gain G... req It may include the gain of the first signal path, the first gain dGain may include the gain of the first DAC and the gain of the second DAC, and the first variable gain GC reqThis may include the gain of the first VGA, wherein the first processor may also be configured to determine the second analog gain G of the second signal path. req The second variable gain GC of the second VGA req And where the second variable gain GC req It can be in the first variable gain GC req Within the predetermined difference.

[0004] An example embodiment provides a closed-loop power control system, which may include a first signal path for a first polarization and a second signal path for a second polarization, wherein the first signal path may include: a first power amplifier; and a first output power detector, which can be configured to detect a first output power level P of the first power amplifier. det The first processor can be configured to determine the first analog gain G of the first controller. req The first gain dGain of the first digital-to-analog converter can be based on the first output power level P. det The first accumulated error between the effective isotropic radiated power of the target and the first accumulated error between the target and the target's effective isotropic radiated power; and the second processor, which can be configured to set the first variable gain GC of the first variable gain amplifier coupled to the input of the first power amplifier. req In one embodiment, the first processor may also be configured to increase the first analog gain G. req The signal is transmitted to the first controller. In another embodiment, the first processor may also be configured to determine the first analog gain G. req And the first gain dGain, which can be based on the first output power level P det The first weighted cumulative error between the target EIRP and the target EIRP. In yet another embodiment, the first processor may also be configured to determine the first variable gain GC of the first VGA. req and the first variable gain GC req The data is transmitted to the first controller. In yet another embodiment, the second processor may also be configured to determine the first variable gain GC. req In one embodiment, the second processor can determine the first variable gain GC. req It can be based on the first output power level P det The second accumulated error between the target EIRP and the target EIRP. In another embodiment, the second processor can determine the first variable gain GC. req It can be based on the first output power level P det A second weighted cumulative error between the target EIRP and the target EIRP. In another embodiment, the second signal path may include: a second power amplifier; and a second output power detector, which can be configured to detect the second output power level P of the second power amplifier. detThe third processor can be configured to determine the second analog gain G of the second controller. req The second gain dGain of the second DAC can be based on the second output power level P. det The second accumulated error between the second VGA and the EIRP; and the fourth processor, which can be configured to set the second variable gain GC of the second VGA coupled to the input of the second power amplifier. req In another embodiment, the second signal path may include a second controller, a third processor, a second VGA, and a second power amplifier, wherein the first processor may also be configured to increase the first analog gain G. req The data is transmitted to the second controller, and the third processor can also be configured to set the first variable gain GC of the second VGA coupled to the input of the second power amplifier. req In one embodiment, the first processor may also be configured to use a first variable-gain GC. req It is transmitted to the first controller and the second controller. Attached Figure Description

[0005] In the following sections, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments shown in the accompanying drawings, wherein:

[0006] Figure 1 A block diagram depicts an example embodiment of a centralized CPLC system based on the subject matter disclosed herein;

[0007] Figure 2 A block diagram depicts an example embodiment of a distributed CLPC system based on the subject matter disclosed herein;

[0008] Figure 3A and Figure 3B Block diagrams of example embodiments of dual IF mode and single IF mode for CLPC systems based on the subject matter disclosed herein are depicted respectively.

[0009] Figure 4 This is a flowchart of an example embodiment of a method for a dual-IF mode centralized CLPC system (single-polarization) based on the subject matter disclosed herein;

[0010] Figure 5 This is a flowchart of an example embodiment of a method for a single-IF mode centralized CLPC system based on the subject matter disclosed herein;

[0011] Figure 6 This is an example embodiment of a method for a dual-IF mode distributed CLPC system for a second processor, based on the subject matter disclosed herein;

[0012] Figure 7This is an example embodiment of a method for a dual-IF mode distributed CLPC system (option 1) for a first processor, based on the subject matter disclosed herein;

[0013] Figure 8 This is an example embodiment of a method for a dual-IF mode distributed CLPC system (option 2) for a first processor, based on the subject matter disclosed herein;

[0014] Figure 9 This is an example embodiment of a method for a single-IF mode distributed CLPC system (Option 1) for a second processor, based on the subject matter disclosed herein;

[0015] Figure 10 This is an example embodiment of a method for a single-IF mode distributed CLPC system (Option 1) for a first processor, based on the subject matter disclosed herein;

[0016] Figure 11 This is an example embodiment of a method for a single-IF mode distributed CLPC system for a second processor, based on the subject matter disclosed herein;

[0017] Figure 12 This is an example embodiment of a method for a single-IF mode distributed CLPC system (option 2) for a first processor, based on the subject matter disclosed herein;

[0018] Figure 13 This is an example embodiment of a joint optimization method for dGain and H / V gain in a centralized CLPC system based on the subject matter disclosed herein (option 1).

[0019] Figure 14 This is an example embodiment of a centralized CLPC system, a joint optimization method for dGain and H / V gain in single-IF mode (option 2), based on the subject matter disclosed herein; and

[0020] Figure 15 Electronic devices that can include centralized CLPC systems and / or distributed CLPC systems according to the subject matter disclosed herein are described. Detailed Implementation

[0021] Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of this disclosure. However, those skilled in the art will understand that the disclosed aspects can be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the subject matter of this disclosure.

[0022] Throughout this specification, references to “an embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with that embodiment may be included in at least one embodiment disclosed herein. Therefore, the appearance of the phrases “in an embodiment,” “in an embodiment,” or “according to an embodiment” (or other phrases with similar meanings) throughout this specification may not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” should not be construed as necessarily preferred or advantageous over other embodiments. Additionally, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner. Moreover, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) are sometimes used interchangeably with their corresponding non-hyphenated versions (e.g., "two-dimensional", "pre-determined", "pixel specific", etc.), while uppercase terms (e.g., "counter clock", "row select", "pixout", etc.) are used interchangeably with their corresponding non-uppercase versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeability should not be considered inconsistent with each other.

[0023] Furthermore, depending on the context of the discussion herein, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms. It should also be noted that the various figures shown and discussed herein (including component diagrams) are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Additionally, reference numerals are repeated in the figures to denote corresponding and / or similar elements where appropriate.

[0024] The terminology used herein is for the purpose of describing some exemplary embodiments only and is not intended to limit the claimed subject matter. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. As used herein, the terms “first,” “second,” etc., are used as labels for the nouns they introduce and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless so explicitly defined. Furthermore, the same reference numerals may be used in two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, this usage is merely for simplification and ease of discussion; it does not imply that the construction or architectural details of these components or units are identical in all embodiments, or that these commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0025] It should be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," or "coupled to another component or layer," it can be directly on, directly connected to, or directly coupled to another component or layer, or there may be intermediate components or layers. In contrast, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," or "directly coupled to another component or layer," there are no intermediate components or layers. The same numbers always refer to the same component. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0026] As used herein, the terms “first,” “second,” etc., are used as labels for the nouns they introduce and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined otherwise. Furthermore, the same reference numerals may be used in two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functions. However, this usage is merely for simplicity of description and ease of discussion; it does not imply that the construction or architectural details of these components or units are identical in all embodiments, or that these commonly referenced parts / modules are the only way to implement some of the exemplary embodiments disclosed herein.

[0027] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject pertains. It should also be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0028] As used herein, the term "module" means any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with modules. For example, software may be embodied as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any implementation described herein may include, for example, assemblies, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware that store instructions executable by programmable circuitry, either individually or in any combination. These modules may be embodied collectively or separately as circuitry forming part of a larger system, such as, but not limited to, integrated circuits (ICs), system-on-a-chip (SoCs), assemblies, etc.

[0029] The subject matter disclosed herein relates to a multi-stage closed-loop power control (CLPC) system for temperature compensation, wherein a first processor and a second processor adjust the analog gain, dGain, and variable gain amplifier (VGA) based on power detection (PDET) readings so that the CLPC system meets a target EIRP.

[0030] In one embodiment, the multi-level CLPC system disclosed herein provides a centralized CLPC system in which a first processor determines analog gain, dGain, and VGA gain based on a single accumulated error between the PDET reading and the target EIRP, transmits the dGain to the IF stage, and transmits the VGA gain setting to the controller. In another embodiment, the multi-level CLPC system disclosed herein provides a distributed CLPC system in which a first processor adjusts the analog gain and dGain, and a second processor adjusts the VGA gain. In the second embodiment, the first and second processors can adjust the respective adjustments based on the single accumulated error between the PDET reading and the target EIRP.

[0031] In the following description, Indicates the VGA gain index GC i The corresponding cumulative VGA gain, and GC cal and DAC set_cal These represent the GC index and DAC value used in the calibration, respectively.

[0032] Figure 1 A block diagram illustrating an example embodiment of a centralized CPLC system 100 according to the subject matter disclosed herein is depicted. The centralized CPLC system 100 includes a modem 101, a central RFIC 102, a controller 103, a first adder 109, a second adder 110, and a multiplier 111. The modem 101 includes a first processor 104. The controller 103 includes a second processor 105, a VGA 106, a power amplifier (PA) 107, and a power detector (PDET) 108. The various components forming the centralized CPLC system 100 may be individual components and / or modules, and / or may be combined into one or more components and / or modules.

[0033] Modem 101 receives target power value P target and cumulative error value αP acc and outputs DAC gain value to the central RFIC 102. req Modem 101 also outputs GC to controller 103. req Value and G req The central RFIC outputs an IF signal to the controller 103. The PDET 108 of the controller 103 outputs the power detection value P to the first adder 109. det.read The first adder 109 also receives the target power value P. target and outputs P to the second adder 110. tarqet With P det.read The difference Δ between PC The second adder 110 outputs the cumulative power error value P. acc The cumulative power error value P acc It is the previous power error value P acc Add Δ weighted by the gain value β PC Value. Cumulative power error value P acc Then, multiply by the loop gain α at multiplier 111 to form αP. acc αP acc It was input to modem 101.

[0034] For temperature compensation, centralized CLPC has αP-based acc，centralized Updated VGA gain and DAC dGain values ​​allow the actual EIRP to smoothly converge to the target value. However, Figure 1 A centralized CLPC system 100 may involve a large number of commands to notify the second processor 105 in the controller 103 of the updated VGA gain selection.

[0035] To reduce the number of commands, the subject matter disclosed herein also provides a distributed CLPC, in which a second processor 105 in controller 103 selects the VGA gain, and a first processor 104 in modem 101 selects the analog gain and DAC dGain value to meet a target EIRP. The second processor 105 selects the VGA gain from a VGA gain table based on errors accumulated at controller 103. The first processor 104 selects the analog gain according to the target EIRP and selects the DAC dGain value based on errors accumulated at modem 101. The distributed CLPC disclosed herein is provided for both dual-IF and single-IF modes. In one embodiment, the distributed CLPC disclosed herein provides the same performance for temperature compensation as the centralized CLPC system 100, but utilizes a reduced number of commands. Compared to conventional single-stage CLPC systems, the centralized and distributed CLPCs disclosed herein also meet target power requirements for larger temperature variations. When temperatures rise rapidly, conventional single-stage CLPC systems may not meet the target EIRP due to limited DAC range. Using the centralized and distributed CLPC systems disclosed in this paper, the target EIRP can always be satisfied by a relatively small range of DAC dGain values.

[0036] Figure 2 A block diagram illustrating an example embodiment of a distributed CLPC system 200 according to the subject matter disclosed herein is depicted. The distributed CLPC system 200 includes a modem 201, a central RFIC 202, a controller 203, a first adder 209, a second adder 210, a first multiplier 211, a third adder 212, a fifth adder 213, a sixth adder 214, and a second multiplier 215. The modem 201 includes a first processor 204. The controller 203 includes a second processor 205, a VGA 206, a PA 207, and a PDET 208. The various components forming the distributed CLPC system 200 can be individual components and / or modules, and / or can be combined into one or more components and / or modules.

[0037] Modem 201 receives target power value P target and cumulative error value αP acc，FProc And output the DAC dGain value to the central RFIC 202. req Modem 201 also outputs G to controller 203. req The central RFIC 202 outputs an IF signal to the controller 203. The PDET 208 of the controller 203 outputs the power detection value P to the first adder 209. det.read The first adder 209 also receives the target power value P. target and outputs P to the second adder 210.target With P det.read The difference Δ between PC The second adder 210 outputs the cumulative power error value P. acc The cumulative power error value P acc It is the previous power error value P acc Add Δ weighted by the gain value β PC Value. Cumulative power error value P acc Then, at multiplier 211, the loop gain value α is multiplied to form αP. acc，SProc αP acc，SProc It is input into the second processor 205. P target It is also input into the second processor 205.

[0038] The third adder 212 receives the power detection value P. det.read and ΔG output from the second processor 205 VGA The third adder 212 outputs the adjusted power detection signal to the fourth adder 213. The fourth adder 213 outputs the Δ signal updated by the fifth adder 214. PC Signal to form P acc，FProc P acc，FProc Multiply by α at the second multiplier 215 to form αP acc，FProc αP acc，FProc It is input into the first processor 204.

[0039] CLPC system 100 and CLPC system 200 can operate in dual IF mode or single IF mode. Figure 3A and Figure 3B Block diagrams of example embodiments of a dual-IF mode 300 and a single-IF mode 350 for a CLPC system, based on the subject matter disclosed herein, are depicted respectively. Figure 3A and Figure 3B The text depicts a portion of the central RFIC 102 / 202 and a portion of the controller 103 / 303.

[0040] RFIC 102 / 202 includes DAC 301 H and 301 V DAC 301 H Receives baseband H signal BB_H. DAC 301 V Receives baseband V signal BB_V. DAC 301 H and 301 V The corresponding outputs are routed to the controller terminal 304 via RFIC terminals 302H and 302V. H and 304 V Transmission line 303 H and 303 VThe input is then sent to controller 103 / 203. In one embodiment, controller 103 / 203 includes a first double-pole, single-throw (DPST) switch 305. H Second DPST switch 305 V First mixer 306 H Second mixer 306 V First power amplifier 307 H Second power amplifier 307 V The two DPST switches 305H and 305V allow either the IF_H signal or the IF_V signal to be selected for operation in single IF mode. In an alternative embodiment, one of the two DPST switches 305 can be replaced by a single-pole, single-throw (SPST) switch, in which case the IF signal path including the DPST switch 305 will be the IF polarization controlled by the CPLC for both IF channels.

[0041] In dual IF mode, the first DPST switch 305 can be controlled. H This causes the IF_H signal to pass through the first DPST switch 305. H Reaching the first mixer 306 H and the first power amplifier 307 H Similarly, the second DPST switch 305 can be controlled. V This causes the IF_V signal to pass through the second DPST switch 303. y Reaching the second mixer 306 V Second power amplifier 307 V In single IF mode, the first DPST switch 305 can be controlled. H The second DPST switch 305V couples the IF_H signal to the mixer 306. H and 306 V Both, while the IF_V signal comes from mixer 306 V disconnect.

[0042] In other words, in dual-IF mode, both data streams are enabled, and IF_H and IF_V can have different information. In single-IF mode, only one data stream is transmitted from both the H and V antennas. Since the H and V paths can separately select analog gain, VGA gain, and dGain in dual-channel IF mode, the following description focuses on the single IF path, as the other polarization works in a similar manner.

[0043] Figure 4This is a flowchart of an example embodiment of a method 400 for a dual-IF mode centralized CLPC system (single-polarization) according to the subject matter disclosed herein. Modem 101 periodically issues PDET read commands. At 401, a second processor 105 determines whether modem 101 has issued a PDET read command. If not, the process remains at 401. If yes, the process continues to 402, where PDET 108 is read to obtain P... det，read Additionally, at 402, Δ PC Updated by the first adder 109

[0044] Δ PC =P target -P det，read (1)

[0045] And the second adder 110 will P acc，centralized Updated to

[0046] P acc，centralized =P acc，centralized +βΔ PC (2)

[0047] Where β is based on the size of the resource block (RB) and is described in conjunction with equation (12).

[0048] At 403, the first processor 104 is based on the following equation from the VGA gain table. Select VGA gain index GC req

[0049]

[0050] In 404, DAC dB_normal Determined by the first processor 104 as

[0051]

[0052] Where α is the loop gain. P acc，centralized The multiplier 111 is multiplied by α to form αP acc，centralized ( Figure 1 αP in acc ).

[0053] In 405, DAC req Determined by the first processor 104 as

[0054] DAC req =max(min(DAC) dB_normal DAC max ), DAC min (5)

[0055] In 406, the first processor 104 will perform GC. req Set to the selected VGA gain index and set GC req and G req The data is transmitted to controller 103. The first processor 104 will also transmit the data to the DAC. req The signal is transmitted to the central RFIC 102. The controller 103 sends a Tx signal, and the process returns to 401.

[0056] Figure 5 This is a flowchart of an example embodiment of a method 500 for a single-IF mode centralized CLPC system according to the subject matter disclosed herein. Modem 101 periodically issues PDET read commands. At 501, a second processor 105 determines whether modem 101 has issued a PDET read command. If not, the process remains at 501. If yes, the process continues to 502, where PDET 108 is read to obtain P... det，read Additionally, at 502, Δ PC Updated by the first adder 109

[0057]

[0058] Where P target This refers to the target power for H+V. P acc，centralized ( Figure 1 P in acc ) was updated by the second adder 110 to

[0059] P acc，centralized =P acc，centralized +βΔ PC (7)

[0060] In 503, the first processor 104 selects the VGA gain index GC for H-polarization. req，H and VGA gain index GC for V-polarization req，V ,as follows

[0061]

[0062]

[0063] In 504, the first processor 104 is based on P. lookup =P target -3 Select the gain index G for H from the H / V gain table. req，H and the gain index G for V req，V In the 505, the first processor 104 will connect the DAC. dB_nomal Determined as

[0064]

[0065] In 506, the first processor 104 will integrate the DAC. req Determined as

[0066] DAC req =max(min(DAC) aB_normal DAC max ), DAC min (11)

[0067] In 507, the first processor 104 sets the GC for H based on the selected VGA gain index. req，H and GC for V req，V And GC req，H GC req，V G req，H and G req，V It is transmitted to controller 103. The first processor 104 will also transmit the DAC... req Transmitted to central RFIC 102. The Tx signal is sent, and the process returns to 501.

[0068] For the distributed CLPC system 200, the second processor 205 selects the VGA gain index GC. req And the first processor 204 selects the analog gain index G. req and dGain DAC req To meet the target power. Such as the GC used in this article. cal and DAC set_cal These represent the VGA gain index and DAC value used in the calibration, respectively.

[0069] Different weights β can be used to accumulate the error between PDET and the target power. The weights β can be determined based on the resource block (RB) size, for example,

[0070]

[0071] Based on equation (12), the larger the value of RB, the greater the error accumulation. Unless otherwise specified, the loop gain α can be fixed, for example, α = 1 / 16.

[0072] Figure 6 This is an example embodiment of a method 600 for a dual-IF mode distributed CLPC system for a second processor (SProc) 205, based on the subject matter disclosed herein. Modem 201 periodically issues PDET read commands. At 601, the second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 601. If yes, the process continues to 602, where PDET 208 is read to obtain P...det，read Additionally, at 602, Δ PC The first adder 209 was updated to

[0073] Δ PC =P target -P det，read (13)

[0074] And the second adder 210 will P acc，SProc Updated to

[0075] P acc，SProc =P acc，SProc +βΔ PC (14)

[0076] β is based on the resource block (RB) size and is described in conjunction with equation (12).

[0077] In 603, the second processor 205 is based on the following equation from the VGA gain table. Select VGA gain index GC req

[0078]

[0079] In 604, the second processor 205 will ΔG VGA Determined as

[0080]

[0081] ΔG VGA It is provided to the first processor 204. In 605, the second processor 205 will perform GC. req Set to the selected VGA gain index. Controller 203 is configured with G received from the first processor 204. req And the Tx signal is sent. The process returns to 601.

[0082] Figure 7 This is an example embodiment of a method 700 for a dual-IF mode distributed CLPC (Option 1) for a first processor (FProc) 204, based on the subject matter disclosed herein. Modem 201 periodically issues PDET read commands. At 701, second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 701. If yes, the process continues to 702, where P... det，read，adj Determined by the third adder 212 as

[0083] P det，read，adj =P det，read +ΔG VGA / αβ (17)

[0084] The fourth adder 213 will Δ PC Updated to

[0085] Δ PC =P tarqet -P det，read，adj (18)

[0086] And, the fifth adder 214 will P acc，FProc Updated to

[0087] P acc，FProc =P acc，FProc +βΔ PC (19)

[0088] In the 703, the first processor 204 is based on P. lookup =P target Select the gain index G from the gain table. req In 704, the first processor 204 will connect the DAC. dB_normal Determined as

[0089]

[0090] In the 705, the first processor will have a DAC req Determined as

[0091] DAC req =max(min(DAC) dB_normal DAC max ), DAC min ) (twenty one).

[0092] In the 706, the first processor will G req The data is transmitted to controller 203, and the DAC is... req Transmitted to central RFIC 202. The Tx signal is sent, and the process returns to 701.

[0093] Methods 600 and 700 do not necessarily use the same α and β to apply to the second processor 205 and the first processor 204. However, it may still be desirable to have similar α. FProc P acc，FProc α SProc P acc，SProc This allows the DAC in the central RFIC 402 to operate within a relatively small range. Method 700 at the first processor 204 can be exactly the same as an existing Level 1 CLPC system without VGA gain updates; for distributed CLPCs, VGA gain updates are provided at 603 in method 600.

[0094] As an alternative to method 700, the first processor 204 can independently track the accumulated VGA gain P. acc，FProcThis alternative is referred to as Option 2 in this article. Figure 8 This is an example embodiment of method 800 for a dual-IF mode distributed CLPC system (option 2) for a first processor (FProc) according to the subject matter disclosed herein. Note that options 1 and 2 are essentially equivalent except for implementation details, wherein for option 2, the first processor 204 tracks the accumulated VGA gain and accumulates P without adjusting the PDET reading. acc，FProc This was not done in option 1.

[0095] Modem 201 periodically issues PDET read commands. Figure 8 In step 801, the second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 801. If yes, the process continues to 802, where the first processor 204 or an adder (not shown) will G VGA Determined as

[0096] G VGA =G VGA，prev +ΔG VGA (twenty two),

[0097] Δ PC Updated by the first processor 204 or the adder (not shown)

[0098] Δ PC =P tarqet -P det，read，H (23), and

[0099] P acc，FProc Updated by the first processor 204 or the adder (not shown)

[0100] P acc，FProc =P acc，FProc +βΔ PC (twenty four).

[0101] In the 803, the first processor 204 is based on P lookup =P target Select the gain index G from the gain table. req In the 804, the first processor 204 will connect the DAC. dB_normal Determined as

[0102]

[0103] In the 805, the first processor 204 will integrate the DAC. req Determined as

[0104] DAC req =max(min(DAC) dB_normal DACmax ), DAC min (26)

[0105] In the 806, the first processor will G req The data is transmitted to controller 203, and the DAC is... req Transmitted to central RFIC 202. The Tx signal is sent, and the process returns to 801.

[0106] As an alternative to methods 600 and 700, instead of providing the PDET reading and incremental VGA gain separately, the second processor 205 can directly provide the regulated PDET reading to the first processor 204. This is equivalent to providing the regulated PDET reading (P...) to the first processor 204 at 702 in method 700. det，read，adj The determination of ) is moved to method 600 and executed by the second processor 205.

[0107] For single IF mode, the same dGain can be applied to both H-polarization and V-polarization. That is, the second processor 205 can individually select the VGA gain index (GC) for H. req，H ) and VGA gain index for V (GC) req，V Furthermore, the first processor 204 can individually select the analog gain (G) for H. req，H ) and analog gain for V (G req，V ) and dGain (DAC req To meet the H+V power target. For Option 1 in Single IF mode, the second processor 205 can provide the first processor 204 with incremental VGA gain for H+V.

[0108] Figure 9 This is an example embodiment of method 900 for a single-IF mode distributed CLPC system (Option 1) for a second processor (SProc) 205, according to the subject matter disclosed herein. Modem 201 periodically issues PDET read commands. At 901, the second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 901. If yes, the process continues to 902, where PDET 208 is read to obtain P. det，read Additionally, Δ PC Updated by the first adder 209

[0109]

[0110] And P acc，SProc Updated by the second adder 210

[0111] P acc，SProc =P acc，SProc +βΔPC (26)

[0112] Where P target It is the target power for H+V polarization.

[0113] In 903, the second processor 205 selects the VGA gain index GC for H based on the following equation: req，H and VGA gain index GC for V req，V

[0114] as well as

[0115]

[0116] In 904, G VGA，H+V and ΔG VGA，H+V Determined by the second processor 205

[0117]

[0118] and

[0119] ΔG VGA，H+V =G VGA，H+V -G VGA，H+V，prev (30)

[0120] ΔG VGA，H+V It is transmitted to the first processor 204. At 905, the second processor 20 sets the VGA gain index to GC for H. req，H For V, set the VGA gain index to GC. req，V The Tx signal is sent, and the process returns to 901.

[0121] Figure 10 This is an example embodiment of method 1000 for a single-IF mode distributed CLPC system (option 1) for a first processor (FProc) 204, according to the subject matter disclosed herein. Modem 201 periodically issues PDET read commands. At 1001, second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 1001. If yes, the process continues to 1002, where P... det，read，adj，H and P det，read，adj，V Determined by the third adder 212 as

[0122]

[0123]

[0124] Δ PC Updated by the fourth adder 213

[0125] as well as

[0126] P acc，FProc Updated by the fifth adder 215

[0127] P acc，FProc =P acc，FProc +βΔ PC (34)

[0128] Where P target It refers to the target power for H+V.

[0129] In 1003, the first processor 204, according to P lookup =P target -3 Select the gain index G for H from the H / V gain table. req，H and the gain index G for V req，V In 1004, the first processor 204 will connect the DAC. dB_normal Determined as

[0130]

[0131] In 1005, the first processor 204 will use the DAC req Determined as

[0132] DAC req =max(min(DAC) dB_normal DAC max ), DAC min (36).

[0133] In 1006, the first processor 204 will target H's G. req，H and G against V req，V The data is transmitted to the second processor 205, and the DAC is... req Transmitted to central RFIC 202. The Tx signal is sent, and the process returns to 1001.

[0134] It should be noted that for Option 1, when the analog gain and VGA gain for H and V are different, some spikes may appear in the output power when the VGA gain selection is changed. In Option 2, the second processor 205 provides ΔG to the first processor 204. VGA，H and ΔG VGA，V Once this information is received, the first processor 204 can track the adjusted VGA gain for the VGA gain used in calibration. This ensures that the VGA gain and dGain are updated consistently based on the accumulated error, thereby avoiding output power spikes that may occur in Option 1.

[0135] Figure 11This is an example embodiment of method 1100 for a single-IF mode distributed CLPC system (option 2) for a second processor (SProc) according to the subject matter disclosed herein. Modem 201 periodically issues PDET read commands. At 1101, the second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 1101. If yes, the process continues to 1102, where the PDET is read to obtain the P... det，read In addition, Δ PC Updated by the first adder 209

[0136]

[0137] And P acc，SProc Updated by the second adder 201

[0138] P acc，SProc =P acc，SProc +βΔ PC (38)

[0139] Where P target It is the target power for H+V polarization.

[0140] At 1103, the second processor 205 selects the VGA gain index GC for H based on the following equation: req，H and VGA gain index GC for V req , V

[0141] as well as

[0142]

[0143] In 1104, the second processor 205 will G VGA，H+V and ΔG VGA，H+V Determined as

[0144] as well as

[0145]

[0146] The second processor 205 provides ΔG to the first processor 204. VGA，H and ΔG VGA，V In step 1105, the second processor 205 sets the VGA gain index to GC for H. req，H and GC for V req，V The Tx signal is sent, and the process returns to 1101.

[0147] Figure 12This is an example embodiment of method 1200 for a single-IF mode distributed CLPC system (option 2) for a first processor (FProc) 404, according to the subject matter disclosed herein. Modem 201 periodically issues PDET read commands. At 1201, second processor 205 determines whether a PDET read command has been issued. If not, the process remains at 1201. If yes, the process continues to 1202, where G... VGA，H and G VGA，V Determined by a separate adder (not shown)

[0148] G VGA，H =G VGA，H，prev +ΔG VGA，H (43), and

[0149] G VGA，V =G VGA，V，prev +ΔG VGA，V (44)

[0150] Δ PC The adder (not shown) is updated to

[0151] as well as

[0152] P acc，FProc Updated by another adder (not shown)

[0153] P acc，FProc =P acc，FProc +βΔ PC (46)

[0154] Where P target It refers to the target power for H+V.

[0155] In 1203, the first processor 204, according to P lookup =P target -3 Select the gain index G for H from the H / V gain table. req，H and the gain index G for V req，V In 1204, the first processor 204 will connect the DAC. dB_normal Determined as

[0156]

[0157] At 1205, the first processor 204 will use the DAC req Determined as

[0158] DAC req =max(min(DAC) dB_normal DAC max ), DAC min (48).

[0159] In 1206, the first processor will target H's G. req，H and targeting VG req，V The data is transmitted to the controller 203 and the DAC is... req Transmitted to central RFIC 402. The Tx signal is sent, and the process returns to 1201.

[0160] A comparison between Option 1 and Option 2 shows that in Option 2, the first processor 204 tracks the updated VGA gain in 1102, allowing the DAC value to be selected accordingly in 1103, which is not the case in Option 1. This ensures equivalence to a centralized CLPC process and can be expected to result in smooth convergence. Option 2 is equivalent to a centralized CLPC process and can be superior to Option 1. Options 1 and 2 can be equivalent if the selected analog gain or VGA gain is the same for H and V. Option 2 does not involve applying the same α or β to the second processor 205 and the first processor 204. However, it may be desirable to have similar α. FProc P acc，FProc and α SProc P acc，SProc This allows dGain to be adjusted within a small range. If α SProc P acc，SProc If α is relatively small, VGA gain updates may be slower, and dGain may primarily be used for temperature compensation until dGain saturates. SProc P acc，SProc If the value is relatively large, the VGA gain may be significantly compensated, to the point that dGain may back off significantly until dGain is out of the operating range.

[0161] Figure 13 This is an example embodiment of method 1300 for joint optimization of dGain and H / V gain in a centralized CLPC system, single IF mode (option 1), based on the subject matter disclosed herein. The focus of method 1300 is to drive power for both H-polarization and V-polarization to a target power, but also to ensure that the power for H-polarization and V-polarization has similar values, i.e., a balanced power for H-polarization and V-polarization. Figure 13 In this process, modem 101 periodically issues PDET read commands. At 1301, second processor 105 determines whether a PDET read command has been issued. If not, the process remains at 1301. If yes, the process continues to 1302, where PDET 108 is read to obtain P. det，read，H and P det，read，V Additionally, at 1302, Δ PC，H and Δ PC，VThe adder (not shown, but corresponding to the first adder 109) is updated to

[0162] Δ PC，H =P target -P det，read，H -ε H (49), and

[0163] Δ PC，V =P target -P det，read，V -ε V (50)

[0164] Where P target It is the target power of a single polarization, and ε H and ε V These are the bias terms for H-polarization and V-polarization, respectively.

[0165] Also at 1302, an additional adder (not shown, but corresponding to the second adder 110) will P acc，H and P acc，V Updated to

[0166] P acc，H =P acc，H +βΔ PC，H (51), and

[0167] P acc，V =P acc，V +βΔ PC，V (52).

[0168] In step 1303, the first processor 104 determines the GC based on the following equation. req，H and GC req，V

[0169]

[0170] in and

[0171] If such a solution does not exist, the first processor 105 determines GC based on the following equation. req，H and GC req，V

[0172]

[0173] In 1304, the first processor 105 is based on P. lookup =P target Select the target for G from the VGA lookup table. req，H and G req，V Gain index.

[0174] At 1305, the first processor 105 will integrate the DAC. dB_normal Determined as

[0175] DAC dB_normal =DAC set_cal +dGain, (55)

[0176] in

[0177] At 1306, the first processor 104 will set the bias term ε H and ε V Determined as

[0178] ε H =αP acc，H -G VGA，H (GC H )-dGain (56), and

[0179] ε V =-ε H (57)

[0180] Bias term ε H and ε V It provides indications of how far the H power value and V power value are from the target power value. For example, if ε H If the bias is 0.5dB, the system will drive the H power value approximately 0.5dB higher than the target power value and the V power value approximately 0.5dB lower than the target power value. The bias term tends to eliminate spikes in power operation.

[0181] In 1307, the first processor will use the DAC req Determined as

[0182] DAC req =max(min(DAC) dB_normal DAC max ), DAC min (58).

[0183] In 1308, the first processor 104 will perform GC for H-polarization and V-polarization respectively. req，H and GC req，V Set to the selected VGA gain, both of which are related to the gain for G. req，H and G req，V The gain index is sent together with the DAC data to controller 103. The first processor 104 also sends the DAC data to controller 103. req The signal is transmitted to the central RFIC 102. The Tx signal is sent by the controller 103, and the process returns to 1301.

[0184] Figure 14This is an example embodiment of method 1400 for joint optimization of dGain and H / V gain in a centralized CLPC system, single IF mode (option 2), based on the subject matter disclosed herein. Option 2 differs from Option 1 (i.e., method 1300) in that it determines the H-polarized VGA gain and V-polarized VGA gain separately, which reduces complexity at the cost of a potentially slightly increased power difference between H-polarized and V-polarized. For a given VGA gain step size Δ, Option 2 provides a power difference of less than Δ / 2 for H-polarized and V-polarized.

[0185] exist Figure 14 In this process, modem 101 periodically issues PDET read commands. At 1401, second processor 105 determines whether a PDET read command has been issued. If not, the process remains at 1401. If yes, the process continues to 1402, where PDET 108 is read to obtain P. det，read，H and P det，read，V Additionally, at 1402, Δ PC，H and Δ PC，V The adder (not shown, but corresponding to the first adder 109) is updated to

[0186] Δ PC，H =P target -P det，read，H -ε H (59), and

[0187] Δ PC，V =P target -P det，read，V -ε V (60)

[0188] Where is P target For a target power of a single polarization, ε H and ε V These are the bias terms for H-polarization and V-polarization, respectively.

[0189] Also at 1402, an additional adder (not shown, but corresponding to the second adder 110) will P acc，H and P acc，V Updated to

[0190] P acc，H =P acc，H +βΔ PC，H (61), and

[0191] P acc，V =P acc，V +βΔ PC，V (62)

[0192] In 1403, if P acc，H <Pacc，V Then the first processor 101 will GC req，H and GC req，v Determined as

[0193] as well as

[0194]

[0195] If P acc，H ≥P acc，V Then the first processor 101 will GC req，V and GC req，H Determined as

[0196] as well as

[0197]

[0198] In 1404, the first processor 105 is based on P lookup =P target Select the target for G from the VGA lookup table. req，H and G req，V Gain index.

[0199] At 1405, the first processor 105 will connect the DAC. dB_normal Determined as

[0200] DAC dB_normal =DAC set_cal +dGain (67),

[0201] in

[0202] At 1406, the first processor 104 will set the bias term ε H and ε V Determined as

[0203] ε H =αP acc，H -G VGA，H (GC H )-dGain (68), and

[0204] ε V =-ε H (69)

[0205] In 1407, the first processor will DAC req Determined as

[0206] DAC req =max(min(DAC) dB_normal DAC max ), DACmin (70).

[0207] In 1408, the first processor 104 will perform GC for polarizations H and V respectively. req，H and GC req，V Set to the selected VGA gain, both of which are related to the gain for G. req，H and G req，V The gain index is sent together with the DAC data to controller 103. The first processor 104 also sends the DAC data to controller 103. req The signal is transmitted to the central RFIC 102. The Tx signal is sent by the controller 103, and the process returns to 1301.

[0208] Figure 15 An electronic device 1500, which may include a centralized CLPC system and / or a distributed CLPC system, is depicted according to the subject matter disclosed herein. The electronic device 1500 and its various system components may be formed from one or more modules. The electronic device 1500 may include a controller (or CPU) 1510, input / output devices 1520 (such as, but not limited to, a keypad, keyboard, display, touchscreen display, 2D image sensor, 3D image sensor), memory 1530, interface 1540, GPU 1550, image processing unit 1560, neural processing unit 1570, and TOF processing unit 1580, which are coupled to each other via bus 1590. The controller 1510 may include, for example, at least one microprocessor, at least one digital signal processor, at least one microcontroller, etc. The memory 1530 may be configured to store command codes to be used by the controller 1510 and / or to store user data.

[0209] Interface 1540 may be configured to include a wireless interface configured to transmit or receive data from, for example, a wireless communication network using RF signals. In one embodiment, wireless interface 1540 may include a centralized or distributed CLPC system according to the subject matter disclosed herein. Wireless interface 1540 may include, for example, an antenna.Electronic device 1500 can also be used for communication interface protocols of communication systems, such as, but not limited to, Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Communications (NADC), Extended Time Division Multiple Access (ETDMA), Wideband CDMA (WCDMA), CDMA2000, WiFi, Municipal WiFi (Muni WiFi), Bluetooth, Digital Enhanced Cordless Telecommunications (DECT), Wireless UniVersal Serial Bus (Wireless USB), Fast-latency access with seamless handoff Orthogonal Frequency Division Multiplexing (Flash-OFDM), IEEE 802, General Packet Radio Service (GPRS), iBurst, and Wireless Broadband. Broadband (WiBro), WiMAX, WiMAX Advanced, Universal Mobile Telecommunication Service - Time Division Duplex (UMTSTDD), High Speed ​​Packet Access (HSPA), Evolution Data Optimized (EVDO), Long Term Evolution-Advanced (LTE-Advanced), Multichannel Multipoint Distribution Service (MMDS), Fifth Generation Wireless (5G), Sixth Generation Wireless (6G), and so on.

[0210] Embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuits, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their equivalents), or in a combination of one or more of these. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more computer program instruction modules encoded on a computer storage medium for execution by or control of the operation of a data processing apparatus. Alternatively or additionally, program instructions may be encoded on artificially generated propagated signals (e.g., machine-generated electrical, optical, or electromagnetic signals) generated to encode information for transmission to a suitable receiver device for execution by the data processing apparatus. The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or may be included therein. Furthermore, although the computer storage medium is not a propagated signal, it may be a source or destination of computer program instructions encoded in artificially generated propagated signals. The computer storage medium may also be one or more separate physical components or media (e.g., multiple CDs, discs, or other storage devices), or may be included therein. In addition, the operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0211] While this specification may contain numerous specific implementation details, these details should not be construed as limiting the scope of any claimed subject matter, but rather as descriptions of features characteristic of particular embodiments. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations, and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0212] Similarly, although operations are described in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or requiring all illustrated operations to be performed to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0213] Therefore, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still yield the desired result. Furthermore, the processes described in the drawings do not necessarily require the specific order or sequence shown to obtain the desired result. In some embodiments, multitasking and parallel processing may be advantageous.

[0214] As those skilled in the art will recognize, the innovative concepts described herein can be modified and varied across a wide range of applications. Therefore, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but is defined by the appended claims.

Claims

1. A closed-loop power control system, comprising: First power amplifier; A first output power detector is configured to detect the first output power level of the first power amplifier. ; The first processor is configured to operate based on the first output power level. The first accumulated error between the target's effective isotropic radiated power (EIRP) and the target's effective isotropic radiated power (EIRP) determines the first analog gain used for the first controller. and the first gain for the first digital-to-analog converter (DAC) The first cumulative error is weighted based on the resource block size; as well as The second processor is configured to set the first variable gain of the first variable gain amplifier VGA coupled to the input of the first power amplifier. .

2. The closed-loop power control system according to claim 1, wherein, The first processor is also configured to increase the first analog gain. It is transmitted to the first controller.

3. The closed-loop power control system according to claim 1, wherein, The first processor is also configured to operate based on the first output power level. The first weighted cumulative error between the target EIRP and the target EIRP determines the first analog gain. and the first gain .

4. The closed-loop power control system according to claim 1, wherein, The first processor is also configured to determine the first variable gain of the first VGA. and the first variable gain It is transmitted to the first controller.

5. The closed-loop power control system according to claim 1, wherein, The second processor is also configured to determine the first variable gain. The value of .

6. The closed-loop power control system according to claim 5, wherein, The second processor is based on the first output power level The first variable gain is determined by the second cumulative error between the target EIRP and the target EIRP. .

7. The closed-loop power control system according to claim 5, wherein, The second processor is based on the first output power level The first variable gain is determined by the second weighted cumulative error between the target EIRP and the target EIRP. .

8. The closed-loop power control system according to claim 1, wherein, The system includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes the first power amplifier, the first output power detector, the first processor, the first DAC, the first controller, and the second processor. The second signal path includes: Second power amplifier; The second output power detector is configured to detect the second output power level of the second power amplifier. ; The third processor is configured based on the second output power level. The second accumulated error between the target EIRP and the target EIRP determines the second analog gain for the second controller. and the second gain for the second DAC ;as well as A fourth processor is configured to set a second variable gain of a second VGA coupled to the input of the second power amplifier. .

9. The closed-loop power control system according to claim 1, wherein, The system includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes the first power amplifier, the first output power detector, the first processor, the first controller, and the second processor. The second signal path includes a second controller, a third processor, a second VGA, and a second power amplifier. The first processor is further configured to convert the first analog gain The data is transmitted to the second controller, and the third processor is further configured to set a second variable gain of the second VGA coupled to the input of the second power amplifier. .

10. The closed-loop power control system according to claim 9, wherein, The first processor is also configured to transfer the first variable gain It is transmitted to the first controller and the second controller.

11. The closed-loop power control system according to claim 1, wherein, The system includes a first signal path for a first polarization and a second signal path for a second polarization. The first signal path includes the first power amplifier, the first output power detector, the first processor, the first DAC, the first controller, and the second processor. The second signal path includes a second DAC, a second controller, a third processor, a second VGA, and a second power amplifier. Wherein, the first analog gain Including the gain for the first signal path, the first gain Includes the gain for the first DAC and the gain for the second DAC, and the first variable gain Including the gain of the first VGA, and The first processor is further configured to determine a second analog gain for the second signal path. and the second variable gain for the second VGA The second variable gain In the first variable gain Within the predetermined difference.

12. A closed-loop power control system, comprising: A first signal path for a first polarization and a second signal path for a second polarization, wherein the first signal path includes: First power amplifier; A first output power detector is configured to detect the first output power level of the first power amplifier. ; The first processor is configured to operate based on the first output power level. The first accumulated error between the target's effective isotropic radiated power (EIRP) and the target's effective isotropic radiated power (EIRP) determines the first analog gain used for the first controller. and the first gain for the first digital-to-analog converter (DAC) The first accumulated error is weighted based on the resource block size; and The second processor is configured to set the first variable gain of the first variable gain amplifier VGA coupled to the input of the first power amplifier. .

13. The closed-loop power control system according to claim 12, wherein, The first processor is also configured to increase the first analog gain. It is transmitted to the first controller.

14. The closed-loop power control system according to claim 12, wherein, The first processor is also configured to operate based on the first output power level. The first weighted cumulative error between the target EIRP and the target EIRP determines the first analog gain. and the first gain .

15. The closed-loop power control system according to claim 12, wherein, The first processor is also configured to determine a first variable gain of the first VGA. and the first variable gain It is transmitted to the first controller.

16. The closed-loop power control system according to claim 12, wherein, The second processor is also configured to determine the first variable gain. The value of .

17. The closed-loop power control system according to claim 16, wherein, The second processor is based on the first output power level The first variable gain is determined by the second cumulative error between the target EIRP and the target EIRP. .

18. The closed-loop power control system according to claim 16, wherein, The second processor is based on the first output power level The first variable gain is determined by the second weighted cumulative error between the target EIRP and the target EIRP. .

19. The closed-loop power control system according to claim 12, wherein, The second signal path includes: Second power amplifier; The second output power detector is configured to detect the second output power level of the second power amplifier. ; The third processor is configured based on the second output power level. The second accumulated error between the target EIRP and the target EIRP determines the second analog gain for the second controller. and the second gain for the second DAC .

20. The closed-loop power control system according to claim 12, wherein, The second signal path includes a second controller, a third processor, a second VGA, and a second power amplifier, and The first processor is further configured to convert the first analog gain It is transmitted to the second controller.

21. The closed-loop power control system according to claim 20, wherein, The first processor is also configured to transfer the first variable gain It is transmitted to the first controller and the second controller.

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