Filter with tunable center frequency and bandwidth
Through innovative design of multi-parallel filter structure and clock generation circuit, a filter with tunable center frequency and bandwidth was realized, solving the problem that silicon-based tunable filters in the prior art are difficult to balance miniaturization and high-order filtering performance, and achieving efficient frequency and bandwidth tuning.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHENGZHOU UNIV
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-17
AI Technical Summary
Existing silicon-based tunable filters have limitations in center frequency and bandwidth tuning, making it difficult to balance miniaturization and high-order filtering performance. Furthermore, traditional structures are complex and consume a lot of power.
A multi-channel parallel filtering structure and clock generation circuit are adopted. The center frequency and bandwidth are independently controlled by eight non-overlapping clock signals. Combined with negative resistance technology and low-pass filtering circuit, the filter is modularly designed. The non-overlapping clock signal is generated using a CML frequency divider and logic gates.
Independent tuning of center frequency and bandwidth was achieved, significantly reducing chip area while maintaining high-order filtering performance and low insertion loss, and improving out-of-band rejection capability.
Smart Images
Figure CN121887153A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of wireless communication and radio frequency anti-interference technology, and specifically to a filter with tunable center frequency and bandwidth. Background Technology
[0002] As wireless communication systems evolve towards multi-band, multi-standard (e.g., 4G / 5G, Wi-Fi, Bluetooth coexistence) and cognitive radio, the radio frequency front-end needs to handle complex and ever-changing signal environments. While capturing wide-spectrum signals, broadband receivers are also highly susceptible to strong out-of-band interference, leading to decreased sensitivity or even jamming. Therefore, tunable filters capable of dynamically adjusting frequency selectivity during system operation become crucial.
[0003] Traditional tunable filters, such as LC resonant filters based on varactor diodes, have limited tuning ranges, poor linearity, and are not easily integrated using standard silicon-based CMOS processes. In recent years, N-path filters based on switched capacitors have attracted widespread attention due to their high linearity, high Q-value, and good integrability. However, most existing N-path filter structures can only achieve tuning of the center frequency, and the bandwidth is often fixed or has a very narrow tuning range. To achieve higher-order filtering characteristics (such as high out-of-band rejection and steep roll-off), it is usually necessary to increase the number of paths or the filter order, which leads to a significant increase in chip area and power consumption, and also makes the clock generation and control circuitry more complex. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to reduce the chip size while achieving tunability in center frequency and bandwidth of silicon-based tunable filters. To solve the above problem, a filter with tunable center frequency and bandwidth is provided.
[0005] The object of this invention is achieved in the following manner: A filter with tunable center frequency and bandwidth. This includes: a multi-channel filtering structure and a clock generation circuit; The input terminal of the multi-channel filter structure is connected to the signal input terminal. The output terminal is connected to the signal output terminal. ; The clock generation circuit has a first clock input terminal. Second clock input terminal The clock generation circuit is used to generate clocks based on the first clock input. The input signal generates a first set of multi-phase clock signals; and according to the second clock input terminal... The input signal generates a second set of multiphase clock signals; wherein, the first set of multiphase clock signals are multiple non-overlapping clock signals, which are respectively connected to each parallel branch of the multi-path filtering structure, and are used to control the periodic on and off of each signal path to achieve the tuning of the filter center frequency; the second set of multiphase clock signals are multiple non-overlapping clock signals, which are connected to the filtering unit inside each branch of the multi-path filtering structure, and are used to control the change of the equivalent parameter of the filtering unit to achieve the tuning of the filter bandwidth.
[0006] The multi-channel filtering structure includes N parallel filtering branches; the input terminals of the N parallel filtering branches are all connected to the signal input terminal. The output terminals are all connected to the signal output terminal. The first group of multi-phase clock signals is an N-phase non-overlapping clock signal.
[0007] The preferred value of N is 8; the first group of multiphase clock signals consists of eight non-overlapping clock signals, and the second group of multiphase clock signals consists of four non-overlapping clock signals.
[0008] Each filtering branch structure includes: a first switching transistor M1, a low-pass filter circuit, and a second switching transistor M2 connected in series; one of the eight non-overlapping clock signals simultaneously controls the gates of the first switching transistor M1 and the second switching transistor M2 in that branch.
[0009] The low-pass filter unit is a third-order quasi-elliptic filter structure composed of four parallel sub-branches; the four non-overlapping clock signals are connected to the low-pass filter unit to control the conduction state of the transistors in its four parallel sub-branches.
[0010] The low-pass filter circuit adopts a negative resistance structure to compensate for insertion loss; and in the four parallel sub-filter units, a shared capacitor C is connected in series between two paths with a phase difference of 180 degrees, and each path is connected in parallel with a capacitor grounded.
[0011] The clock generation circuit includes a first frequency divider module and a second frequency divider module; The input terminal of the first frequency divider module is connected to the first clock input terminal. It includes four cascaded CML frequency dividers and subsequent logic combination circuits to generate eight non-overlapping clock signals with phases 45 degrees apart. The input terminal of the second frequency divider module is connected to the second clock input terminal. It includes two cascaded current-mode logic CML dividers and subsequent logic combination circuits to generate four non-overlapping clock signals with phases 90 degrees apart.
[0012] The logic combination circuit includes NAND gates and buffers; the overlapping clock signal output by the CML frequency divider is logically combined by the NAND gates and then shaped by the buffers to output the non-overlapping clock signal.
[0013] The CML frequency divider is a divide-by-two circuit based on a D flip-flop, which includes: The first MOS transistor M3 and the second MOS transistor M4 have gates that receive differential data signals D and Db, respectively, and their sources are connected to each other. The gates of the third MOSFET M5 and the fourth MOSFET M8 receive differential clock signals Clk and Clk- respectively, and their sources are connected to each other and grounded through a bias MOSFET M9. The fifth MOSFET M6 and the sixth MOSFET M7 are connected in a gate-drain cross-coupled manner to form a latch; In this configuration, the drain of the first MOSFET M3 is connected to the power supply VDD through a load resistor R1 and is connected to the gate of the fifth MOSFET M6, serving as the output terminal Q; the drain of the second MOSFET M4 is connected to the power supply VDD and is connected to the gate of the sixth MOSFET M7, serving as the complementary output terminal Qb.
[0014] In each filter branch structure, a first parallel capacitor C1 is connected between the input terminal of the first switching transistor M1 and ground, and a second parallel capacitor C2 is connected between the output terminal of the second switching transistor M2 and ground.
[0015] The beneficial effects of this invention: The tunable center frequency and bandwidth filter proposed in this invention can achieve independent tuning of the center frequency and bandwidth while significantly reducing the chip area. Traditional silicon-based tunable filters struggle to balance multi-parameter tuning and miniaturization, but this invention overcomes this technical bottleneck through an innovative eight-channel filtering architecture and a high-efficiency clock generation circuit. Its core innovation lies in the modular design of the eight-channel symmetrical filtering structure. Each channel consists of parallel transistors, capacitors, and negative resistance units to form a low-pass filter circuit, which, together with the switches and capacitors on both sides of the low-pass filter circuit, forms a third-order quasi-elliptic filter structure, greatly improving out-of-band interference suppression. The innovative use of a non-overlapping clock generation circuit allows for independent control of the center frequency and bandwidth through four and eight non-overlapping clock signals respectively. The clock is based on a CML divider and a combination of logic gates (NAND gates + buffers) to achieve precise driving of the filter transistor gates, ensuring tuning linearity and stability. In terms of area and performance optimization, the eight-channel parallel processing combined with negative resistance technology significantly reduces the occupied area while maintaining high-order filtering performance (high suppression ratio, low insertion loss). Attached Figure Description
[0016] Figure 1 A structural block diagram of a filter with tunable center frequency and bandwidth provided in an embodiment of the present invention; Figure 2 This is a block diagram of the structure of each of the eight-channel filters provided in an embodiment of the present invention; Figure 3 This is a structural block diagram of a four-channel clock generation circuit provided in an embodiment of the present invention; Figure 4 This is a structural block diagram of an eight-channel clock generation circuit provided in an embodiment of the present invention; Figure 5 This is a block diagram of the structure of two CML frequency dividers connected in a four-channel clock generation circuit provided in an embodiment of the present invention; Figure 6 This is a block diagram of the structure of four CML frequency dividers connected in an eight-channel clock generation circuit provided in an embodiment of the present invention; Figure 7 This is a structural block diagram of a CML-based frequency divider provided in an embodiment of the present invention; Figure 8 This is a structural block diagram of a NAND gate provided in an embodiment of the present invention; Figure 9 The insertion loss of 200-900MHz is provided for embodiments of the present invention; Figure 10 The return loss of 200-900MHz is provided for the embodiments of the present invention; Figure 11 The input P1dB of the filter with tunable center frequency and bandwidth provided in the embodiments of the present invention. Detailed Implementation
[0017] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0018] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0019] like Figure 1 As shown, the present invention provides a filter with tunable center frequency and bandwidth. A filter with tunable center frequency and bandwidth. This includes: a multi-channel filtering structure and a clock generation circuit; The input terminal of the multi-channel filter structure is connected to the signal input terminal. The output terminal is connected to the signal output terminal. ; The clock generation circuit has a first clock input terminal. Second clock input terminal The clock generation circuit is used to generate clocks based on the first clock input. The input signal generates a first set of multi-phase clock signals; and according to the second clock input terminal... The input signal generates a second set of multiphase clock signals; wherein, the first set of multiphase clock signals are multiple non-overlapping clock signals, which are respectively connected to each parallel branch of the multi-path filtering structure, and are used to control the periodic on and off of each signal path to achieve the tuning of the filter center frequency; the second set of multiphase clock signals are multiple non-overlapping clock signals, which are connected to the filtering unit inside each branch of the multi-path filtering structure, and are used to control the change of the equivalent parameter of the filtering unit to achieve the tuning of the filter bandwidth.
[0020] The multi-channel filtering structure includes N parallel filtering branches; the input terminals of the N parallel filtering branches are all connected to the signal input terminal. The output terminals are all connected to the signal output terminal. The first group of multi-phase clock signals is an N-phase non-overlapping clock signal.
[0021] The preferred value of N is 8; the first group of multiphase clock signals consists of eight non-overlapping clock signals, and the second group of multiphase clock signals consists of four non-overlapping clock signals.
[0022] Each filtering branch structure includes: a first switching transistor M1, a low-pass filter circuit, and a second switching transistor M2 connected in series; one of the eight non-overlapping clock signals simultaneously controls the gates of the first switching transistor M1 and the second switching transistor M2 in that branch.
[0023] The low-pass filter unit is a third-order quasi-elliptic filter structure composed of four parallel sub-branches; the four non-overlapping clock signals are connected to the low-pass filter unit to control the conduction state of the transistors in its four parallel sub-branches.
[0024] The low-pass filter circuit adopts a negative resistance structure to compensate for insertion loss; and in the four parallel sub-filter units, a shared capacitor C is connected in series between two paths with a phase difference of 180 degrees, and each path is connected in parallel with a capacitor grounded.
[0025] The clock generation circuit includes a first frequency divider module and a second frequency divider module; The input terminal of the first frequency divider module is connected to the first clock input terminal. It includes four cascaded CML frequency dividers and subsequent logic combination circuits to generate eight non-overlapping clock signals with phases 45 degrees apart. The input terminal of the second frequency divider module is connected to the second clock input terminal. It includes two cascaded current-mode logic CML dividers and subsequent logic combination circuits to generate four non-overlapping clock signals with phases 90 degrees apart.
[0026] The logic combination circuit includes NAND gates and buffers; the overlapping clock signal output by the CML frequency divider is logically combined by the NAND gates and then shaped by the buffers to output the non-overlapping clock signal.
[0027] The CML frequency divider is a divide-by-two circuit based on a D flip-flop, which includes: The first MOS transistor M3 and the second MOS transistor M4 have gates that receive differential data signals D and Db, respectively, and their sources are connected to each other. The gates of the third MOSFET M5 and the fourth MOSFET M8 receive differential clock signals Clk and Clk- respectively, and their sources are connected to each other and grounded through a bias MOSFET M9. The fifth MOSFET M6 and the sixth MOSFET M7 are connected in a gate-drain cross-coupled manner to form a latch; In this configuration, the drain of the first MOSFET M3 is connected to the power supply VDD through a load resistor R1 and is connected to the gate of the fifth MOSFET M6, serving as the output terminal Q; the drain of the second MOSFET M4 is connected to the power supply VDD and is connected to the gate of the sixth MOSFET M7, serving as the complementary output terminal Qb.
[0028] In each filter branch structure, a first parallel capacitor C1 is connected between the input terminal of the first switching transistor M1 and ground, and a second parallel capacitor C2 is connected between the output terminal of the second switching transistor M2 and ground.
[0029] like Figure 1 As shown, the present invention provides a filter with tunable center frequency and bandwidth, the filter comprising eight parallel filter branches, the signal of the tunable filter being drawn from... The input signal simultaneously enters the eight-channel filter branch, where it is filtered by each of the eight filters before being output simultaneously. The clock signal (center frequency and bandwidth) is generated by the clock generation circuit, and the clock generation circuit signal comes from... and The terminal input generates four and eight clock signals, controls signal filtering, and enables tunable center frequency and bandwidth.
[0030] The aforementioned filter with tunable center frequency and bandwidth has a signal input terminal. The system connects to eight filter branches, allowing signals to enter the eight-channel filter structure simultaneously. The clock signal is generated by a clock generation circuit and input to the gate of the filter transistor.
[0031] like Figure 2 As shown, each filter branch of the filter with tunable center frequency and bandwidth includes parallel transistors M1, The signal enters the low-pass filter circuit through M1, and then flows from the parallel transistor. Output signal.
[0032] The low-pass filter circuit of the filter with tunable center frequency and bandwidth consists of a four-way filter structure, with the signal passing through parallel transistors. It is then divided into four paths, with capacitor C1 and The signal is grounded in parallel and uses a negative resistance structure. Each signal is filtered by controlling the conduction of the transistor through a clock signal that controls the bandwidth.
[0033] The eight-channel filter structure of the tunable center frequency and bandwidth filter is identical. In one channel filter structure, transistor M1 is connected in series in the circuit, and capacitor... and With input and output connected in parallel to ground, the signal passes through the capacitor. Then it enters the low-pass filter circuit, and the output signal passes through the parallel capacitor C2 and capacitor C3. Connecting series transistors .
[0034] The low-pass filter structure of the tunable center frequency and bandwidth filter adopts a negative resistance structure, consisting of four identical circuits. One circuit has an input transistor B0, a capacitor C, and an output transistor B0 connected in series. The other three circuits have the same connections. In addition, a capacitor is connected in parallel to ground between the two transistors in each circuit.
[0035] like Figure 3 As shown, the clock generation circuit has four clock signal inputs. The signal is split into two paths: one passes through a buffer circuit, and the other passes through a transmission gate circuit. The generated clock signal with tuning bandwidth enters two CML dividers to generate four overlapping clock signals, which are then combined and passed through NAND gates and buffer circuits to generate four non-overlapping clock signals with tuning bandwidth.
[0036] like Figure 4 As shown, the clock generation circuit has eight clock signal inputs. The signal is divided into two paths: one passes through a buffer circuit, and the other passes through a transmission gate circuit. The generated clock signal controlling the center frequency enters four CML dividers to generate eight overlapping clock signals, which are then combined and passed through NAND gates and buffer circuits to generate eight non-overlapping clock signals controlling the center frequency.
[0037] like Figure 5As shown, the clock generation circuit includes four clock signals. The Q signal of the CML1 divider and the Db signal of the CML2 divider are connected to output signal B1. Similarly, the D signal of CML1 and the Q signal of CML2 are connected to output signal B2, the Qb signal of CML1 and the D signal of CML2 are connected to output signal B3, and the Db signal of CML1 and the Qb signal of CML2 are connected to output signal B4. B1 and B4 are input to a circuit connected to a NAND gate and three inverters to generate clock signal B0. Similarly, B1 and B2 generate clock signal B90, B2 and B3 generate clock signal B180, and B3 and B4 generate clock signal B270.
[0038] like Figure 6 As shown, the clock generation circuit contains eight clock signals. The Q of CML3 and the D of CML4 generate RF1, the Db of CML3 and the Q of CML6 generate RF2, the Qb of CML5 and the Db of CML6 generate RF3, the Q of CML4 and the D of CML5 generate RF4, the Qb of CML3 and the Db of CML4 generate RF5, the D of CML3 and the Qb of CML6 generate RF6, the Q of CML5 and the D of CML6 generate RF7, and the Qb of CML4 and the Db of CML5 generate RF8. RF2 and RF5 are input to a circuit connected to a NAND gate and three inverters to generate clock signal RF0. Similarly, RF1 and RF4 generate clock signal RF45, RF8 and RF3 generate clock signal RF90, RF7 and RF2 generate clock signal RF135, RF6 and RF1 generate clock signal RF180, RF5 and RF8 generate clock signal RF225, RF4 and RF7 generate clock signal RF270, and RF3 and RF6 generate clock signal RF315.
[0039] like Figure 7 As shown, the clock generation circuit uses a CML-based frequency divider with a capacitor connected in series at the input, which then splits into two paths. One path passes through three inverters, while the other path connects in series with a transmission gate circuit consisting of two MOS transistors, and also connects in series with two inverters. The outputs are Clk and Clk- signals, which enter two CML frequency dividers. The frequency divider circuit inputs the Clk and Clk- signals and the bias voltage EN DFF. Drain resistor Connect to VDD, with the gate being signal D, and the source and... The source is connected, and with The drain connection. The gate is signal Db. The source and drain are connected. The gate is connected to the clock signal Clk. The gate is biased to EN DFF. The gate of M1 is connected to the clock signal Clk-, and the drain is connected to the source of M6 and M7 and grounded. gate connection The drain and and The drain is connected to the output signal Q. The gate of M7 is connected to the drain of M7 and is also connected to the drain of M4 to output signal Qb.
[0040] like Figure 8 As shown, the clock generation circuit consists of two PMOS and two NMOS transistors as its NAND gates. It takes two input signals, IN+ and IN-, and outputs an OUT signal, which enters the buffer.
[0041] Figure 9 The insertion loss of the tunable filter at a tunable frequency of 200-900MHz provided in the embodiment of the present invention is shown by the simulation curve. The insertion loss is less than 6dB and the out-of-band rejection is greater than 23dB, which shows that it has high out-of-band rejection and low insertion loss. Figure 10 The return loss of the tunable filter simulated at a tunable frequency of 200-900MHz provided in the embodiments of the present invention is less than -15dB in the center frequency and bandwidth range, which shows good return loss. Figure 11 The input compression point P1dB of the simulated filter with tunable center frequency and bandwidth provided in the embodiment of the present invention is 2.7dBm.
[0042] This invention employs a third-order quasi-elliptic N-path tunable filter using negative resistance technology. As a silicon-based tunable filter, it replaces existing fixed-frequency filters. Modern CMOS N-path filters utilize multiphase switched-capacitor circuits, enabling high linearity, high compactness, high Q, and tunability as an on-chip filter. A high-order N-path filter is used to achieve high out-of-band rejection, high roll-off, and low insertion loss. A CML-based frequency divider is used to ensure strict duty cycle requirements for the generated clock waveform.
[0043] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several changes and improvements without departing from the overall concept of the present invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A filter with tunable center frequency and bandwidth, characterized in that: include: Multi-channel filtering structure and clock generation circuit; The input terminal of the multi-channel filter structure is connected to the signal input terminal. The output terminal is connected to the signal output terminal. ; The clock generation circuit has a first clock input terminal. Second clock input terminal The clock generation circuit is used to generate clocks based on the first clock input. The input signal generates the first set of multiphase clock signals; And according to the second clock input terminal The input signal generates a second set of multiphase clock signals; wherein, the first set of multiphase clock signals are multiple non-overlapping clock signals, which are respectively connected to each parallel branch of the multi-path filtering structure, and are used to control the periodic on and off of each signal path to achieve the tuning of the filter center frequency; the second set of multiphase clock signals are multiple non-overlapping clock signals, which are connected to the filtering unit inside each branch of the multi-path filtering structure, and are used to control the change of the equivalent parameter of the filtering unit to achieve the tuning of the filter bandwidth.
2. The filter with tunable center frequency and bandwidth according to claim 1, characterized in that: The multi-channel filtering structure includes N parallel filtering branches; the input terminals of the N parallel filtering branches are all connected to the signal input terminal. The output terminals are all connected to the signal output terminal. The first group of multi-phase clock signals is an N-phase non-overlapping clock signal.
3. The filter with tunable center frequency and bandwidth according to claim 2, characterized in that: The preferred value of N is 8; the first group of multiphase clock signals consists of eight non-overlapping clock signals, and the second group of multiphase clock signals consists of four non-overlapping clock signals.
4. The filter with tunable center frequency and bandwidth according to claim 3, characterized in that: Each filtering branch structure includes: a first switching transistor (M1), a low-pass filter circuit, and a second switching transistor (M2) connected in series; one of the eight non-overlapping clock signals simultaneously controls the gates of the first switching transistor (M1) and the second switching transistor (M2) in that branch.
5. The filter with tunable center frequency and bandwidth according to claim 4, characterized in that: The low-pass filter unit is a third-order quasi-elliptic filter structure composed of four parallel sub-branches; the four non-overlapping clock signals are connected to the low-pass filter unit to control the conduction state of the transistors in its four parallel sub-branches.
6. The filter with tunable center frequency and bandwidth according to claim 5, characterized in that: The low-pass filter circuit adopts a negative resistance structure to compensate for insertion loss; and in the four parallel sub-filter units, a shared capacitor C is connected in series between two paths with a phase difference of 180 degrees, and each path is connected in parallel with a capacitor grounded.
7. The filter with tunable center frequency and bandwidth according to claim 1, characterized in that: The clock generation circuit includes a first frequency divider module and a second frequency divider module; The input terminal of the first frequency divider module is connected to the first clock input terminal. It includes four cascaded CML frequency dividers and subsequent logic combination circuits to generate eight non-overlapping clock signals with phases 45 degrees apart. The input terminal of the second frequency divider module is connected to the second clock input terminal. It includes two cascaded current-mode logic CML dividers and subsequent logic combination circuits to generate four non-overlapping clock signals with phases 90 degrees apart.
8. The filter with tunable center frequency and bandwidth according to claim 7, characterized in that: The logic combination circuit includes NAND gates and buffers; the overlapping clock signal output by the CML frequency divider is logically combined by the NAND gates and then shaped by the buffers to output the non-overlapping clock signal.
9. The filter with tunable center frequency and bandwidth according to any one of claims 7 or 8, characterized in that: The CML frequency divider is a divide-by-two circuit based on a D flip-flop, which includes: The first MOS transistor (M3) and the second MOS transistor (M4) have gates that receive differential data signals D and Db, respectively, and their sources are connected to each other. The third MOSFET (M5) and the fourth MOSFET (M8) have gates that receive differential clock signals Clk and Clk-, respectively, and their sources are connected to each other and grounded through a bias MOSFET (M9). The fifth MOSFET (M6) and the sixth MOSFET (M7) form a latch through their gate-drain cross-coupling; The drain of the first MOSFET (M3) is connected to the power supply (VDD) through a load resistor (R1) and is connected to the gate of the fifth MOSFET (M6) as the output terminal Q; the drain of the second MOSFET (M4) is connected to the power supply (VDD) and is connected to the gate of the sixth MOSFET (M7) as the complementary output terminal Qb.
10. The filter with tunable center frequency and bandwidth according to claim 1, characterized in that: In each filter branch structure, a first parallel capacitor (C1) is connected between the input terminal of the first switching transistor (M1) and ground, and a second parallel capacitor (C2) is connected between the output terminal of the second switching transistor (M2) and ground.