High-voltage silicon carbide device and manufacturing method thereof
By forming steps and etching grooves in the sidewall layer during the manufacturing of high-voltage silicon carbide devices, the contact area is increased, solving the problems of contact resistance and capacitance, and improving the performance and reliability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIEFANG SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2024-10-12
- Publication Date
- 2026-04-17
AI Technical Summary
In the manufacturing process of high-voltage silicon carbide devices, the reduction in the size of the contact hole leads to an increase in contact resistance, which affects the switching speed. The method of increasing the injection concentration has reached the technical limit, making it difficult to simultaneously reduce capacitance and increase contact area.
By forming a step at the junction of the lower and upper parts of the contact hole, combining the first sidewall layer and the second sidewall layer, etching to form a groove and filling the source and drain contact layer, the contact area is increased and the dielectric constant is reduced, thus optimizing the electric field distribution.
This effectively increases the contact area of the contact holes, reduces contact resistance and capacitance, and improves device performance and reliability.
Smart Images
Figure CN121888673A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage silicon carbide device and its manufacturing method. Background Technology
[0002] High-voltage silicon carbide (SiC) devices, also known as power electronic devices, are high-power electronic components used in power equipment's power conversion and control circuits due to SiC's high critical electric field, high thermal conductivity, and high saturation drift velocity. These include power diodes, power transistors, thyristors, MOSFETs, and IGBTs. SiC power devices have a significant impact in medium- and high-voltage applications above 1000V, primarily in electric vehicle charging stations, photovoltaic new energy, rail transit, and smart grids. As the design size of SiC devices gradually shrinks, the size of the contact holes also decreases. In current high-voltage SiC device manufacturing, increasing the contact hole size to reduce contact resistance, while achieving this goal, inevitably increases input capacitance, negatively impacting switching speed. Increasing the injection concentration has also reached its technological limit. Summary of the Invention
[0003] The purpose of this invention is to provide a high-voltage silicon carbide device and its manufacturing method, so as to increase the contact area of the contact hole and reduce the capacitance.
[0004] To achieve the above objectives, the present invention provides a method for manufacturing a high-voltage silicon carbide device, comprising:
[0005] A substrate is provided, on which an epitaxial layer is formed, in which source / drain regions are formed, and in which through-contact regions are formed, the top surface of the contact regions is lower than the top surface of the source / drain regions. An interlayer dielectric layer is formed on the substrate, and a contact hole is formed in the interlayer dielectric layer on the source / drain regions. The width of the lower part of the contact hole is smaller than the width of the upper part of the contact hole, so that the junction of the lower part and the upper part of the contact hole forms a step.
[0006] A first sidewall layer is formed, which at least covers the upper sidewall of the contact hole and the top surface of the step;
[0007] A second sidewall layer is formed, which is located on the first sidewall layer on the top surface of the step and covers the sidewall of the first sidewall layer;
[0008] The first sidewall layer is etched to remove the first sidewall layer located on the top surface of the step, so as to form a groove between the bottom of the second sidewall layer and the top surface of the step.
[0009] A source / drain contact layer is formed, which fills the groove and extends to cover the sidewall of the second sidewall layer, the inner surface of the lower part of the contact hole, and the top surface of the interlayer dielectric layer.
[0010] Optionally, the first sidewall layer is made of silicon oxide and is formed by chemical vapor deposition. In the process of forming the first sidewall layer, the first sidewall layer also covers the inner surface of the lower part of the contact hole and the top surface of the interlayer dielectric layer.
[0011] Optionally, the method for etching the first sidewall layer includes:
[0012] The first sidewall layer is etched using a wet etching process to remove the first sidewall layer located on the top surface of the step, the first sidewall layer located on the inner surface below the contact hole, and the first sidewall layer on the interlayer dielectric layer.
[0013] Optionally, the method for forming the second sidewall layer includes:
[0014] A second sidewall material layer is formed, which covers the first sidewall layer;
[0015] The second sidewall material layer is etched using a dry etching process to remove the second sidewall material layer at the bottom of the contact hole and the second sidewall material layer on the interlayer dielectric layer, while retaining the second material layer on the sidewall of the first sidewall layer to form the second sidewall layer.
[0016] Optionally, the second sidewall material layer is made of silicon nitride and is formed by chemical vapor deposition.
[0017] Optionally, the source / drain contact layer may be made of at least one of nickel silicide, titanium silicide, and platinum silicide.
[0018] Optionally, both the substrate and the epitaxial layer are made of silicon carbide.
[0019] Optionally, after forming the source / drain contact layer, the method further includes:
[0020] A conductive layer is filled into the contact hole, and the conductive layer covers the source / drain contact layer.
[0021] Based on the same inventive concept, the present invention also provides a high-voltage silicon carbide device, comprising:
[0022] A substrate on which an epitaxial layer is formed, wherein a source / drain region is formed, and a through-contact region is formed in the source / drain region, wherein the top surface of the contact region is lower than the top surface of the source / drain region, wherein an interlayer dielectric layer is formed on the substrate, and a contact hole is formed in the interlayer dielectric layer on the source / drain region, wherein the width of the lower part of the contact hole is smaller than the width of the upper part of the contact hole, so that the boundary between the lower part and the upper part of the contact hole forms a step;
[0023] A first sidewall layer, the first sidewall layer at least covers the upper sidewall of the contact hole;
[0024] The second sidewall layer covers the sidewall of the first sidewall layer, and a groove is formed between the bottom of the second sidewall layer and the top surface of the step.
[0025] A source / drain contact layer that fills the groove and extends to cover the sidewall of the second sidewall layer and the inner surface of the inner wall below the contact hole.
[0026] Optionally, the first sidewall layer is made of silicon oxide; the second sidewall layer is made of silicon nitride.
[0027] In the manufacturing method of the high-voltage silicon carbide device provided by the present invention, a first sidewall layer is first formed, which at least covers the upper sidewall of the contact hole and the top surface of the step; then, a second sidewall layer is formed, which is located on the first sidewall layer on the top surface of the step and covers the sidewall of the first sidewall layer; next, the first sidewall layer is etched to remove the first sidewall layer located on the top surface of the step, so as to form a groove between the bottom of the second sidewall layer and the top surface of the step; then, a source / drain contact layer is formed, which fills the groove and extends to cover the sidewall of the second sidewall layer, the lower inner surface of the contact hole, and the top surface of the interlayer dielectric layer. Since a groove is formed between the bottom of the second sidewall layer and the top surface of the step, the contact area of the contact hole is increased, thereby increasing the contact area between the source / drain contact layer and the source / drain region, thereby reducing the contact resistance between the source / drain contact layer and the contact hole, improving the performance of the device, and using a sidewall combining the first and second sidewall layers can reduce the dielectric constant, thereby effectively reducing the capacitance in the contact hole. Attached Figure Description
[0028] Figure 1 This is a schematic flowchart of the manufacturing method of the high-voltage silicon carbide device provided in the embodiment of the present invention;
[0029] Figures 2-8 This is a schematic diagram of the structure formed in the manufacturing method of the high-voltage silicon carbide device provided in the embodiment of the present invention;
[0030] The reference numerals in the attached figures are explained as follows:
[0031] 101-Substrate; 102-Epipolar layer; 103-Body region; 104-Source / drain region; 105-Contact region; 106-Gate dielectric layer; 107-Gate; 110-Interlayer dielectric layer; 120-Contact hole; 120a-Lower part; 120b-Upper part; 120c-Step; 130-First sidewall layer; 140-Second sidewall layer; 150-Groove; 160-Source / drain contact layer; 170-Conductive layer. Detailed Implementation
[0032] The high-voltage silicon carbide device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0033] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.
[0034] Figure 1 This is a schematic flowchart of the manufacturing method of the high-voltage silicon carbide device provided in an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for manufacturing a high-voltage silicon carbide device, including:
[0035] Step S1: Provide a substrate on which an epitaxial layer is formed, a source / drain region is formed in the epitaxial layer, a through contact region is formed in the source / drain region, the top surface of the contact region is lower than the top surface of the source / drain region, an interlayer dielectric layer is formed on the epitaxial layer, and a contact hole is formed in the interlayer dielectric layer on the source / drain region, wherein the width of the lower part of the contact hole is smaller than the width of the upper part of the contact hole, so that the junction of the lower part of the contact hole and the upper part of the contact hole forms a step;
[0036] Step S2: Form a first sidewall layer, which at least covers the upper sidewall of the contact hole and the top surface of the step;
[0037] Step S3: Form a second sidewall layer, which is located on the first sidewall layer on the top surface of the step and covers the sidewall of the first sidewall layer;
[0038] Step S4: Etch the first sidewall layer to remove the first sidewall layer located on the top surface of the step, so as to form a groove between the bottom of the second sidewall layer and the top surface of the step;
[0039] Step S5: Form a source / drain contact layer that fills the groove and extends to cover the sidewall of the second sidewall layer, the inner surface of the lower part of the contact hole, and the top surface of the interlayer dielectric layer.
[0040] Figures 2-8 This is a schematic diagram of the structure formed in the manufacturing method of the high-voltage silicon carbide device provided in the embodiments of the present invention. The following will refer to the attached diagram. Figures 2-8 The present invention provides a more detailed description of the manufacturing method of the high-voltage silicon carbide device.
[0041] First, refer to Figure 2 As shown, in step S1, a substrate 101 is provided, on which an epitaxial layer 102 is formed. A source / drain region 104 is formed in the epitaxial layer 102, and a through-type contact region 105 is formed in the source / drain region 104. The top surface of the contact region 105 is lower than the top surface of the source / drain region 104. An interlayer dielectric layer 110 is formed on the epitaxial layer 102, and a contact hole 120 is formed in the interlayer dielectric layer 110 on the source / drain region 104. The width of the lower portion 120a of the contact hole 120 is smaller than the width of the upper portion 120b of the contact hole 120, so that a step 120c is formed at the junction of the lower portion 120a and the upper portion 120b of the contact hole 120.
[0042] In this embodiment, the substrate 101 can be made of silicon carbide, and the epitaxial layer 102 can also be made of silicon carbide, that is, the material of the epitaxial layer 102 and the material of the substrate 101 can be the same.
[0043] After that, as Figure 2 As shown, a body region 103 is formed in the epitaxial layer 102. The conductivity type of the body region 103 can be a first conductivity type, such as P-type.
[0044] Next, as Figure 2 As shown, a source / drain region 104 is formed in the epitaxial layer 102. The source / drain region 104 is formed in the body region 103. The conductivity type of the source / drain region 104 can be a second conductivity type, such as N-type.
[0045] Specifically, such as Figure 2As shown, the source / drain region 104 is located within the body region 103, and the injection depth of the source / drain region 104 is less than the injection depth of the body region 103. The bottom surface of the source / drain region 104 is lower than the bottom surface of the body region 103, and the top surface of the source / drain region 104 is flush with the top surface of the body region 103. Furthermore, the sidewalls of the source / drain region 104 do not overlap with the sidewalls of the body region 103, and the edge of the source / drain region 104 is located within the body region 103.
[0046] After that, as Figure 2 As shown, a contact region 105 is formed in the epitaxial layer 102 between adjacent source / drain regions 104. The contact region 105 penetrates the body region 103 and extends into the epitaxial layer 102. Specifically, the contact region 105 is located between two adjacent source / drain regions 104 and is in contact with them. That is, the contact region 105 penetrates the body region 103 between adjacent source / drain regions 104 and extends into the epitaxial layer 102. In other words, the contact region 105 partially overlaps with the body region 103 between the source / drain regions 104, but the depth of the contact region 105 is greater than the depth of the body region 103.
[0047] For example, contact region 105 is a p-type heavily doped contact region 105. The doping concentration of contact region 105 is greater than the doping concentration of bulk region 103 and greater than the ion doping concentration in epitaxial layer 102. The ions in contact region 105 can be, for example, aluminum ions.
[0048] Next, as Figure 2 As shown, a gate dielectric layer 106 and a gate 107 are sequentially formed on the substrate 101. The gate 107 is formed on the substrate 101 between two adjacent contact regions 105. The gate dielectric layer 106 is located between the gate 107 and the substrate 101. The gate dielectric layer 106 can be made of silicon oxide, and the gate 107 can be made of polysilicon. The source and drain regions 104 on both sides of the gate 107 are the source and drain, respectively.
[0049] Next, as Figure 2 As shown, an interlayer dielectric layer 110 and a patterned photoresist layer (not shown) are sequentially formed. The interlayer dielectric layer 110 covers the gate 107, the source / drain region 104, and the contact region 105. The patterned photoresist layer is located on the interlayer dielectric layer 110 and has an opening that exposes a portion of the interlayer dielectric layer 110 on the contact region 105.
[0050] Subsequently, using the patterned photoresist layer as a mask, the interlayer dielectric layer 110 is etched to form an initial contact hole, which exposes the top surface of the contact area 105.
[0051] After that, as Figure 2 As shown, a wet etching process is used to increase the width of the initial contact hole to form a contact hole 120. The contact hole 120 exposes the top surface of the contact region 105 and part of the top surface and sidewalls of the source / drain region 104. The etching solution used in the wet etching process can be hydrofluoric acid. The thickness of the interlayer dielectric layer 110 on the sidewalls of the contact hole 120 can be adjusted according to the pressure resistance requirements; the thickness of the interlayer dielectric layer 110 on the sidewalls of the contact hole 120 can be 0.1 μm to 0.2 μm.
[0052] In this embodiment, as Figure 2 As shown, the contact hole 120 has a lower portion 120a and an upper portion 120b. The lower portion 120a of the contact hole 120 is located between two adjacent source / drain regions and exposes the top surface of the contact region 105 and the sidewall of the source / drain region 104. The upper portion 120b of the contact hole 120 is located in the interlayer dielectric layer 110 and exposes part of the top surface of the source / drain region 104.
[0053] In this embodiment, the width of the lower portion 120a of the contact hole 120 is smaller than the width of the upper portion 120b of the contact hole 120, so that a step 120c is formed at the junction of the lower portion 120a and the upper portion 120b of the contact hole 120. The step 120c is formed by the top surface and sidewall of the exposed source / drain region 104.
[0054] Next, refer to Figure 3 Step S2 is executed to form a first sidewall layer 130. The first sidewall layer 130 at least covers the sidewall of the upper portion 120b of the contact hole 120 and the top surface of the step 120c. Furthermore, the first sidewall layer 130 also covers the inner surface of the lower portion 120a of the contact hole 120 and the top surface of the interlayer medium layer 110, that is, the first sidewall layer 130 can cover the inner surface of the contact hole 120 and extend to cover the top surface of the interlayer medium layer 110.
[0055] Specifically, the first sidewall layer 130 is made of silicon oxide and is formed by chemical vapor deposition. The first sidewall acts as a buffer layer, which helps to balance the stress introduced by the subsequent second sidewall, thereby improving the performance and reliability of the device. The thickness of the first sidewall layer 130 can be between 70 angstroms and 150 angstroms.
[0056] Next, refer to Figure 4 and combined Figure 5As shown, step S3 is performed to form a second sidewall layer 140a, which is located on the top surface of the step 120c above the first sidewall layer 130 and covers the sidewall of the first sidewall layer 130.
[0057] Specifically, the method for forming the second sidewall layer 140a includes: firstly, as... Figure 4 As shown, a second sidewall material layer 140 is formed, which covers the first sidewall layer 130. The second sidewall material layer 140 can be formed using a chemical vapor deposition process, and its thickness can be 260 angstroms to 350 angstroms.
[0058] Preferably, the second sidewall layer 140a can be made of silicon nitride, so that the material of the second sidewall layer 140a is different from that of the first sidewall layer 130. This allows the subsequently formed first and second sidewall layers to form a composite sidewall with a dielectric constant between silicon oxide and silicon nitride. Compared to a silicon nitride sidewall, using a composite sidewall combining the first and second sidewall layers can reduce the dielectric constant, thereby optimizing the distribution of the electric field on the sidewall of the contact hole, making it more uniform, and helping to reduce electric field concentration and partial discharge phenomena, thus reducing capacitance and consequently reducing parasitic capacitance in the contact hole.
[0059] Next, as Figure 5 As shown, a dry etching process is used to etch the second sidewall material layer 140 to remove the second sidewall material layer 140 at the bottom of the contact hole 120 (i.e., the bottom of the lower part of the contact hole 120) and the second sidewall material layer 140 on the interlayer dielectric layer 110, while retaining the second sidewall material layer 140 on the sidewall of the first sidewall layer 130 to form the second sidewall layer 140a. Furthermore, a portion of the thickness of the first sidewall layer 130 at the bottom of the contact hole 120 (i.e., the bottom of the lower part of the contact hole 120) can also be removed.
[0060] Next, as Figure 6 As shown, in step S4, the first sidewall layer 130 is etched to remove the first sidewall layer 130 located on the top surface of the step 120c, so as to form a groove 150 between the bottom of the second sidewall layer 140a and the top surface of the step 120c. The groove 150 communicates with the contact hole 120, and by forming the groove 150, the contact area of the contact hole 120 can be increased.
[0061] Preferably, a wet etching process is used to etch the first sidewall layer 130 to remove the first sidewall layer 130 located on the top surface of the step 120c, that is, to remove the first sidewall layer 130 between the bottom of the second sidewall layer 140a and the top surface of the source / drain region 104, and to remove the first sidewall layer 130 located on the inner surface of the lower part 120a of the contact hole 120 and the first sidewall layer 130 on the interlayer dielectric layer 110. The etching solution used in the wet etching process can be hydrofluoric acid to achieve a high etching selectivity between the first sidewall layer 130 and the second sidewall layer 140a, thereby avoiding damage to the second sidewall layer 140a.
[0062] Next, as Figure 7 As shown, a source / drain contact layer 160 is formed, which fills the groove 150 and extends to cover the sidewall of the second sidewall layer 140a, the inner surface of the lower portion 120a of the contact hole 120, and the top surface of the interlayer dielectric layer 110. That is, the source / drain contact layer 160 is recessed horizontally into the bottom of the second sidewall layer 140a and contacts the top surface of the source / drain region 104 exposed in the groove 150. The source / drain contact layer 160 also contacts the sidewall of the source / drain region 104 exposed in the contact hole 120. This increases the contact area between the source / drain contact layer 160 and the source / drain region 104, thereby reducing the contact resistance between the source / drain contact layer 160 and the contact hole 120 and improving device performance.
[0063] In this embodiment, the source / drain contact layer 160 is made of at least one of nickel silicide, titanium silicide, and platinum silicide. The method for forming the source / drain contact layer 160 includes: first, forming a metal layer that fills the groove 150 and extends to cover the sidewall of the second sidewall layer 140a, the inner surface of the lower portion 120a of the contact hole 120, and the top surface of the interlayer dielectric layer 110; wherein the metal layer can be made of at least one of nickel, titanium, and platinum; then, performing an annealing process to react the metal layer with silicon in the contact hole 120 to form the source / drain contact layer, i.e., the source / drain contact layer 160 is a metal silicide layer.
[0064] Next, as Figure 8 As shown, a conductive layer 170 is formed in the contact hole 120, and the conductive layer 170 covers the source / drain contact layer 160, that is, the conductive layer 170 fills the contact hole 120 and covers the source / drain contact layer 160. The conductive layer 170 can be made of metal, such as aluminum.
[0065] refer to Figure 8As shown, this embodiment also provides a high-voltage silicon carbide device, including: a substrate 101, an epitaxial layer 102 formed on the substrate 101, a source / drain region 104 formed in the epitaxial layer 102, a through contact region 105 formed in the source / drain region 104, the top surface of the contact region 105 being lower than the top surface of the source / drain region 104, an interlayer dielectric layer 110 formed on the epitaxial layer 102, a contact hole 120 formed in the interlayer dielectric layer 110 on the source / drain region 104, the width of the lower part 120a of the contact hole 120 being smaller than the width of the upper part 120b of the contact hole 120, so that the junction of the lower part 120a and the upper part 120b of the contact hole 120 forms a step 120c;
[0066] The first sidewall layer 130 at least covers the sidewall of the upper portion 120b of the contact hole 120;
[0067] The second sidewall layer 140a covers the sidewall of the first sidewall layer 130, and a groove 150 is formed between the bottom of the second sidewall layer 140a and the top surface of the step 120c.
[0068] A source / drain contact layer 160 fills the groove 150 and extends to cover the sidewall of the second sidewall layer 140a, the inner surface of the lower portion 120a of the contact hole 120, and the top surface of the interlayer dielectric layer 110. Because a groove is formed between the bottom of the second sidewall layer 140a and the top surface of the step 120c, the contact area between the source / drain contact layer 160 and the source / drain region 104 can be increased, thereby reducing the contact resistance between the source / drain contact layer and the contact hole 120 and improving device performance.
[0069] In this embodiment, the first sidewall layer 130 can be made of silicon oxide; the second sidewall layer 140a can be made of silicon nitride, which can effectively reduce the capacitance in the contact hole 120.
[0070] In this embodiment, the high-voltage silicon carbide device further includes a conductive layer 170, which fills the contact hole 120 and covers the source / drain contact layer 160.
[0071] In summary, in the high-voltage silicon carbide device and its manufacturing method provided by this invention, a first sidewall layer is first formed, which at least covers the upper sidewall of the contact hole and the top surface of the step. Then, a second sidewall layer is formed, located on the first sidewall layer on the top surface of the step and covering the sidewall of the first sidewall layer. Next, the first sidewall layer is etched to remove the first sidewall layer located on the top surface of the step, forming a groove between the bottom of the second sidewall layer and the top surface of the step. Then, a source / drain contact layer is formed, filling the groove and extending to cover the sidewall of the second sidewall layer and the lower inner surface of the contact hole. Because a groove is formed between the bottom of the second sidewall layer and the top surface of the step, the contact area of the contact hole is increased, thus increasing the contact area between the source / drain contact layer and the source / drain region. This reduces the contact resistance between the source / drain contact layer and the contact hole, improving device performance. Furthermore, the combination of the first and second sidewall layers effectively reduces the capacitance in the contact hole.
[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
[0073] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method for manufacturing a high-voltage silicon carbide device, characterized in that, include: A substrate is provided, on which an epitaxial layer is formed, in which source / drain regions are formed, and in which through-contact regions are formed, the top surface of the contact regions is lower than the top surface of the source / drain regions, an interlayer dielectric layer is formed on the epitaxial layer, and a contact hole is formed in the interlayer dielectric layer on the source / drain regions, wherein the width of the lower part of the contact hole is smaller than the width of the upper part of the contact hole, so that the boundary between the lower part and the upper part of the contact hole forms a step; A first sidewall layer is formed, which at least covers the upper sidewall of the contact hole and the top surface of the step; A second sidewall layer is formed, which is located on the first sidewall layer on the top surface of the step and covers the sidewall of the first sidewall layer; The first sidewall layer is etched to remove the first sidewall layer located on the top surface of the step, so as to form a groove between the bottom of the second sidewall layer and the top surface of the step. A source / drain contact layer is formed, which fills the groove and extends to cover the sidewall of the second sidewall layer, the inner surface of the lower part of the contact hole, and the top surface of the interlayer dielectric layer.
2. The method for manufacturing a high-voltage silicon carbide device as described in claim 1, characterized in that, The first sidewall layer is made of silicon oxide and is formed by chemical vapor deposition. When forming the first sidewall layer, the first sidewall layer also covers the inner surface of the lower part of the contact hole and the top surface of the interlayer dielectric layer.
3. The method for manufacturing a high-voltage silicon carbide device as described in claim 2, characterized in that, The method for etching the first sidewall layer includes: The first sidewall layer is etched using a wet etching process to remove the first sidewall layer located on the top surface of the step, the first sidewall layer located on the inner surface below the contact hole, and the first sidewall layer on the interlayer dielectric layer.
4. The method for manufacturing a high-voltage silicon carbide device as described in claim 3, characterized in that, The method for forming the second sidewall layer includes: A second sidewall material layer is formed, which covers the first sidewall layer; The second sidewall material layer is etched using a dry etching process to remove the second sidewall material layer at the bottom of the contact hole and the second sidewall material layer on the interlayer dielectric layer, while retaining the second material layer on the sidewall of the first sidewall layer to form the second sidewall layer.
5. The method for manufacturing a high-voltage silicon carbide device as described in claim 4, characterized in that, The second sidewall material layer is made of silicon nitride and is formed by chemical vapor deposition.
6. The method for manufacturing a high-voltage silicon carbide device as described in claim 1, characterized in that, The source / drain contact layer is made of at least one of nickel silicide, titanium silicide, and platinum silicide.
7. The method for manufacturing a high-voltage silicon carbide device as described in claim 1, characterized in that, Both the substrate and the epitaxial layer are made of silicon carbide.
8. The method for manufacturing a high-voltage silicon carbide device as described in claim 1, characterized in that, After forming the source / drain contact layer, the method further includes: A conductive layer is filled into the contact hole, and the conductive layer covers the source / drain contact layer.
9. A high-voltage silicon carbide device, characterized in that, include: A substrate on which an epitaxial layer is formed, wherein a source / drain region is formed, and a through-contact region is formed in the source / drain region, wherein the top surface of the contact region is lower than the top surface of the source / drain region, wherein an interlayer dielectric layer is formed on the substrate, and a contact hole is formed in the interlayer dielectric layer on the source / drain region, wherein the width of the lower part of the contact hole is smaller than the width of the upper part of the contact hole, so that the boundary between the lower part and the upper part of the contact hole forms a step; A first sidewall layer, the first sidewall layer at least covers the upper sidewall of the contact hole; The second sidewall layer covers the sidewall of the first sidewall layer, and a groove is formed between the bottom of the second sidewall layer and the top surface of the step. A source / drain contact layer that fills the groove and extends to cover the sidewall of the second sidewall layer, the inner surface of the lower part of the contact hole, and the top surface of the interlayer dielectric layer.
10. The high-voltage silicon carbide device as described in claim 9, characterized in that, The first sidewall layer is made of silicon oxide; the second sidewall layer is made of silicon nitride.