Photoelectric conversion element

Abstract

The photoelectric conversion element includes: a semiconductor layer of a first conductivity type; a low-concentration impurity semiconductor layer formed on the semiconductor layer and having an impurity concentration lower than that of the semiconductor layer; and a high-concentration impurity semiconductor region formed on a surface layer of the low-concentration impurity semiconductor layer, the high-concentration impurity semiconductor region having an impurity concentration higher than that of the low-concentration impurity semiconductor layer and being different from the first conductivity type, the high-concentration impurity semiconductor region being formed on the surface layer of the low-concentration impurity semiconductor layer. The high-concentration impurity semiconductor region is linearly distributed, and has substantially no width in a direction perpendicular to both the longitudinal direction thereof and the thickness direction of the low-concentration impurity semiconductor layer.

Description

Technical Field

[0001] This invention relates to a photoelectric conversion element. Background Technology

[0002] Photodiodes, as devices that convert light energy into electrical signals, are widely regarded as photoelectric conversion elements. Among them, PIN photodiodes are widely used in remote controls, optical communication equipment, and other fields due to their excellent high response speed, high sensitivity, and low dark current characteristics.

[0003] Figure 16 The diagram shows a schematic cross-sectional view illustrating the structure of a traditional PIN photodiode.

[0004] In a conventional PIN photodiode, an intrinsic layer (i-layer) 102 is formed on a p-type substrate 101. An n+ type region 103 is formed on the surface region of the i-layer 102. When the cathode 104 and anode 105 of the PIN photodiode are connected to a high potential and a low potential, respectively, and a reverse bias is applied to the PIN photodiode, the depletion layer will... + The junction between region 103 and layer 102 diffuses towards layer 102. When light shines on the PIN photodiode, valence band electrons are excited to the conduction band, leaving holes in the valence band. This primarily generates carriers (electrons and holes) in the depletion layer. Driven by the internal electric field, electrons migrate to the n-layer. + Holes migrate to the neutral region of the p-type substrate 101, while the load resistor is connected to the anode 105. For example, when the load resistor is connected to the anode 105, current flows through the load resistor and generates a voltage across it. This voltage is amplified by an amplifier and extracted as an electrical signal for output.

[0005] The response speed of a PIN photodiode is determined by the following three factors: t1, t2, and t3.

[0006] (1) The time constant t1 in an electronic circuit containing a PIN photodiode and a load resistor (2) The time t2 required for the diffusion of carriers generated outside the depletion layer (3) The time t3 required for charge carriers to traverse the depletion layer The response speed of a PIN photodiode can be improved by reducing the values ​​of various parameters t1, t2, and t3. The time constant t1 is directly proportional to the product of the inter-terminal capacitance of the PIN photodiode and the load resistance. Improvements in the response speed of a PIN photodiode are often limited by the time constant t1. Therefore, reducing the inter-terminal capacitance of the PIN photodiode to reduce the time constant t1 is the most effective way to improve its response speed. Summary of the Invention

[0007] The purpose of this invention is to provide a photoelectric conversion element that can reduce inter-terminal capacitance.

[0008] To achieve the above objectives, a photoelectric conversion element according to one aspect of the present invention includes: a first conductivity type semiconductor layer, a low-concentration impurity semiconductor layer formed on the first conductivity type semiconductor layer, and a high-concentration impurity semiconductor region formed in the surface layer of the low-concentration impurity semiconductor layer. The impurity concentration of the low-concentration impurity semiconductor layer is lower than that of the first conductivity type semiconductor layer. The high-concentration impurity semiconductor region has a second conductivity type different from the first conductivity type. The impurity concentration of the high-concentration impurity semiconductor region is higher than that of the low-concentration impurity semiconductor layer. This region is linear and substantially has no width in the width direction, which is perpendicular to both the length direction of the high-concentration impurity semiconductor region and the thickness direction of the low-concentration impurity semiconductor layer.

[0009] According to this structure, a low-concentration impurity semiconductor layer with a low impurity concentration is formed on a first conductivity type semiconductor layer. A high-concentration impurity semiconductor region of a second conductivity type is formed on the surface region of the low-concentration impurity semiconductor layer. This high-concentration impurity semiconductor region is linear and has a negligible width.

[0010] In traditional photoelectric conversion devices (PIN photodiodes), the high-concentration impurity semiconductor region (corresponding to...) Figure 16 As shown in n + Type region 103) on the surface layer of the low-concentration impurity semiconductor layer (corresponding to Figure 16 As shown, layer i (102) is planarized and formed over a large area. In contrast, the photoelectric conversion element of the present invention forms a high-concentration impurity semiconductor region within the surface layer of a low-concentration impurity semiconductor layer, with a morphology of a linear structure with a width of nearly zero. Therefore, the photoelectric conversion element of the present invention can achieve a smaller junction capacitance, thereby reducing the inter-terminal capacitance. This improves the response speed of the photoelectric conversion element.

[0011] In the photoelectric conversion element, a receiving area is provided for introducing external light into a low-concentration impurity semiconductor layer. The photoelectric conversion element may also include an anti-reflective coating. The anti-reflective coating is formed on the light-receiving area and is in contact with the surface of the low-concentration impurity semiconductor layer.

[0012] According to this structure, the anti-reflective film contacts the surface of the low-concentration impurity semiconductor layer within the light-receiving region. No electrodes (wiring connecting to the high-concentration impurity semiconductor region) or insulating films are formed between the surface of the low-concentration impurity semiconductor layer and the anti-reflective film. Therefore, optical interference between the anti-reflective film and the low-concentration impurity semiconductor layer can be avoided.

[0013] The photoelectric conversion element may further include a first conductive layer. The first conductive layer is formed above a low-concentration impurity semiconductor layer and is opposite at least a portion of the high-concentration impurity semiconductor region in the thickness direction. The first conductive layer may extend along the length direction and be connected to a fixed potential.

[0014] This structure allows electromagnetic noise that intrudes into the high-concentration impurity semiconductor region from the outside to be blocked by the first conductive layer. This prevents external electromagnetic noise from reaching the high-concentration impurity semiconductor region, thereby eliminating the adverse effects caused by electromagnetic noise.

[0015] The photoelectric conversion element may also include multiple second conductive layers. These multiple second conductive layers are formed above a low-concentration impurity semiconductor layer. Each of the multiple second conductive layers is opposite a different portion of the high-concentration impurity semiconductor region in the thickness direction. Each of the multiple second conductive layers may extend along its length and be connected to a fixed potential.

[0016] With this configuration, even if external electromagnetic noise intrudes into the high-concentration impurity semiconductor region, the electromagnetic noise can be blocked by the first conductive layer or the second conductive layer. Therefore, it is possible to further prevent external electromagnetic noise from reaching the high-concentration impurity semiconductor region, thereby eliminating the adverse effects caused by electromagnetic noise.

[0017] The photoelectric conversion element can adopt the following structure: an interlayer film is formed between the first conductive layer and the second conductive layer, and a longitudinally extending via is provided, which penetrates the interlayer film in the thickness direction, thereby connecting the first conductive layer and the second conductive layer.

[0018] In this structure, even if external electromagnetic noise intrudes into the high-concentration impurity semiconductor region in a manner perpendicular to the thickness direction, the noise can still be blocked by the first conductive layer, the second conductive layer, or vias. Therefore, external electromagnetic noise can be prevented from reaching the high-concentration impurity semiconductor region, eliminating the negative impact caused by electromagnetic noise.

[0019] The photoelectric conversion element can adopt the following structure: an interlayer film is formed between a low-concentration doped semiconductor layer and a first conductive layer, and two vias extending along the length direction penetrate the interlayer film in the thickness direction, connecting the first conductive layer and the low-concentration doped semiconductor layer. In this structure, a first conductivity type contact region with a doping concentration higher than that of the low-concentration doped semiconductor layer is formed on the surface layer of the low-concentration doped semiconductor layer. This contact region is positioned at an interval between one side and the other side of the high-concentration doped semiconductor region in the width direction. The two vias are respectively connected to the contact regions on one side and the other side of the high-concentration doped semiconductor region in the width direction.

[0020] This structure allows the first conductive layer to block electromagnetic noise in the thickness direction from entering the high-concentration impurity semiconductor region from the outside. Furthermore, even if electromagnetic noise enters the high-concentration impurity semiconductor region from the outside at an angle intersecting the thickness direction, it can still be blocked by the first conductive layer or vias. Therefore, external electromagnetic noise can be prevented from reaching the high-concentration impurity semiconductor region, eliminating the adverse effects caused by electromagnetic noise.

[0021] The photoelectric conversion element can be structured as follows: a first conductivity type semiconductor region for fixed potential connection is formed on the surface layer of a low-concentration impurity semiconductor layer. In this structure, the fixed potential connection semiconductor region can be spaced apart from the high-concentration impurity semiconductor region in the width direction, extend in the length direction, and be connected to the fixed potential.

[0022] In this configuration, even if external electromagnetic noise intrudes into the region adjacent to the high-concentration impurity semiconductor region in the width direction, the fixed-potential connected semiconductor region can block the electromagnetic noise. Therefore, external electromagnetic noise can be prevented from reaching the high-concentration impurity semiconductor region, thereby eliminating the adverse effects of electromagnetic noise.

[0023] Furthermore, by bonding the electrode to the surface of the semiconductor region used for fixed-potential connection and connecting it to a fixed potential, the semiconductor layer can be connected to a fixed potential via the semiconductor region used for fixed-potential connection and the low-concentration impurity semiconductor layer. Therefore, when the photoelectric conversion element is a photodiode, this electrode can serve as an anode electrode or a cathode electrode.

[0024] The region of high concentration of impurities is essentially not wide in the width direction, meaning that the region is essentially linear.

[0025] In photoelectric conversion elements, a light-receiving region is provided to receive external light entering a low-concentration impurity semiconductor layer. The high-concentration impurity semiconductor region is essentially linear and has no substantial width in the width direction. However, if the width (thickness) of the high-concentration impurity semiconductor region is intentionally compared with the width of the light-receiving region in the width direction, the ratio of the width of the high-concentration impurity semiconductor region to the width of the light-receiving region in the width direction can be considered to be set to 1% or less.

[0026] The essentially linear structure of the high-concentration impurity semiconductor region can be applied to photoelectric conversion elements employing a shielded structure. For example, a photoelectric conversion element employing a shielded structure includes a conductive layer formed above a low-concentration impurity semiconductor layer. This conductive layer extends along the length of the high-concentration impurity semiconductor region, faces at least a portion of the high-concentration impurity semiconductor region and the thickness direction of the low-concentration impurity semiconductor layer, and is connected to a fixed potential.

[0027] For example, in a structure where the width of the first conductive layer is equal to the linewidth of the high-concentration impurity semiconductor region and the thickness covers the entire high-concentration impurity semiconductor region, electromagnetic noise intruding into the high-concentration impurity semiconductor region from the outside can be effectively blocked by the first conductive layer. Therefore, photoelectric conversion elements using this structure can exhibit high shielding performance against external electromagnetic noise.

[0028] In photoelectric conversion elements employing the aforementioned shielding structure, as the proportion of high-concentration impurity semiconductor regions in the light-receiving region increases, the area shielded by the first conductive layer also increases, leading to a reduction in the amount of light received. This reduction in the amount of light received causes a decrease in the photocurrent value.

[0029] In a structure where the high-concentration impurity semiconductor region is essentially linear, the light-blocking area of ​​the first conductive layer can be as close to 0 (zero) as possible. Therefore, the reduction in light reception caused by the shielding structure can be suppressed, thereby suppressing the decrease in photocurrent value.

[0030] It goes without saying that the linear structure of the high-concentration impurity semiconductor region can also be applied to photoelectric conversion devices without shielding. Photoelectric conversion devices employing this linear structure can have an external shielding structure added.

[0031] When multiple high-concentration impurity semiconductor regions are set, the total area of ​​these regions should be controlled to account for less than 5% of the area of ​​the light-receiving region.

[0032] A photoelectric conversion element with a shielded structure was compared with a control group that was otherwise identical but without shielding. In the shielded photoelectric conversion element, to achieve a signal-to-noise ratio (S / N ratio) comparable to the unshielded element, the resistance value of the resistor connected to the photoelectric conversion element (current-to-voltage conversion resistor) must be increased. Specifically, the resistance value connected to the photoelectric conversion element must be increased proportionally to the square of the inverse of the photocurrent attenuation rate (the ratio of the reduction in photocurrent value of the shielded photoelectric conversion element to that of the unshielded photoelectric conversion element).

[0033] Furthermore, as the total area of ​​high-concentration impurity semiconductor regions increases, the junction area between the low-concentration impurity semiconductor layer and the high-concentration impurity semiconductor region also increases, leading to an increase in the inter-terminal capacitance of the photoelectric conversion element.

[0034] The response speed of a photoelectric conversion element is significantly affected by the product of its inter-terminal capacitance and connection resistance. Therefore, as... Figure 17 As shown, the response speed of a photoelectric conversion element with a shielded structure decreases as the proportion of high-concentration impurity semiconductor regions in the light-receiving area increases. If the proportion of high-concentration impurity semiconductor regions in the light-receiving area is controlled to below 5%, the attenuation of the optical signal intensity can be suppressed to below -3dB compared to a photoelectric conversion element without a shielded structure. Therefore, even with a shielded structure, as long as the proportion of high-concentration impurity semiconductor regions in the light-receiving area is controlled to below 5%, adverse effects on the circuit design and specifications of this type of photoelectric conversion element can be avoided. Attached Figure Description

[0035] Various exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic cross-sectional view of the PIN photodiode structure according to an embodiment of the present invention.

[0036] Figure 2 yes Figure 1 The diagram shows a plan view of a PIN photodiode.

[0037] Figure 3 This is a schematic cross-sectional view of a PIN photodiode with a shielding structure.

[0038] Figure 4 yes Figure 3 The diagram shows a plan view of a PIN photodiode.

[0039] Figure 5 This is a schematic cross-sectional view of a PIN photodiode with a different shielding structure.

[0040] Figure 6 yes Figure 5 The diagram shows a plan view of a PIN photodiode.

[0041] Figure 7 This is a schematic cross-sectional view of a PIN photodiode with another type of shielding structure.

[0042] Figure 8 yes Figure 7 The diagram shows a plan view of a PIN photodiode.

[0043] Figure 9 This is a cross-sectional schematic diagram of a PIN photodiode with yet another type of shielding structure.

[0044] Figure 10 yes Figure 9 The diagram shows a plan view of a PIN photodiode.

[0045] Figure 11 This is a cross-sectional schematic diagram of a PIN photodiode with another type of shielding structure.

[0046] Figure 12 yes Figure 11 The diagram shows a plan view of a PIN photodiode.

[0047] Figure 13 This is a schematic cross-sectional view of a PIN photodiode with two electrodes arranged on its surface.

[0048] Figure 14 This is a cross-sectional view of another structural example, in which the two electrodes of a PIN photodiode are arranged on a surface.

[0049] Figure 15Yes Figure 14 Planar view of the PIN photodiode shown

[0050] Figure 16 Is a cross-sectional view illustrating the structure of a conventional PIN photodiode

[0051] Figure 17 Is a graph showing the relationship between the ratio of the high-concentration impurity semiconductor region in the light-receiving region and the response speed in a photoelectric conversion element employing a shield structure, and comparing it with the response speed (corresponding response speed) of a photoelectric conversion element not employing a shield structure Detailed implementation mode

[0052] <PIN Photodiode> Figure 1 Is a schematic cross-sectional view of the structure of PIN photodiode 1 according to an embodiment of the present invention Figure 2 Is a plan view of PIN photodiode 1

[0053] PIN photodiode 1 includes a substrate 11 constituting its main body. The substrate 11 is made of, for example, p-type silicon (Si)

[0054] An i-layer (intrinsic layer) 12 is stacked on the substrate 11. The i-layer 12 is composed of p-type silicon with a doping concentration lower than that of the substrate 11, and its impurity (acceptor) concentration is 1e16 cm - ³ or lower. The i-layer 12 can be formed by, for example, epitaxial growth or the like

[0055] On the surface layer of the i-layer 12, multiple (such as Figure 1 and Figure 2 shown in the structure as five) n + -type semiconductor regions 13 are formed. The impurity doping concentration of the n + -type semiconductor region 13 is higher than that of the i-layer 12. The n + -type semiconductor region 13 is formed by diffusing impurities (donors) from the surface into the interior of the i-layer 12. As Figure 2 shown, the n + -type semiconductor region 13 is formed in a linear shape, extends in a single direction in a plan view, and has substantially no width in the width direction (this direction is perpendicular to both the length direction of the n + -type semiconductor region 13 and the thickness direction of the i-layer 12). The n + -type semiconductor region 13 extends outward in the vertical direction (i.e., the length direction of the n + -type semiconductor region 13) beyond the outer edge of the light-receiving region LA. In addition, multiple n + -type semiconductor regions 13 are arranged at intervals in the lateral direction (i.e., the width direction of the n + [[ID=5

[0056] An insulating film 14 is formed on the i-layer 12, which surrounds the light-receiving region LA. The insulating film 14 does not cover the light-receiving region LA. Therefore, the surface of the i-layer 12 is exposed outside the insulating film 14 throughout the entire light-receiving region LA. That is, the insulating film 14 has an opening to expose the surface of the i-layer 12, and the light-receiving region LA is defined by this opening. The insulating film 14 is made of an insulating material such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0057] An antireflective film 15 is formed on the surface of layer 12 within the light-receiving region LA. The antireflective film 15 is made of a dielectric material with a refractive index between that of silicon and air, such as silicon nitride (Si3N4) or magnesium fluoride (MgF2).

[0058] An electrode 16, made of a metallic or non-metallic conductive material, is disposed outside the light-receiving region LA in the vertical direction when viewed from above. The electrode 16 extends laterally linearly on the insulating film 14, spanning multiple n... + Type semiconductor region 13. On insulating film 14, along the thickness direction, with each n + At a position opposite to the semiconductor region 13, a contact hole (not shown) is formed penetrating the thickness direction of the insulating film 14. The contact hole is filled with the material of the electrode 16. The electrode 16 communicates with each n-type semiconductor region through the contact hole. + Type semiconductor region 13 is connected.

[0059] An electrode 17, made of a metallic or non-metallic conductive material, is formed on the back side of the substrate 11.

[0060] In PIN photodiode 1, electrode 16 serves as the cathode and electrode 17 as the anode. To apply reverse bias, electrode 16 (cathode) must be connected to a high potential and electrode 17 (anode) to a low potential. Furthermore, PIN photodiode 1 is connected to an amplifier circuit, such as a transimpedance amplifier (TIA). Electrode 17 (anode) is connected to the input of the TIA via wiring.

[0061] When a reverse bias is applied to PIN photodiode 1, the depletion layer from n + The junction of semiconductor region 13 and i-layer 12 diffuses into i-layer 12. When light shines on the light-receiving region LA, electrons in the valence band are excited to the conduction band, leaving holes in the valence band. Thus, charge carriers (electrons and holes) are mainly generated within i-layer 12. Electrons then migrate to n-layer 12. + Holes migrate to the neutral region of the substrate 11 while the cathode is in the neutral region of the semiconductor region 13. As a result, current flows from electrode 16 (cathode) to the input of the transimpedance amplifier and through its feedback resistor. The current flowing through this feedback resistor is converted into a voltage, which is output from the transimpedance amplifier.

[0062] As described above, in PIN photodiode 1, multiple linear n + Semiconductor regions 13 are formed on the surface layer of layer i 12 and are spaced apart in the lateral direction. The inter-terminal capacitance of the PIN photodiode 1 is the sum of the package capacitance and the junction capacitance. The junction capacitance depends on the inter-terminal capacitance of layer i 12 and n. + The junction area (i.e., the junction area) of semiconductor region 13. For example... Figure 16 As shown, in a traditional PIN photodiode, n + Region 103 employs a large-area planar structure. In contrast, the n in PIN photodiode 1... + The semiconductor region 13 is linear. Therefore, this device can achieve a smaller junction capacitance than conventional PIN photodiodes, thereby reducing inter-terminal capacitance. This improves the response speed of the PIN photodiode 1.

[0063] To compare with traditional PIN photodiodes (see...) Figure 16 ) and PIN photodiode 1, specific numerical examples are provided. Assume the light-receiving area size of a conventional PIN photodiode is 1 mm × 1 mm. Furthermore, in a conventional PIN photodiode, n + The junction depth (i.e., n) of type region 103 + The thickness of region 103 relative to the surface of layer i 102 is 0.4 μm, while the thickness of layer i 102 and n + The junction area of ​​region 103 is approximately 1 mm². 2 For the PIN photodiode 1, the size of its light-receiving region LA is set to be the same as that of a conventional PIN photodiode. Furthermore, in the PIN photodiode 1, n + The junction depth of semiconductor region 13 is 0.4 μm. The light-receiving region LA contains n + The linewidth (lateral length) of semiconductor region 13 is set to 0.4 μm, n + The line length (vertical length) of semiconductor region 13 and adjacent n + The spacing (hereinafter referred to as "line spacing") between the type semiconductor regions 13 is set to 30 μm, so that the i-layer 12 and n-layer 13 are connected. + The junction area between the semiconductor regions 13 is approximately 1 / 25 of that of a conventional PIN photodiode. Therefore, the junction capacitance of the PIN photodiode 1 is approximately 1 / 25 of that of a conventional PIN photodiode, allowing the inter-terminal capacitance of the PIN photodiode 1 to be smaller than that of a conventional PIN photodiode. The PIN photodiode 1 using this design can be manufactured using widely adopted 0.25μm process specifications.

[0064] n +The linewidth of the semiconductor region 13 is limited by the process specifications (process node) used to manufacture the PIN photodiode 1. For example, if the PIN photodiode 1 is manufactured using a 0.6μm process specification, then n + The linewidth of the semiconductor region 13 is at least approximately 1 μm. When the PIN photodiode 1 is manufactured using a 0.25 μm process specification, n + The linewidth of the semiconductor region 13 is at least approximately 0.4 μm. By employing finer process rules to fabricate the PIN photodiode 1, the n-type semiconductor region 13 can be reduced in size. + The linewidth of the semiconductor region 13 is increased, thereby further reducing the junction capacitance.

[0065] When PIN photodiode 1 is used for optical communication, n + The linewidth of the type semiconductor region 13 can be set according to the transmission rate of optical communication. For example, the material of the i-layer 12 can be a compound semiconductor such as gallium arsenide (GaAs), and is not limited to silicon. When the i-layer 12 is made of a compound semiconductor, it is expected that the PIN photodiode 1 can receive optical signals with a rate of 40 Gbps and above. Based on this assumption, considering n + The lateral mobility of minority carriers in semiconductor region 13 is optimized, and the linewidth of this region should preferably be controlled within 2 μm. To meet the current demand for maximum communication rates of 100 Gbps, it is even more preferable to [further optimize the process]. + The linewidth of the semiconductor region 13 is controlled to be within 1μm.

[0066] In addition, the size of the light-receiving region LA is typically 200 μm. 2 Or larger. Even if the PIN photodiode 1 uses the smallest size (200μm) 2 The optical receiving area (LA) is designed, and n + When the junction depth of the semiconductor region 13 is 0.4 μm, the linewidth is 2 μm, and the line spacing is 20 μm, the junction area and junction capacitance of the PIN photodiode 1 can still reach about 1 / 7 of those of a conventional photodiode with a light-receiving region of the same size. For a region with a 200 μm junction depth... 2 Even with a line spacing of 20 μm or greater, the conversion efficiency of the PIN photodiode 1 with a light receiving area LA remains essentially unchanged.

[0067] When layer 12 is made of silicon, assuming it receives near-infrared light with a wavelength ≤ 870 nm and an absorption coefficient α of approximately 500, if the thickness of layer 12 is 32 μm, more than 80% of the received optical signal can be absorbed by layer 12. When layer 12 is made of compound semiconductor, assuming it receives light with a wavelength of 850 nm (for example), and its extinction coefficient α is 8000 or higher, if the thickness of layer 12 is 2 μm, more than 80% of the received optical signal can be absorbed. Therefore, the thickness of layer 12 should preferably be between 2 and 32 micrometers.

[0068] Furthermore, holes generated in layer 12 due to light irradiating the light-receiving region LA will move towards the substrate 11 along the thickness direction. On the other hand, with the line spacing (adjacent n... + As the distance between the semiconductor regions 13 increases, the amount of electrons generated in layer i 12 moving perpendicular to the thickness direction will be greater, and their movement direction will be towards n. + Type semiconductor region 13. Depending on the line spacing, the amount of movement perpendicular to the thickness direction may be greater than the amount of movement in the thickness direction.

[0069] Therefore, by changing the line spacing, the amount of electrons reaching n generated by light irradiation can be adjusted. + The average arrival time of the type semiconductor region 13 is used to adjust the conversion efficiency of the PIN photodiode 1. Because n + The linewidth of the semiconductor region 13 is small enough relative to the line spacing to enable high-precision adjustment of the conversion efficiency of the PIN photodiode 1.

[0070] Furthermore, by changing the line spacing, the rising waveform of the photocurrent generated by illumination can be adjusted. This is because the electron mobility in semiconductors is greater than that of holes (e.g., the electron mobility in a single-crystal silicon substrate is 1500 cm⁻¹). 2 / V·s, hole mobility is 450cm 2 Increasing the line spacing (n / V·s) makes the electron propagation time closer to the hole propagation time, thus smoothing the rise and fall waveforms of the photocurrent. Relative to the line spacing, n + The linewidth of the semiconductor region 13 is small enough to enable high-precision control of the rising and falling waveforms of the photocurrent.

[0071] Furthermore, if undepleted regions exist in a portion of layer i, the component carriers generated by photoelectric conversion will also appear in these undepleted regions (most carrier holes are not generated), and these component carriers move within the undepleted regions. Even in this case, if the line spacing is sufficiently large relative to the average penetration depth of the light incident on layer i, the arrival of electrons in layer n can still be modulated. + The average arrival time of the semiconductor region 13 is adjusted to improve the conversion efficiency of the PIN photodiode 1.

[0072] Furthermore, when light of the wavelength that penetrates the i-layer 12 and reaches the substrate 11 illuminates the light-receiving region LA, photoelectric conversion also occurs in the substrate 11, generating electrons as partial charge carriers. The impurity charge carriers generated in the substrate 11 reduce the response speed of the PIN photodiode 1. Therefore, a barrier layer (a layer that acts as a potential barrier to impurity charge carrier electrons) can be provided between the substrate 11 and the i-layer 12. This layer needs to be homogeneous with the substrate 11 (p-type) and have a higher concentration to improve the response characteristics.

[0073] In the PIN photodiode 1, since electrode 16 (connecting n) is not formed on the light-receiving region LA. + (parallel wiring of semiconductor region 13), so that electrode 16 will not interfere with the light irradiated to light receiving region LA.

[0074] Furthermore, since no insulating film 14 is formed on the light-receiving region LA, the entire exposed area of ​​the i-layer 12 on the light-receiving region LA can be covered by the anti-reflective film 15.

[0075] When the PIN photodiode 1 is connected to the transimpedance amplifier, if the capacitance between its pins is small, there is no need to add the feedback capacitor required for the negative feedback stability of the transimpedance amplifier, thus effectively suppressing noise near the cutoff frequency of the transimpedance amplifier. Furthermore, since there is no need to add a feedback capacitor to the transimpedance amplifier to reduce noise, its frequency bandwidth is unrestricted, thereby enabling a wider bandwidth to be achieved.

[0076] <Shielding Structure 1> Figure 3 This is a schematic cross-sectional view showing the structure of the PIN photodiode 21 equipped with a shielding structure. Figure 4 This is a plan view of the PIN photodiode 21. (Refer to...) Figure 3 and Figure 4 , respectively corresponding to Figure 1 and Figure 2 The components shown are labeled with the same reference numerals as those shown. Descriptions of components with the same reference numerals will be omitted below.

[0077] The PIN photodiode 21 is fabricated together with other semiconductor devices such as a CMOS (Complementary Metal-Oxide-Semiconductor) transistor on the substrate 11 that forms the main body. Therefore, on the i-layer 12, the interlayer films 22 and 23, which are included in the multilayer wiring structure of other semiconductor devices, are stacked sequentially from the i-layer 12 side. In the light-receiving region LA, the interlayer films 22 and 23 are also retained on the i-layer 12 and are not removed. The interlayer films 22 and 23 are made of insulating materials such as silicon dioxide or silicon nitride.

[0078] A first conductive layer 24 is disposed on the interlayer film 23, which corresponds to each n + Type semiconductor region 13. The first conductive layer 24 extends vertically to n + Above the type semiconductor region 13, and in the thickness direction with the entire n +Opposite to the semiconductor region 13. The first conductive layer 24 is made of a metallic or non-metallic conductive material (e.g., polycrystalline silicon). Outside the light-receiving region LA, for example, another interlayer film is further stacked on the interlayer film 23, and wiring (fixed potential wiring) connected to a fixed potential (e.g., ground potential or power supply potential) is formed on this interlayer film. The first conductive layer 24 is connected to the wiring through vias that perpendicularly penetrate the interlayer film, thereby connecting to the fixed potential.

[0079] With this structure, even external electromagnetic noise can be directed towards n + When the semiconductor region 13 penetrates, the electromagnetic noise is also blocked by the first conductive layer 24. Therefore, external electromagnetic noise can be prevented from reaching n. + Type semiconductor region 13, to eliminate the harmful effects of electromagnetic noise.

[0080] In the PIN photodiode 21, the first conductive layer 24 is described as being perpendicular to the entire underlying n-layer in the thickness direction. + The type semiconductor region 13 is opposite. However, even if the first conductive layer 24 is only opposite to the lower n in the thickness direction. + Although a portion of the semiconductor region 13 is relatively isolated, it can still provide a certain degree of electromagnetic noise shielding.

[0081] Although the first conductive layer 24 is described as a fixed-potential wiring connected to the outside of the light-receiving region LA, this layer can also be connected to a fixed-potential wiring inside the light-receiving region LA. Furthermore, a highly concentrated impurity-doped semiconductor region can be formed in the surface region of the i-layer 12, through which the first conductive layer 24 can be connected to the fixed potential.

[0082] Furthermore, the first conductive layer 24 can be divided into two parts in the vertical direction, with these partitions spaced apart from each other in the vertical direction (forming a gap between the two partitions), and each partition can be connected to a fixed potential outside the light-receiving region LA. The first conductive layer 24 can also be divided into three or more parts in the vertical direction, with these partitions spaced apart from each other in the vertical direction, and each partition connected to a fixed potential outside or inside the light-receiving region LA. In other words, regardless of whether the first conductive layer 24 is divided into multiple parts in the vertical direction, its connection method is not limited as long as the first conductive layer 24 can be connected to a fixed potential.

[0083] <Shielding Structure 2> Figure 5 This is a schematic cross-sectional view of a PIN photodiode 31 that employs a different shielding structure. Figure 6 This is a plan view of the PIN photodiode 31. (Refer to...) Figure 5 and Figure 6 ,and Figure 3 and Figure 4The corresponding parts shown use the same reference numerals. Components with the same reference numerals will not be described again below.

[0084] Like PIN photodiode 21, PIN photodiode 31 is fabricated on the substrate 11 that forms the main body, together with other semiconductor devices. In PIN photodiode 31, an interlayer film 22 is formed on the i-layer 12 within the light-receiving region LA.

[0085] A plurality of second conductive layers 32 are disposed on the interlayer film 22, corresponding to each n + Type semiconductor region 13. Each second conductive layer 32 has its corresponding n + The semiconductor region 13 extends vertically above it. Multiple second conductive layers 32 are respectively positioned in the thickness direction relative to n... + Different portions of the semiconductor region 13 are relative. For example... Figure 5 and Figure 6 In the structure shown, each n + Two second conductive layers 32 are disposed above the semiconductor region 13. These two second conductive layers 32 are respectively positioned in the lateral direction and connected to n... + One edge and the other edge of the n+ type semiconductor region 13 are opposite each other in the thickness direction. The second conductive layer 32 is opposite to the n+ type semiconductor region 13 along its entire length in the vertical direction. The second conductive layer 32 is made of a metallic or non-metallic conductive material (e.g., polycrystalline silicon). Outside the light-receiving region LA, for example, another interlayer film is further stacked on the interlayer film 22, and wiring connected to a fixed potential (such as ground potential or power supply potential) is formed on this interlayer film (fixed potential wiring). The second conductive layer 32 is connected to the fixed potential wiring through vias penetrating the thickness direction of the dielectric film, thereby connecting to the fixed potential.

[0086] In this structure, when external electromagnetic noise is directed towards n + When the semiconductor region 13 invades, the noise will be blocked by the second conductive layer 32. Therefore, external electromagnetic noise can be prevented from reaching n. + Type semiconductor region 13, to eliminate the adverse effects caused by electromagnetic noise.

[0087] Although the second conductive layer 32 is described above as being connected to a fixed-potential wiring outside the light-receiving region LA, the second conductive layer 32 can also be connected to a fixed-potential wiring inside the light-receiving region LA. Furthermore, a highly concentrated impurity-doped semiconductor region can be formed in the surface region of layer i 12, and the second conductive layer 32 can be connected to the fixed potential through this semiconductor region.

[0088] Furthermore, the second conductive layer 32 can be divided into two parts in the vertical direction, with these partitions spaced apart from each other in the vertical direction (forming a gap between the two partitions), and each part can be connected to a fixed potential outside the light-receiving region LA. The second conductive layer 32 can also be divided into three or more parts in the vertical direction, with these partitions spaced apart from each other in the vertical direction, and each partition connected to a fixed potential outside or inside the light-receiving region LA. In other words, regardless of whether the second conductive layer 32 is divided into multiple parts in the vertical direction, its connection method is not limited as long as the second conductive layer 32 can be connected to a fixed potential.

[0089] Because the second conductive layer 32 is perpendicular to n in the thickness direction + The portion of the semiconductor region 13 is opposite, and therefore can also be regarded as an embodiment of the "first conductive layer" of the present invention.

[0090] <Shielding Structure 3> Figure 7 This is a schematic cross-sectional view of a PIN photodiode 41 employing a different shielding structure. Figure 8 This is a plan view of the PIN photodiode 41. (Refer to...) Figure 7 and Figure 8 , respectively corresponding to Figure 3 and Figure 4 The areas shown are labeled with the same reference numerals. Descriptions of these areas with the same reference numerals will be omitted below.

[0091] Similar to PIN photodiode 21, PIN photodiode 41 is fabricated on the substrate 11 that forms the main body, co-fabricated with other semiconductor elements. In PIN photodiode 41, a first conductive layer 42 is formed on the interlayer film 23, which corresponds to each n... + Type semiconductor region 13. The first conductive layer 42 extends vertically to n + Above the semiconductor region 13. This first conductive layer is perpendicular to the entire n-type semiconductor region in the thickness direction. + The semiconductor region 13 is opposite. Furthermore, the lateral dimension of the first conductive layer 42 is greater than n. + Type semiconductor region 13. Therefore, the first conductive layer 42 is respectively connected to n on both sides in the lateral direction. + Semiconductor region 13 is opposite to i-layer 12 on both sides in the lateral direction. The first conductive layer 42 is made of a metallic or non-metallic conductive material (e.g., polysilicon). The first conductive layer 42 is connected to wiring with a fixed potential (fixed potential wiring) such as ground potential or power supply potential outside the light receiving region LA.

[0092] Furthermore, vias 43 and 44 are formed in the lateral direction between one end of the first conductive layer 42 and the other end, and between the first conductive layer 42 and the i-layer 12, respectively. The vias 43 and 44 are made of metal (such as tungsten). The vias 43 and 44 penetrate the interlayer films 22 and 23. The length of the vias 43 and 44 extending in the vertical direction is greater than n. + The vertical length of the semiconductor region 13. The upper ends of vias 43 and 44 are connected to the first conductive layer 42, and the lower ends are connected to the i-layer 12. In the i-layer 12, contact regions 45 and 46 with a higher doped acceptor concentration than the surrounding region are formed at the connection of vias 43 and 44. In other words, on the surface layer of the i-layer 12, at n + On both sides (arranged laterally), p-type contact regions 45 and 46 with a higher doping concentration than the surrounding region are respectively provided. Contact regions 45 and 46 extend in the vertical direction, and the lower ends of vias 43 and 44 are connected to contact regions 45 and 46 respectively. Thus, vias 43 and 44 form ohmic contacts with i-layer 12.

[0093] With this structure, even if electromagnetic noise penetrates from the outside along the thickness direction, n + In the semiconductor region 13, this noise is also blocked by the first conductive layer 42. Furthermore, even if electromagnetic noise intrudes from the outside at an angle intersecting with the thickness direction, n... + In the semiconductor region 13, this noise is also blocked by the first conductive layer 42 or vias 43 and 44. Therefore, external electromagnetic noise can be prevented from reaching n. + Type semiconductor region 13, to eliminate the harmful effects of electromagnetic noise.

[0094] Although the first conductive layer 42 is described as a fixed-potential wiring connected to the outside of the light-receiving region LA, this conductive layer can also be connected to a fixed-potential wiring inside the light-receiving region LA. Furthermore, a highly concentrated impurity-doped semiconductor region can be formed on the surface of the i-layer 12, through which the first conductive layer 42 can be connected to the fixed potential.

[0095] Furthermore, the first conductive layer 42 can be divided into two parts in the vertical direction, with these partitions spaced apart from each other in the vertical direction (forming a gap between the two partitions), and each part can be connected to a fixed potential outside the light-receiving region LA. The first conductive layer 42 can also be divided into three or more parts in the vertical direction, with these partitions spaced apart from each other in the vertical direction, and each partition connected to a fixed potential outside or inside the light-receiving region LA. That is, regardless of whether the first conductive layer 42 is divided into multiple parts in the vertical direction, as long as the first conductive layer 42 can be connected to a fixed potential, its connection method is unrestricted.

[0096] In addition, vias 43 and 44 can each be divided into multiple parts along the vertical direction. These partitions are spaced apart from each other in the vertical direction, and there may be gaps between adjacent partitions.

[0097] <Shielding Structure 4> Figure 9 This is a schematic cross-sectional view of a PIN photodiode 51 with a different shielding structure. Figure 10 This is a plan view of the PIN photodiode 51. (Refer to...) Figure 9 and Figure 10 ,and Figure 7 and Figure 8 The corresponding parts shown use the same reference numerals. Descriptions of the parts with the same reference numerals will be omitted below.

[0098] The PIN photodiode 51 is similar to the PIN photodiode 21, both being fabricated together with other semiconductor elements on the substrate 11 that constitutes the main body. In the PIN photodiode 51, multiple second conductive layers 52 are formed on the interlayer film 22, each corresponding to a specific n... + Semiconductor region 13. Each second conductive layer 52 extends vertically to the corresponding n. + Above the semiconductor region 13. Each second conductive layer 52 may be in the thickness direction with n + Different portions of the semiconductor region 13 may or may not be opposite. For example... Figure 9 and Figure 10 In the structure shown, each n + Two second conductive layers 52 are disposed above the semiconductor region 13, and the two second conductive layers 52 are not perpendicular to n in the thickness direction. + Type semiconductor region 13 is opposite. In Figure 9 and 10 In the structure shown, each n + Two second conductive layers 52 are disposed above the semiconductor region 13, and these two second conductive layers 52 are not perpendicular to n in the thickness direction. + The semiconductor region 13 is opposite. The second conductive layer 52 is made of a metallic or non-metallic conductive material (e.g., polycrystalline silicon).

[0099] Furthermore, in the PIN photodiode 51, one side of the first conductive layer 42 on the interlayer film 23 faces the second conductive layer 52 in the thickness direction. Additionally, vias 53 and 54 are formed laterally between the two ends of the first conductive layer 42 and the second conductive layer 52. The vias 53 and 54 are made of a metal such as tungsten and penetrate the interlayer film 23. The upper ends of the vias 53 and 54 are connected to the first conductive layer 42, and the lower ends are connected to the second conductive layer 52. Furthermore, the length of the vias 53 and 54 extending in the vertical direction is greater than n. + The vertical length of the semiconductor region 13.

[0100] This structure ensures that even if electromagnetic noise intrudes from the outside along the thickness direction, n + In the semiconductor region 13, this noise is also blocked by the first conductive layer 42 or the second conductive layer 52. Furthermore, even if electromagnetic noise intrudes from the outside at an angle intersecting the thickness direction, n... + In the semiconductor region 13, the electromagnetic noise is also blocked by the first conductive layer 42, the second conductive layer 52, or vias 53 and 54. Therefore, external electromagnetic noise can be prevented from reaching n. + Type semiconductor region 13, to eliminate the harmful effects of electromagnetic noise.

[0101] In addition, vias 53 and 54 can be divided into multiple parts along the vertical direction. These separated parts are spaced apart from each other in the vertical direction, and there may be gaps between adjacent separated parts.

[0102] In addition, the first conductive layer 42 can be connected to a fixed potential, while the second conductive layer 52 can be connected to a fixed potential outside or inside the light receiving region LA.

[0103] <Shielding Structure 5> Figure 11 This is a schematic cross-sectional view of a PIN photodiode 61 that employs a different shielding structure. Figure 12 This is a plan view of the PIN photodiode 61. (Refer to...) Figure 11 and Figure 12 , respectively corresponding to Figure 3 and Figure 4 The components shown use the same reference numerals. Descriptions of components with the same reference numerals will be omitted below.

[0104] Similar to PIN photodiode 21, PIN photodiode 61 is fabricated on the substrate 11 that forms the main body, together with other semiconductor devices. In PIN photodiode 61, multiple (e.g., ...) are disposed in the surface region of layer i 12. Figure 11 and Figure 12 The structure shown contains six p) + Type semiconductor region 62. p + The p-type semiconductor region 62 is formed by diffusing impurities (acceptors) from the surface of layer i 12, and its doping concentration is higher than that of layer i 12. + The type semiconductor region 62 forms a vertically linearly extending strip structure, which is related to the n-type semiconductor region 62. + The semiconductor regions 13 are spaced apart in the lateral direction. Wiring is formed outside the light-receiving region LA, for example, on the interlayer film 22. + Type semiconductor region 62 is connected to a fixed potential (such as ground potential or power supply potential) via wiring, thereby enabling the adjacent n + Type semiconductor region 13 and p +A reverse bias voltage is applied between the semiconductor regions 62.

[0105] With this structure, even external electromagnetic noise can be directed towards n + Even if the semiconductor region 13 penetrates, it will be blocked by the first conductive layer 24. Furthermore, even if electromagnetic noise penetrates from the outside into the adjacent n... + Within the semiconductor region 13, this noise will still be p + The semiconductor region 62 is blocked. Therefore, external electromagnetic noise can be prevented from reaching n. + Type semiconductor region 13, to eliminate the harmful effects of electromagnetic noise.

[0106] Although the above p + The semiconductor region 62 is connected to a fixed potential via wiring outside the light-receiving region LA, but this region can also be connected to a fixed potential via wiring inside the light-receiving region LA. Furthermore, p-shaped structures extending perpendicular to the vertical direction can be formed on the surface layer of layer i12. + Type semiconductor region, and p + Type semiconductor region 62 extends through p in a direction perpendicular to the vertical direction + The semiconductor region is connected to a fixed potential.

[0107] In addition, p + The semiconductor region 62 can be divided into two parts in the vertical direction, these partitions being spaced apart from each other in the vertical direction (forming a gap between the two partitions), and each part can be connected to a fixed potential outside the light-receiving region LA. + The semiconductor region 62 can be vertically divided into three or more segments, which are spaced apart from each other in the vertical direction. Each segment is connected to a fixed potential outside or inside the light-receiving region LA. That is, regardless of p + Whether the semiconductor region 62 is divided into multiple parts in the vertical direction depends on p. + The semiconductor region 62 can be connected to a fixed potential, so the connection method is not limited.

[0108] <Surface Electrode 1> Figure 13 This is a schematic cross-sectional view of the PIN photodiode 1, where electrode 17 is located on the surface.

[0109] exist Figure 1 In the structure shown, electrode 17 is formed on the back side of substrate 11. However, as... Figure 13 As shown, electrode 17 can also be formed on the surface of PIN photodiode 1. Figure 13 In the PIN photodiode 1 shown, a ring-shaped p is formed around the light-receiving region LA by diffusing impurities (acceptors) from the surface to the peripheral region of the surface layer i 12.+ Contact area 76. An annular contact hole is formed on the portion of the insulating film 14 surrounding the light-receiving region LA, extending through the thickness of the insulating film 14 towards the contact area 76. The contact hole is filled with the material of the electrode 17. The electrode 17 is connected to the contact area 76 through the contact hole, thereby forming an ohmic contact with the i-layer 12.

[0110] Furthermore, due to p + The contact area 76 is formed in a ring structure surrounding the light receiving area LA, which can suppress the diffusion of the depletion layer from the interior of the light receiving area LA in the vertical and lateral directions, thereby suppressing the adverse effects of the depletion layer diffusion on the surrounding circuits.

[0111] <Surface Electrode 2> Figure 14 This is a cross-sectional schematic diagram of another structure, in which the electrode 17 of the PIN photodiode 1 is arranged on the surface. Figure 15 yes Figure 14 The diagram shows a plan view of the structure.

[0112] like Figure 13 In the structure shown, p + The contact area 76 is formed in the peripheral region of the surface layer portion of layer i 12. In contrast, in Figure 14 and Figure 15 In the structure shown, p + Type contact area 77 is disposed in the adjacent linear n in the surface layer region of layer i 12. + Between the type semiconductor regions 11 and 12. The contact region 77 is formed by diffusing impurities (acceptors) from the surface of the i-layer 12, and its doping concentration is higher than that of the substrate 11 and the i-layer 12. Furthermore, when viewed from above, the contact region 77 extends linearly in the vertical direction, extending straight outward in the vertical direction beyond the two edges of the light-receiving region LA.

[0113] Furthermore, an electrode 17, made of a metallic or non-metallic conductive material, is formed on the insulating film 14. This electrode 17 is located in a region perpendicular to the electrode 16 in the vertical direction, extending beyond the light-receiving region LA in a plan view. The electrode 17 extends linearly in the lateral direction, spanning multiple contact areas 77. At each contact area 77, opposite the electrode 17 in the thickness direction, a contact hole (not shown) is formed on the insulating film 14, penetrating its thickness direction. The contact hole is filled with the material of the electrode 17. The electrode 17 forms an ohmic contact with each contact area 77 through the contact hole.

[0114] <Improved Embodiment> For example, layer 12 can be made of p-type silicon with a lower doping concentration than substrate 11, or it can be made of intrinsic semiconductor (single crystal silicon) without impurities.

[0115] exist Figure 9 and Figure 10In the PIN photodiode 51 shown, vias 53 and 54 can be omitted, and the first conductive layer 42 and the second conductive layer 52 are connected to a fixed potential outside the light-receiving region LA. In this structure, when electromagnetic noise invades from the outside along the thickness direction, n + When the semiconductor region 13 is in the form of a semiconductor, the noise can be blocked by the first conductive layer 42 or the second conductive layer 52. Furthermore, even if electromagnetic noise intrudes from the outside at an angle intersecting the thickness direction, n... + In the semiconductor region 13, the noise can still be blocked by the first conductive layer 42 or the second conductive layer 52. Therefore, this solution can effectively prevent external electromagnetic noise from reaching n. + Type semiconductor region 13, to eliminate its harmful effects.

[0116] exist Figure 13 In the structure shown, the contact area 76 and the electrode 17 can form a shape that surrounds the light-receiving region LA on three sides. The L-shaped structure formed by the contact area 76 and the electrode 17 extends vertically and laterally outside the light-receiving region LA. The contact area 76 and the electrode 17 can form a strip-like structure that extends linearly on both the vertical and horizontal sides relative to the light-receiving region LA. The contact area 76 and the electrode 17 can also form a strip-like structure that extends linearly vertically or laterally outside the light-receiving region LA.

[0117] The foregoing embodiments describe a configuration in which n + The semiconductor region 13 is formed in a plan view as a straight line extending in a single direction. However, as long as n + The semiconductor region 13 forms a linear structure, the shape of which does not have to be strictly straight. For example, its shape can be partially curved or bent (such as arc or approximately V-shaped), or it can be serpentine or sawtooth-shaped.

[0118] In addition, at least one n can be set. + Type semiconductor region 13.

[0119] Multiple n can be used + The semiconductor regions 13 are arranged in an interleaved manner. For example, multiple n... + The semiconductor region 13 can be arranged in a grid or mesh pattern.

[0120] Furthermore, although the case where the first conductivity type is p-type and the second conductivity type is n-type has been described, the first conductivity type can also be n-type and the second conductivity type can also be p-type.

[0121] Detailed embodiments of the present invention have been disclosed herein as needed; however, it should be understood that the disclosed embodiments are merely examples of the present invention, which can be implemented in various forms. Therefore, the specific structural and functional details disclosed herein should not be construed as limiting, but rather serve as the basis for the claims and as a representative basis for teaching those skilled in the art how to flexibly apply the present invention in virtually any suitable detailed structure.

[0122] While the exemplary embodiments of the invention disclosed in this specification clearly achieve the above objectives, those skilled in the art will understand that numerous modifications and other embodiments can be devised. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and embodiments, provided they fall within the spirit and scope of the invention.

Claims

1. A photoelectric conversion element, comprising: First conductivity type semiconductor layer; A low-concentration impurity semiconductor layer formed on the first conductivity type semiconductor layer and having an impurity concentration lower than that semiconductor layer; as well as A high-concentration impurity semiconductor region is formed on the surface layer of the low-concentration impurity semiconductor layer, having a second conductivity type different from the first conductivity type and an impurity concentration higher than that of the low-concentration impurity semiconductor layer. The high-concentration impurity semiconductor region is linear and has virtually no width in the width direction perpendicular to the length direction of the high-concentration impurity semiconductor region and the thickness direction of the low-concentration impurity semiconductor layer.

2. The photoelectric conversion element according to claim 1, wherein... The photoelectric conversion element is provided with a light-receiving region for receiving external light entering the low-concentration impurity semiconductor layer. The width of the high-concentration impurity semiconductor region is set such that the ratio of the width of this region to the width of the light-receiving region in the width direction is less than or equal to 1%.

3. The photoelectric conversion element according to claim 1 further comprises: A first conductive layer is formed above the low-concentration impurity semiconductor layer. The first conductive layer extends along the length direction, is opposite to at least a portion of the high-concentration impurity semiconductor region in the thickness direction, and is connected to a fixed potential.

4. The photoelectric conversion element according to claim 3 further comprises: Multiple second conductive layers are formed above the low-concentration impurity semiconductor layer. The plurality of second conductive layers extend along the length direction, face different portions of the high-concentration impurity semiconductor region in the thickness direction, and are connected to a fixed potential.

5. The photoelectric conversion element according to claim 3, further comprising: An interlayer film formed between the low-concentration impurity semiconductor layer and the first conductive layer; as well as Two vias extending in the length direction and penetrating the interlayer film in the thickness direction connect the first conductive layer and the low-concentration impurity semiconductor layer, wherein... A first conductivity type contact region is formed in the surface layer region of the low-concentration impurity semiconductor layer, wherein the impurity concentration is higher than that of the low-concentration impurity semiconductor layer. This contact region is spaced apart from one side and the other side of the high-concentration impurity semiconductor region in the width direction. The two vias are respectively connected to contact areas on one side and the other side of the high-concentration impurity semiconductor region in the width direction.

6. The photoelectric conversion element according to any one of claims 1 to 5, further comprising: A fixed-potential connected semiconductor region having a first conductivity type is formed on the surface layer of the low-concentration impurity semiconductor layer. The fixed potential connected semiconductor region is spaced apart from the high concentration impurity semiconductor region in the width direction, extends in the length direction, and is connected to the fixed potential.

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