Test structure and preparation method thereof

Abstract

The invention discloses a test structure and a preparation method of the test structure, and belongs to the technical field of semiconductors. The test structure comprises an epitaxial layer, one side of the epitaxial layer is provided with a groove, and the groove is provided with a side wall and a bottom; the oxide layer covers the side wall and the bottom of the groove, and the first thickness of the oxide layer at the bottom of the groove is larger than the second thickness of the oxide layer at the side wall of the groove, so that the unit area capacitance of the bottom of the groove is smaller than that of the side wall of the groove. According to the test structure, the first thickness of the oxide layer at the bottom of the groove is larger than the thickness of the second oxide layer on the side wall, namely, the test structure with the thick bottom and the thin side wall is formed, and the thicker oxide layer at the bottom of the groove can shield the influence of the capacitance at the bottom of the groove, so that the interference of the capacitance at the bottom on data analysis can be weakened when the capacitance of the side wall is tested; and the accuracy of a gate-oxide interface quality evaluation result is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a test structure and a method for preparing the test structure. Background Technology

[0002] In the manufacturing process of semiconductor devices, especially MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), the interface quality of the gate oxide layer is a key factor affecting performance.

[0003] The interface quality of the gate oxide layer can be determined by detecting its capacitance characteristics. Traditionally, capacitance-voltage testing is performed using planar capacitor structures. However, with technological advancements, the gate oxide layers to be evaluated are no longer limited to simple planar structures but are increasingly found on the sidewalls and bottom of trenches. When extracting the sidewall capacitance of the trenches, the bottom capacitance interferes with the analytical data, making it difficult to accurately assess the gate oxide interface quality and affecting the precision of performance evaluation. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a test structure and a method for preparing the test structure. The thicker oxide layer at the bottom of the trench can shield the influence of the trench bottom capacitance, thereby reducing the interference of the bottom capacitance on data analysis when testing the sidewall capacitance and improving the accuracy of the gate oxide interface quality assessment results.

[0005] Firstly, this application provides a test structure, which includes: An epitaxial layer, with a groove on one side of the epitaxial layer, the groove having sidewalls and a bottom; An oxide layer covers the sidewalls and bottom of the trench. The first thickness of the oxide layer at the bottom of the trench is greater than the second thickness of the oxide layer at the sidewalls of the trench, so that the capacitance per unit area at the bottom of the trench is less than the capacitance per unit area at the sidewalls of the trench.

[0006] According to the test structure of this application, the first oxide layer thickness at the bottom of the trench is greater than the second oxide layer thickness on the sidewall, which forms a test structure with a thicker bottom and thinner sidewall. The thicker oxide layer at the bottom of the trench can shield the influence of the bottom capacitance, thereby reducing the interference of the bottom capacitance on data analysis when testing the sidewall capacitance and improving the accuracy of the gate oxide interface quality assessment results.

[0007] According to one embodiment of this application, the ratio of the first thickness to the second thickness ranges from 3 to 10.

[0008] According to one embodiment of this application, the first thickness is 1500 angstroms to 5000 angstroms.

[0009] According to one embodiment of this application, the test structure further includes: The conductive layer is located in the trench and is in contact with the oxide layer.

[0010] According to one embodiment of this application, the conductive layer includes a polysilicon layer located in a trench and in contact with an oxide layer.

[0011] According to one embodiment of this application, the conductive layer further includes: The metal layer is located on the side of the polysilicon layer away from the bottom of the trench.

[0012] According to one embodiment of this application, the test structure further includes: An insulating layer covers the epitaxial layer and has an opening that exposes the top region of the trench; The metal layer is located inside the opening, and the insulating layer is in contact with the sidewalls on opposite sides of the metal layer.

[0013] Secondly, this application provides a method for preparing a test structure, characterized in that the method for preparing the test structure includes: Provide an epitaxial layer; A groove with sidewalls and a bottom is formed on one side of the epitaxial layer; The epitaxial layer located at the bottom of the trench is doped with negatively charged ions; An oxide layer is formed on the sidewalls and bottom of the trench through a thermal oxidation process; In this process, the oxide layer formed by the thermal oxidation process has a first thickness at the bottom of the trench that is greater than the second thickness on the sidewall of the trench.

[0014] According to the fabrication method of the test structure in this application, the first thickness of the oxide layer at the bottom of the trench is greater than the second thickness of the oxide layer on the sidewall, that is, a test structure with a thick bottom and thin sidewall is formed. The thicker oxide layer at the bottom of the trench can shield the influence of the bottom capacitance, so that when testing the sidewall capacitance, the interference of the bottom capacitance on the data analysis can be weakened, and the accuracy of the gate oxide interface quality assessment results can be improved.

[0015] According to one embodiment of this application, the negatively charged ion is a nitrogen ion or an oxygen ion.

[0016] According to one embodiment of this application, after forming an oxide layer on the sidewalls and bottom of the trench by a thermal oxidation process, the process further includes: A conductive layer is deposited in the trench, and the conductive layer is in contact with the oxide layer; An insulating layer is deposited on top of the epitaxial layer and the conductive layer; The insulating layer is patterned and etched to create openings that expose portions of the conductive layer.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the structural schematic diagrams of the test structure provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the test structure provided in the embodiments of this application; Figure 3 This is a flowchart illustrating the fabrication process of the test structure provided in the embodiments of this application; Figure 4 This is a schematic diagram of the preparation process of the test structure provided in the embodiments of this application.

[0019] Figure label: Epitaxial layer 10, trench 20, oxide layer 30, conductive layer 40, polysilicon layer 41, metal layer 42, insulating layer 50, doped layer 60, first thickness D1, second thickness D2. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0021] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled at" or "connected at" two nodes, it can be directly coupled to or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0022] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0023] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0024] In semiconductor device manufacturing, especially MOSFET manufacturing, the interface quality of the gate oxide layer is a key factor affecting performance. The interface quality can be determined by testing the capacitance characteristics of the gate oxide layer. However, in silicon carbide trench structures, due to differences in crystal orientation, the sidewall oxidation rate is faster than the bottom oxidation rate during the high-temperature oxidation stage. This results in a significant decrease in the bottom withstand voltage. When testing the sidewall capacitance, the bottom capacitance interferes with the analytical data, making it difficult to accurately assess the gate oxide interface quality and affecting the accuracy of performance evaluation.

[0025] To achieve accurate characterization of the gate oxide interface quality on the sidewalls of trench devices, one embodiment of this application proposes a test structure. By forming a "thick bottom, thin sidewall" oxide layer structure within the trench, the capacitance generated in the bottom region of the trench is smaller during subsequent capacitance-voltage testing, reducing the interference of the bottom capacitance on data analysis and improving the accuracy of the gate oxide interface quality assessment results.

[0026] Figure 1 A schematic diagram of the test structure provided in an embodiment of this application is shown. (Refer to...) Figure 1One embodiment of this application proposes a test structure including an epitaxial layer 10, a trench 20, and an oxide layer 30. A trench 20 is formed on one side of the epitaxial layer 10, and the trench 20 has sidewalls and a bottom. The oxide layer 30 covers the sidewalls and bottom of the trench 20. A first thickness of the oxide layer 30 at the bottom of the trench 20 is greater than a second thickness of the oxide layer 30 at the sidewalls of the trench 20, so that the capacitance per unit area at the bottom of the trench 20 is less than the capacitance per unit area at the sidewalls of the trench 20.

[0027] It should be noted that the first thickness refers to the thickness of the oxide layer 30 in the direction perpendicular to the bottom surface of the trench 20, such as... Figure 1 As indicated by label D1; the second thickness refers to the thickness of the oxide layer 30 in the direction perpendicular to the sidewall surface of the trench 20, as shown in the figure. Figure 1 As shown in the label D2.

[0028] Epitaxial layer 10 is the foundation layer of the entire test structure, providing a good crystal structure and effectively supporting subsequent processing steps. The specific material of epitaxial layer 10 can be selected according to the actual application scenario, and is not limited here. For example, the specific material of epitaxial layer 10 can be silicon carbide.

[0029] It should be noted that the thickness of the epitaxial layer 10 can also be adjusted according to specific application requirements, and is not limited here. For example, the thickness of the epitaxial layer 10 can be 5um-12um, specifically, the thickness of the epitaxial layer 10 can be 10um or 12um, etc.

[0030] The trench 20 is typically formed using dry or wet etching techniques. Oxidation of the trench 20 forms the gate oxide layer 30. The size and depth of the trench 20 can be adjusted according to specific application requirements and are not limited here. For example, the depth of the trench 20 can be 1µm-1.5µm; specifically, the depth of the trench 20 can be 1.2µm or 1.3µm, etc.

[0031] The oxide layer 30 can be formed by processes such as thermal oxidation or chemical vapor deposition, continuously covering the sidewalls and bottom of the trench 20. To meet the different requirements of the test structure, the thickness of the oxide layer 30 can be precisely controlled by controlling process parameters such as deposition time and temperature.

[0032] The specific material of the oxide layer 30 can be selected according to the actual application scenario, and is not limited here. For example, the specific material of the oxide layer 30 can be silicon dioxide.

[0033] In other embodiments, by pre-doping the bottom region of the trench 20 (e.g., implanting nitrogen ions), the doped region accelerates oxidation during the high-temperature oxidation process, so that the first thickness D1 of the final oxide layer 30 at the bottom of the trench 20 is significantly greater than its second thickness D2 on the sidewall of the trench 20.

[0034] This "thick bottom, thin sidewall" oxide layer 30 structure significantly reduces the capacitance contribution from the bottom region of the trench 20 during subsequent capacitance-voltage testing due to the greater thickness of the oxide layer 30. Therefore, the capacitance per unit area at the bottom of the trench 20 is smaller than that on the sidewalls, and the total capacitance signal obtained from the test will be primarily dominated by the capacitance of the thin gate oxide layer 30 on the sidewalls. This reduces the interference of the bottom capacitance on the sidewall gate oxide interface characteristic analysis and improves the accuracy of the gate oxide interface quality assessment results.

[0035] According to the test structure of this application, the first thickness D1 of the oxide layer 30 at the bottom of the trench 20 is greater than the thickness of the second oxide layer 30 on the sidewall, that is, a test structure with a thick bottom and thin sidewall is formed. The thicker oxide layer 30 at the bottom of the trench 20 can shield the influence of the bottom capacitance of the trench 20, so that when testing the sidewall capacitance, the interference of the bottom capacitance on the data analysis can be weakened, and the accuracy of the gate oxide interface quality assessment results can be improved.

[0036] In some embodiments, the ratio of the first thickness D1 to the second thickness D2 ranges from 3 to 10.

[0037] When the ratio of the first thickness D1 to the second thickness D2 is too small (less than 3), the contribution of the capacitance at the bottom of the trench 20 is still significant. When extracting the sidewall capacitance of the trench 20, the capacitance at the bottom of the trench 20 will still interfere with the analysis data. When the ratio of the first thickness D1 to the second thickness D2 is too large (greater than 10), extreme process conditions (such as excessively long oxidation time or excessively high doping concentration) may be required. This is not only economically inefficient, but may also introduce unnecessary lattice damage or stress, affecting the quality of the oxide layer 30 itself.

[0038] The ratio of the first thickness D1 to the second thickness D2 ranges from 3 to 10. This ensures that, during capacitance-voltage testing, the capacitance signal from the sidewall gate oxide dominates the total capacitance, allowing the test data to reflect the interface characteristics of the sidewall gate oxide. Meanwhile, interference from the bottom capacitance is suppressed to a negligible level, guaranteeing the accuracy of parameter extraction. In some embodiments, the first thickness D1 is 1500 angstroms to 5000 angstroms.

[0039] The first thickness D1 of the oxide layer 30 at the bottom of the trench 20 is much greater than the thickness of the conventional gate oxide layer 30. Since the capacitance value is inversely proportional to the dielectric thickness, increasing the thickness of the oxide layer 30 at the bottom of the trench 20 to more than 1500 angstroms can drastically reduce its capacitance per unit area. Thus, in the test structure, its contribution to the total capacitance is attenuated to a negligible level, ensuring that the test signal is dominated by the sidewall capacitance.

[0040] An excessively thick oxide layer 30 (e.g., well over 5000 angstroms) will introduce excessive mechanical stress at the bottom of the trench 20, posing a risk of lattice damage or cracking of the oxide layer 30. A thickness range of 1500 to 5000 angstroms can achieve the testing objectives while avoiding the risk of lattice damage or cracking of the oxide layer 30, ensuring the structural integrity of the test structure.

[0041] It should be noted that the specific value of the first thickness D1 can be determined according to the actual application scenario, and is not limited here. For example, the first thickness D1 can be 2500 angstroms or 3000 angstroms, etc.

[0042] Figure 2 A schematic diagram of the test structure provided in an embodiment of this application is shown. (Refer to...) Figure 2 In some embodiments, the test structure further includes a conductive layer 40 located in the trench 20 and in contact with the oxide layer 30.

[0043] In the test structure proposed in the embodiments of this application, the conductive layer 40 is mainly used as the upper electrode of the trench 20 capacitor. During capacitance-voltage testing, the test signal is applied between the conductive layer 40 and the semiconductor substrate through a probe, establishing a complete electrical test circuit between the test structure and the analyzer.

[0044] The conductive layer 40 can be composed of one or more conductive materials. The low resistivity of the conductive materials ensures that the test signal (voltage signal or current signal) is minimally lost during transmission, thus ensuring the accuracy of the characterization data.

[0045] At the set frequency and amplitude, a DC bias voltage is applied to the test structure, and the capacitance-voltage characteristic curve of the test structure is recorded and plotted using an instrument. Since the first thickness D1 of the oxide layer 30 at the bottom of the trench 20 is much larger than its second thickness D2 on the sidewall, according to the parallel plate capacitance formula, the bottom capacitance is inversely proportional to the thickness. Therefore, based on this physical principle, the measured capacitance-voltage characteristic curve is actually mainly dominated by the capacitance of the thin gate oxide layer on the sidewall.

[0046] The specific material of the conductive layer 40 can be determined according to the actual application scenario, and is not limited here. For example, the conductive layer 40 can be formed by filling doped polycrystalline silicon through a chemical vapor deposition process. In addition, the conductive layer 40 can also be a metal (such as nickel, titanium, aluminum) or a composite stacked structure of metal and polycrystalline silicon (for example, first depositing polycrystalline silicon to fill most of the trench 20, and then forming a metal layer on top as a low-resistance contact).

[0047] The conductive layer 40 is typically filled using chemical vapor deposition to ensure a void-free filling even within the trench 20, which has a high aspect ratio. After deposition, etch-back or chemical mechanical polishing processes can be used to remove excess conductive material outside the trench 20 region, thereby confining the conductive layer 40 within the trench 20 and forming a smooth surface, preparing it for subsequent possible interconnect structures or capping layers.

[0048] In some embodiments, the conductive layer 40 includes a polysilicon layer 41 located in the trench 20 and in contact with the oxide layer 30.

[0049] Polycrystalline silicon material can be filled with excellent conformality and no voids inside irregular, high aspect ratio trench structures through low-pressure chemical vapor deposition. When applied to test structures, it does not introduce additional pollution or complex process steps, thus making the test structures of this application highly feasible and low-cost.

[0050] In some embodiments, the conductive layer 40 further includes a metal layer 42 located on the side of the polysilicon layer 41 away from the bottom of the trench 20.

[0051] The metal layer 42 is formed on the side of the polysilicon layer 41 away from the bottom of the trench 20, that is, the metal layer 42 is located on top of the polysilicon layer 41, and together with the polysilicon layer 41, they form a low-resistance, reliable composite electrode.

[0052] The polysilicon layer 41 serves as the main filling material, ensuring perfect filling of the trench 20 structure and an excellent interface with the gate oxide layer 30; while the metal layer 42 serves as a top low-resistance capping layer or contact layer, directly connected to subsequent test probes or interconnect structures.

[0053] Although polysilicon has some conductivity, its resistivity is still much higher than that of metals. Integrating a metal layer 42 on top of the polysilicon layer 41 can greatly reduce the series resistance from the test contact to the entire trench 20 electrode, effectively avoiding signal attenuation and test errors caused by excessive resistance of the electrode itself, and improving the accuracy of trench 20 sidewall capacitance analysis.

[0054] Optimizing ohmic contact and improving test reliability: During electrical testing, the probe is directly embedded in the metal layer 42, forming a near-ideal ohmic contact. In contrast, direct contact between the probe and polysilicon can result in unstable contact resistance, introducing additional measurement noise and uncertainty. The presence of the metal layer 42 ensures the stability and repeatability of the test signal injection.

[0055] The specific material of the metal layer 42 can be determined according to the actual application scenario, and is not limited here. For example, the material of the metal layer 42 can be nickel, titanium, or aluminum.

[0056] In summary, the conductive layer 40 can be formed from a single polysilicon layer or from a stacked structure of polysilicon layers and metal layers.

[0057] In some embodiments, the test structure further includes an insulating layer 50 covering the epitaxial layer 10 and having an opening that exposes the top region of the trench 20; wherein the conductive layer 40 is located within the opening and the insulating layer 50 is in contact with the sidewalls of opposite sides of the conductive layer 40.

[0058] The conductive layer 40 is partially embedded within the insulating layer 50. The inner sidewall of the opening in the insulating layer 50 is in direct contact and close abutment with the sidewalls on opposite sides of the conductive layer 40. The insulating layer 50 primarily serves to electrically isolate the conductive layer 40 at the top of the trench 20 from the surface of the epitaxial layer 10, preventing the conductive layer 40 from directly contacting the epitaxial layer 10 or other adjacent test structures and causing a short circuit, thus preventing testing from being performed. Furthermore, the insulating layer 50 effectively avoids unnecessary leakage paths, improving the accuracy of the sidewall capacitance analysis of the trench 20.

[0059] The specific material of the insulating layer 50 can be determined according to the actual application scenario, and is not limited here. For example, the material of the insulating layer 50 can be silicon oxide or silicon nitride, etc.

[0060] The patterned etching creates openings that precisely define the effective contact area between the test probe and the electrode in metal layer 42. This ensures that each test is performed at the same location, guaranteeing the consistency and comparability of the measurement results.

[0061] Figure 3 A flowchart illustrating the fabrication process of the test structure provided in an embodiment of this application is shown. (Refer to...) Figure 3 One embodiment of this application proposes a method for preparing a test structure, which includes steps 10, 20, 30 and 40.

[0062] Step 10: Provide epitaxial layer 10; Step 20: Form a trench 20 with sidewalls and a bottom on one side of the epitaxial layer 10; Step 30: Negatively charge-doped epitaxial layer 10 located at the bottom of trench 20; Step 40: An oxide layer 30 is formed on the sidewalls and bottom of the trench 20 by a thermal oxidation process; In this process, the oxide layer 30 formed by the thermal oxidation process has a first thickness D1 at the bottom of the trench 20 that is greater than the second thickness D2 on the sidewall of the trench 20.

[0063] Figure 4 A schematic diagram illustrating the fabrication process of the test structure provided in an embodiment of this application is shown. (Refer to...) Figure 4 In the process of fabricating the test structure, a semiconductor substrate (not shown in the figure) is usually provided first, and an epitaxial layer 10 is grown on it. The specific material of the epitaxial layer 10 can be selected according to the actual application scenario, and is not limited here. For example, the specific material of the epitaxial layer 10 can be silicon carbide.

[0064] On the epitaxial layer 10, trenches 20 can be formed by photolithography and dry etching processes. Specifically, photoresist is first coated and patterned on the surface of the epitaxial layer 10 to form a hard mask defining the region of trench 20; subsequently, anisotropic dry etching (e.g., etching using fluorine- or chlorine-based plasma) is performed to etch trenches 20 with substantially vertical sidewalls and flat bottoms in the epitaxial layer 10.

[0065] The size and depth of the trench 20 can be adjusted according to specific application requirements and are not limited here. For example, the depth of the trench 20 can be 1um-1.5um, specifically, the depth of the trench 20 can be 1.2um or 1.3um, etc.

[0066] After forming trench 20, selective ion implantation is performed on the bottom region of trench 20 to introduce negatively charged ions (i.e., N-type dopants or ions that can enhance the oxidation rate), forming a doped layer 60. Specifically, steep-angle ion implantation or vertical ion implantation techniques can be used to ensure that the dopant ions mainly enter the bottom of trench 20, while minimizing the impact on the sidewalls of trench 20. The implanted ions can be nitrogen ions or argon ions. For example, if nitrogen ions are used as N-type dopants, they can act as catalysts for the oxidation reaction in subsequent thermal oxidation, accelerating the oxidation rate at the bottom of trench 20.

[0067] After selective doping, a thermal oxidation process is performed. The wafer is placed in a high-temperature oxidation atmosphere for oxidation. Since the bottom region of trench 20 has a doped layer 60 formed through the aforementioned doping process, the oxidation rate of the bottom region of trench 20 is greater than that of the sidewalls of trench 20. Therefore, within the same oxidation time, the first thickness D1 of the oxide layer 30 ultimately grown at the bottom of trench 20 will be significantly greater than the second thickness D2 of the oxide layer 30 grown on the sidewalls of trench 20, thus forming a differentiated gate oxide structure that is "thick at the bottom and thin at the sidewalls". This structure significantly weakens the capacitance contribution at the bottom of trench 20 during capacitance-voltage testing due to the thicker oxide layer 30, and the test signal will primarily reflect the interface characteristics of the gate oxide on the sidewalls of trench 20, improving the accuracy of the gate oxide interface quality assessment results for the sidewalls of trench 20.

[0068] According to the preparation method of the test structure in this application, the first thickness D1 of the oxide layer 30 at the bottom of the trench 20 is greater than the thickness of the second oxide layer 30 on the sidewall, that is, a test structure with a thick bottom and thin sidewall is formed. The thicker oxide layer 30 at the bottom of the trench 20 can shield the influence of the bottom capacitance of the trench 20, so that when testing the sidewall capacitance, the interference of the bottom capacitance on the data analysis can be weakened, and the accuracy of the gate oxide interface quality assessment results can be improved.

[0069] In some embodiments, the negatively charged ion is a nitrogen ion or an oxygen ion.

[0070] Nitrogen ions are an N-type dopant. When implanted into a silicon lattice, they accumulate at the silicon oxide interface (the bottom of trench 20 in this application) under high-temperature oxidation conditions. The presence of nitrogen can break the silicon bonds in silicon, generating silicon-nitrogen bonds that are more readily reacted with oxygen, thereby significantly reducing the activation energy of the oxidation reaction, acting as a catalyst, and increasing the oxidation rate at the bottom of trench 20.

[0071] Oxygen ion implantation is a homogeneous element implantation process. High-dose oxygen ion implantation forms an oxygen-rich damage layer beneath the silicon surface at the bottom of trench 20. During subsequent thermal oxidation, these pre-existing oxygen atoms and the lattice defects generated by the implantation become additional oxidation reaction initiation sites, making it easier for oxygen molecules to dissociate and diffuse, thereby accelerating the overall propagation of oxide layer 30 into the silicon.

[0072] Choosing either nitrogen or oxygen ions can effectively achieve an oxide layer morphology of "thick bottom and thin sidewalls," reducing the interference of bottom capacitance on the analysis of sidewall gate oxide interface characteristics and improving the accuracy of gate oxide interface quality assessment results.

[0073] In some embodiments, after forming an oxide layer 30 on the sidewalls and bottom of the trench 20 by a thermal oxidation process, steps 50, 60 and 70 are further included.

[0074] Step 50: Deposit a conductive layer 40 in the trench 20, wherein the conductive layer 40 is in contact with the oxide layer 30; Step 60: Deposit an insulating layer 50 on the epitaxial layer 10 and the conductive layer 40; Step 70: Pattern the insulating layer 50 to form an opening that exposes part of the conductive layer 40.

[0075] A conductive layer 40 is deposited in the trench 20, which completely fills the trench 20. The conductive layer 40 is in direct contact with the oxide layer 30 formed in the previous step, together forming a complete trench 20 capacitor structure.

[0076] The conductive layer 40 can be made of polycrystalline silicon, which can be deposited by low-pressure chemical vapor deposition. After deposition, excess polycrystalline silicon outside the trench 20 area can be removed by chemical mechanical polishing or back etching process, so that the polycrystalline silicon is confined inside the trench 20 to form a flat surface.

[0077] In some embodiments, the conductive layer 40 further includes a metal layer 42 located on the side of the polysilicon layer 41 away from the bottom of the trench 20, that is, the metal layer 42 is located on top of the polysilicon layer 41, and together with the polysilicon layer 41, they form a low-resistance, reliable composite electrode.

[0078] The polysilicon layer 41 serves as the main filling material, ensuring perfect filling of the trench 20 structure and an excellent interface with the gate oxide layer 30; while the metal layer 42 serves as a low-resistance capping layer or contact layer on top, directly connected to subsequent test probes or interconnect structures, improving the accuracy of trench 20 sidewall capacitance analysis.

[0079] After depositing the conductive layer 40, an insulating layer 50 is deposited over the entire epitaxial layer 10 and the conductive layer 40 located within the trench 20. This insulating layer 50 serves as an interlayer dielectric layer, and its material can be silicon oxide or other dielectric materials with good insulating properties (such as silicon nitride or its composite stacked layers).

[0080] After depositing the insulating layer 50, the deposited insulating layer 50 is patterned and etched to form an opening that exposes the metal layer 42 on top of the underlying conductive layer 40. This step first involves coating the surface of the insulating layer 50 with photoresist, and then transferring the designed contact window pattern onto the photoresist using photolithography. Subsequently, using the photoresist as a mask, anisotropic dry etching is performed to precisely remove the insulating layer 50 in the window area until the underlying metal layer 42 is exposed. The resulting opening precisely defines the contact area between the probe and the conductive layer 40 during subsequent electrical testing.

[0081] Through these steps, a complete test structure with clearly defined electrodes, good electrical isolation, and standardized test interfaces was fabricated, providing a reliable hardware foundation for subsequent accurate capacitance-voltage testing and effective evaluation of the sidewall gate oxide interface quality.

[0082] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A test structure, characterized by, include: An epitaxial layer, wherein a trench is provided on one side of the epitaxial layer, the trench having a sidewall and a bottom; An oxide layer covers the sidewalls and bottom of the trench, wherein the first thickness of the oxide layer at the bottom of the trench is greater than the second thickness of the oxide layer at the sidewalls of the trench, such that the capacitance per unit area at the bottom of the trench is less than the capacitance per unit area at the sidewalls of the trench.

2. The test structure of claim 1, wherein, The ratio of the first thickness to the second thickness ranges from 3 to 10.

3. The test structure of claim 1, wherein, The first thickness is 1500 angstroms to 5000 angstroms.

4. The test structure according to any of claims 1-3, characterized in that, The test structure also includes: A conductive layer is located in the trench and is in contact with the oxide layer.

5. The test structure of claim 4, wherein, The conductive layer includes a polycrystalline silicon layer located in the trench and in contact with the oxide layer.

6. The test structure of claim 5, wherein, The conductive layer further includes: A metal layer is located on the side of the polysilicon layer away from the bottom of the trench.

7. The test structure of claim 4, wherein, The test structure also includes: An insulating layer covers the epitaxial layer and has an opening that exposes the top region of the trench; The conductive layer is located within the opening, and the insulating layer is in contact with the sidewalls on opposite sides of the conductive layer.

8. A method of preparing a test structure, characterized by The method for preparing the test structure includes: Provide an epitaxial layer; A groove with sidewalls and a bottom is formed on one side of the epitaxial layer; The epitaxial layer located at the bottom of the trench is doped with negatively charged ions; An oxide layer is formed on the sidewalls and bottom of the trench through a thermal oxidation process; The oxide layer formed by the thermal oxidation process has a first thickness at the bottom of the trench that is greater than a second thickness on the sidewall of the trench.

9. The method of claim 8, wherein The negatively charged ions are nitrogen ions or oxygen ions.

10. The method of claim 8, wherein After forming an oxide layer on the sidewalls and bottom of the trench through a thermal oxidation process, the method further includes: A conductive layer is deposited in the trench, and the conductive layer is in contact with the oxide layer; An insulating layer is deposited on the epitaxial layer and the conductive layer; The insulating layer is patterned and etched to form openings that expose portions of the conductive layer.

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