Semiconductor element

Abstract

The invention provides a semiconductor device. The semiconductor device includes a substrate, a transistor, and a buffer circuit. The transistor and the buffer circuit are arranged on the same substrate, and the buffer circuit is electrically connected with the transistor. The buffer circuit is provided with a polycrystalline silicon layer and a dielectric layer which are adjacently arranged and electrically connected in series. Wherein the polycrystalline silicon layer is electrically connected to the source electrode of the transistor, and the dielectric layer is electrically connected to the drain electrode of the transistor, so that the polycrystalline silicon layer becomes a resistor, the dielectric layer becomes a capacitor, and the buffer circuit becomes a resistor-capacitor buffer circuit.

Description

Technical Field

[0001] This invention relates to a semiconductor element, and more specifically, to a semiconductor element capable of suppressing surges. Background Technology

[0002] Because of the parasitic inductance present in the application circuits of power transistors, the power transistors will generate large voltage surges and ringing when they are turned off. In addition to generating electromagnetic interference (EMI) to the application circuits, when the surge exceeds the component's rating, it may even damage the power transistors or other electronic components in the circuit.

[0003] To dissipate surge energy, a common practice is to add an external snubber circuit, especially in high-speed switching circuits with high current. Among the many types of external snubbers, the RC snubber is the most commonly used. However, adding an external RC snubber circuit to power transistor applications incurs additional costs. In summary, voltage surges and ringing caused by parasitic inductance when power transistors are turned off are a significant problem in power transistor applications. While external RC snubber circuits are effective, they increase cost and circuit design complexity. Therefore, effectively suppressing power transistor surges without excessively increasing component costs is a pressing issue for the industry. Summary of the Invention

[0004] The main objective of this invention is to provide an innovative semiconductor element that integrates an RC snubber circuit into the semiconductor element structure design of the power transistor itself. Therefore, no external snubber is needed in the application circuit, which can effectively suppress voltage surges when the power transistor is switched, thereby protecting the gate oxide layer of the power transistor from damage.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising a substrate, a transistor, and a buffer circuit. The transistor and the buffer circuit are disposed on the same substrate, and the buffer circuit and the transistor are electrically connected. The buffer circuit has a polysilicon layer and a dielectric layer, which are disposed adjacently and electrically connected in series. The polysilicon layer is electrically connected to the source of the transistor, and the dielectric layer is electrically connected to the drain of the transistor, making the polysilicon layer a resistor and the dielectric layer a capacitor, thus making the buffer circuit a resistive-capacitive buffer circuit.

[0006] In an embodiment of the semiconductor element of the present invention, the substrate is a silicon carbide substrate.

[0007] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an epitaxial layer disposed on a substrate, wherein a dielectric layer is disposed on the epitaxial layer.

[0008] In an embodiment of the semiconductor element of the present invention, the semiconductor element further includes a drain metal disposed on the back side of the substrate as a drain, wherein the polysilicon layer, the epitaxial layer and the substrate between the source metal and the drain metal have the resistance.

[0009] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a source metal disposed above the epitaxial layer and electrically connected to the source and the polysilicon layer.

[0010] To achieve the above objectives, the present invention provides a semiconductor device comprising a substrate, a transistor, and a buffer circuit. The transistor and the buffer circuit are disposed on the same substrate, and the buffer circuit is electrically connected to the transistor. The buffer circuit has a polysilicon layer and a dielectric layer, which are disposed adjacent to each other and electrically connected in series. The polysilicon layer is electrically connected to the gate of the transistor, and the dielectric layer is electrically connected to the source of the transistor, making the polysilicon layer a resistor and the dielectric layer a capacitor.

[0011] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an epitaxial layer and an interlayer dielectric layer, wherein the epitaxial layer is disposed on a substrate, the interlayer dielectric layer is disposed on the epitaxial layer, and a polysilicon layer is disposed on the interlayer dielectric layer.

[0012] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a gate metal disposed on an interlayer dielectric layer and electrically connected to a gate, wherein the polysilicon layer and the gate metal have the resistance.

[0013] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a source metal disposed above the interlayer dielectric layer and electrically connected to the source and the dielectric layer.

[0014] To achieve the above objectives, the present invention provides a semiconductor device comprising a substrate, a transistor, a first buffer circuit, and a second buffer circuit. The transistor, the first buffer circuit, and the second buffer circuit are disposed on the same substrate, and the first buffer circuit and the second buffer circuit are electrically connected to the transistor. The first buffer circuit has a first polysilicon layer and a first dielectric layer, which are disposed adjacent to each other and electrically connected in series. The second buffer circuit has a second polysilicon layer and a second dielectric layer, which are disposed adjacent to each other and electrically connected in series. The first polysilicon layer is electrically connected to the source of the transistor, and the first dielectric layer is electrically connected to the drain of the transistor, making the first polysilicon layer a first resistor and the first dielectric layer a first capacitor. The second polysilicon layer is electrically connected to the gate of the transistor, and the second dielectric layer is electrically connected to the source of the transistor, making the second polysilicon layer a second resistor and the second dielectric layer a second capacitor.

[0015] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an epitaxial layer disposed on a substrate, wherein a first dielectric layer is disposed on the epitaxial layer.

[0016] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes an interlayer dielectric layer disposed on the epitaxial layer, wherein a second polysilicon layer is disposed on the interlayer dielectric layer.

[0017] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a gate metal disposed on an interlayer dielectric layer and electrically connected to a gate, wherein a second resistance exists between the second polysilicon layer and the gate metal.

[0018] In an embodiment of the semiconductor device of the present invention, the semiconductor device further includes a source metal disposed above the interlayer dielectric layer and electrically connected to the source, the first polysilicon layer and the second dielectric layer.

[0019] In an embodiment of the semiconductor element of the present invention, the semiconductor element further includes a drain metal disposed on the back side of the substrate as a drain, wherein the first polysilicon layer, the epitaxial layer and the substrate between the source metal and the drain metal have a first resistance.

[0020] Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a power transistor element in the first embodiment of the present invention; Figure 2 This is a cross-sectional schematic diagram of a power transistor element in the first embodiment of the present invention; Figure 3 This is a circuit diagram of a power transistor element in the second embodiment of the present invention; Figure 4 This is a cross-sectional schematic diagram of a power transistor element in the second embodiment of the present invention; Figure 5 This is a circuit diagram of a power transistor element in the third embodiment of the present invention; and Figure 6 This is a cross-sectional schematic diagram of a power transistor element in the third embodiment of the present invention. Detailed Implementation

[0022] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and drawings, elements not directly related to this invention have been omitted and are not drawn, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.

[0023] Please refer to Figure 1 , Figure 1 This diagram illustrates a circuit schematic of a semiconductor device according to a first embodiment of the present invention, particularly a circuit schematic of a power transistor device. This power transistor device (e.g., a semiconductor device), in addition to having a transistor 1 as in the conventional form, also has a buffer circuit 2 built into the device along with the transistor 1. This allows the power transistor device in the first embodiment to already possess the function of suppressing voltage surges and protecting the oxide dielectric layer of the transistor's gate G from damage, without the need for additional surge protection circuitry. Specifically, as... Figure 1 As shown, the buffer circuit 2 in this embodiment is a resistor-capacitor type RC buffer circuit connected between the source S and drain D of transistor 1.

[0024] Please refer to the combined reference. Figure 2 , Figure 2 As shown Figure 1 The diagram shows a cross-sectional view of a power transistor element in the first embodiment of the present invention. Clearly, the power transistor element 100 of the present invention integrates transistor 1 and buffer circuit 2 on the same substrate within the element structure, as detailed below. This power transistor element 100 has a substrate 10, specifically, this substrate 10 is an N-type heavily doped silicon carbide substrate, but is not limited thereto. An epitaxial (e.g., epitaxial) layer 20 is provided on the substrate 10; similarly, this epitaxial layer 20 can be, but is not limited to, an N-type lightly doped silicon carbide epitaxial layer. Next, a patterned dielectric layer and a patterned polysilicon layer are sequentially formed on the epitaxial layer 20. The dielectric layer can be a silicon dioxide layer or a silicon nitride layer. Furthermore, a portion of the patterned dielectric layer and the patterned polysilicon layer can serve as the gate 30 in the transistor 1 structure, while the other portion of the patterned dielectric layer 80 and the patterned polysilicon layer 90 can serve as the capacitor and resistor in the buffer circuit 2. The dielectric layer 80 and the polysilicon layer 90 are arranged adjacent to each other and electrically connected in series, as detailed later.

[0025] like Figure 2As shown, next, using the aforementioned gate 30 as a mask, the P-type well region 22 of transistor 1 and the heavily N-type doped source 40 of transistor 1 are formed successively on the surface region of the epitaxial layer 20. Subsequently, an interlayer dielectric layer 50 is formed on the epitaxial layer 20 to cover the gate 30 and the dielectric layer 80 and polysilicon layer 90 in the buffer circuit 2, respectively. Finally, a metallization interconnect process is performed to form the gate metal (not shown), source metal 60, and drain metal 70, respectively. The source metal 60 is electrically connected to the source 40 of transistor 1 and also electrically connected to the polysilicon layer 90 in the buffer circuit 2. The drain metal 70 is electrically connected to the dielectric layer 80 in the buffer circuit 2 through the substrate 10 and the epitaxial layer 20.

[0026] As shown in the accompanying drawings, the power transistor element 100 of the present invention integrates both a transistor 1 and a buffer circuit 2. The dielectric layer 80 of the buffer circuit 2 can be made of a dielectric material with a suitable dielectric constant, and the geometry of the dielectric film (including film thickness, length, width, etc.) can be selected to adjust its capacitance value. Furthermore, the polysilicon layer 90 of the buffer circuit 2 can have its resistance value adjusted by the doping concentration of the polysilicon dopant and the geometry of the polysilicon film (including film thickness, length, width, etc.), thereby determining the overall resistance value of the polysilicon layer 90, the epitaxial layer 20, and the substrate 10 between the source metal 60 and the drain metal 70 in the entire buffer circuit 2. When the power transistor element 100 of the present invention is actually applied in a circuit, during the switching process from the on state to the off state, the current generated by the high-voltage surge will flow through the loop formed by the buffer circuit 2 and the switch. The capacitor C in the buffer circuit will block the DC portion of the surge current. On the other hand, the resistor R in the buffer circuit will dissipate the AC portion of the surge current passing through the capacitor C, thereby reducing the peak surge voltage felt at the load end and protecting the gate dielectric layer of the transistor in the power transistor element.

[0027] Please refer to Figure 3 , Figure 3 A circuit diagram of a power transistor element according to a second embodiment of the present invention is shown. Similar to the embodiments described above, this power transistor element (e.g., a semiconductor element) has a buffer circuit 2 integrated within the element, in addition to having the same transistor 1 as conventional transistors. Specifically, as... Figure 3 As shown, the buffer circuit 2 in the second embodiment is a resistor-capacitor type RC buffer circuit connected between the source S and the gate G of transistor 1.

[0028] Please refer to the combined reference. Figure 4 , Figure 4 As shown Figure 3The diagram shows a cross-sectional view of the power transistor element 100 in the second embodiment of the present invention. Clearly, the power transistor element 100 of the present invention integrates the transistor 1 and the buffer circuit 2 within the element structure, as detailed below. Similar to the aforementioned embodiment, this power transistor element 100 has a substrate 10, on which an epitaxial layer 20 is formed. Next, a gate 30 is formed on the epitaxial layer 20, and a P-type well region 22 and a source 40 are formed on the surface region of the epitaxial layer 20. Then, an interlayer dielectric layer 50 is formed on the epitaxial layer 20 to cover the gate 30. Subsequently, a dielectric layer 80 and a polysilicon layer 90 of the buffer circuit 2 are formed above the interlayer dielectric layer 50, the dielectric layer 80 and the polysilicon layer 90 being disposed adjacent to each other and electrically connected in series. Finally, a metallization interconnect process is performed to form a gate metal 35, a source metal 60, and a drain metal 70, respectively. The source metal 60 is electrically connected to the source 40 of the transistor 1 and the dielectric layer 80 of the buffer circuit 2. On the other hand, the gate metal 35 is electrically connected to the polysilicon layer 90 of the buffer circuit 2.

[0029] like Figure 3 and Figure 4 As shown, the power transistor element 100 of the present invention integrates both transistor 1 and buffer circuit 2 on the same substrate 10. Similar to the aforementioned embodiments, the dielectric layer 80 of the buffer circuit 2 can be adjusted to have a capacitance value by selecting a dielectric material with a suitable dielectric constant and the geometry of the dielectric film. Additionally, the polysilicon layer 90 can have its resistance value adjusted by the doping concentration of the polysilicon dopant and the geometry of the polysilicon film. When the power transistor element 100 of the present invention is actually applied in a circuit, during the switching process from the on state to the off state, the current generated by the high-voltage surge will flow through the loop formed by the buffer circuit 2 and the switch. The capacitor C (i.e., dielectric layer 80) in the buffer circuit will block the DC portion of the surge current. On the other hand, the resistor R (i.e., polysilicon layer 90) in the buffer circuit will dissipate the AC portion of the surge current passing through capacitor C, thereby reducing the peak surge voltage experienced at the load end and protecting the gate dielectric layer of the transistor in the power transistor element.

[0030] Please refer to Figure 5 , Figure 5 A circuit diagram of a power transistor element according to a third embodiment of the present invention is shown. The third embodiment combines the first and second embodiments described above; this power transistor element (e.g., a semiconductor element) integrates a conventional transistor 1 and two buffer circuits. Specifically, as... Figure 5 As shown, buffer circuit A is an RC buffer circuit connected between the source S and drain D of transistor 1, and buffer circuit B is an RC buffer circuit connected between the source S and gate G of transistor 1.

[0031] Please refer to the combined reference. Figure 6 , Figure 6 As shown Figure 5 The diagram shows a cross-sectional view of the power transistor element 100 in the third embodiment of the present invention. Clearly, the power transistor element 100 of the present invention integrates transistor 1 with buffer circuit A and buffer circuit B within the element structure, as detailed below. Similar to the aforementioned embodiments, this power transistor element 100 has an epitaxial layer 20 on its substrate 10, and a gate 30 and a dielectric layer 80 for buffer circuit A are provided on the epitaxial layer 20. A and polycrystalline silicon layer 90 A The surface region of the epitaxial layer 20 has a P-type well region 22 and a source 40. Additionally, an interlayer dielectric layer 50 is formed on the epitaxial layer 20 to cover the gate 30 and the dielectric layer 80 of the buffer circuit A. A and polycrystalline silicon layer 90 A Subsequently, a dielectric layer 80 having (for example, forming) a buffer circuit B is formed above the interlayer dielectric layer 50. B and polycrystalline silicon layer 90 B Finally, the metallized interconnect has a gate metal 35, a source metal 60, and a drain metal 70. The source metal 60 is electrically connected to the source 40 of transistor 1 and the polysilicon layer 90 of buffer circuit A. A and the dielectric layer 80 of buffer circuit B B On the other hand, the gate metal 35 is electrically connected to the polysilicon layer 90 of the buffer circuit B. B The drain metal 70 is electrically connected to the dielectric layer 80 in the buffer circuit A through the substrate 10 and the epitaxial layer 20. A .

[0032] like Figure 5 and Figure 6 As shown in the figure, the power transistor element 100 in the third embodiment has integrated transistor 1 with buffer circuit A and buffer circuit B. Buffer circuit A has a resistor R. A Capacitor C A An RC snubber circuit, wherein the resistor R A A first polysilicon layer 90 is formed between the source metal 60 and the drain metal 70. A The overall resistance and capacitance C of the epitaxial layer 20 and the substrate 10 A From the first dielectric layer 80 A Decision. Buffer circuit B has a resistor R. B Capacitor C B The RC buffer circuit, wherein the second polysilicon layer 90 B There is a resistance R between the gate metal 35 and the gate metal 35 B Capacitor C B From the second dielectric layer 80 BThe decision is made. Buffer circuits A and B can provide more complete suppression of high voltage surges for power transistor devices, thereby protecting the gate dielectric layer of the transistors in the power transistor devices.

[0033] The above embodiments are merely illustrative of the present invention and to explain its technical features, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of protection of the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims.

[0034] [Symbol Explanation] 1 transistor 2. Buffer circuit 10 substrates 20 epitaxial layers 22P type well region 30 gate 35 gate metal 40 source poles 50 interlayer dielectric layers 60 source metal 70 drain metal 80 dielectric layers 80 A (First) Dielectric layer 80 B (Second) Dielectric layer 90 polycrystalline silicon layers 90 A (First) Polycrystalline silicon layer 90 B (Second) Polycrystalline silicon layer 100 power transistor device A buffer circuit B buffer circuit C capacitor C A capacitance C B capacitance D drain G gate R resistor R A resistance R B resistance S source pole.

Claims

1. A semiconductor element, the semiconductor element comprising: Substrate; Transistors are disposed on the substrate; as well as A buffer circuit is disposed on the substrate and electrically connected to the transistor. The buffer circuit has a polysilicon layer and a dielectric layer, the polysilicon layer and the dielectric layer being disposed adjacent to each other and electrically connected in series. The polysilicon layer is electrically connected to the source of the transistor, and the dielectric layer is electrically connected to the drain of the transistor, making the polysilicon layer a resistor and the dielectric layer a capacitor.

2. The semiconductor element according to claim 1, wherein The substrate is a silicon carbide substrate.

3. The semiconductor device according to claim 1, further comprising an epitaxial layer provided on the substrate, wherein, The dielectric layer is disposed on the epitaxial layer.

4. The semiconductor device of claim 3, further comprising a source metal disposed above the epitaxial layer and electrically connected to the source and the polysilicon layer.

5. The semiconductor element according to claim 4, further comprising a drain metal provided on a back side of the substrate as the drain, wherein The polysilicon layer, the epitaxial layer, and the substrate between the source metal and the drain metal have the resistance.

6. A semiconductor element, said semiconductor element comprising: Substrate; Transistors are disposed on the substrate; as well as A buffer circuit is disposed on the substrate and electrically connected to the transistor. The buffer circuit has a polysilicon layer and a dielectric layer, the polysilicon layer and the dielectric layer being disposed adjacent to each other and electrically connected in series. The polysilicon layer is electrically connected to the gate of the transistor, and the dielectric layer is electrically connected to the source of the transistor, making the polysilicon layer a resistor and the dielectric layer a capacitor.

7. The semiconductor device according to claim 6, wherein The substrate is a silicon carbide substrate.

8. The semiconductor device according to claim 6, further comprising an epitaxial layer provided on the substrate, and an interlayer dielectric layer provided on the epitaxial layer, wherein The polycrystalline silicon layer is disposed on the interlayer dielectric layer.

9. The semiconductor device of claim 8, further comprising a gate metal disposed on the interlayer dielectric layer and electrically connected to the gate, wherein, The polysilicon layer has the resistance between it and the gate metal.

10. The semiconductor device of claim 8, further comprising a source metal disposed on the interlayer dielectric layer and electrically connected to the source and the dielectric layer.

11. A semiconductor element, the semiconductor element comprising: Substrate; Transistors are disposed on the substrate; A first buffer circuit is disposed on the substrate and electrically connected to the transistor. The first buffer circuit has a first polysilicon layer and a first dielectric layer, which are disposed adjacent to each other and electrically connected in series. as well as A second buffer circuit is disposed on the substrate and electrically connected to the transistor. The second buffer circuit has a second polysilicon layer and a second dielectric layer, which are disposed adjacent to each other and electrically connected in series. In this configuration, the first polysilicon layer is electrically connected to the source of the transistor, and the first dielectric layer is electrically connected to the drain of the transistor, making the first polysilicon layer a first resistor and the first dielectric layer a first capacitor. The second polysilicon layer is electrically connected to the gate of the transistor, and the second dielectric layer is electrically connected to the source of the transistor, such that the second polysilicon layer becomes a second resistor and the second dielectric layer becomes a second capacitor.

12. The semiconductor device according to claim 11, wherein The substrate is a silicon carbide substrate.

13. The semiconductor device according to claim 11, further comprising an epitaxial layer provided on the substrate, wherein, The first dielectric layer is disposed on the epitaxial layer.

14. The semiconductor device according to claim 13, further comprising an interlayer dielectric layer provided on the epitaxial layer, wherein The second polysilicon layer is disposed on the interlayer dielectric layer.

15. The semiconductor device of claim 14, further comprising a gate metal disposed on the interlayer dielectric layer and electrically connected to the gate, wherein, The second polysilicon layer has the second resistance between it and the gate metal.

16. The semiconductor device of claim 14, further comprising a source metal disposed above the interlayer dielectric layer and electrically connected to the source, the first polysilicon layer and the second dielectric layer.

17. The semiconductor device of claim 16, further comprising a drain metal disposed on the back side of the substrate as the drain, wherein, The first polysilicon layer, the epitaxial layer, and the substrate between the source metal and the drain metal have the first resistance.

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