Semiconductor package

Abstract

An embodiment provides a semiconductor package including a package substrate including a substrate pad, and a chip stack including a plurality of semiconductor chips stacked on the package substrate, the plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip having device regions of the same size and shape, the first semiconductor chip and the second semiconductor chip including first chip pad regions and second chip pad regions protruding from different regions of a first side of the device regions, respectively, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the same direction and do not overlap each other in the stacking direction, and each of the chip pads is connected to the substrate pad by a lead.

Description

Technical Field

[0001] The present invention relates to semiconductor packaging. Background Technology

[0002] With the development of the electronics industry, the demand for high functionality, high speed, and miniaturization of electronic components is increasing. In response to this trend, semiconductor packaging technologies are being developed for embedding multiple semiconductor chips within a single package. Methods are needed to minimize the increase in package size caused by the arrangement of multiple semiconductor chips. Summary of the Invention

[0003] One aspect of the present invention is to provide a semiconductor package that is advantageous in terms of lightweight, thinness and miniaturization while ensuring reliability.

[0004] According to one aspect of the present invention, a semiconductor package includes: a package substrate having a first side and a second side opposite to the first side, the package substrate including a first substrate pad adjacent to the first side and a second substrate pad adjacent to the second side; and a chip stack comprising a plurality of semiconductor chips disposed on the package substrate between the first substrate pad and the second substrate pad, wherein the plurality of semiconductor chips includes a first semiconductor chip to a fourth semiconductor chip each having the same device region, wherein each of the first semiconductor chip and the third semiconductor chip includes a corresponding first chip pad region protruding from a first region on a first side of the device region of the first semiconductor chip and the third semiconductor chip, each of the second semiconductor chip and the fourth semiconductor chip includes a corresponding second chip pad region protruding from a second region on a first side of the device region of the second semiconductor chip and the fourth semiconductor chip, and the plurality of chip pads are disposed in each of the first chip pad region and the second chip pad region, the plurality of chip pads being disposed in each of the first chip pad region and the second chip pad region. The pads include a first plurality of chip pads located in the first chip pad regions of the first semiconductor chip and the third semiconductor chip, and a second plurality of chip pads located in the second chip pad regions of the second semiconductor chip and the fourth semiconductor chip; the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad regions of the first semiconductor chip and the second chip pad regions of the second semiconductor chip face the first side of the packaging substrate and do not overlap each other in the stacking direction, and the first plurality of chip pads of the first semiconductor chip and the second plurality of chip pads of the second semiconductor chip are electrically connected to the first substrate pads; and the third semiconductor chip and the fourth semiconductor chip are stacked such that the first chip pad regions of the third semiconductor chip and the second chip pad regions of the fourth semiconductor chip face the second side of the packaging substrate and do not overlap each other in the stacking direction, and the first plurality of chip pads of the third semiconductor chip and the second plurality of chip pads of the fourth semiconductor chip are electrically connected to the second substrate pads.

[0005] According to one aspect of the present invention, a semiconductor package includes: a package substrate having a first side and a second side opposite to the first side, the package substrate including a first substrate pad adjacent to the first side and a second substrate pad adjacent to the second side; and a chip stack comprising a plurality of sub-stacks disposed on the package substrate between the first substrate pad and the second substrate pad, each of the plurality of sub-stacks having a corresponding first semiconductor chip and a second semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip includes a device region, the first semiconductor chip including a corresponding first chip pad region protruding from a first region on a first side of the device region of the first semiconductor chip, the second semiconductor chip including a corresponding second chip pad region protruding from a second region on a first side of the device region of the second semiconductor chip, and the plurality of chip pads being disposed in the first chip pad region and the second chip pad region. The plurality of sub-stacks include a first sub-stack and a second sub-stack sequentially stacked on the package substrate. In the first sub-stack, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the first side of the package substrate and do not overlap each other in the stacking direction. Each chip pad in the first chip pad region and the second chip pad region of the first sub-stack is connected to a corresponding substrate pad in the first substrate pad via a corresponding lead. In the second sub-stack, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the second side of the package substrate and do not overlap each other in the stacking direction. Each chip pad in the first chip pad region and the second chip pad region of the second sub-stack is connected to a corresponding substrate pad in the second substrate pad via a corresponding lead.

[0006] According to one aspect of the present invention, a semiconductor package includes: a package substrate including substrate pads; a chip stack including a plurality of semiconductor chips stacked on the package substrate; and a molding film surrounding the chip stack on the package substrate, wherein the plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip, each of the first and second semiconductor chips including a device region having the same size and shape, the first and second semiconductor chips respectively including a first chip pad region and a second chip pad region protruding from different regions on a first side of the device region, and a plurality of chip pads located in each of the first and second chip pad regions, each of the plurality of chip pads being connected to the substrate pads via a corresponding lead, and the first and second semiconductor chips being stacked such that the first and second chip pad regions face the same direction and do not overlap each other in the stacking direction. Attached Figure Description

[0007] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view showing a semiconductor package according to an embodiment.

[0008] Figure 2A and Figure 2B They are shown respectively Figure 1 Top view and side cross-sectional view of the semiconductor package.

[0009] Figure 3A and Figure 3B These are top views of the first semiconductor chip and the second semiconductor chip in the semiconductor package according to the embodiments.

[0010] Figure 4 It is shown that it is used for Figure 3A and Figure 3B Top view of the wafers of the first and second semiconductor chips.

[0011] Figures 5A to 5C It shows the manufacturing process. Figure 1 A three-dimensional view of the main process of a semiconductor packaging method.

[0012] Figure 6A and Figure 6B These are top views of a first wafer and a second wafer used for the first semiconductor chip and the second semiconductor chip, respectively.

[0013] Figure 7and Figure 8 This is a cross-sectional side view showing a semiconductor package according to various embodiments.

[0014] Figure 9 and Figure 10 This is a cross-sectional side view showing a semiconductor package according to various embodiments.

[0015] Figure 11 This is a perspective view showing a semiconductor package according to an embodiment.

[0016] Figure 12 It is shown Figure 11 A side view of a semiconductor package.

[0017] Figures 13A to 13E It shows the manufacturing process. Figure 11 A three-dimensional view of the main process of a semiconductor packaging method.

[0018] Figure 14 This is a cross-sectional side view showing a semiconductor package according to an embodiment. Detailed Implementation

[0019] Various embodiments will be described below with reference to the accompanying drawings.

[0020] As can be seen, for example, in the accompanying figures, terms described herein in a singular form may be provided in a plural form. Therefore, unless the context otherwise indicates, the description of a single term provided in a plural form should be understood to apply to the remaining multiple terms.

[0021] As used herein, the term "overlapping" is intended to mean that one element is located above, on top of, or beside at least a portion of another element. Elements may or may not be in contact. An element does not need to cover the entire surface of the element considered "overlapping." The term is intended to encompass an element that overlaps with all or any portion of another element.

[0022] It will be understood that the terms “comprises” and / or “comprising” or “includes” and / or “including”, when used in this specification, specify the presence of the said feature, region, integer, step, operation, element and / or component, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0023] When referring to orientation, layout, location, shape, size, composition, quantity, or other measures, terms such as “identical,” “equal,” “flat,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, composition, quantity, or other measures, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, compositions, quantities, or other measures within the typical variations that may arise from conventional manufacturing processes. Unless otherwise indicated by context or other statements, the term “substantially” may be used herein to emphasize this meaning.

[0024] It will be understood that although the terms first, second, etc., may be used in this document to describe various elements, components, or materials, these elements, components, or materials should not be limited by these terms. Unless the context otherwise indicates, these terms are used only to distinguish one element, component, or material from another, for example, as a naming convention.

[0025] The various pads of the devices described herein can be conductive terminals connected to the internal wiring of the device and can transmit signals and / or supply voltages between the internal wiring and / or internal circuitry of the device and external sources. For example, chip pads of a semiconductor chip can be electrically connected to the integrated circuit of the semiconductor chip and the devices to which the semiconductor chip is connected, and transmit supply voltages and / or signals between the integrated circuit of the semiconductor chip and the devices to which the semiconductor chip is connected. Various pads can be disposed on or near the outer surface of the device and can have dimensions larger than the flat surface of the wiring (e.g., the XY horizontal dimensions of the pad are both larger than the width of the internal wiring to which it is connected) to facilitate electrical connections to another terminal (such as a bump or solder ball) and / or external wiring.

[0026] Figure 1 This is a perspective view showing a semiconductor package according to an embodiment, and Figure 2A and Figure 2B They are shown respectively Figure 1 Top view and cross-sectional side view of a semiconductor package.

[0027] refer to Figure 1 , Figure 2A and Figure 2B According to this embodiment, the semiconductor package 100 may include a package substrate 150, a chip stack ST, and a molding film 190. The molding film 190 surrounds the chip stack ST on the package substrate 150. In the chip stack ST, a plurality of first semiconductor chips 110 and a plurality of second semiconductor chips 120 are stacked on the package substrate 150.

[0028] The package substrate 150 may include, for example, a printed circuit board (PCB). The package substrate 150 may include substrate pads 155 disposed on its upper surface and connection pads 156 disposed on its lower surface. External connection terminals 160 configured to electrically connect external devices and the semiconductor package 100 may be disposed on the connection pads 156. The external connection terminals 160 may be, for example, solder balls, solder bumps, or solder pillars.

[0029] The chip stack ST may include a plurality of first semiconductor chips 110 and a plurality of second semiconductor chips 120 stacked on a package substrate 150 in a vertical direction (e.g., stacking direction (D3)). In this embodiment, the chip stack ST is shown to include two first semiconductor chips 110 and two second semiconductor chips 120, i.e., four semiconductor chips, but is not limited thereto. For example, the chip stack ST may include fewer or more numbers of semiconductor chips (e.g., eight or twelve).

[0030] The stacked first semiconductor chip 110 and second semiconductor chip 120 can be bonded by an adhesive member 131. The adhesive member 131 can be disposed between adjacent first semiconductor chips 110 and second semiconductor chips 120. Similarly, the adhesive member 131 can be disposed between the lower surface of the bottommost first semiconductor chip 110 and the upper surface of the package substrate 150, so that the chip stack ST can be attached to the package substrate 150. For example, the adhesive member 131 can be a die attach film (DAF).

[0031] In this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 may be the same type of semiconductor chip, but may include chip pad regions (CP1 and CP2) of different shapes. This will be described later.

[0032] The first semiconductor chip 110 and the second semiconductor chip 120 can be semiconductor memory chips. The memory chip can be, for example, a volatile memory semiconductor chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or a non-volatile memory semiconductor chip such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). In some embodiments, the memory chip can be flash memory, such as NAND flash memory.

[0033] In other embodiments, the chip stack ST may include at least one different type of semiconductor chip. For example, some semiconductor chips may be memory chips. Other semiconductor chips may be logic chips. For example, a logic chip may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0034] As described above, in this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 may be the same type of semiconductor chip, but may have different shapes in the top view.

[0035] Figure 3A and Figure 3B These are top views of the first semiconductor chip 110 and the second semiconductor chip 120 in the semiconductor package according to the embodiments.

[0036] refer to Figure 3A and Figure 3B Together Figure 1 In this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 may have the same device region DA in which the integrated circuit is implemented. In some embodiments, the device region DA of the first semiconductor chip 110 and the second semiconductor chip 120 may have the same size. For example, the device region DA of the first semiconductor chip 110 and the second semiconductor chip 120 may have the same shape and the same area.

[0037] The device may include a first chip pad region CP1 and a second chip pad region CP2, in which chip pads 115 of a first semiconductor chip 110 and chip pads 125 of a second semiconductor chip 120 are disposed, and the first chip pad region CP1 and the second chip pad region CP2 may have different structures. Chip pads 115 and 125 may be configured to be electrically connected to an integrated circuit in each device region DA. Chip pads 115 and 125 may be disposed in each of the first chip pad region CP1 and the second chip pad region CP2 along a second direction (D2). For example, the integrated circuit may constitute a memory circuit or a logic circuit.

[0038] As used herein, a component described as an “electrical connection” is configured such that an electrical signal can be transmitted from one component to another (although the signal will attenuate in strength as it is transmitted and can be transmitted selectively).

[0039] The first chip pad region CP1 and the second chip pad region CP2 can protrude from different first and second regions located on the same side of the device region DA of each of the first semiconductor chip 110 and the second semiconductor chip 120. In this case, the first and second regions may not have overlapping portions. In a top view, the first semiconductor chip 110 may have an L-shape, and the second semiconductor chip 120 may have an inverted L-shape (see...). Figure 3A and Figure 3B ).

[0040] When these first semiconductor chips 110 and second semiconductor chips 120 are stacked such that the device regions DA overlap each other (see...) Figure 2A The first chip pad region CP1 and the second chip pad region CP2 may not overlap in the stacking direction (D3). Even when the first semiconductor chip 110 is stacked below the second semiconductor chip 120 such that the device regions DA almost completely overlap, the second chip pad region CP2 may not cover the first chip pad region CP1 (see [link to documentation]). Figure 1 and Figure 2A ).

[0041] In this way, the chip stack ST in this embodiment can keep the first chip pad region CP1 and the second chip pad region CP2 open (i.e., not covered) without shifting the first chip pad region CP1 and the second chip pad region CP2 in the first direction (D1) (i.e., without staggered stacking). Therefore, the chip stack ST in this embodiment can be implemented compactly without the additional space consumption (or area occupied) caused by staggered stacking.

[0042] refer to Figure 3A and Figure 3B The length L1 of the first chip pad region CP1 and the length L2 of the second chip pad region CP2 can be equal to each other, and the sum of their lengths (L1+L2) can be less than the total length L of one side (the first side of the device region). The difference between the total length L and the sum of the two lengths (L1+L2), i.e., the gap between the first chip pad region CP1 and the second chip pad region CP2, can be determined by the width of the cut during the process of cutting the first semiconductor chip 110 and the second semiconductor chip 120.

[0043] In this embodiment, when the same device region DA is rectangular in the top view, the longer side (S1' or S2') of the device region DA has a longer length than the shorter side (S3' or S4'), making it easier to place the non-overlapping first chip pad region CP1 and the second chip pad region CP2 on the longer side (S1' or S2') than on the shorter side (S3' or S4') (see [link]). Figure 4 For example, the ratio of the long side to the short side of the device region DA can be 1.5:1 or greater (in a specific example, 2:1 or greater).

[0044] refer to Figure 3A and Figure 3B The protruding length d1 of the first chip pad region CP1 and the protruding length d2 of the second chip pad region CP2 can be equal to each other, and each protruding length can be greater than the width dp of each of chip pads 115 and 125. Chip pads 115 and 125 can be located on the first chip pad region CP1 and the second chip pad region CP2, respectively. Even when the device region DA of the first semiconductor chip 110 is covered by the device region DA of the second semiconductor chip 120, the chip pad 115 located on the first chip pad region CP1 can be open, thereby ensuring the bonding of the lead 135 (see [link to documentation]). Figure 1 , Figure 2A and Figure 2B ).

[0045] In this embodiment, reference Figure 1 , Figure 2A and Figure 2B The packaging substrate 150 may have a first side S1 and a second side S2 opposite to each other in a first direction (D1) (e.g., a second horizontal direction), and a third side S3 and a fourth side S4 opposite to each other in a second direction (D2) (e.g., a first horizontal direction). The substrate pads 155 may include a first substrate pad 155A and a second substrate pad 155B disposed along the first side S1 and the second side S2 and adjacent to the first side S1 and the second side S2, respectively.

[0046] A chip stack ST can be disposed on the package substrate 150 between a first substrate pad 155A and a second substrate pad 155B. In this embodiment, the chip stack ST can be described as including two sub-stacks SS1 and SS2, each including a pair of first semiconductor chips 110 and a pair of second semiconductor chips 120, respectively.

[0047] The first semiconductor chips 110 of the first sub-stacking assembly SS1 and the second sub-stacking assembly SS2 have the same shape (structure) as each other, and the second semiconductor chips 120 of the first sub-stacking assembly SS1 and the second sub-stacking assembly SS2 have the same shape (structure) as each other. In a top view, the first semiconductor chips 110 and the second semiconductor chips 120 of the second sub-stacking assembly SS2 can be understood as being arranged rotated 180 degrees relative to the first semiconductor chips 110 and the second semiconductor chips 120 of the first sub-stacking assembly SS1. In this specification, the "first semiconductor chip 110 and the second semiconductor chip 120" of the second sub-stacking assembly SS2 may be referred to as the "third semiconductor chip and the fourth semiconductor chip," respectively, to distinguish them from the first semiconductor chips 110 and the second semiconductor chips 120 of the first sub-stacking assembly SS1.

[0048] like Figure 2A and Figure 2B As shown, in the chip stack ST, the first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that their device regions DA overlap each other, but the first sub-stack SS1 and the second sub-stack SS2 can be stacked such that the first chip pad region CP1 and the second chip pad region CP2 face opposite directions (+D1 and -D1) in the first direction (D1).

[0049] Specifically, in the first sub-stacking assembly SS1, the first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that the device regions DA overlap each other, and their first chip pad regions CP1 and CP2 face the first side S1 of the package substrate 150. Similarly, in the second sub-stacking assembly SS2, the first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that the device regions DA overlap each other, and the first chip pad regions CP1 and CP2 face the second side S2 of the package substrate 150.

[0050] like Figure 2A As shown, even when all the first semiconductor chips 110 and the second semiconductor chips 120 are stacked such that the device regions DA almost overlap, the chip pads 115 of the first chip pad region CP1 and the chip pads 125 of the second chip pad region CP2 can be open in the upward direction.

[0051] Therefore, even without substantial stepped stacking, the chip pads 115 of the first semiconductor chip 110 and the chip pads 125 of the second semiconductor chip 120 of the first sub-stack SS1 can be electrically connected to the first substrate pad 155A using leads 135, and similarly, the chip pads 115 of the first semiconductor chip 110 and the chip pads 125 of the second semiconductor chip 120 of the second sub-stack SS2 can be electrically connected to the second substrate pad 155B using leads 135.

[0052] In this embodiment, the first sub-stacking component SS1 and the second sub-stacking component SS2 can be stacked separately such that their sides, except for the sides where the chip pad regions CP1 and CP2 are located, are substantially coplanar with each other. In this embodiment, all the first semiconductor chips 110 and the second semiconductor chips 120 can be stacked such that the sides of the chip stack ST in the second direction (D2) are substantially coplanar.

[0053] In this embodiment, all the device regions DA of the first semiconductor chip 110 and the second semiconductor chip 120 are shown to have the same area and the same shape and to overlap substantially completely. However, even when the device regions DA have the same area and the same shape, in some embodiments, at least some semiconductor chips may be additionally stacked in an offset manner for a more stable connection space.

[0054] A molding film 190 may be disposed on a package substrate 150. The molding film 190 may cover the chip stack ST and leads 135 on the package substrate 150. The side surfaces of the molding film 190 may be substantially coplanar with the side surfaces of the package substrate 150. For example, the molding film 190 may include an insulating polymer, such as epoxy molding compound (EMC).

[0055] In this way, the chip stack ST in this embodiment can reduce the area occupied by the chip stack ST without the additional space consumption caused by the stepped stacking, and furthermore, the size of the semiconductor package 100 can be reduced. In this embodiment, the first sub-stack SS1 and the second sub-stack SS2 are shown stacked in the same order of the first semiconductor chip 110 and the second semiconductor chip 120, but it is not limited thereto, and at least one sub-stack may include the first semiconductor chip 110 and the second semiconductor chip 120 stacked in a different order.

[0056] According to this embodiment, the chip stack ST can be implemented by a first semiconductor chip 110 and a second semiconductor chip 120, which may be of the same type of semiconductor chip but have different shapes in a top view. In some embodiments, the first semiconductor chip 110 and the second semiconductor chip 120 can be obtained from the same wafer. Figure 4 It is shown that it is used for Figure 3A and Figure 3B A top view of the wafer W of the first semiconductor chip 110 and the second semiconductor chip 120.

[0057] refer to Figure 4 The enlarged view shows a 4×4 chip array as part of wafer W. The 4×4 chip array includes eight pairs of first semiconductor chips 110 and second semiconductor chips 120 (a 4×2 chip array). In wafer W, the first semiconductor chips 110 and second semiconductor chips 120 can be configured such that first chip pad regions CP1 and second chip pad regions CP2 are located on opposite sides of paired adjacent columns. The first semiconductor chip 110 located in odd-numbered columns may have a first chip pad region CP1 protruding from a first region located on one side (the first side of the device region), and the second semiconductor chip 120 located in even-numbered columns may have a second chip pad region CP2 protruding from a second region located on that side / first side of the device region.

[0058] Figure 4 The first semiconductor chip 110 and the second semiconductor chip 120 can be diced along a scribe lane SL. The scribe lane SL can include a horizontal scribe lane SL1 and a vertical first scribe lane SL2a and a vertical second scribe lane SL2b. Each pair of first scribe lanes SL2a can extend in a curved shape between the first chip pad region CP1 and the second chip pad region CP2. The dicing process including these curved scribe lanes can be performed by "plasma dicing".

[0059] The scribe line SL between unscribed chips can include areas of wafer W in which no circuitry (e.g., no transistors) is formed and / or no circuitry (e.g., no transistors) is formed as part of the integrated circuit of the unscribed chip C.

[0060] Plasma dicing is a method of dividing a wafer into chips by forming a mask to cover chip areas (device areas and chip pad areas) and then using plasma etching to etch the areas not covered by the mask (e.g., dicing tracks). Because plasma etching can be applied to the entire wafer, multiple chips can be separated simultaneously. For example, plasma etching can use fluorine-based gases, such as SF6 or CF4, that are highly reactive with the wafer.

[0061] In this way, the mask can be patterned relatively freely during plasma dicing, and the exposed areas can be etched simultaneously by applying plasma, making it easy to remove dicing tracks, including the second dicing track, as... Figure 4 As shown.

[0062] In this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120, which are of the same type but have different shapes, can be manufactured from a single wafer. (As in...) Figure 3A and Figure 3B As described above, the first semiconductor chip 110 and the second semiconductor chip 120 have the same device region DA, and the first chip pad region CP1 of the first semiconductor chip 110 and the second chip pad region CP2 of the second semiconductor chip 120 can protrude from different first and second regions on the same side of their respective device regions DA. In another embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 can be formed on different wafers W1 and W2, and in this case, different types of dicing traces can be configured (see [link to documentation]). Figure 6A and Figure 6B ).

[0063] Figures 5A to 5C It shows the manufacturing process. Figure 1 A three-dimensional view of the main process of a semiconductor packaging method.

[0064] refer to Figure 5A A first sub-stack SS1 comprising a pair of first semiconductor chips 110 and second semiconductor chips 120 can be formed on the packaging substrate 150.

[0065] The packaging substrate 150 has a first side S1 and a second side S2 opposite to each other in a first direction (D1), and a first substrate pad 155A and a second substrate pad 155B can be respectively configured to be adjacent to the first side S1 and the second side S2. A first semiconductor chip 110 can be disposed between the first substrate pad 155A and the second substrate pad 155B on the packaging substrate 150, such that the first chip pad region CP1 faces the first side S1. The first semiconductor chip 110 can be bonded to the upper surface of the packaging substrate using an adhesive member 131 such as a DAF. Next, a second semiconductor chip 120 can be stacked on the first semiconductor chip 110, such that the device regions DA overlap each other, and the second chip pad region CP2 faces the first side S1. In another embodiment, the stacking order of the first semiconductor chip 110 and the second semiconductor chip 120 can be changed in the opposite direction.

[0066] Next, refer to Figure 5B The desired chip stack ST can be formed by forming a second sub-stack SS2, which includes different pairs of first semiconductor chips 110 and second semiconductor chips 120, on the first sub-stack SS1.

[0067] The process for forming the second sub-stacking assembly SS2 can be performed similarly to that for the first sub-stacking assembly SS1. The second sub-stacking assembly SS2 can be formed on the first sub-stacking assembly SS1 by sequentially stacking the first semiconductor chip and the second semiconductor chip such that the device regions DA overlap. The first semiconductor chip 110 and the second semiconductor chip 120 of the second sub-stacking assembly SS2 can be stacked such that the first chip pad region CP1 and the second chip pad region CP2 face the second side S2. As a result, a chip stack comprising four semiconductor chips 110 and 120 can be configured. The device regions DA of the four semiconductor chips 110 and 120 can all overlap, while the protruding first chip pad regions CP1 and CP2 can be configured such that the first sub-stacking assembly SS1 and the second sub-stacking assembly SS2 face different opposite sides S1 and S2 of the package substrate 150. Furthermore, the first chip pad regions and the second chip pad regions of the first sub-stacking assembly SS1 and the second sub-stacking assembly SS2 can not overlap in the stacking direction (D3). In another embodiment, the stacking order of the first semiconductor chip 110 and the second semiconductor chip 120 can be changed in the opposite direction.

[0068] Next, refer to Figure 5C The chip pad 115 of the first semiconductor chip 110 and the chip pad 125 of the second semiconductor chip 120 can be electrically connected to the first substrate pad 155A and the second substrate pad 155B respectively via leads 135.

[0069] The chip pads 115 of the first semiconductor chip 110 and the chip pads 125 of the second semiconductor chip 120 of the first sub-stacking assembly SS1 can be electrically connected to the first substrate pad 155A using leads 135, and similarly, the chip pads 115 of the first semiconductor chip 110 and the chip pads 125 of the second semiconductor chip 120 of the second sub-stacking assembly SS2 can be electrically connected to the second substrate pad 155B using leads 135.

[0070] In each of the first sub-stacking assembly SS1 and the second sub-stacking assembly SS2, the first chip pad region CP1 of the first semiconductor chip 110 located below the second semiconductor chip 120 can be open and not covered by the second chip pad region CP2. Therefore, even when the device regions DA of all the first semiconductor chips 110 and the second semiconductor chips 120 almost overlap each other, the chip pads 115 of the first chip pad region CP1 and the chip pads 125 of the second chip pad region CP2 can be open in the upward direction, and easy wire bonding processes can be performed. Furthermore, since there is no additional space consumption due to the stepped stacking, the occupied area of ​​the chip stack ST can be reduced. Next, it can be manufactured by forming a molding film 190 covering the chip stack ST and the leads 135 on the packaging substrate 150. Figure 1 and Figure 2A The semiconductor package 100 shown.

[0071] In the previous embodiments (see...) Figure 4 The diagram shows that the first semiconductor chip 110 and the second semiconductor chip 120 in this embodiment are configured as a diced form of a single wafer W, but the first semiconductor chip 110 and the second semiconductor chip 120 can also be manufactured from two wafers W1 and W2, respectively.

[0072] Figure 6A and Figure 6B These are top views of a first wafer and a second wafer used for the first semiconductor chip and the second semiconductor chip, respectively.

[0073] refer to Figure 6A and Figure 6B The diagram shows a 4×3 chip array that is part of a first wafer W1 and a second wafer W2, and the first wafer W1 and the second wafer W2 may respectively include a first semiconductor chip 110 and a second semiconductor chip 120 with different shapes in the top view.

[0074] First, refer to Figure 6A In the first wafer W1, the first semiconductor chip 110 can be configured such that the first chip pad region CP1 is located on opposite sides of a pair of adjacent columns. The first semiconductor chip 110 may have a first chip pad region CP1 protruding from a first region on a first side of the device region. Similarly, referring to... Figure 6BIn the second wafer W2, the second semiconductor chip 120 can be configured such that the second chip pad region CP2 is located on opposite sides of a pair of adjacent columns. The second semiconductor chip 120 may have a second chip pad region CP2 protruding from a second region on a first side of the device region. The arrangement of these chips can be achieved by changing the design and process of the semiconductor chips (the positions of the device region and the chip pad region) so that the chip boundaries are different between opposite sides, and a semiconductor chip of the desired shape can be manufactured by forming curved first scribe lines (SL2a' and SL2a') along the chip boundaries.

[0075] In this way, first semiconductor chips 110 and second semiconductor chips 120 of the same type but with different shapes can be manufactured from different wafers W1 and W2, and the first semiconductor chips 110 and second semiconductor chips 120 can be appropriately selected to form a desired chip stack ST, and a semiconductor package 100 with optimized dimensions can be provided (see [link to product]). Figures 5A to 5C ).

[0076] In the preceding embodiments, a chip stack ST was shown to include two first semiconductor chips 110 and two second semiconductor chips 120, for example, four semiconductor chips, but is not limited thereto. For example, the chip stack ST may include fewer or more numbers of semiconductor chips (e.g., 8 or 12).

[0077] Figure 7 and Figure 8 Semiconductor packages according to various embodiments are shown, including a chip stack in which eight semiconductor chips are stacked.

[0078] For ease of illustration, the semiconductor package 100A and semiconductor package 100B according to this embodiment are shown with leads and molding films omitted. In this case, it can be understood that the first semiconductor chip 110 and the second semiconductor chip 120 are respectively the first semiconductor chip 110 and the second semiconductor chip 120 described in the previous embodiments ( Figures 1 to 6B )same.

[0079] refer to Figure 7 According to this embodiment, the semiconductor package 100A may include a chip stack ST1 in which four first semiconductor chips 110 and four second semiconductor chips 120 are stacked.

[0080] In this embodiment, the chip stack ST1 may include first to fourth sub-stacks SS1, SS2, SS3 and SS4, each including a pair of first semiconductor chips 110 and a pair of second semiconductor chips 120.

[0081] The first semiconductor chips 110 of the first to fourth sub-stacking units SS1, SS2, SS3, and SS4 may have the same shape (or structure) as each other, and the second semiconductor chips 120 of the first to fourth sub-stacking units SS1, SS2, SS3, and SS4 may have the same shape (or structure) as each other. In the top view, it can be understood that the first semiconductor chips 110 and 120 of the second sub-stacking units SS2 and SS4 are configured to rotate 180 degrees from the first semiconductor chips 110 and 120 of the first sub-stacking units SS1 and SS3.

[0082] like Figure 7 As shown, in the chip stack ST1, the first semiconductor chip 110 and the second semiconductor chip 120 can both be configured such that their device regions DA overlap each other. However, the first sub-stack SS1 and the third sub-stack SS3 can be stacked such that their respective first chip pad regions CP1 and second chip pad regions CP2 face the first side S1 of the package substrate 150. Conversely, the second sub-stack SS2 and the fourth sub-stack SS4 can be stacked such that their respective first chip pad regions CP1 and second chip pad regions CP2 face the second side S2 of the package substrate 150.

[0083] In the chip stack ST1 according to this embodiment, even when the device regions DA of all the first semiconductor chips 110 and the second semiconductor chips 120 overlap with each other, the first chip pad region CP1 and the second chip pad region CP2 of a sub-stack (e.g., SS2) may not overlap with the first chip pad region CP1 and the second chip pad region CP2 of other adjacent sub-stacks (e.g., SS1, SS3) in the stacking direction (D3).

[0084] The first chip pad region CP1 and the second chip pad region CP2 of the first sub-stacking assembly SS1 may overlap with the first chip pad region CP1 and the second chip pad region CP2 of the non-adjacent third sub-stacking assembly SS3, and similarly, the first chip pad region CP1 and the second chip pad region CP2 of the second sub-stacking assembly SS2 may overlap with the first chip pad region CP1 and the second chip pad region CP2 of the non-adjacent fourth sub-stacking assembly SS4. Even when the first chip pad region CP1 and the second chip pad region CP2 overlap in the chip stack ST1, it may not be a significant obstacle to performing wire bonding because they can be spaced apart by at least three semiconductor chip thicknesses.

[0085] refer to Figure 8 ,and Figure 7Similar to other embodiments, the semiconductor package 100B according to this embodiment may include a chip stack ST2 in which four first semiconductor chips 110 and four second semiconductor chips 120 are stacked. The chip stack ST2 may include first to fourth sub-stacks SS1', SS2', SS3' and SS4', each including a pair of first semiconductor chips 110 and a pair of second semiconductor chips 120.

[0086] The first semiconductor chip 110 of the first to fourth sub-stacks SS1', SS2', SS3' and SS4' can have the same shape (structure) as each other, and the second semiconductor chip 120 of the first to fourth sub-stacks SS1', SS2', SS3' and SS4' can have the same shape (structure) as each other.

[0087] In each of the first to fourth sub-stacks SS1', SS2', SS3' and SS4', similar to the previous embodiments, the first semiconductor chip 110 and the second semiconductor chip 120 may be stacked such that their device regions DA overlap each other, but the first chip pad region CP1 and the second chip pad region CP2 may be stacked such that they do not overlap when facing the same side of the package substrate 150.

[0088] In this embodiment, the first chip pad region CP1 and the second chip pad region CP2 of the first sub-stack SS1' and the second sub-stack SS2' can be set as the first side S1 facing the package substrate 150, and the first chip pad region CP1 and the second chip pad region CP2 of the third sub-stack SS3' and the fourth sub-stack SS4' can be set as the second side S2 facing the package substrate 150.

[0089] Furthermore, the chip stack ST2 in this embodiment can partially incorporate a stepped stacking method. The second sub-stack SS2' can be stacked on top of the first sub-stack SS1' at a first offset distance O1 in the negative first direction (-D1), and the fourth sub-stack SS4' can be stacked on top of the third sub-stack SS3' at a second offset distance O2 in the positive first direction (+D1). The third sub-stack SS3' can be configured such that the second sub-stack SS2' and all device regions DA overlap each other.

[0090] In this way, in the chip stack ST2 of this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 do not overlap with the first chip pad area CP1 and the second chip pad area CP2 of the adjacent other semiconductor chips, but the first chip pad area CP1 and the second chip pad area CP2 of the second sub-stack SS2' can overlap with the non-adjacent fourth sub-stack SS4'.

[0091] In this embodiment, even when the first chip pad region CP1 and the second chip pad region CP2 of the second sub-stacking component SS2' overlap with the device region DA of the fourth sub-stacking component SS4' in the stacking direction (D3), they can be spaced apart by at least the thickness of two semiconductor chips, so as not to pose a significant obstacle to achieving wire bonding. In some embodiments, by offsetting the third sub-stacking component SS3' in the negative first direction (-D1), the overlap of the device region DA of the non-adjacent fourth sub-stacking component SS4' with the first chip pad region CP1 and the second chip pad region CP2 of the second sub-stacking component SS2' can also be prevented (see...). Figure 14 ).

[0092] Figure 9 and Figure 10 This is a cross-sectional side view showing a semiconductor package according to various embodiments.

[0093] For ease of explanation, semiconductor packages 100C and 100D according to this embodiment are shown having structures in which leads and molding films are omitted. In this case, it can be understood that the first semiconductor chip 110 and the second semiconductor chip 120 are respectively the first semiconductor chip 110 and the second semiconductor chip 120 described in the previous embodiments ( Figures 1 to 6B )same.

[0094] refer to Figure 9 Compared with the previous embodiment ( Figure 1 Similarly, the semiconductor package 100C according to this embodiment may include a chip stack STa in which two first semiconductor chips 110 and two second semiconductor chips 120 are stacked. However, in the chip stack STa of this embodiment, the four semiconductor chips may be stacked in a different order. For example, if Figure 1 The stacking order of the chip stack ST in the semiconductor package shown (see...) Figure 5C Since the shape and arrangement direction of the semiconductor chip are defined as ①-②-③-④, the chip stack STa in this embodiment can be stacked in the order of ①-③-②-④.

[0095] In the chip stack STa of this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 can be stacked such that the device regions DA overlap each other, but the first chip pad region CP1 and the second chip pad region CP2 do not overlap each other in the stacking direction (D3).

[0096] Specifically, the first sub-stacking assembly SS1a may include two first semiconductor chips 110, which are stacked such that their first chip pad regions CP1 face the first side S1 and the second side S2 of the package substrate 150, respectively. The second sub-stacking assembly SS2a may include two second semiconductor chips 120, which are stacked such that their second chip pad regions CP2 face the first side S1 and the second side S2 of the package substrate 150, respectively.

[0097] In this way, with Figure 1 Similar to other embodiments, in the semiconductor package 100C according to this embodiment, the first chip pad region CP1 and the second chip pad region CP2 may not overlap in the stacking direction (D3), and all chip pads 115 and chip pads 125 may be open in the upward direction to facilitate wire bonding connections.

[0098] refer to Figure 10 Compared with the previous embodiment ( Figure 1 and Figure 9 Similarly, the semiconductor package 100D according to this embodiment includes a chip stack STb in which two first semiconductor chips 110 and two second semiconductor chips 120 are stacked. However, in the chip stack STb of this embodiment, the four semiconductor chips can be stacked in a different order. For example, if Figure 1 The stacking order of the chip stack ST is defined as ①-②-③-④ according to the shape and arrangement direction of the semiconductor chip. Therefore, the chip stack STb in this embodiment can be stacked in the order of ①-④-②-③.

[0099] In the chip stack STb of this embodiment, the first semiconductor chip 110 and the second semiconductor chip 120 can be stacked such that the device regions DA overlap each other, but the first chip pad regions CP1 and the second chip pad regions CP2 do not overlap each other in the stacking direction (D3).

[0100] Specifically, the first sub-stack SS1b may include a pair of first semiconductor chips 110 and second semiconductor chips 120, which are stacked such that first chip pad regions CP1 and CP2 face the first side S1 and the second side S2 of the package substrate 150, respectively. The second sub-stack SS2a may include a pair of first semiconductor chips 110 and second semiconductor chips 120, which are stacked such that first chip pad regions CP1 and CP2 face the first side S1 and the second side S2 of the package substrate 150, respectively.

[0101] In this way =, with Figure 1 and Figure 9 Similar to other embodiments, the semiconductor package 100D according to this embodiment may have a first chip pad region CP1 and a second chip pad region CP2 that do not overlap with each other in the stacking direction (D3), and all chip pads 115 and chip pads 125 may be open in the upward direction to facilitate wire bonding connections.

[0102] like Figure 9 and Figure 10 The first and second semiconductor chips can be stacked in various stacking orders and orientations to achieve similar effects. This variation is not limited to a stacked structure of four semiconductor chips, and can be achieved through… Figure 9 and Figure 10 Additional stacks are made on the chip stacks STa and STb. Figure 9 and Figure 10 The chip stacking components STa and STb are used to realize the stacked structure of eight semiconductor chips.

[0103] Figure 11 This is a perspective view showing a semiconductor package according to an embodiment, and Figure 12 It is shown Figure 11 A side view of a semiconductor package. Figure 11 This is a perspective view of the semiconductor package 200 from the lower surface, where the molding film 190 and the package substrate 250 are indicated by dashed lines, making it easier to understand the connection structure of the chip stack ST3 and the lead 235.

[0104] refer to Figure 11 and Figure 12 According to this embodiment, the semiconductor package 200 may include a package substrate 250, a chip stack ST3 and a molding film 190. The molding film 190 surrounds the chip stack ST3 on the package substrate 250. In the chip stack ST3, a plurality of first semiconductor chips 110 and a plurality of second semiconductor chips 120 are stacked on the package substrate 250.

[0105] In this embodiment, the chip stack ST3 can be understood as... Figure 1 The chip stack ST is in an inverted form. Chip stack ST3 can be stacked such that... Figure 1 The chip stack ST has chip pads 115 and 125 facing the package substrate 250. The chip stack ST3 may be spaced apart from the upper surface of the package substrate 250. The molding film 190 may have a portion that fills the space between the chip stack ST3 and the package substrate 250.

[0106] The chip stack ST3 may include a plurality of first semiconductor chips 110 and a plurality of second semiconductor chips 120 stacked on the package substrate 250 in a vertical direction (e.g., stacking direction (D3)). In this embodiment, the chip stack ST3 is shown as including two first semiconductor chips 110 and two second semiconductor chips 120 (e.g., four semiconductor chips), but is not limited thereto. For example, the chip stack ST3 may include fewer or more numbers of semiconductor chips (e.g., 8 or 12).

[0107] The stacked first semiconductor chip 110 and second semiconductor chip 120 can be joined by an adhesive member 131. The adhesive member 131 can be disposed between adjacent first semiconductor chips 110 and second semiconductor chips 120. The adhesive member 131' can also be disposed on the upper surface of the chip stack ST3, that is, on the upper surface of the first semiconductor chip 110 at the uppermost height, but unlike other adhesive members 131, at least a portion of the adhesive member 131' can be removed.

[0108] Similar to the previous embodiments, the first semiconductor chip 110 and the second semiconductor chip 120 may have the same device region DA in which the integrated circuit is implemented. Chip pads 115 of the first semiconductor chip 110 and chip pads 125 of the second semiconductor chip 120 may be provided, and the first chip pad region CP1 and the second chip pad region CP2 may protrude from different first and second regions on the same side of the device region DA of each of the first semiconductor chip 110 and the second semiconductor chip 120. In this case, the first and second regions may not have overlapping portions.

[0109] In the chip stack ST3, as described above, the first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that the first chip pad region CP1 and the second chip pad region CP2 face the upper surface of the package substrate 250. The first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that the device regions DA overlap each other, while the first chip pad regions CP1 and the second chip pad regions CP2 do not overlap in the stacking direction (D3). Even if the second semiconductor chip 120 is stacked below the first semiconductor chip 110, the first chip pad regions CP1 and the second chip pad regions CP2 can still be open towards the upper surface of the package substrate 250.

[0110] In this way, the chip stack ST3 in this embodiment can be configured such that, without a stepped stack, both the first chip pad area of ​​the first semiconductor chip and the second chip pad area of ​​the second semiconductor chip are open in the downward direction.

[0111] In this embodiment, the chip stack ST3 can be described as comprising two sub-stacks SS1 and SS2, each sub-stack including a pair of first semiconductor chips 110 and second semiconductor chips 120. Based on the upper surface of the packaging substrate 250, the first sub-stack SS1 can be disposed on the second sub-stack SS2. In a top view, the first semiconductor chips 110 and 120 of the second sub-stack SS2 can be understood as the first semiconductor chips 110 and 120 of the first sub-stack SS1 being rotated 180 degrees respectively.

[0112] In this embodiment, the packaging substrate 250 may have a first side S1 and a second side S2 that are opposite to each other in a first direction (D1), and the substrate pads 155 may include a first substrate pad 255A and a second substrate pad 255B that are adjacent to the first side S1 and the second side S2 and disposed along the first side S1 and the second side S1, respectively. A chip stack ST3 may be disposed on the packaging substrate 250 between the first substrate pad 255A and the second substrate pad 255B.

[0113] In the first sub-stacking assembly SS1, the first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that device regions DA overlap each other, and the first chip pad region CP1 and the second chip pad region CP2 face the first side S1 of the package substrate 250. Similarly, in the second sub-stacking assembly SS2, the first semiconductor chip 110 and the second semiconductor chip 120 can be configured such that device regions DA overlap each other, and the first chip pad region CP1 and the second chip pad region CP2 face the second side S2 of the package substrate 250.

[0114] In this way, in the chip stack ST3, even if all the first semiconductor chips 110 and the second semiconductor chips 120 can be stacked such that their device regions DA almost overlap, the chip pads 115 of the first chip pad region CP1 and the chip pads 125 of the second chip pad region CP2 can be open in the downward direction.

[0115] In this embodiment, the first substrate pad 255A and the second substrate pad 255B can be disposed on the upper surface of the package substrate 250 in the region overlapping with the first chip pad region CP1 and the second chip pad region CP2 of the first sub-stack SS1 and the second sub-stack SS2. Chip pads 115 and 125 can be connected to the first substrate pad 255A and the second substrate pad 255B respectively via leads 235 formed almost perpendicularly.

[0116] Specifically, the chip pads 115 of the first semiconductor chip 110 and the chip pads 125 of the second semiconductor chip 120 of the first sub-stacking assembly SS1 can be electrically connected to the first substrate pad 255A using vertical leads 235, and similarly, the chip pads 115 of the first semiconductor chip 110 and the chip pads 125 of the second semiconductor chip 120 of the second sub-stacking assembly SS2 can be electrically connected to the second substrate pad 255B using vertical leads 235.

[0117] Vertical leads 235 can extend from chip pads 115 and 125 of each of the plurality of first semiconductor chips 110 and second semiconductor chips 120 to the lower surface of the molding film 190, and can be connected to the first substrate pads and the second substrate pads. Similar to conventional leads, vertical leads 235 can include, but are not limited to, gold (Au), silver (Ag), lead (Pb), aluminum (Al), copper (Cu), or alloys thereof.

[0118] In this way, the chip stack ST3 in this embodiment can reduce the area occupied by the chip stack ST3 without the additional space consumption caused by the stepped stacking, and furthermore, the size of the semiconductor package 200 can be reduced. In this embodiment, the first sub-stack SS1 and the second sub-stack SS2 are shown stacked in the same order of the first semiconductor chip 110 and the second semiconductor chip 120, but it is not limited to this, and at least one sub-stack may include the first semiconductor chip 110 and the second semiconductor chip 120 stacked in a different order.

[0119] The packaging substrate 250 in this embodiment may include a redistribution structure. The packaging substrate 250 may be disposed below the molding film 190. The packaging substrate 250 may include a plurality of insulating layers 251, a first substrate pad 255A and a second substrate pad 255B connected to a vertical lead 235, and a redistribution layer 252 and a redistribution path 253 for redistributing the first substrate pad 255A and the second substrate pad 255B.

[0120] Multiple insulating layers 251 may include insulating resins. Insulating resins may include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimides, or resins with inorganic fillers and / or glass fibers impregnated in these resins, such as prepregs, Ajinomoto laminated film (ABF), flame retardant-4 (FR-4), bismaleimide triazine (BT), etc. According to embodiments, insulating layer 251 may include photosensitive resins such as photoimageable dielectrics (PIDs), such as photosensitive polyimides, polybenzoxazole (PBO), phenolic polymers, benzocyclobutene polymers, etc.

[0121] The redistribution layer 252 may be disposed below the uppermost insulating layer 251 and may include a first substrate pad 255A and a second substrate pad 255B connected as the uppermost layer to the vertical lead 235. The redistribution layer 252 may include, for example, ground patterns, power patterns, and signal patterns. The signal patterns may provide paths for transmitting / receiving various signals (e.g., data signals, excluding ground signals, power signals, etc.). The redistribution layer 252 may include more or fewer layers than those shown in the figures (e.g., three layers). The redistribution path 253 may penetrate the insulating layer 251 to connect the redistribution layer 252. The redistribution layer 252 and the redistribution path 253 may include, for example, metallic materials including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution path 253 may have a structure integrated with adjacent redistribution layers 252, but is not limited thereto.

[0122] External connection terminals 160 may be disposed below the package substrate 250 and may be connected to the redistribution layer 252. The package substrate 250 may also include an under-bump metallization layer located between the external connection terminals 160 and the redistribution layer 252. A protective layer 261 may be disposed below the package substrate 250. The protective layer 261 may protect the bottommost redistribution layer 252 or the under-bump metallization layer from external physical and chemical damage. The protective layer 261 may include an insulating material and may be formed using, for example, photoresist (PSR).

[0123] Figures 13A to 13E It shows the manufacturing process. Figure 11 A three-dimensional view of the main process of a semiconductor packaging method.

[0124] refer to Figure 13A The chip stack ST3 can be prepared by sequentially stacking a first semiconductor chip 110 and a second semiconductor chip 120 on a carrier substrate 310.

[0125] The carrier substrate 310 can be a temporary support including a glass wafer, a curable resin layer, etc. The chip stack ST3 can be similar to... Figure 5A and Figure 5BThe chip stack ST described herein, and its associated description, can be combined with the description of this embodiment. Specifically, a plurality of first semiconductor chips 110 and second semiconductor chips 120 can be stacked such that chip pads 115 and chip pads 125 face upwards. The plurality of first semiconductor chips 110 and second semiconductor chips 120 can be bonded to each other by adhesive members 131. In the chip stack ST3, even if all the first semiconductor chips 110 and second semiconductor chips 120 are stacked such that device regions DA almost overlap, all chip pads 115 and chip pads 125 of the first chip pad region CP1 and the second chip pad region CP2 can be open in the upward direction.

[0126] Next, refer to Figure 13B Leads 235 can be formed on chip pads 115 and 125. Next, refer to... Figure 13C A molded film 190 can be formed to cover the chip stack ST3 on which leads 235 are formed.

[0127] Leads 235 can be formed on each of chip pads 115 and 125 using the capillary of a wire bonding machine. Leads 235 can be formed in a nearly vertical direction (D3) and at a height sufficiently higher than the upper surface of the chip stack ST3. After forming the leads 235, a molding film 190 can be formed on the carrier substrate 310 to cover the chip stack ST3 and the leads 235. The molding film 190 can be formed to cover at least the upper surface of all leads 235.

[0128] Next, refer to Figure 13D The molding film 190 can be polished to expose the upper surface 190T of the flat molding film 190, which exposes the upper surface of the leads 235. Even after the polishing process, the molding film portion 190F can remain on the upper surface of the chip stack ST3. All leads 235 connected to chip pads 115 and 125 can be disposed on the remaining molding film portion 190F. In addition, all leads 235 can be exposed on the upper surface 190T of the molding film 190, and the exposed surface can have an elliptical shape.

[0129] Next, refer to Figure 13E An encapsulation substrate 250, which can serve as a redistribution structure, and an external connection terminal 160 can be formed on the molding film 190.

[0130] The package substrate 250 may include an insulating layer 251, a redistribution layer 252 having a first substrate pad 255A and a second substrate pad 255B, and redistribution pathways 253. The insulating layer 251 can be formed by sequentially applying and curing a photosensitive material (e.g., PID). The redistribution layer 252 and redistribution pathways 253 can be formed by performing an exposure process and a development process to form vias penetrating the insulating layer 251, and by using an electroplating process to pattern a metal material on the insulating layer 251. In this embodiment, the package substrate 250 can be formed by repeatedly performing exposure, development, electroplating, and other processes. External connection terminals 160 can be formed within openings in the protective layer 161. For example, the external connection terminals 160 can be formed using a solder ball attachment process.

[0131] In some embodiments, after removing the carrier substrate 310, an additional molding layer may be applied to the chip stack ST3 from its exposed molding film 190. Figure 13A Before forming the chip stack in the process, an additional molding layer can be provided on the carrier substrate as a preliminary molding layer.

[0132] In some embodiments, the packaging substrate 250 may include the packaging substrate 150, such as Figure 1 The printed circuit board described in [the document], and can be used via [the following] Figure 13D This is achieved by bonding the pre-manufactured package substrate 150 after the process. For example, this can be done by bonding the first substrate pad 155A and the second substrate pad 155B of the package substrate 150 to connect to the leads 235 exposed on the upper surface 190T of the molding film 190.

[0133] The semiconductor package according to this embodiment can be implemented using a structure that includes different numbers of semiconductor chips. Figure 14 This is a cross-sectional side view of a semiconductor package according to an embodiment, which may include a chip stack having eight semiconductor chips.

[0134] refer to Figure 14 According to this embodiment, the semiconductor package 200A includes a chip stack ST4 in which four first semiconductor chips 110 and four second semiconductor chips 120 are stacked, and is configured to... Figure 11 and Figure 12 In a similar manner to the embodiments, chip pads 115 and 125 can be configured to face the upper surface of the package substrate 250.

[0135] In this embodiment, the chip stack ST4 may include first to fourth sub-stacks SS1”, SS2”, SS3” and SS4”, each including a pair of first semiconductor chips 110 and a pair of second semiconductor chips 120.

[0136] The first semiconductor chip 110 of the first to fourth sub-stacks SS1”, SS2”, SS3” and SS4” can have the same shape (structure) as each other, and the second semiconductor chip 120 of the first to fourth sub-stacks SS1”, SS2”, SS3” and SS4” can have the same shape (structure) as each other.

[0137] Each of the first to fourth sub-stacks SS1”, SS2”, SS3” and SS4” may include a first semiconductor chip 110 and a second semiconductor chip 120 stacked such that device regions DA overlap each other, but the first chip pad region CP1 of the first semiconductor chip 110 and the second chip pad region CP2 of the second semiconductor chip 120 may be stacked without overlapping, while facing the same side of the package substrate 250.

[0138] In this embodiment, the chip stack ST4 can partially incorporate a ladder stacking method.

[0139] Specifically, the first chip pad region CP1 of the first sub-stacking component SS1” and the second chip pad region CP2 of the second sub-stacking component SS2” can be configured to face the first side S1 of the package substrate 250, and the second sub-stacking component SS2” can be offset and stacked on the first sub-stacking component SS1” in a positive first direction (+D1) with a third distance O1'. Similarly, the first chip pad region CP1 of the third sub-stacking component SS3” and the second chip pad region CP2 of the fourth sub-stacking component SS4” can be configured to face the second side S2 of the package substrate 250, and the fourth sub-stacking component SS4” can be offset and stacked on the third sub-stacking component SS3” in a negative first direction (-D1) with a fourth distance O2'.

[0140] Alternatively, in this embodiment, the third sub-stacking component SS3” can also be stacked at a predetermined distance O3 from the second sub-stacking component SS2” relative to the device region DA.

[0141] In this way, by appropriately stacking the first to fourth sub-stacks SS1”, SS2”, SS3” and SS4” with offset, all chip pads 115 and chip pads 125 of the eight semiconductor chips 110 and 120 can be configured to be vertically connected to the first substrate pad 255A and the second substrate pad 255B of the package substrate 250 via leads 235.

[0142] According to the above embodiments, the semiconductor chip may have a chip pad region that protrudes from other regions located on a first side of the device region, and may be stacked such that the chip pad regions do not overlap in the stacking direction, so as to minimize the area occupied by the chip stack in the semiconductor package and reduce the size of the semiconductor package.

[0143] The various advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of describing specific embodiments.

[0144] While exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.

Claims

1. A semiconductor package, the semiconductor package comprising: A packaging substrate having a first side and a second side opposite to the first side, the packaging substrate including a first substrate pad adjacent to the first side and a second substrate pad adjacent to the second side; and A chip stack comprising a plurality of semiconductor chips disposed on a packaging substrate between first substrate pads and second substrate pads, wherein the plurality of semiconductor chips includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip, each having the same device region. Each of the first semiconductor chip and the third semiconductor chip includes a corresponding first chip pad region protruding from a first region on a first side of the device region of the first semiconductor chip and the third semiconductor chip; each of the second semiconductor chip and the fourth semiconductor chip includes a corresponding second chip pad region protruding from a second region on a first side of the device region of the second semiconductor chip and the fourth semiconductor chip; and a plurality of chip pads are disposed in each of the first chip pad regions and the second chip pad regions, the plurality of chip pads including a first plurality of chip pads located in the first chip pad regions of the first semiconductor chip and the third semiconductor chip, and a second plurality of chip pads located in the second chip pad regions of the second semiconductor chip and the fourth semiconductor chip; The first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region of the first semiconductor chip and the second chip pad region of the second semiconductor chip face the first side of the packaging substrate and do not overlap each other in the stacking direction, and the first plurality of chip pads of the first semiconductor chip and the second plurality of chip pads of the second semiconductor chip are electrically connected to the first substrate pads. The third semiconductor chip and the fourth semiconductor chip are stacked such that the first chip pad region of the third semiconductor chip and the second chip pad region of the fourth semiconductor chip face the second side of the packaging substrate and do not overlap each other in the stacking direction, and the first plurality of chip pads of the third semiconductor chip and the second plurality of chip pads of the fourth semiconductor chip are electrically connected to the second substrate pads.

2. The semiconductor package according to claim 1, wherein, The device region of each of the first to fourth semiconductor chips has a rectangular shape in a top view, and The first side of the device region of each of the first to fourth semiconductor chips corresponds to the long side of the rectangular shape.

3. The semiconductor package according to claim 1, wherein, Each of the first chip pad region and the second chip pad region has a protruding width that is greater than the width of each of the first plurality of chip pads and the second plurality of chip pads.

4. The semiconductor package according to claim 1, wherein, In a first horizontal direction along the first side of the device region, the first length of the first chip pad region is equal to the second length of the second chip pad region, and the number of chip pads in the first plurality of chip pads disposed in the first chip pad region is equal to the number of chip pads in the second plurality of chip pads disposed in the second chip pad region.

5. The semiconductor package according to claim 1, wherein, The first chip pad region and the second chip pad region, facing the same direction, are spaced apart from each other in a first horizontal direction along the first side of the device region.

6. The semiconductor package according to claim 1, wherein, The first to the fourth semiconductor chips are stacked such that the plurality of chip pads face upward with their backs to the packaging substrate, and each of the plurality of chip pads is connected to a corresponding substrate pad in the first substrate pad and the second substrate pad via a corresponding lead.

7. The semiconductor package according to claim 1, wherein, The first to the fourth semiconductor chips are stacked such that the plurality of chip pads face the package substrate, and each of the plurality of chip pads is connected to a corresponding substrate pad in the first substrate pad and the second substrate pad via a corresponding lead.

8. The semiconductor package according to claim 7, wherein, The first substrate pad and the second substrate pad are disposed on the upper surface of the package substrate in the area overlapping with the first chip pad area and the second chip pad area.

9. The semiconductor package of claim 7, further comprising a molded film disposed on the package substrate and surrounding the chip stack. in, The molded film has a portion located between the chip stack and the packaging substrate.

10. The semiconductor package according to claim 1, wherein, The chip stack includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip stacked in sequence.

11. The semiconductor package according to claim 1, wherein, The chip stack includes a first semiconductor chip, a third semiconductor chip, a second semiconductor chip, and a fourth semiconductor chip stacked in sequence.

12. The semiconductor package according to claim 1, wherein, The chip stack includes the first semiconductor chip, the fourth semiconductor chip, the second semiconductor chip, and the third semiconductor chip stacked in sequence.

13. A semiconductor package, the semiconductor package comprising: A packaging substrate having a first side and a second side opposite to the first side, the packaging substrate including a first substrate pad adjacent to the first side and a second substrate pad adjacent to the second side; and A chip stacking assembly includes a plurality of sub-stacks disposed on a packaging substrate between first substrate pads and second substrate pads, and each of the plurality of sub-stacks has a corresponding first semiconductor chip and a second semiconductor chip. Each of the first semiconductor chip and the second semiconductor chip includes a device region. The first semiconductor chip includes a corresponding first chip pad region protruding from a first region on a first side of the device region of the first semiconductor chip. The second semiconductor chip includes a corresponding second chip pad region protruding from a second region on a first side of the device region of the second semiconductor chip. A plurality of chip pads are disposed in the first chip pad region and the second chip pad region. The plurality of sub-stacks includes a first sub-stack and a second sub-stack sequentially stacked on the packaging substrate. In the first sub-stack, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the first side of the package substrate and do not overlap each other in the stacking direction, and each of the plurality of chip pads in the first chip pad region and the second chip pad region of the first sub-stack is connected to a corresponding substrate pad in the first substrate pad via a corresponding lead. In the second sub-stack, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the second side of the package substrate and do not overlap each other in the stacking direction, and each of the plurality of chip pads in the first chip pad region and the second chip pad region of the second sub-stack is connected to a corresponding substrate pad in the second substrate pad via a corresponding lead.

14. The semiconductor package of claim 13, wherein, The plurality of sub-stacks also includes a third sub-stack and a fourth sub-stack. In the third sub-stack, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the first side and do not overlap each other in the stacking direction, and each of the plurality of chip pads in the first chip pad region and the second chip pad region of the third sub-stack is connected to a corresponding substrate pad in the first substrate pad via a corresponding lead. In the fourth sub-stack, the first semiconductor chip and the second semiconductor chip are stacked such that the first chip pad region and the second chip pad region face the second side and do not overlap each other in the stacking direction, and each of the plurality of chip pads in the first chip pad region and the second chip pad region of the fourth sub-stack is connected to a corresponding substrate pad in the second substrate pad via a corresponding lead.

15. The semiconductor package of claim 14, wherein, The first semiconductor chip and the second semiconductor chip are stacked such that the plurality of chip pads face upward with their backs to the packaging substrate, and each of the plurality of chip pads is connected to a corresponding substrate pad in the first substrate pad and the second substrate pad via a corresponding lead.

16. The semiconductor package of claim 15, wherein, The chip stack includes a first sub-stack, a second sub-stack, a third sub-stack, and a fourth sub-stack, which are stacked sequentially. The first to the fourth sub-stacking components are stacked sequentially such that the device regions of the first semiconductor chip and the device regions of the second semiconductor chip overlap in the stacking direction.

17. The semiconductor package of claim 15, wherein, The chip stack includes a first sub-stack, a third sub-stack, a second sub-stack, and a fourth sub-stack that are stacked sequentially. The third sub-stacking component is stacked in a stepped manner on the first sub-stacking component, such that the first chip pad area and the second chip pad area of ​​the first sub-stacking component are open. The fourth sub-stacking component is stacked in a stepped manner on the second sub-stacking component, such that the first chip pad area and the second chip pad area of ​​the second sub-stacking component are open, and The second sub-stacking member and the third sub-stacking member are stacked such that the device region of the first semiconductor chip and the device region of the second semiconductor chip overlap in the stacking direction.

18. The semiconductor package of claim 14, wherein, The first semiconductor chip and the second semiconductor chip are stacked such that the plurality of chip pads face the package substrate, and each of the plurality of chip pads is connected to a corresponding substrate pad in the first substrate pad and the second substrate pad via a corresponding lead.

19. The semiconductor package of claim 18, wherein, The chip stack includes a first sub-stack, a third sub-stack, a second sub-stack, and a fourth sub-stack that are stacked sequentially. The third sub-stacking component is stacked in a stepped manner on the first sub-stacking component, such that the first chip pad area and the second chip pad area of ​​the first sub-stacking component are open. The fourth sub-stacking component is stacked in a stepped manner on the second sub-stacking component, such that the first chip pad area and the second chip pad area of ​​the second sub-stacking component are open, and The second sub-stacking member and the third sub-stacking member are stacked such that the device region of the first semiconductor chip and the device region of the second semiconductor chip overlap in the stacking direction.

20. A semiconductor package, the semiconductor package comprising: A packaging substrate, the packaging substrate including substrate pads; A chip stack comprising a plurality of semiconductor chips stacked on the packaging substrate; as well as A molded film, said molded film surrounding the chip stack on the packaging substrate. The plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip, each of which includes a device region having the same size and shape. The first semiconductor chip and the second semiconductor chip each include a first chip pad region and a second chip pad region protruding from different regions on a first side of the device region, and a plurality of chip pads located in each of the first chip pad region and the second chip pad region, each of the plurality of chip pads being connected to the substrate pads via a corresponding lead. The first semiconductor chip and the second semiconductor chip are stacked such that the pad regions of the first chip and the pad regions of the second chip face a first direction and do not overlap each other in the stacking direction.

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