Light detection device

Abstract

The light detection device includes: a semiconductor substrate including a photoelectric conversion unit; a floating diffusion formed from the surface of the semiconductor substrate toward the inside of the semiconductor substrate; and a transistor disposed in the semiconductor substrate. The transistor includes a gate electrode embedded in the semiconductor substrate in a manner having a surface substantially flush with a surface of the semiconductor substrate.

Description

Technical Field

[0001] This disclosure relates to optical detection devices. Background Technology

[0002] For example, Patent Document 1 discloses an image sensor in which a portion of the gate electrode is embedded in a semiconductor substrate.

[0003] Reference List

[0004] Patent documents

[0005] PTL 1: JP 2022-146934 A Summary of the Invention

[0006] Technical issues

[0007] In Patent Document 1, the remaining portion of the gate electrode is located above the surface of the semiconductor substrate, thus forming a step. This can lead to various problems. For example, with advancements in miniaturization, parasitic capacitance generated between the electrode and vias becomes significant. When such electrodes and vias are provided for floating diffusion, the capacitance of the floating diffusion increases, and the effect of noise becomes more pronounced. Furthermore, in order to compensate for the difference between densely layered and non-densely layered areas, when a dummy electrode is provided on the surface of the semiconductor substrate in the latter area, parasitic capacitance may be generated between the dummy electrode and other wiring.

[0008] One aspect of this disclosure is to suppress the increase in parasitic capacitance caused by the gate electrode.

[0009] Solution to the problem

[0010] A photodetector according to one aspect of the present disclosure includes: a semiconductor substrate including a photoelectric conversion unit; a floating diffusion formed from the surface of the semiconductor substrate into the interior of the semiconductor substrate; and a transistor disposed in the semiconductor substrate, wherein the transistor includes a gate electrode embedded in the semiconductor substrate in such a manner as to include a surface substantially flush with the surface of the semiconductor substrate. Attached Figure Description

[0011] [ Figure 1 [Illustration] is a schematic diagram showing an example of the structure of a light detection device according to an embodiment.

[0012] [ Figure 2 [ ] is a diagram showing an example of a pixel circuit.

[0013] [ Figure 3 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0014] [ Figure 4 [ ] is a diagram showing a comparative example.

[0015] [ Figure 5 [ ] is a diagram showing an example of a basically flush construction.

[0016] [ Figure 6 [ ] is a diagram showing an example of a pixel circuit.

[0017] [ Figure 7 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0018] [ Figure 8 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0019] [ Figure 9 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0020] [ Figure 10 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0021] [ Figure 11 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0022] [ Figure 12 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0023] [ Figure 13 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0024] [ Figure 14 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0025] [ Figure 15 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0026] [ Figure 16 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0027] [ Figure 17 [Illustration] is a schematic diagram showing an example of the structure of a light detection device.

[0028] [ Figure 18 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0029] [ Figure 19 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0030] [ Figure 20 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0031] [ Figure 21[Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0032] [ Figure 22 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0033] [ Figure 23 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0034] [ Figure 24 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0035] [ Figure 25 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0036] [ Figure 26 [Illustration] is an illustration showing an example of a method for manufacturing a light detection device.

[0037] [ Figure 27 [Illustration] is a diagram illustrating an example of pixel circuit commonality.

[0038] [ Figure 28 [Illustration 1] is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0039] [ Figure 29 [This is an illustration of an example of the installation location of the vehicle exterior information detection unit and the imaging unit.] Detailed Implementation

[0040] Embodiments of the present disclosure are described below with reference to the accompanying drawings. In the following embodiments, redundant descriptions are omitted by assigning the same reference numerals to the same elements.

[0041] This disclosure will now be described in the following order.

[0042] 1. Implementation Method

[0043] 2. Variations

[0044] 2.1 First Variation Example

[0045] 2.2 Second variation

[0046] 2.3 Third variation

[0047] 2.4 Application Examples

[0048] 3. Examples of manufacturing methods

[0049] 4. Examples of pixel circuit commonality

[0050] 5. Summary

[0051] 6. Examples of applications of moving bodies

[0052] 1. Implementation Method

[0053] Figure 1 This is a schematic diagram illustrating a possible configuration of a light detection device according to an embodiment. The light detection device 90 illustrated herein is a solid-state imaging device (also known as an image sensor, etc.), wherein components are disposed, for example, in a silicon semiconductor substrate and a semiconductor substrate. The light detection device 90 includes a light detection region 91, a control circuit 93, a vertical drive circuit 94, a column signal processing circuit 95, a horizontal drive circuit 96, an output circuit 97, signal lines 98H, 98V, and 99.

[0054] The light detection area 91 is a pixel area including multiple pixels 92, and may also be referred to as a pixel array section, etc. The multiple pixels 92 are arranged in a two-dimensional array. Figure 1 The XYZ coordinate system for the light detection region 91 is also shown. The X-axis direction corresponds to the row direction of the array, and for example, to the transverse direction (horizontal direction) of the light detection device 90. The Y-axis direction corresponds to the column direction of the array, and for example, to the longitudinal direction (vertical direction) of the light detection device 90. The Z-axis direction corresponds, for example, to the front-back direction (up-down direction) of the light detection device 90.

[0055] The light detection device 90 detects the light incident on the light detection area 91. Unless otherwise stated, the light detection device 90 is a back-illuminated type light detection device that detects light propagating in the positive Z-axis direction (light incident from the rear).

[0056] Pixel 92 includes a photoelectric conversion unit. The photoelectric conversion unit generates a charge corresponding to the amount of incident light. For example, the photoelectric conversion unit is a photodiode (PD). Circuitry is also provided to generate and output a voltage signal (pixel signal) corresponding to the amount of charge generated in the photoelectric conversion unit. Pixel 92 can be understood to also include such circuitry, and in this case, pixel 92 can also be referred to as a pixel circuit.

[0057] Control circuit 93, vertical drive circuit 94, column signal processing circuit 95, horizontal drive circuit 96, and output circuit 97 constitute the peripheral circuitry of the light detection region 91. The area where these circuits are arranged is labeled as the peripheral region SR (described later). Figure 3 wait).

[0058] The control circuit 93 receives data indicating the input clock, operating mode, etc., and outputs data such as internal information of the photodetector 90. Based on the vertical synchronization signal, horizontal synchronization signal, and master clock, the control circuit 93 generates clock signals and control signals that serve as references for the operation of the vertical drive circuit 94, column signal processing circuit 95, horizontal drive circuit 96, etc. The control circuit 93 inputs (provides) the generated signals to the vertical drive circuit 94, column signal processing circuit 95, horizontal drive circuit 96, etc.

[0059] The vertical drive circuit 94 includes, for example, a shift register. The vertical drive circuit 94 is connected to the light detection region 91 via multiple signal lines 98H (horizontal signal lines) extending in the row direction (X-axis direction) of the pixel 92. Each signal line 98H extends for each pixel row, and each signal line 98H may include, for example, multiple signal lines. The vertical drive circuit 94 provides a drive signal (e.g., a pulse signal) for driving the pixel 92 to the selected signal lines 98H.

[0060] The driving of the driving pixel 92 by the vertical driving circuit 94 includes the pixel transistor described later. Figure 2 The pixel transistor 1) is driven to output a voltage signal (pixel signal) corresponding to the amount of charge generated at the photoelectric conversion unit in pixel 92 to the corresponding signal line 98V among the multiple signal lines 98V (vertical signal lines) extending in the column direction (Y-axis direction) of pixel 92.

[0061] Column signal processing circuitry 95 is connected to photodetection area 91 via signal line 98V. Each signal line 98V may include multiple signal lines. For example, column signal processing circuitry 95 is configured for each pixel column and performs signal processing such as noise removal on the pixel signals from pixels 92 in a row for each pixel column. Column signal processing circuitry 95 performs signal processing such as correlated double sampling (CDS) for removing fixed-pattern noise inherent in pixels 92, signal amplification, and analog-to-digital (AD) conversion. A horizontal selection switch (not shown) is connected between the output stage of column signal processing circuitry 95 and signal line 98V.

[0062] The horizontal drive circuit 96 includes, for example, a shift register. The horizontal drive circuit 96 sequentially selects each column signal processing circuit 95 by sequentially outputting horizontal scan pulses, and causes each column signal processing circuit 95 to output a pixel signal to the signal line 99.

[0063] The output circuit 97 performs signal processing on the pixel signals sequentially supplied from each column signal processing circuit 95 via signal lines 99 and outputs them. For example, it performs buffering, black level adjustment, column deviation correction, and various digital signal processing.

[0064] Figure 2 This is a diagram illustrating an example of a pixel circuit. The photoelectric conversion unit included in pixel 92 is referred to as and shown as photoelectric conversion unit 3. As described above, photoelectric conversion unit 3 generates a charge corresponding to the amount of incident light. Figure 2 In the diagram, photoelectric conversion unit 3 is shown as a photodiode with anode grounded (GND).

[0065] As components of the circuit (pixel circuit) disposed around the photoelectric conversion unit 3, a plurality of transistors 1 and a floating diffuser 2 are exemplified. Transistors 1 may also be referred to as pixel transistors.

[0066] Four transistors are illustrated as a plurality of transistors 1. To distinguish them, they are referred to and shown as transistor 1-1, transistor 1-2, transistor 1-3, and transistor 1-4. When there is no need to specifically distinguish them, they are simply referred to as transistor 1.

[0067] Partial gate electrodes of transistor 1 are shown using reference numerals. The gate electrode of transistor 1-1 is labeled and shown as gate electrode 11-1. The gate electrode of transistor 1-2 is labeled and shown as gate electrode 11-2. The gate electrode of transistor 1-4 is labeled and shown as gate electrode 11-4. When no special distinction is needed, they are simply referred to as gate electrode 11. Examples of materials for gate electrode 11 include polycrystalline silicon.

[0068] In the following description, the connection of transistor 1 between two elements means that one of the source and drain of transistor 1 is connected to one element, and the other of the source and drain is connected to the other element.

[0069] Transistor 1-1 is disposed between photoelectric conversion unit 3 and floating diffuser 2. Transistor 1-1 is a transfer transistor that transfers charge from photoelectric conversion unit 3 to floating diffuser 2. The gate electrode 11-1 of transistor 1-1 is connected to the corresponding signal line 98H. The conduction and non-conduction (on / off) of transistor 1-1 between the drain and source of transistor 1-1 is controlled by a control signal from signal line 98H. When transistor 1-1 is on, charge in photoelectric conversion unit 3 is transferred to floating diffuser 2 through transistor 1-1.

[0070] The floating diffusion 2 accumulates the charge transferred from the photoelectric conversion unit 3 by the transistor 1-1, and generates a voltage signal corresponding to the accumulated charge.

[0071] Transistor 1-2 is connected between floating diffusion 2 and node VDD. Node VDD has, for example, the voltage required to operate transistor 1 (supply voltage). Transistor 1-2 is a reset transistor that discharges charge from floating diffusion 2. The gate electrode 11-2 of transistor 1-2 is connected to the corresponding signal line 98H. The on / off state of transistor 1-2 is controlled by a control signal from signal line 98H. When transistor 1-2 is on, charge in floating diffusion 2 is discharged to node VDD through transistor 1-2.

[0072] Transistor 1-3 is connected between node VDD and transistor 1-4. The gate of transistor 1-3 is connected to floating diffuser 2. Transistor 1-3 can also be referred to as an amplifying transistor that amplifies and outputs the voltage generated by floating diffuser 2.

[0073] Transistor 1-4 is connected between transistor 1-3 and signal line 98V. Transistor 1-4 is a selector transistor that selectively outputs the output voltage of transistor 1-3 to signal line 98V. The gate electrode 11-4 of transistor 1-4 is connected to the corresponding signal line 98H. The on / off state of transistor 1-4 is controlled by a control signal from signal line 98H. When transistor 1-4 is on, the output voltage of transistor 1-3 is output to signal line 98V through transistor 1-4. This voltage signal is used as the pixel signal.

[0074] Figure 3 This is a schematic diagram illustrating a possible structure of a light detection device. Figure 3 A schematic cross-sectional view is shown of a portion of the light detection device 90 as viewed in the Y-axis direction, and more specifically, a portion of the light detection region 91 and a portion of the surrounding region SR.

[0075] The photodetector 90 includes a semiconductor substrate 4, a connection layer 5, and a wiring layer 6. In this example, the semiconductor substrate 4, the connection layer 5, and the wiring layer 6 are positioned in this order along the positive Z-axis.

[0076] Regarding the light detection region 91, the semiconductor substrate 4 includes a photoelectric conversion unit 3. Furthermore, the semiconductor substrate 4 is provided with a transistor 1 and a floating diffuser 2. Note that the surface of the semiconductor substrate 4 located on the positive Z-axis side is marked and shown as surface 4a.

[0077] Transistor 1 is disposed in semiconductor substrate 4. Figure 3 Transistor 1-1 and transistor 1-2 are illustrated. The gate electrode 11-1 of transistor 1-1 and the gate electrode 11-2 of transistor 1-2 are also shown in the figure. When there is no need to distinguish them, they are simply referred to as transistor 1.

[0078] The surface 11a of the gate electrode 11-1 of transistor 1-1 is labeled and shown as surface 11a-1. The surface 11a of the gate electrode 11-2 of transistor 1-2 is labeled and shown as surface 11a-2. When there is no need to specifically distinguish them, they are simply referred to as surface 11a.

[0079] The gate electrode 11 of transistor 1 is embedded in semiconductor substrate 4 in such a way that it includes a surface 11a that is substantially flush with surface 4a of semiconductor substrate 4. In the Z-axis direction, surfaces 2a and 4a are located at substantially the same position (at the same height). For example, even if surfaces 2a and 4a are not perfectly flush and their positions are offset from each other, they can be considered substantially flush as long as the offset falls within the range of manufacturing variations, etc. Furthermore, they can be considered substantially flush as long as the offset is within the range described later to achieve the purpose of this example.

[0080] The floating diffusion 2 is formed from the surface 4a of the semiconductor substrate 4 into the interior of the semiconductor substrate 4. The surface of the floating diffusion 2 on the positive Z-axis direction is labeled as surface 2a. Surface 2a extends in the XY plane direction. Surface 2a of the floating diffusion 2 may also be flush with the surface 4a of the semiconductor substrate 4. In the Z-axis direction, surface 2a and surface 4a are located at the same position.

[0081] The photoelectric conversion unit 3 is formed within the semiconductor substrate 4. Figure 3 In the example shown, the photoelectric conversion unit 3 is formed at a position away from the surface 4a of the semiconductor substrate 4.

[0082] For convenience, the wiring layer 6 and the connection layer 5 will be described in that order. The wiring layer 6 is disposed on the upper side of the semiconductor substrate 4. In this example, the wiring layer 6 is disposed on the opposite side of the semiconductor substrate 4, separated from the connection layer 5. The wiring layer 6 includes wiring for electrically connecting circuit elements such as transistor 1 and floating diffuser 2.

[0083] Among the wirings included in wiring layer 6, the wiring that is electrically connected to the gate electrode 11 of transistor 1 is labeled as wiring 61. Specifically, the wiring 61 that is electrically connected to the gate electrode 11-1 of transistor 1-1 is labeled and shown as wiring 61-1. The wiring 61 that is electrically connected to the gate electrode 11-2 of transistor 1-2 is labeled and shown as wiring 61-2.

[0084] Among the wiring contained in wiring layer 6, the wiring electrically connected to floating diffusion 2 is labeled and shown as wiring 62.

[0085] Note that the portions of wiring layer 6 without wiring 61 and wiring 62 can be made of an insulator.

[0086] A connection layer 5 is disposed between the semiconductor substrate 4 and the wiring layer 6. The connection layer 5 includes vias for electrically connecting components disposed in the semiconductor substrate 4 (such as transistor 1 and floating diffuser 2) to the wiring layer 6.

[0087] Among the vias included in the connection layer 5, the via for connecting the wiring layer 6 and the transistor 1 is labeled as via 51 (first via). Specifically, the via 51 for connecting the wiring 61-1 of the wiring layer 6 and the gate electrode 11-1 of the transistor 1-1 is labeled and shown as via 51-1. The via 51 for connecting the wiring 61-2 of the wiring layer 6 and the gate electrode 11-2 of the transistor 1-2 is labeled and shown as via 51-2. When there is no need to specifically distinguish them, they are simply referred to as via 51.

[0088] Among the vias included in the connection layer 5, the via used to connect the wiring layer 6 and the floating diffuser 2 is labeled and shown as via 52 (second via). Via 52 connects the wiring 62 of the wiring layer 6 to the floating diffuser 2.

[0089] Note that the portion of the connecting layer 5 without vias 51 and 52 can be made of an insulator.

[0090] As described above, the surface 11a of the gate electrode 11 of transistor 1 is substantially flush with the surface 4a of semiconductor substrate 4. Furthermore, the surface 2a of floating diffuser 2 is also flush with the surface 4a of semiconductor substrate 4. Therefore, vias 51 and 52 have substantially the same length (length in the Z-axis direction).

[0091] Regarding the surrounding area SR, a virtual diffusion region D1 is provided on the semiconductor substrate 4. Similar to the photoelectric conversion unit 3 in the photodetector region 91, the virtual diffusion region D1 can be formed in the semiconductor substrate 4. Among the wirings included in the wiring layer 6, the wiring located above the virtual diffusion region D1 is labeled and shown as wiring M.

[0092] According to the photodetector 90 described above, the gate electrode 11 of the transistor 1 is embedded in the transistor 1 in such a way that it includes a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. In this way, compared to, for example, when the gate electrode 11 is disposed on the surface 4a of the semiconductor substrate 4, the increase in parasitic capacitance caused by the gate electrode 11 can be suppressed. The following description also refers to a comparative example.

[0093] Figure 4 This is a diagram showing a comparative example. The light detection device according to the comparative example is labeled and shown as light detection device 90E. In light detection device 90E, corresponding to light detection device 90 ( Figure 3The transistor of transistor 1 is labeled as transistor 1E. Specifically, in the photodetector 90E, the transistors corresponding to transistors 1-1 and 1-2 of the photodetector 90 are labeled as transistor 1E-1 and transistor 1E-2. When there is no need to specifically distinguish them, they are simply referred to as transistor 1E.

[0094] In the photodetector 90E, the gate electrode corresponding to the gate electrode 11 of the transistor 1 of the photodetector 90 is labeled as gate electrode 11E. Specifically, in the photodetector 90E, the gate electrodes corresponding to gate electrodes 11-1 and 11-2 of the photodetector 90 are labeled and shown as gate electrode 11E-1 and gate electrode 11E-2. When there is no need to specifically distinguish them, they are simply referred to as gate electrode 11E.

[0095] The gate electrode 11E of the transistor 1E in the photodetector 90E is disposed on the semiconductor substrate 4 (on surface 4a). The gate electrode 11E is not embedded in the semiconductor substrate 4.

[0096] In the photodetector 90E, the via corresponding to the via 51 of the photodetector 90 is labeled and shown as via 51E. Specifically, the via for connecting the wiring 61-1 of the wiring layer 6 and the gate electrode 11E-1 is labeled and shown as via 51E-1. The via for connecting the wiring 61-2 and the gate electrode 11E-2 is labeled and shown as via 51E-2.

[0097] As from Figure 4 As understood, the length of via 51E in the photodetector 90E is shorter than the length of via 52 by the thickness (length in the Z-axis direction) of the gate electrode 11E.

[0098] Furthermore, in the photodetector 90E, a virtual electrode D2 is provided on the peripheral region SR, or more specifically, on the virtual diffusion region D1 in this example. The virtual electrode D2 is provided to suppress any step that may occur between the photodetector region 91, where the gate electrode 11E is densely arranged, and the peripheral region SR, where the gate electrode 11E is not densely arranged, due to the gate electrode 11E.

[0099] In the photodetector 90E, unintended parasitic capacitances are generated due to the gate electrode 11E and the dummy electrode D2. Some of these parasitic capacitances are schematically shown as parasitic capacitance Cp using dashed lines. Specifically, because the side of the gate electrode 11E is opposite to the via 52, a parasitic capacitance Cp is generated between the gate electrode 11E and the via 52. Furthermore, because the dummy electrode D2 is opposite to the wiring M, a parasitic capacitance Cp is generated between the dummy electrode D2 and the wiring M. Due to the parasitic capacitance Cp, problems such as noise become apparent. For example, the capacitance of the floating diffuser 2 increases due to the parasitic capacitance Cp generated between the gate electrode 11E and the via 52, resulting in noise degradation.

[0100] Furthermore, in the photodetector 90E, as the structure becomes increasingly miniaturized, the increase in parasitic capacitance Cp becomes significant. For example, reducing the distance between the gate electrode 11E and the via 52 increases the parasitic capacitance Cp generated there. Additionally, reducing the thickness of the interconnect layer 5 to decrease the distance between the dummy electrode D2 and the wiring M also increases the parasitic capacitance Cp generated there. Therefore, miniaturization is difficult to achieve with the structure of the photodetector 90E.

[0101] On the other hand, in the light detection device 90 according to this embodiment ( Figure 3 The gate electrode 11 is embedded in the semiconductor substrate 4, and therefore the side surface of the gate electrode 11 does not face the via 52. Thus, the increase in parasitic capacitance generated between the gate electrode 11 and the via 52 can be suppressed. Furthermore, since there is no dummy electrode D2 in the peripheral region SR, the increase in parasitic capacitance that may occur between the dummy electrode D2 and the wiring M can be suppressed. For example, noise degradation associated with the increase in parasitic capacitance can be suppressed.

[0102] By suppressing the increase of parasitic capacitance, the possibility of structural miniaturization can be improved. For example, the distance between the gate electrode 11 and the via 51 can be reduced. In addition, the thickness (height) of the interconnect layer 5 can be reduced.

[0103] Furthermore, in the optical detection apparatus 90E, vias 51E and 52 with different lengths (different types) need to be formed, and therefore, the manufacturing process becomes complex due to the increase in the number of manufacturing steps, etc. In the optical detection apparatus 90 according to this embodiment ( Figure 3 Vias 51 and via 52 have substantially the same length. Vias 51 and via 52 can be formed simultaneously (in combination) through the same manufacturing process. Therefore, compared with the photodetector 90E, the manufacturing process for forming vias can be simplified and costs can be reduced.

[0104] As described above, even if the surface 11a of the gate electrode 11 of transistor 1 is not completely flush with the surface 4a of semiconductor substrate 4, they can be considered substantially flush as long as the offset falls within the range that allows the purpose of this example to be achieved. This will also be referenced below. Figure 5 describe.

[0105] Figure 5 This is a diagram showing an example of a substantially flush construction. Figure 5 In the example shown, the surface 11a of the gate electrode 11 of transistor 1 is located slightly above the surface 4a of semiconductor substrate 4 (on the positive Z-axis side). The length of the portion of the gate electrode 11 that protrudes upward from the surface 4a of semiconductor substrate 4 is denoted as the offset ΔZ.

[0106] A parasitic capacitance of displacement ΔZ may occur between the gate electrode 11 and the via 52, but when the displacement ΔZ is small, the parasitic capacitance is also small enough. Furthermore, when the step size caused by the displacement ΔZ is small, there is no need to set up a dummy electrode D2. Even with the presence of the offset Z, the purpose of this example can be achieved, so it can be said that the surface 11a of the gate electrode 11 is substantially flush with the surface 4a of the semiconductor substrate 4.

[0107] Furthermore, the length of via 51 is greater than the length of via 52 ( Figure 3 The amount of short offset ΔZ. It should be noted that the purpose of this embodiment is achieved when vias 51 and 52 are formed simultaneously through the same manufacturing process by adapting the displacement amount ΔZ. In this case, it can also be said that the surface 11a of the gate electrode 11 is substantially flush with the surface 4a of the semiconductor substrate 4.

[0108] 2. Variations

[0109] 2.1 First Variation Example

[0110] In this embodiment, the elements of the pixel circuit can be disposed across multiple semiconductor substrates. See below. Figures 6 to 8 This will be described.

[0111] Figure 6 This is a diagram illustrating an example of a pixel circuit. The components of the pixel circuit are respectively disposed on two semiconductor substrates 4. The first semiconductor substrate is labeled and shown as semiconductor substrate 4-1. The second semiconductor substrate is labeled and shown as semiconductor substrate 4-2.

[0112] In this example, photoelectric conversion unit 3, transistor 1-1, and floating diffuser 2 are disposed in semiconductor substrate 4-1. Transistors 1-2, 1-3, and 1-4 are disposed in semiconductor substrate 4-2. Transistor 1-1 can also be referred to as the first transistor disposed in the first semiconductor substrate. Transistors 1-2, 1-3, and 1-4 can also be referred to as the second transistor disposed in the second semiconductor substrate.

[0113] By providing transistors 1-2, 1-3, and 1-4 in the semiconductor substrate 4-2, the number of transistors 1 provided in the semiconductor substrate 4-1 can be reduced. Therefore, for example, the area used for the photoelectric conversion unit 3 can be guaranteed, and the detection performance (sensitivity, etc.) of the photodetector 90 can be improved. Furthermore, for example, transistor 1-1 can be easily formed in the semiconductor substrate 4-1.

[0114] Figure 7 and Figure 8 This is a schematic diagram illustrating an example of the structure of a light detection device. The light detection device 90 includes a semiconductor substrate 4-1, a connection layer 5-1, a semiconductor substrate 4-2, a connection layer 5-2, and a wiring layer 6. In this example, the semiconductor substrate 4-1, the connection layer 5-1, the semiconductor substrate 4-2, the connection layer 5-2, and the wiring layer 6 are arranged sequentially in the positive Z-axis direction.

[0115] Semiconductor substrate 4-2 is disposed above semiconductor substrate 4-1. In this example, semiconductor substrate 4-2 is disposed on the connection layer 5-1 on the opposite side of semiconductor substrate 4-1, separated by connection layer 5-1. The surface of semiconductor substrate 4-1 on the positive Z-axis side is marked and shown as surface 4a-1. The surface of semiconductor substrate 4-2 on the positive Z-axis side is marked and shown as surface 4a-2.

[0116] With the above-mentioned semiconductor substrate 4 ( Figure 3 Similar to the semiconductor substrate 4-2, the semiconductor substrate 4-1 includes a photoelectric conversion unit 3. Furthermore, the semiconductor substrate 4 is provided with a floating diffuser 2 and a transistor 1-1. The transistor 1-2 is disposed in the semiconductor substrate 4-2, but not in the semiconductor substrate 4-1. Although in Figure 7 and Figure 8 Although not shown in the figure, transistors 1-3 and 1-4 are also disposed in the semiconductor substrate 4-2.

[0117] Figure 7 The drain and source of transistor 1-2 are also shown. The drain and source of transistor 1-2 are labeled and shown as drain 12-2 and source 13-2.

[0118] A connection layer 5-1 is disposed between semiconductor substrate 4-1 and semiconductor substrate 4-2. A connection layer 5-2 is disposed between semiconductor substrate 4-2 and wiring layer 6. A via 51-1 passes through connection layer 5-2, semiconductor substrate 4-2, and connection layer 5-1, and electrically connects wiring 61-1 of wiring layer 6 to the gate electrode 11-1 of transistor 1-1. A via 52 passes through connection layer 5-2, semiconductor substrate 4-2, and connection layer 5-1, and electrically connects wiring 62 of wiring layer 6 to floating diffusion 2. Wiring 61-2 passes through connection layer 5-2, and links wiring 61-2 of wiring layer 6 to the gate electrode 11-2 of transistor 1-2.

[0119] The gate electrode 11-1 of transistor 1-1 is embedded in semiconductor substrate 4-1 in such a way that it includes a surface 11a-1 that is substantially flush with the surface 4a-1 of semiconductor substrate 4-1. In the peripheral region SR, semiconductor substrate 4-1 has a virtual diffusion region D1-1, but no virtual electrode.

[0120] Transistor 1-2 may be disposed on surface 4a-2 of semiconductor substrate 4-2 or embedded in semiconductor substrate 4-2.

[0121] exist Figure 7 In the example shown, the gate electrode 11-2 of transistor 1-2 is disposed on the surface 4a-2 of semiconductor substrate 4-2. In the peripheral region SR, a dummy diffusion region D1-2 is disposed in semiconductor substrate 4-2, and a dummy electrode D2 is disposed on the surface 4a-2 of semiconductor substrate 4-2. For example, the dummy electrode D2 is configured to suppress steps that may occur between the photodetector region 91 where the gate electrode 11-2 is densely disposed and the peripheral region SR where the gate electrode 11-2 is not densely disposed.

[0122] exist Figure 8 In the example shown, the gate electrode 11-2 of transistor 1-2 is embedded in semiconductor substrate 4-2 in such a way that it includes a surface 11a-2 that is substantially flush with surface 4a of semiconductor substrate 4-2. No dummy electrode is present in the peripheral region SR.

[0123] use Figure 7 and Figure 8The above-described structure shown can suppress the increase of parasitic capacitance that may occur between the gate electrode 11 and the wiring 62. Specifically, with the construction using two semiconductor substrates (i.e., semiconductor substrate 4-1 and semiconductor substrate 4-2), the via 52 has a larger length and is prone to parasitic capacitance; however, in the above-described structure, by embedding the gate electrode 11-1 in the semiconductor substrate 4-1, the thickness (height) of the interconnect layer 5-1 can be reduced, and the length of the via 51 can be suppressed. Thus, the increase of parasitic capacitance can be suppressed, and in turn, the noise degradation caused by the increase in capacitance of the floating diffusion 2 can be suppressed.

[0124] Furthermore, since vias 51-1 and 52 have substantially the same length, they can be formed together. Additionally, in Figure 8 In the configuration shown, the increase in parasitic capacitance that may occur between the gate electrode 11-2 and the via 52 can be suppressed. Furthermore, since there is no dummy electrode D2 in the peripheral region SR, the increase in parasitic capacitance that may occur between the dummy electrode D2 and the wiring M can be suppressed.

[0125] Furthermore, in transistor 1, transistors other than transistor 1-1 (such as transistor 1-2, transistor 1-3, and transistor 1-4) are disposed in semiconductor substrate 4-2. Only transistor 1-1 is disposed in semiconductor substrate 4-1. Because there are no transistors 1 other than transistor 1-1 in semiconductor substrate 4-1, it is easy to embed the gate electrode 11-1 of transistor 1-1 in semiconductor substrate 4-1.

[0126] For example, the aforementioned photodetector 90, comprising two semiconductor substrates (i.e., semiconductor substrate 4-1 and semiconductor substrate 4-2), can be obtained by bonding semiconductor substrate 4-1 and semiconductor substrate 4-2 via the connecting layer 5-1. The gate electrode 11-2 of transistor 1-2 may be provided in semiconductor substrate 4-2 after or before bonding semiconductor substrate 4-1 and semiconductor substrate 4-2.

[0127] For example, using Figure 8 The illustrated configuration offers the following advantages by forming the gate electrode 11-2 of the transistor 1-2 in the semiconductor substrate 4-2 after bonding the semiconductor substrate 4-1 and the semiconductor substrate 4-2. Specifically, for example, when the gate electrode 11-2 is formed after bonding, miniaturization may be difficult to achieve because the planarization of the semiconductor substrate 4-2 after bonding may affect the formation of the gate electrode 11-2. Conversely, in... Figure 8In the illustrated configuration, because the semiconductor substrate 4-2 remains planar even after the gate electrode 11-2 is formed, the semiconductor substrates 4-1 and 4-2 can be bonded together without planarization after the gate electrode 11-2 has been pre-formed. Since there is no effect of planarization on the formation of the gate electrode 11-2, this offers advantages in miniaturization.

[0128] 2.2 Second variation

[0129] In this embodiment, a portion of the gate electrode 11 of transistor 1 is located on the element separation unit, and via 51 can be connected to this portion. This will be referred to below. Figure 9 Describe it.

[0130] Figure 9 This is a schematic diagram illustrating a possible structure of a light detection device. Note that, unlike the diagrams shown so far, the cross-sectional view shown in the accompanying drawing is a view taken along the X-axis.

[0131] The semiconductor substrate 4 has a component separation unit 7. In this example, the component separation unit 7 is an oxide film (STI (shallow trench isolation)) disposed near the surface 4a of the semiconductor substrate 4.

[0132] The gate electrode 11 of transistor 1 includes a central portion 111 and an end portion 112. The central portion 111 is the portion located at the center of the gate electrode 11 in the XY plane direction. The end portion 112 is the portion located at the end of the gate electrode 11 in the XY plane direction.

[0133] Regarding the central portion 111 and the end portion 112 of the gate electrode 11, the end portion 112 is located on the element separation unit 7. A via 51 is connected to the end portion 112 of the gate electrode 11.

[0134] For example, if the via 51 is connected to the central portion 111 of the gate electrode 11, and the thickness (length in the Z-axis direction) of the gate electrode 11 is small, it may be difficult to form the via 51 due to damage to the underside that occurs during its formation. This damage can be suppressed by connecting the via 51 to the end 112 located on the element separation unit 7, rather than to the central portion 111 of the gate electrode 11. Therefore, the via 51 can be formed more easily.

[0135] 2.3 Third variation

[0136] In one embodiment, the gate electrode 11 of transistor 1 may include a downwardly extending extension. This will be referred to below. Figures 10 to 13 Describe it.

[0137] Figures 10 to 13This is a schematic diagram illustrating a possible structure of a light detection device. Figures 10 to 12 A cross-sectional view schematically depicting a portion of a light detection device 90 as viewed in the X-axis direction is shown. Figure 13 Schematic illustration along Figure 12 A cross-sectional view taken along line XIII-XIII (as viewed in the Z-axis direction). Note that... Figure 12 Schematic illustration along Figure 13 The cross-sectional view taken from line XII-XII.

[0138] The gate electrode 11 of transistor 1 includes a surface portion 113 and an extension portion 114. The extension portion 114 includes the surface 11a of the gate electrode 11. The extension portion 114 extends from the surface portion 113 toward the interior of the semiconductor substrate 4 (in the negative Z-axis direction).

[0139] Via 51 can be connected to the surface portion 113 of the gate electrode 11 on the side opposite to the extension portion 114, across the surface portion 113. Due to the presence of the extension portion 114, the thickness of the portion of the gate electrode 11 connected to the via 51 is increased, and thus the effects of damage that may occur during the formation of the via 51 can be suppressed.

[0140] Furthermore, since the via 51 can be made closer to the center of the surface portion 113 of the gate electrode 11, the width of the surface portion 113 (in this example, the length in the Y-axis direction) can be reduced. Specifically, when viewed in the Z-axis direction, the area occupied by the gate electrode 11, the via 51, and the wiring 61 can be reduced (shrunken).

[0141] exist Figure 10 In the example shown, the surface portion 113 includes the aforementioned central portion 111 and end portion 112. An extension 114 extends downward from the central portion 111 of the surface portion 113. The width (length in the XY plane direction) of the extension 114 is smaller than the overall width of the central portion 111 and the end portion 112. The gate electrode 11 is generally T-shaped. Therefore, a more miniaturized structure is obtained than that shown virtually by dashed lines.

[0142] exist Figure 11 In the example shown, the surface portion 113 of the gate electrode 11 of transistor 1 includes a central portion 111, but does not include the end portion 112. Figure 10 Since the end 112 is absent, further miniaturization is possible.

[0143] exist Figure 12 and Figure 13In the example shown, the gate electrode 11 of transistor 1 is disposed such that it covers the upper and side surfaces of the channel region in semiconductor substrate 4. This increases the channel width per unit area. The gate electrode 11 of transistor 1 includes a surface portion 113 and a pair of extension portions 114. The pair of spaced-apart extension portions 114 extend downward from the surface portion 113. The gate electrode 11 is generally U-shaped. Similarly, in this case, as... Figure 12 As shown, a smaller structure is obtained than the structure virtually shown with dashed lines.

[0144] 2.4 Application Examples

[0145] The following will be referred to Figures 14 to 17 Describe some application examples of the above construction.

[0146] Figures 14 to 17 This is a schematic diagram illustrating a possible structure of a light detection device.

[0147] Figure 14 and Figure 15 The example shown is based on Figure 7 and Figure 8 The above-described structure is modified so that the gate electrode 11-1 of transistor 1-1 has a T-shape. The gate electrode 11-1 includes a surface portion 113-1 and an extension portion 114-1. The surface portion 113-1 includes a central portion 111-1 and an end portion 112-1. These are consistent with the above-referenced... Figure 10 The surface portion 113, extension portion 114, central portion 111, and end portion 112 are the same as described, so they will not be described again. The via 51-1 is connected to the central portion 111-1 of the surface portion 113-1 of the gate electrode 11-1.

[0148] exist Figure 16 In the example shown, in transistors 1-1 and 1-2 disposed on semiconductor substrate 4, the gate electrode 11-1 of transistor 1-1 is T-shaped.

[0149] exist Figure 17 In the example shown, the gate electrode 11-1 of transistor 1-1 and the gate electrode 11-2 of transistor 1-2 each have a downwardly extending shape. Specifically, the gate electrode 11-1 of transistor 1-1 includes a surface portion 113-1 and an extension portion 114-1. The gate electrode 11-2 of transistor 1-2 includes a surface portion 113-2 and an extension portion 114-2. The surface portion 113-2 and the extension portion 114-2 are the same as those referenced above. Figure 10 The surface portion 113 and the extension portion 114 are the same as described, so they will not be described again.

[0150] 3. Examples of manufacturing methods

[0151] Figures 18 to 26These are diagrams illustrating an example of a manufacturing method for a light detection device. Figure (A) schematically shows a cross-sectional view along the Y-axis. Figure (B) schematically shows a cross-sectional view along the X-axis.

[0152] Figures 18 to 22 The following describes some manufacturing steps for obtaining a gate electrode 11, which includes the gate electrode located as described above. Figure 9 End 112 on the component separation unit 7 in the middle.

[0153] like Figure 18 As shown, prepare semiconductor substrate 4. Figure 19 As shown, component separation units 7 are formed inside the semiconductor substrate 4. For example, STI technology is used as described above. Figure 20 As shown, photoresist PR is applied to a semiconductor substrate 4. The photoresist PR is patterned to cover the portion of the semiconductor substrate 4 except for the portion where the gate electrode 11 is embedded. A recess 4r corresponding to the gate electrode 11 is obtained by etching a portion of the semiconductor substrate 4 and the device separation unit 7. The photoresist PR is removed by ashing or the like, and the material for the gate electrode 11 is deposited. For example, polysilicon is deposited and planarized by CMP or the like. Figure 21 As shown, a gate electrode 11 is obtained by embedding it in the semiconductor substrate 4 in such a manner that it includes a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. Figure 22 As shown, the drain 12 and source 13 of transistor 1 are formed using photoresist PR. Thus, transistor 1 including gate electrode 11, drain 12 and source 13 is obtained.

[0154] Figures 23 to 26 The diagram illustrates some manufacturing steps for obtaining the gate electrode 11, which includes the above-described... Figure 12 A pair of surface portions 113. Assuming the above... Figure 18 and Figure 19 The manufacturing process shown has been completed.

[0155] like Figure 23 As shown, photoresist PR is disposed on semiconductor substrate 4. The photoresist PR is patterned to obtain the surface portion 113 of the gate electrode 11 in semiconductor substrate 4. A recess 4r corresponding to the surface portion 113 of the gate electrode 11 is obtained by etching a portion of semiconductor substrate 4 and device separation unit 7. (See diagram) Figure 24 As shown, a photoresist PR is applied. The photoresist PR is patterned to obtain a pair of extensions 114 of the gate electrode 11. Recesses 4r corresponding to the pair of extensions 114 of the gate electrode 11 are obtained by etching a portion of the semiconductor substrate 4 and the device separation unit 7. The photoresist PR is removed, and the material of the gate electrode 11 is deposited and planarized. Figure 25As shown, a gate electrode 11 is obtained, which is embedded in the semiconductor substrate 4 in such a manner as to include a surface 11a that is substantially flush with the surface 4a of the semiconductor substrate 4. The gate electrode 11 includes a surface portion 113 and a pair of extensions 114. Figure 26 As shown, the drain 12 and source 13 of the gate electrode 11 are formed using photoresist PR. Thus, a transistor 1 including the gate electrode 11, drain 12, and source 13 is obtained.

[0156] 4. Examples of pixel circuit commonality

[0157] In this embodiment, the pixel circuitry can be shared among multiple pixels 92. Reference will be made below. Figure 27 This will be described.

[0158] Figure 27 This is a diagram illustrating an example of pixel circuitry sharing. Figure 27 In the example shown, four transistors 1-1 are configured corresponding to the four pixels 92. Alternatively, for the four pixels 92, a floating diffuser 2, a transistor 1-2, a transistor 1-3, and a transistor 1-4 are configured. The photoelectric conversion unit 3 of each pixel 92 is connected to the same floating diffuser 2 via the corresponding transistor 1-1. The four pixels 92 share the floating diffuser 2, transistor 1-2, transistor 1-3, and transistor 1-4.

[0159] 5. Summary

[0160] For example, the aforementioned technical specifications are as follows. One of the disclosed technologies is a light detection device 90. (Refer to the above...) Figures 1 to 3 and Figures 5 to 17 As described above, the light detection device 90 (e.g., a solid-state imaging device) includes: a semiconductor substrate 4 including a photoelectric conversion unit 3, a floating diffusion 2 formed from the surface 4a of the semiconductor substrate 4 into the interior of the semiconductor substrate 4, and a transistor 1 disposed in the semiconductor substrate 4. The transistor 1 includes a gate electrode 11 embedded in the semiconductor substrate 4 in such a manner as to include a surface 11a substantially flush with the surface 4a of the semiconductor substrate 4. Using the light detection device 90 including such a gate electrode 11, as previously described, the increase in parasitic capacitance caused by the gate electrode 11 can be suppressed.

[0161] As referenced above Figure 2 and Figure 3As described above, transistor 1 may include a transfer transistor (transistor 1-1) that transfers charge from photoelectric conversion unit 3 to floating diffusion 2. By embedding the gate electrode 11 of transistor 1 (gate electrode 11-1 of transistor 1-1) into semiconductor substrate 4, the increase of parasitic capacitance can be suppressed. Transistor 1, arranged in the same manner, may also include a reset transistor (transistor 1-2) that discharges charge from floating diffusion 2; an amplifying transistor (transistor 1-3) that amplifies and outputs the voltage generated by floating diffusion 2; a selection transistor (transistor 1-4) that selectively outputs the output voltage of the amplifying transistor to signal line 98V; and so on.

[0162] See above. Figure 3 As described above, the photodetector 90 may include a wiring layer 6 disposed on the upper side (positive Z-axis side) of the semiconductor substrate 4, a via 51 (first via) connecting the wiring layer 6 and the gate electrode 11, and a via 52 (second via) connecting the wiring layer 6 and the floating diffuser 2, and the vias 51 and 52 may have substantially the same length. Thus, the vias 51 and 52 can be formed simultaneously through the same manufacturing process. This simplifies the manufacturing process for via formation, thereby reducing costs.

[0163] As per the above reference Figure 9 As described above, the semiconductor substrate 4 may include a component separation unit 7, the gate electrode 11 may include an end portion 112 located on the component separation unit, and the via 51 may be connected to the end portion 112. In this way, the effects of damage that may occur during the formation of the via 51 can be suppressed.

[0164] As referenced above Figures 10 to 12 As described above, the gate electrode 11 may include a surface portion 113 and an extension portion 114. The surface portion 113 includes the surface 11a of the gate electrode 11, and the extension portion 114 extends from the surface portion 113 toward the interior of the semiconductor substrate 4. A via 51 may be connected to the surface portion 113 on the side opposite to the extension portion 114, across the surface portion 113. Similarly, in this case, the effects of damage that may occur during the formation of the via 51 can be suppressed.

[0165] As referenced above Figure 12 and Figure 13 As described above, the extension 114 may be a pair of extensions 114 spaced apart from each other and extending from the surface portion 113 toward the interior of the semiconductor substrate 4. By using the gate electrode 11 including the surface portion 113 and the extension portion 114, the channel width per unit area can be increased.

[0166] As referenced above Figure 7 and Figure 8As described above, the photodetector 90 may include a semiconductor substrate 4-2 (second semiconductor substrate) disposed on the upper side of the semiconductor substrate 4 and transistors 1-2 (second transistors) disposed in the semiconductor substrate 4-2. In this way, the various transistors 1 included in the photodetector 90 may be disposed in the two semiconductor substrates, namely semiconductor substrate 4-1 (first semiconductor substrate) and semiconductor substrate 4-2. For example, since the number of transistors 1 disposed in semiconductor substrate 4-1 can be reduced, the area used for photoelectric conversion unit 3 can be ensured, and the detection performance (sensitivity, etc.) of the photodetector 90 can be improved.

[0167] As per the above reference Figure 7 As described above, transistor 1-2 may include a gate electrode 11-2 disposed on the surface 4a-2 of semiconductor substrate 4-2. Even with this configuration, since the gate electrode 11-1 of transistor 1-1 disposed in semiconductor substrate 4-1 (first semiconductor substrate) is embedded in semiconductor substrate 4-1, the increase in parasitic capacitance due to gate electrode 11-1 can be suppressed. Furthermore, photodetector 90 may include a dummy electrode D2 disposed on the surface 4a-2 of semiconductor substrate 4-2. For example, this suppresses the steps that may occur between the photodetector region 91 where gate electrodes 11-2 are densely disposed and the peripheral region SR where gate electrodes 11-2 are not densely disposed due to gate electrodes 11-2.

[0168] As referenced above Figure 8 As described above, transistor 1-2 may include a gate electrode 11-2 embedded in semiconductor substrate 4-2 in such a manner as to include a surface 11a-2 that is substantially flush with surface 4a-2 of semiconductor substrate 4-2. In this way, the increase of parasitic capacitance due to gate electrode 11-2 can be suppressed.

[0169] See above. Figure 2 , Figure 7 , Figure 8 As described above, the transistor 1-1 disposed in the semiconductor substrate 4-1 can be a transfer transistor that transfers charge in the photoelectric conversion unit 3 to the floating diffusion 2, and the transistor 1-2 disposed in the semiconductor substrate 4-2 can be a reset transistor that discharges charge in the floating diffusion 2. For example, such transfer transistors and reset transistors can be disposed separately in the semiconductor substrate 4-1 and the semiconductor substrate 4-2.

[0170] 6. Examples of applications of moving bodies

[0171] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body (such as vehicles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, aircraft, drones, ships, and robots).

[0172] Figure 28 This is a block diagram illustrating a schematic construction example of a vehicle control system, which serves as an example of a mobile body control system to which the technology according to embodiments of this disclosure can be applied.

[0173] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 28 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0174] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 acts as a control device to control: drive force generating equipment for generating the vehicle's driving force, such as an internal combustion engine or drive motor; drive force transmission mechanism for transmitting the driving force to the wheels; steering mechanism for adjusting the vehicle's steering angle; and braking equipment for generating the vehicle's braking force.

[0175] The body system control unit 12020 controls the operation of various types of equipment installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device to control the following: keyless entry system, smart key system, power window devices, or various lights such as headlights, reversing lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from mobile devices that replace the key as input. The body system control unit 12020 receives these input radio waves or signals to control the vehicle's door locking devices, power window devices, lights, etc.

[0176] The exterior information detection unit 12030 detects external information of the vehicle equipped with the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to an imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to image an image of the exterior of the vehicle and receives the image. Based on the received image, the exterior information detection unit 12030 can perform processing for detecting objects (such as people, vehicles, obstacles, signs, symbols, etc. on the road) or processing for the distance of the detected objects.

[0177] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0178] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 can be connected to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 may include, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or the driver's level of concentration, or it can determine whether the driver is dozing off.

[0179] The microcomputer 12051 can calculate control target values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control to realize functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation for the vehicle, distance-based following, speed-maintaining driving, vehicle collision warning, lane departure warning, etc.

[0180] Furthermore, the microcomputer 12051 can control the drive force generation device, steering mechanism, and braking device based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing coordinated control intended for automatic driving that does not depend on the driver's operation.

[0181] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights from high beam to low beam based on the position of the vehicle ahead or oncoming vehicle detected by the external information detection unit 12030, thereby performing coordinated control aimed at preventing glare by controlling the headlights.

[0182] The sound / image output unit 12052 transmits at least one of sound and image output signals to an output device capable of visually or audibly notifying passengers of the vehicle or the outside of the vehicle. Figure 28 In the example, audio speaker 12061, display unit 12062, and instrument panel 12063 are shown as output devices. Display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0183] Figure 29 This is a diagram showing an example of the mounting position of the imaging unit 12031.

[0184] exist Figure 29 In the imaging unit 12031, there are imaging units 12101, 12102, 12103, 12104 and 12105.

[0185] Imaging units 12101, 12102, 12103, 12104, and 12105 can be arranged at the front nose, side mirrors, rear bumper, rear door, and upper part of the windshield inside the vehicle 12100. Imaging unit 12101 at the front nose and imaging unit 12105 at the upper part of the windshield inside the vehicle primarily acquire images of the front of the vehicle 12100. Imaging units 12102 and 12103 at the side mirrors primarily acquire images of the sides of the vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of the rear of the vehicle 12100. Imaging unit 12105 at the upper part of the windshield inside the vehicle is mainly used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0186] Incidentally, Figure 29Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located on the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located on the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above can be obtained.

[0187] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0188] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111-12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101-12104, and thereby extract the nearest three-dimensional object as the vehicle ahead, which specifically exists on the driving path of the vehicle 12100 and is traveling in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset the following distance to be maintained from the vehicle ahead and execute automatic braking control (including following stop control), automatic acceleration control (including following start control), etc. Therefore, it is possible to perform cooperative control intended for automatic driving and the like, independent of driver operation.

[0189] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101-12104, and extract the classified three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 can distinguish whether obstacles around vehicle 12100 are obstacles that the driver of vehicle 12100 can visually recognize, or obstacles that are difficult for the driver of vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is a possibility of collision, the microcomputer 12051 outputs an alarm to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collision.

[0190] At least one of the imaging units 12101-12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units 12101-12104. This pedestrian identification is performed, for example, by a program that extracts characteristic points from the image captured by the imaging units 12101-12104, which are infrared cameras, and a program that determines whether it is a pedestrian by performing pattern matching processing on a series of characteristic points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101-12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian to emphasize the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0191] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. The technology according to this disclosure can be applied to the imaging unit 12031, etc., in the above configuration. Specifically, the light detection device 90 according to this embodiment can be used as the imaging unit 12031. By applying the technology according to this disclosure, the performance of the imaging unit 12031 can be improved, and its size can be reduced. For example, a captured image with better visibility can be obtained, which in turn increases the likelihood of reducing driver fatigue.

[0192] Note that the effects described in this disclosure are merely examples and are not limited to the disclosed content. Other effects may be achieved.

[0193] Embodiments of this disclosure have been described above. However, the technical scope of this disclosure is not limited to the above embodiments, and various modifications can be made without departing from the spirit of this disclosure. The constituent elements in different examples and variations may be combined as appropriate.

[0194] It should be noted that this technology can also be configured as follows.

[0195] (1) A light detection device, comprising: Semiconductor substrate, including photoelectric conversion unit; Floating diffusion, formed from the surface of the semiconductor substrate into the interior of the semiconductor substrate; and Transistors are disposed in a semiconductor substrate, wherein... The transistor includes a gate electrode embedded in the semiconductor substrate in such a way that it includes a surface substantially flush with the surface of the semiconductor substrate.

[0196] (2) The photodetector according to (1), wherein the transistor includes a transfer transistor configured to transfer charge in the photoelectric conversion unit to floating diffusion.

[0197] (3) The light detection device according to (2), wherein the transistor includes at least one of the following: The reset transistor is configured to discharge charge in the floating diffusion; An amplifying transistor is configured to amplify and output the voltage generated by the floating diffusion; and The selector transistor is configured to selectively output the output voltage of the amplifying transistor to the signal line.

[0198] (4) The light detection device according to any one of (1) to (3) further includes: Wiring layer, disposed on the upper side of semiconductor substrate; The first via is configured to connect the wiring layer and the gate electrode; and The second via is configured to connect the routing layer and the floating diffuser, wherein... The first via and the second via have substantially the same length.

[0199] (5) The optical detection device according to (4), wherein, The semiconductor substrate includes component separation units. The gate electrode includes an end located on the element separation unit, and The first via is connected to the end.

[0200] (6) The optical detection device according to (4), wherein, The gate electrode includes: Surface portion, including the surface of the gate electrode, and The extension extends from the surface portion toward the interior of the semiconductor substrate, and The first via is connected to the surface portion on the side opposite to the extension, wherein the surface portion is sandwiched between the first via and the extension.

[0201] (7) The light detection device according to (6), wherein the extension is a pair of extensions, the pair of extensions being spaced apart from each other and extending from the surface portion toward the interior of the semiconductor substrate.

[0202] (8) The light detection device according to any one of (1) to (7) further includes: A second semiconductor substrate is disposed on the upper side of the semiconductor substrate; and The second transistor is disposed in the second semiconductor substrate.

[0203] (9) The light detection device according to (8), wherein the second transistor includes a gate electrode disposed on the surface of the second semiconductor substrate.

[0204] (10) The light detection device according to (8) or (9), wherein the light detection device includes a virtual electrode disposed on the surface of the second semiconductor substrate.

[0205] (11) The photodetector according to (8), wherein the second transistor includes a gate electrode embedded in the second semiconductor substrate in such a manner as to include a surface substantially flush with the surface of the second semiconductor substrate.

[0206] (12) A light detection device according to any one of (8) to (11), wherein, The transistor includes a transfer transistor configured to transfer charge in the photoelectric conversion unit to a floating diffuser, and The second transistor includes a reset transistor configured to discharge charge in the floating diffusion.

[0207] (13) The light detection device according to any one of (1) to (12), wherein the light detection device is a solid-state imaging device.

[0208] Reference number list

[0209] 1 transistor

[0210] 11 Gate electrode

[0211] 111 Central Department

[0212] 112 end

[0213] 113 Surface part

[0214] 114 Extension

[0215] 11a Surface

[0216] 12 Drain

[0217] 13 Source

[0218] 2. Floating diffusion

[0219] 3 Photoelectric conversion unit

[0220] 4. Semiconductor substrate

[0221] 4-1 Semiconductor substrate

[0222] 4-2 Semiconductor substrate

[0223] 4a surface

[0224] 4r recess

[0225] 5. Connection Layer

[0226] 51 Via

[0227] 52 vias

[0228] 6 Wiring Layer

[0229] 61 Wiring

[0230] 62 Wiring

[0231] 7 Component Separation Unit

[0232] 90 Optical Detection Device

[0233] 91 Light Detection Area

[0234] 92 pixels

[0235] 93 Control Circuit

[0236] 94 Vertical Drive Circuit

[0237] 95-column signal processing circuits

[0238] 96 Horizontal Drive Circuit

[0239] 97 Output Circuit

[0240] 98H signal line

[0241] 98V signal cable

[0242] 99 signal lines

[0243] D1 Virtual Diffusion Region

[0244] D1-1 Virtual Diffusion Region

[0245] D1-2 Virtual Diffusion Region

[0246] D2 Virtual Electrode

[0247] M wiring

[0248] PR photoresist

[0249] The area surrounding SR.

Claims

1. A light detection device, comprising: Semiconductor substrate, including photoelectric conversion unit; Floating diffusion occurs from the surface of the semiconductor substrate into the interior of the semiconductor substrate. as well as A transistor is disposed in the semiconductor substrate, wherein, The transistor includes a gate electrode embedded in the semiconductor substrate in such a manner that it includes a surface substantially flush with the surface of the semiconductor substrate.

2. The light detecting device according to claim 1, wherein The transistor includes a transfer transistor configured to transfer charge in the photoelectric conversion unit to the floating diffuser.

3. The light detecting device according to claim 2, wherein The transistor includes at least one of the following: A reset transistor is configured to discharge the charge in the floating diffusion; An amplifying transistor is configured to amplify and output the voltage generated by the floating diffusion; as well as The selector transistor is configured to selectively output the output voltage of the amplifying transistor to the signal line.

4. The optical detection device according to claim 1, further comprising: A wiring layer is disposed on the upper side of the semiconductor substrate; A first via is configured to connect the wiring layer to the gate electrode; as well as A second via is configured to connect the wiring layer and the floating diffuser, wherein... The first via and the second via have substantially the same length.

5. The optical detection device according to claim 4, wherein, The semiconductor substrate includes a component separation unit. The gate electrode includes an end located on the element separation unit, and The first via is connected to the end.

6. The optical detection device according to claim 4, wherein, The gate electrode includes: The surface portion includes the surface of the gate electrode, and The extension extends from the surface portion toward the interior of the semiconductor substrate, and The first through hole is connected to the surface portion on the side opposite to the extension, wherein the surface portion is sandwiched between the first through hole and the extension.

7. The light detecting device according to claim 6, wherein The extension is a pair of extensions, which are spaced apart from each other and extend from the surface portion toward the interior of the semiconductor substrate.

8. The optical detection device according to claim 1, further comprising: A second semiconductor substrate is disposed on the upper side of the semiconductor substrate; as well as The second transistor is disposed in the second semiconductor substrate.

9. The light detecting device of claim 8, wherein, The second transistor includes a gate electrode disposed on the surface of the second semiconductor substrate.

10. The optical detection device according to claim 8, wherein, The photodetector includes a virtual electrode disposed on the surface of the second semiconductor substrate.

11. The light detecting device of claim 8, wherein, The second transistor includes a gate electrode, which is embedded in the second semiconductor substrate in such a way that it includes a surface substantially flush with the surface of the second semiconductor substrate.

12. The optical detection device according to claim 8, wherein, The transistor includes a transfer transistor configured to transfer charge in the photoelectric conversion unit to the floating diffuser. The second transistor includes a reset transistor configured to discharge charge in the floating diffusion.

13. The light detecting device of claim 1, wherein, The optical detection device is a solid-state imaging device.

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