Semiconductor device

Abstract

A semiconductor device (100a) is provided with a semiconductor substrate (1) and a mounting substrate (2). The semiconductor substrate (1) has a first surface (1s1). The mounting substrate (2) has a main surface (20s1). The main surface (20s1) faces the first surface (1s1). The first surface (1s1) is provided with an electric field intensity relaxation part (12) and an electrode (11). The electrode (11) is connected to the mounting substrate (2). A recess (21) is formed in the main surface (20s1). The recessed portion (21) is disposed at a position overlapping the electric field intensity mitigating portion (12) in plan view of the first surface (1s1).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Previously, a semiconductor device was known to use flip-chip mounting, in which the mounting substrate is connected to the electrodes of the semiconductor substrate by means of a mounting substrate facing the back side of the semiconductor substrate (see, for example, Japanese Patent Application Publication No. 2013-89948). In Japanese Patent Application Publication No. 2013-89948, a protective ring is provided in the semiconductor substrate as an electric field strength mitigation part to mitigate the high electric field that occurs in the active region.

[0003] Existing technical documents

[0004] Patent Document 1: Japanese Patent Application Publication No. 2013-89948 Summary of the Invention

[0005] However, in the semiconductor device described above, when the mounting substrate and the protective ring are close together, the electric field in the active region of the semiconductor substrate will not be mitigated, and the withstand voltage of the semiconductor device will deteriorate.

[0006] This disclosure was made to solve the aforementioned problems, and the purpose of this disclosure is to provide a semiconductor device with improved voltage resistance.

[0007] The semiconductor device disclosed herein includes a semiconductor substrate and a mounting substrate. The semiconductor substrate has a first surface. The mounting substrate has a main surface. The main surface is opposite to the first surface. An electric field intensity mitigation portion and an electrode are formed on the first surface. The electrode is connected to the mounting substrate. A recess is formed on the main surface. The recess is positioned at a location that overlaps with the electric field intensity mitigation portion when viewed from above on the first surface.

[0008] Based on the above, a semiconductor device with improved voltage resistance can be obtained. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 1.

[0010] Figure 2 This is a schematic bottom view of the semiconductor substrate in the semiconductor device according to Embodiment 1.

[0011] Figure 3 This is a schematic top view of the mounting substrate in the semiconductor device according to Embodiment 1.

[0012] Figure 4 yes Figure 3 A rough cross-sectional view of line segment IV-IV.

[0013] Figure 5 yes Figure 3 A rough cross-sectional view of line segment VV.

[0014] Figure 6 This is a schematic partial cross-sectional view of the recess in the semiconductor device according to Embodiment 1.

[0015] Figure 7 This is a schematic partial cross-sectional view of a modified example of the recess in the semiconductor device according to Embodiment 1.

[0016] Figure 8 This is a schematic partial cross-sectional view of a modified example of the recess in the semiconductor device according to Embodiment 1.

[0017] Figure 9 This is a schematic partial cross-sectional view of a modified example of the recess in the semiconductor device according to Embodiment 1.

[0018] Figure 10 This is a schematic top view showing the conductive portion in the semiconductor device according to Embodiment 1.

[0019] Figure 11 yes Figure 10 A rough cross-section of line segment XI-XI.

[0020] Figure 12 This is a schematic bottom view of the semiconductor substrate in a modified example 1 of the semiconductor device according to Embodiment 1.

[0021] Figure 13 This is a schematic top view of the mounting substrate in a variation 1 of the semiconductor device according to Embodiment 1.

[0022] Figure 14 This is a schematic top view of the mounting substrate in a modified example 2 of the semiconductor device according to Embodiment 1.

[0023] Figure 15 This is a schematic cross-sectional view of the semiconductor device involved in Embodiment 2.

[0024] Figure 16 This is a schematic top view of the mounting substrate in the semiconductor device according to Embodiment 2.

[0025] Figure 17 yes Figure 16 A schematic cross-section of line segment XVII-XVII.

[0026] Figure 18 This is a schematic cross-sectional view of the semiconductor device involved in Embodiment 3.

[0027] Figure 19This is a schematic cross-sectional view of the semiconductor device involved in Embodiment 4.

[0028] Figure 20 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 5.

[0029] Figure 21 This is a schematic cross-sectional view of a modified example of the semiconductor device according to Embodiment 5. Detailed Implementation

[0030] The embodiments of this disclosure will now be described. Furthermore, unless otherwise specifically mentioned, the same or corresponding parts will be given the same reference numerals in the following drawings, and their descriptions will not be repeated.

[0031] Implementation method 1.

[0032] <Structure of Semiconductor Devices>

[0033] Figure 1 This is a schematic cross-sectional view of the semiconductor device 100a according to Embodiment 1. Figure 2 This is a schematic bottom view of the semiconductor substrate 1 in the semiconductor device 100a according to Embodiment 1. Figure 3 This is a schematic top view of the mounting substrate 2 in the semiconductor device 100a according to Embodiment 1. Figure 4 yes Figure 3 A rough cross-sectional view of line segment IV-IV. Figure 5 yes Figure 3 A rough cross-sectional view of line segment VV. Figure 6 This is a schematic partial cross-sectional view of the electric field intensity mitigation portion 12 and the recess 21 in the semiconductor device 100a according to Embodiment 1.

[0034] Figures 1 to 6 The semiconductor device 100a shown is, for example, a power semiconductor device 100a, and mainly includes a semiconductor substrate 1, a mounting substrate 2, a bonding portion 5, a wiring circuit 6, and a sealing resin 7. The bonding portion 5 includes a first bonding portion 5a, a second bonding portion 5b, a third bonding portion 5c, a fourth bonding portion 5d, and a fifth bonding portion 5e. The wiring circuit 6 includes a first wiring circuit 6a, a second wiring circuit 6b, and a third wiring circuit 6c.

[0035] Semiconductor substrate 1 has a first surface 1s1, a second surface 1s2, and a third surface 1s3. The first surface 1s1 is the surface opposite to the main surface 20s1 of the mounting substrate 2. The second surface 1s2 is the surface opposite to the first surface 1s1. The third surface 1s3 connects the first surface 1s1 and the second surface 1s2. In the semiconductor device 100a according to Embodiment 1, the first surface 1s1 is the back surface of the semiconductor substrate 1. In the semiconductor device 100a according to Embodiment 1, the second surface 1s2 is the surface surface of the semiconductor substrate 1. In the semiconductor device 100a according to Embodiment 1, the third surface 1s3 is the side surface of the semiconductor substrate 1.

[0036] Surface 1s1 and surface 1s2 extend in the x-direction and the y-direction perpendicular to the x-direction. The x-direction is the direction in which the wiring circuit extends. The y-direction is perpendicular to the x-direction. The z-direction is the thickness direction of semiconductor substrate 1. The normal direction of surface 1s1 is the z-direction. Surface 1s2 faces the +z-direction. Surface 1s1 faces the -z-direction.

[0037] like Figure 1 as well as Figure 2 As shown, an electric field intensity mitigation section 12 and an electrode 11 are formed on the first surface 1s1. The electric field intensity mitigation section 12 mitigates the electric field intensity formed on the back surface of the semiconductor substrate 1. Therefore, the electric field intensity mitigation section 12 is disposed on the first surface 1s1 at a distance from the electrode 11. Figure 2 As shown, the electric field intensity mitigation section 12 can also be configured to surround the electrode 11. The shape of the electric field intensity mitigation section 12 can also be, for example, ring-shaped. Specifically, the electric field intensity mitigation section 12 can also be a terminal structure referred to as a guard ring.

[0038] The electric field intensity mitigation section 12 does not necessarily have to be annular. Specifically, the electric field intensity mitigation section 12 can also be a terminal structure known as a JTE (Junction Termination Extension) structure. The electric field intensity mitigation section 12 can also be a p-type region, formed by ion implantation, for example.

[0039] like Figure 2 As shown, electrode 11 includes a first electrode 11a and a second electrode 11b. The first electrode 11a is the main electrode. A main current flows through the main electrode. The second electrode 11b is the control electrode. The control electrode controls the main current. The first electrode 11a and the second electrode 11b are arranged at intervals from each other on the first surface 1s1.

[0040] The first electrode 11a is connected to the mounting substrate 2 via the first joint 5a. The second electrode 11b is connected to the mounting substrate 2 via the second joint 5b.

[0041] like Figure 1 As shown, an upper electrode 11u is formed on the second surface 1s2 of the semiconductor substrate 1. A main current flows through the upper electrode 11u. A third wiring circuit 6c is connected to the upper electrode 11u via a fifth junction 5e. The third wiring circuit 6c extends in the x-direction.

[0042] Semiconductor substrate 1 is a so-called power semiconductor substrate 1 for controlling electricity. Any material can be used as the material constituting semiconductor substrate 1. Materials such as silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (GaO) can also be used as the material constituting semiconductor substrate 1.

[0043] The type of semiconductor element formed on the semiconductor substrate 1 is not particularly limited; for example, it can also be a vertically shaped semiconductor element. In this case, the main current flows in the z-direction (thickness direction) of the semiconductor substrate 1. The semiconductor substrate 1 in this embodiment 1 is a transistor with control electrodes, but as long as it is a vertically shaped semiconductor element, it can also be a diode, or it can have other functions. For example, IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), etc., can be used on the semiconductor substrate 1.

[0044] The material constituting electrode 11 is preferably a material with high electrical and thermal conductivity. For example, the material constituting electrode 11 may also include any material selected from aluminum (Al), aluminum alloys, copper (Cu), and copper alloys. Electrode 11 can be a two-layer structure of Al / Cu, or a multi-layer structure containing any material selected from gold (Au) and silver (Ag).

[0045] Electrode 11 may also include a diffusion-preventing layer. For example, titanium (Ti) may be included as the diffusion-preventing layer. To form an ohmic contact with the semiconductor substrate 1, nickel (Ni) silicide may also be used as the base layer of electrode 11. To prevent oxidation of electrode 11 or improve adhesion, electrode 11 may also include a thin surface layer. The material constituting the surface layer may be, for example, a noble metal such as gold.

[0046] In the semiconductor device 100a according to Embodiment 1, the electrode 11 is not particularly limited. For example, the arrangement of the first electrode 11a and the second electrode 11b is not particularly limited. Specifically, as Figure 2 As shown, the second electrode 11b, as a control electrode, can also be disposed at the corner of the first surface 1s1, but it can also be disposed at the center of the first surface 1s1.

[0047] The shape of the second electrode 11b can also be arbitrary. For example, the shape of the second electrode 11b can also be as follows: Figure 2 The shape shown is rectangular, but it can also be circular, elliptical, or a combination of elliptical and rectangular shapes. The shape of the second electrode 11b can also be hexagonal.

[0048] like Figure 1 As shown, the mounting substrate 2 has a conductive portion 20, a thermally conductive insulating layer 30, and a support layer 40. The conductive portion 20 has a surface, a back surface 20s2, and a side surface 20s3. The surface is opposite to the first surface 1s1 of the semiconductor substrate 1. That is, the main surface 20s1 of the mounting substrate 2 is formed by the surface of the conductive portion 20. The back surface 20s2 is the surface opposite to the surface of the conductive portion 20. The side surface 20s3 is the surface that connects the surface and the back surface 20s2.

[0049] like Figure 1 As shown, the thermally conductive insulating layer 30 is connected to the back surface 20s2 of the conductive portion 20. The support layer 40 is connected to the side opposite to the side of the thermally conductive insulating layer 30 where the conductive portion 20 is connected. In the support layer 40, the side opposite to the side of the thermally conductive insulating layer 30 is exposed from the sealing resin 7.

[0050] The conductive portion 20 includes a first conductive portion 20a and a second conductive portion 20b. The first conductive portion 20a and the second conductive portion 20b are arranged with a gap between them. The first conductive portion 20a and the second conductive portion 20b are insulated from each other. Figure 1 As shown, the space between the first conductive portion 20a and the second conductive portion 20b is preferably filled with an insulating material such as silicone gel or epoxy resin. In the semiconductor device 100a according to Embodiment 1, the insulating material used to fill the space between the first conductive portion 20a and the second conductive portion 20b is, for example, such as... Figure 1 The material shown can also be sealing resin 7.

[0051] In the manufacturing process of the semiconductor device 100a, insulating material may be filled between the first conductive portion 20a and the second conductive portion 20b at any stage. For example, insulating material may be filled between the first conductive portion 20a and the second conductive portion 20b at the initial stage of the manufacturing process of the semiconductor device 100a. For example, insulating material may be filled between the first conductive portion 20a and the second conductive portion 20b at a stage close to the final stage of the manufacturing process of the semiconductor device 100a.

[0052] From the viewpoint of heat resistance, when the insulating material filled between the first conductive portion 20a and the second conductive portion 20b is silicone gel, it is preferable to fill the insulating material after the semiconductor device 100a has undergone a process of being processed at high temperature.

[0053] like Figure 3 As shown, a recess 21 is formed on the main surface 20s1 of the mounting substrate 2. That is, the recess 21 is formed on the surface of the conductive portion 20. In the first conductive portion 20a, the main surface 20s1 includes a first electrode side surface 20as1 and a first wiring circuit side surface 20as2. The recess 21 is formed between the first electrode side surface 20as1 and the first wiring circuit side surface 20as2. Preferably, the recess 21 is filled with a sealing resin 7.

[0054] In the second conductive portion 20b, the main surface 20s1 includes a second electrode side surface 20bs1 and a second wiring circuit side surface 20bs2. A recess 21 is formed between the second electrode side surface 20bs1 and the second wiring circuit side surface 20bs2.

[0055] The conductive part 20 is connected to the electrode 11. Specifically, the first electrode 11a is connected to the first electrode side surface 20as1 of the first conductive part 20a via the first junction 5a. The second electrode 11b is connected to the second electrode side surface 20bs1 of the second conductive part 20b via the second junction 5b.

[0056] That is, when viewed from above in the z-direction, the first electrode 11a is positioned to overlap with the first electrode side surface 20as1 of the first conductive portion 20a. When viewed from above in the z-direction, the second electrode 11b is positioned to overlap with the second electrode side surface 20bs1 of the second conductive portion 20b.

[0057] like Figure 1 As shown, the first wiring circuit 6a is connected to the side surface 20as2 of the first wiring circuit via the third junction 5c. The first wiring circuit 6a extends in the x-direction. The second wiring circuit 6b is connected to the side surface 20bs2 of the second wiring circuit via the fourth junction 5d. The second wiring circuit 6b extends in the -x-direction. Thus, the first electrode 11a, which serves as the main electrode, and the first conductive part 20a are electrically and mechanically connected, and the second electrode 11b, which serves as the control electrode, and the second conductive part 20b are electrically and mechanically connected.

[0058] The material constituting the conductive part 20 is preferably a material with high electrical and thermal conductivity. For example, the material constituting the conductive part 20 may also include any material selected from aluminum (Al), aluminum alloys, copper (Cu), and copper alloys.

[0059] The thermally conductive insulating layer 30 is preferably a material with adhesive, electrical insulation, and thermal conductivity functions. The material constituting the thermally conductive insulating layer 30 may be, for example, a thermosetting resin sheet containing inorganic filler, an inorganic molded sheet impregnated with thermosetting resin, or a coating film. The thermally conductive insulating layer 30 fixes the first conductive portion 20a and the second conductive portion 20b, which are spaced apart from each other.

[0060] A cooler (not shown) may also be connected to the lower surface of the support layer 40. The support layer 40 may also be made of a material capable of transferring heat to the cooler. Specifically, the material constituting the support layer 40 may be a thin sheet or foil of copper, aluminum, or an alloy thereof, which have high thermal conductivity. In addition, the support layer 40 accounts for a large portion of the mechanical strength of the semiconductor device 100a. Therefore, the support layer 40 is preferably characterized by high mechanical strength.

[0061] In the mounting substrate 2, the conductive part 20, the thermally conductive insulating layer 30, and the support layer 40 are bonded together by the adhesive function of the thermally conductive insulating layer 30. Specifically, the conductive part 20, the thermally conductive insulating layer 30, and the support layer 40 are bonded together by applying pressure and heating.

[0062] The components constituting the first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c may, for example, be conductive lead frames. The first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c are preferably arranged parallel to the main surface 20s1. In particular, the shapes of the first wiring circuit 6a and the third wiring circuit 6c are preferably flat. This reduces parasitic inductance.

[0063] Sealing resin 7 covers the semiconductor substrate 1, the mounting substrate 2, a portion of the first wiring circuit 6a, a portion of the second wiring circuit 6b, and a portion of the third wiring circuit 6c. This improves the insulation of the semiconductor device 100a, reducing the impact of external environmental factors such as humidity and contamination.

[0064] The first wiring circuit 6a extends from the first wiring circuit side surface 20as2 of the first conductive portion 20a to the outside of the sealing resin 7. The second wiring circuit 6b extends from the second wiring circuit side surface 20bs2 of the second conductive portion 20b to the outside of the sealing resin 7. The third wiring circuit 6c extends from the second surface 1s2 of the semiconductor substrate 1 to the outside of the sealing resin 7.

[0065] A portion of each of the first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c extends outward from the surface of the sealing resin 7 in a manner that allows connection to external devices outside the sealing resin 7. The first wiring circuit 6a, the second wiring circuit 6b, and the third wiring circuit 6c may also be bent, for example, by molding, in the portions extending outward from the sealing resin 7.

[0066] Solder can be cited as a material constituting the junction 5. However, solder has a relatively high thermal resistance, so materials other than solder can also be used as materials constituting the junction 5 of the semiconductor device 100a according to Embodiment 1. In addition, from the viewpoint of long-term reliability of the junction 5, materials other than solder can also be used. Furthermore, the thermal resistance is determined by the thermal conductivity, the junction thickness in the z-direction, and the cross-sectional area of ​​the junction 5 in the x and y directions.

[0067] In particular, when solder is used to form the third bonding portion 5c, the fourth bonding portion 5d, and the fifth bonding portion 5e, the solder may remelt during the manufacturing process of the semiconductor device 100a due to process temperature and temperature distribution. Therefore, materials different from solder can be used as the materials constituting the third bonding portion 5c, the fourth bonding portion 5d, and the fifth bonding portion 5e of the semiconductor device 100a according to Embodiment 1.

[0068] For example, sintered materials containing microparticles of silver (Ag) or copper (Cu) are preferably used as the material for the bonding portion 5 of the semiconductor device 100a according to Embodiment 1. By using a sintered material to form the bonding portion 5, the bonding thickness is reduced. In addition, the sintered material has high thermal conductivity. As a result, the bonding portion 5 has low thermal resistance. There are no special conditions regarding pressure application, no pressure application, process temperature, or temperature distribution when forming the bonding portion 5.

[0069] The joint 5 can also be formed by liquid-phase diffusion of Cu-Sn or the like. This reduces the joint thickness, thus further reducing the thermal resistance at the joint 5.

[0070] To further suppress thermal resistance, the junction 5 may not be formed. Alternatively, the components constituting the semiconductor device 100a may be directly bonded via a solid-phase reaction. Specifically, the first electrode 11a and the first conductive portion 20a may be directly connected via a solid-phase reaction without passing through the first junction 5a.

[0071] When the semiconductor device 100a operates, the semiconductor substrate 1 heats up. The heat generated by the semiconductor substrate 1 passes through the electrodes 11. The heat passing through the second electrode 11b, which serves as a control electrode, is less than the heat passing through the first electrode 11a, which serves as a main electrode. Therefore, when forming the first bonding portion 5a and the second bonding portion 5b, the first bonding portion 5a and the second bonding portion 5b may not be made of the same material. However, from the viewpoint of shortening the manufacturing process, the first bonding portion 5a and the second bonding portion 5b are preferably made of the same material.

[0072] From the viewpoint of shortening manufacturing processes, the materials constituting the third joint 5c, the fourth joint 5d, and the fifth joint 5e can also be the same as those constituting the first joint 5a and the second joint 5b. Alternatively, the third joint 5c, the fourth joint 5d, and the fifth joint 5e can be omitted, and the lead frame can be directly joined by ultrasonic bonding or laser welding.

[0073] The material constituting the sealing resin 7 may be, for example, a thermosetting resin such as epoxy resin. The sealing resin 7 is formed, for example, by transfer molding. As described later, the sealing resin 7 may also be formed by case molding.

[0074] Here, the semiconductor device 100a according to Embodiment 1 is characterized in that, as Figure 1 as well as Figure 3 As shown, a recess 21 is formed on the main surface 20s1 of the mounting substrate 2. The recess 21 is positioned at a location that overlaps with the electric field intensity mitigation portion 12 when viewed from above on the first surface 1s1.

[0075] As described above, the electric field strength mitigation section 12 mitigates the electric field strength formed on the back surface of the semiconductor substrate 1. However, when the mounting substrate 2 is disposed near the electric field strength mitigation section 12, the mounting substrate 2 affects the electric field strength of the electric field strength mitigation section 12. As a result, the withstand voltage of the semiconductor device 100a may deteriorate.

[0076] In the semiconductor device 100a according to Embodiment 1, by forming a recess 21 on the main surface 20s1 of the mounting substrate 2, the influence of the electric field strength mitigation portion 12 on the mounting substrate 2 is suppressed. As a result, the withstand voltage of the semiconductor device 100a is improved.

[0077] like Figure 3 As shown, the recess 21 is preferably formed along the shape of the electric field intensity easing portion 12. Specifically, when viewed from above the main surface 20s1, the shape of the recess 21 may also be annular.

[0078] As a result, the influence of the electric field strength mitigation section 12 on the mounting substrate 2 is suppressed. Furthermore, the back surface (first surface 1s1) of the semiconductor substrate 1 serves as a heat dissipation surface, suppressing thermal resistance. Consequently, the heat dissipation performance of the semiconductor device 100a is improved.

[0079] like Figure 4 as well as Figure 5 As shown, the recess 21 has a bottom surface 21s1 and a side surface 21s2. The bottom surface 21s1 is the surface in the recess 21 that is furthest away from the first surface 1s1 and the electric field intensity mitigation part 12 in the z direction. The side surface 21s2 is the surface that connects the main surface 20s1 and the bottom surface 21s1.

[0080] like Figure 4 as well as Figure 5 As shown, the distance t1 from the main surface 20s1 to the bottom surface 21s1 is less than the thickness t2 of the conductive portion 20. The thickness t2 of the conductive portion 20 is the distance in the z-direction from the surface of the conductive portion 20 to the back surface 20s2. That is, the inner peripheral surface of the recess 21 is made of a conductor, and this inner peripheral surface is electrically continuous. If explained from a different viewpoint, for example, in the first conductive portion 20a, the first electrode side surface 20as1 and the first wiring circuit side surface 20as2 are connected via the recess 21. In the second conductive portion 20b, the second electrode side surface 20bs1 and the second wiring circuit side surface 20bs2 are connected via the recess 21.

[0081] The recess 21 has an opening 21a formed on the main surface 20s1. For example... Figure 4 as well as Figure 5 As shown, in a cross-section along the z-direction, the shape of the recess 21 can also be a shape that narrows from the opening 21a toward the bottom surface 21s1. Specifically, as... Figure 4 As shown, the width w1 of the bottom surface 21s1 is smaller than the width w2 of the opening 21a. As a result, the flow path width of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 is widened, and the thermal resistance in the semiconductor device 100a is reduced.

[0082] like Figure 6 As shown, in a cross-section along the z-direction, the shape of the side surface 21s2 can also be a straight conical shape. Specifically, in a cross-section along the z-direction, the shape of the side surface 21s2 can also have a straight portion L. As described later, in a cross-section along the z-direction, the side surface 21s2 can also be an arc shape or an ellipse shape. Specifically, in a cross-section along the z-direction, the side surface 21s2 can also have a curved portion R.

[0083] The side surface 21s2 can also be a surface formed by combining the straight part L and the curved part R. Therefore, in the cross-section in the z direction, the shape of the recess 21 can also be a shape that narrows from the opening 21a toward the bottom surface 21s1.

[0084] like Figure 6 As shown, the width w1 of the recess 21 is preferably greater than the width d of the electric field intensity mitigation portion 12. More preferably, the width w1 of the recess 21 is greater than the distance l from the third surface 1s3 to the inner peripheral surface of the electric field intensity mitigation portion 12.

[0085] Figures 7 to 9 This is a schematic partial cross-sectional view of a modified example of the recess 21 in the semiconductor device 100a according to Embodiment 1. Figures 7 to 9 and Figure 6 correspond. Figures 7 to 9 The semiconductor device 100a shown has substantially the same... Figures 1 to 6 The semiconductor device 100a shown has the same structure and can achieve the same effect, but the shape of the recess 21 is different.

[0086] like Figure 7 As shown, the bottom surface 21s1 can also extend to the side surface 20s3 of the mounting substrate 2. For example... Figure 7 As shown, the width w1 of the recess 21 is the distance in the x direction from the side surface 21s2 of the recess 21 to the side surface 20s3 of the mounting substrate 2.

[0087] Furthermore, the lead frames of the first wiring circuit 6a, the second wiring circuit 6b, etc., can also be connected to the bottom surface 21s1 of the recess 21. However, compared to the bottom surface 21s1 of the recess 21, the surface morphology of the main surfaces 20s1, such as the first wiring circuit side surface 20as2 and the second wiring circuit side surface 20bs2, is superior. Therefore, the lead frames of the first wiring circuit 6a, the second wiring circuit 6b, etc., are preferably connected to the main surfaces 20s1, such as the first wiring circuit side surface 20as2 and the second wiring circuit side surface 20bs2.

[0088] like Figure 8 As shown, in a cross-section along the z-direction, the side surface 21s2 may also have a curved portion R. The side surface 21s2 may also be a surface formed by combining a straight portion L and a curved portion R.

[0089] In the recess 21, the shapes of the inner peripheral side surface 21s2 and the outer peripheral side surface 21s2 can also be different from each other. Specifically, they can also be as follows: Figure 9 As shown, the cross-sectional shape of the inner peripheral side surface 21s2 is curved, such as an arc or an ellipse, while the cross-sectional shape of the outer peripheral side surface 21s2 is straight. Alternatively, the outer peripheral side surface 21s2 may be tapered relative to the bottom surface 21s1. Specifically, the inner peripheral side surface 21s2 may have a curved portion R, and the outer peripheral side surface 21s2 may have a straight portion L. Therefore, in the cross-section along the z-direction, the shape of the recess 21 may also be a shape that narrows from the opening 21a toward the bottom surface 21s1.

[0090] The recess 21 described above is preferably filled with an insulating material such as silicone gel or epoxy resin. In the semiconductor device 100a according to Embodiment 1, the insulating material filled into the recess 21 is, for example, such as... Figure 1 The material shown can also be sealing resin 7.

[0091] The recess 21 can also be formed by any method, such as machining or chemical processing. Machining specifically includes removal processes such as cutting, grinding, and milling, as well as forming processes such as stamping, casting, and forging. Chemical processing specifically includes etching.

[0092] <Methods for Manufacturing Semiconductor Devices>

[0093] In the manufacturing method of the semiconductor device 100a according to this embodiment, a process (S1a) for preparing a semiconductor substrate 1 and a conductive portion 20 is first performed. A recess 21 is formed on the surface of the conductive portion 20. The conductive portion 20 includes a first conductive portion 20a and a second conductive portion 20b. The first conductive portion 20a and the second conductive portion 20b are arranged at intervals from each other.

[0094] With the first conductive portion 20a and the second conductive portion 20b spaced apart from each other, the handling of the conductive portion 20b becomes difficult during the manufacturing process of the semiconductor device 100a. Therefore, as Figure 10 as well as Figure 11 As shown, the first conductive part 20a and the second conductive part 20b can also be connected via the insulating part 3, which is an insulating material. Figure 10 This is a schematic top view showing the conductive portion 20 in the semiconductor device 100a according to Embodiment 1. Figure 11 yes Figure 10 A rough cross-section of line segment XI-XI.

[0095] The insulating portion 3 has both an adhesive function that connects the first conductive portion 20a and the second conductive portion 20b, and an electrical insulation function that insulates the first conductive portion 20a and the second conductive portion 20b. The material constituting the insulating portion 3 is, for example, a thermosetting resin such as epoxy resin. Thus, by using the insulating portion 3, the first conductive portion 20a and the second conductive portion 20b can be integrally processed during the manufacturing process of the semiconductor device 100a. Furthermore, since the first conductive portion 20a and the second conductive portion 20b are integrally formed, the mechanical strength of the conductive portion 20 is ensured.

[0096] Next, a process (S2a) is performed in which the semiconductor substrate 1 is mounted onto the conductive portion 20. Specifically, the electrode 11 formed on the first surface 1s1 of the semiconductor substrate 1 and the conductive portion 20 are connected via the bonding portion 5.

[0097] Next, the process of connecting the lead frame is performed (S3a). Specifically, the first wiring circuit 6a is connected to the first conductive part 20a via the joint 5. The second wiring circuit 6b is connected to the second conductive part 20b via the joint 5. The third wiring circuit 6c is connected to the upper electrode 11u of the semiconductor substrate 1 via the joint 5.

[0098] Next, the process of forming the sealing resin 7 is carried out (S4a). Specifically, a support layer 40, a thermally conductive insulating layer 30, and the aforementioned conductive portion 20 on which the semiconductor substrate 1 is mounted are disposed in a mold for transfer molding. Then, the sealing resin 7 is formed by transfer molding.

[0099] In this way, we can obtain Figures 1 to 6 The semiconductor device 100a according to this embodiment 1 is shown.

[0100] <Examples of Semiconductor Device Manufacturing Methods>

[0101] In a variation of the manufacturing method of the semiconductor device 100a according to Embodiment 1, a process (S1b) of preparing a semiconductor substrate 1 and a mounting substrate 2 is first performed. The mounting substrate 2 has a conductive portion 20, a thermally conductive insulating layer 30, and a support layer 40. A recess 21 is formed on the surface of the conductive portion 20.

[0102] Therefore, in the manufacturing process of the semiconductor device 100a, the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are integrated as a mounting substrate 2, thereby ensuring the mechanical strength of the conductive portion 20. Furthermore, since the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are integrated as a mounting substrate 2, the handleability of the conductive portion 20 in the manufacturing process of the semiconductor device 100a is improved. Therefore, in the manufacturing process of the semiconductor device 100a, the conductive portion 20, the thermally conductive insulating layer 30, and the support layer 40 are preferably manufactured as an integrated mounting substrate 2.

[0103] Next, a process (S2b) is performed in which the semiconductor substrate 1 is mounted onto the conductive portion 20. Specifically, the electrode 11 formed on the first surface 1s1 of the semiconductor substrate 1 and the conductive portion 20 are connected via the bonding portion 5.

[0104] Next, the process of connecting the lead frame is performed (S3b). Specifically, the first wiring circuit 6a is connected to the first conductive part 20a via the joint 5. The second wiring circuit 6b is connected to the second conductive part 20b via the joint 5. The third wiring circuit 6c is connected to the upper electrode 11u of the semiconductor substrate 1 via the joint 5.

[0105] Next, the process of forming the sealing resin 7 is carried out (S4b). Specifically, a mounting substrate 2, on which the semiconductor substrate 1 is mounted, is placed in a mold for transfer molding. Then, the sealing resin 7 is formed by transfer molding.

[0106] In this step (S4b), it is not necessary to use resin-based pressure to achieve the bonding and electrical insulation functions of the thermally conductive insulating layer 30. Therefore, the conditions for forming the sealing resin 7 through transfer molding in this step (S4b) are relaxed.

[0107] Therefore, we can obtain Figures 1 to 6 The semiconductor device 100a according to this embodiment 1 is shown.

[0108] <Effects>

[0109] The semiconductor device 100a disclosed herein includes a semiconductor substrate 1 and a mounting substrate 2. The semiconductor substrate 1 has a first surface 1s1. The mounting substrate 2 has a main surface 20s1. The main surface 20s1 is opposite to the first surface 1s1. An electric field intensity mitigation portion 12 and an electrode 11 are formed on the first surface 1s1. The electrode 11 is connected to the mounting substrate 2. A recess 21 is formed on the main surface 20s1. The recess 21 is disposed at a position that overlaps with the electric field intensity mitigation portion 12 when viewed from above on the first surface 1s1.

[0110] Therefore, by forming the recess 21, the distance between the electric field strength mitigation portion 12 and the mounting substrate 2 can be sufficiently increased. As a result, the influence of the electric field strength mitigation portion 12 on the mounting substrate 2 is suppressed. Consequently, the withstand voltage of the semiconductor device 100a is improved.

[0111] In the semiconductor device 100a described above, the direction perpendicular to the first surface 1s1 is defined as the z-direction. The recess 21 has an opening 21a and a bottom surface 21s1. The opening 21a is formed on the main surface 20s1. The bottom surface 21s1 is furthest from the first surface 1s1 in the z-direction. The width w1 of the bottom surface 21s1 is smaller than the width w2 of the opening 21a.

[0112] As a result, the flow path width of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 becomes wider, and the thermal resistance in the semiconductor device 100a is reduced.

[0113] In the semiconductor device 100a described above, the recess 21 has a side surface 21s2. The side surface 21s2 connects the main surface 20s1 and the bottom surface 21s1. In a cross-section along the z-direction, the side surface 21s2 has a straight section L.

[0114] Therefore, in the cross-section along the z-direction, the shape of the recess 21 becomes narrower from the opening 21a toward the bottom surface 21s1. As a result, the flow path width of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 becomes wider, and the thermal resistance in the semiconductor device 100a decreases.

[0115] In the semiconductor device 100a described above, the recess 21 has a side surface 21s2. The side surface 21s2 connects the main surface 20s1 and the bottom surface 21s1. In a cross-section along the z-direction, the side surface 21s2 has a curved portion R.

[0116] Therefore, in the cross-section along the z-direction, the shape of the recess 21 becomes narrower from the opening 21a toward the bottom surface 21s1. As a result, the flow path width of the heat generated in the semiconductor substrate 1 and passing through the electrode 11 becomes wider, and the thermal resistance in the semiconductor device 100a decreases.

[0117] In the semiconductor device 100a described above, electrode 11 includes a first electrode 11a and a second electrode 11b. The first electrode 11a is a main electrode. The second electrode 11b is a control electrode. Mounting substrate 2 has a conductive portion 20. The conductive portion 20 includes a first conductive portion 20a and a second conductive portion 20b. The first conductive portion 20a is connected to the first electrode 11a. The second conductive portion 20b is connected to the second electrode 11b. The first conductive portion 20a and the second conductive portion 20b are connected via an insulating portion.

[0118] Therefore, the first conductive portion 20a and the second conductive portion 20b can be processed as a single unit in the manufacturing process of the semiconductor device 100a. That is, the processability of the conductive portion 20 in the manufacturing process of the semiconductor device 100a is improved. In addition, since the first conductive portion 20a and the second conductive portion 20b are integrated, the mechanical strength of the conductive portion 20 is ensured.

[0119] In the semiconductor device 100a described above, the mounting substrate 2 has a thermally conductive insulating layer 30. The thermally conductive insulating layer 30 is connected to the conductive portion 20.

[0120] This ensures the mechanical strength of the conductive part 20. Furthermore, since the conductive part 20, the thermally conductive insulating layer 30, and the support layer 40 are integrated as a mounting substrate 2, the handleability of the conductive part 20 during the manufacturing process of the semiconductor device 100a is improved.

[0121] <Structure of Variation Example 1>

[0122] Figure 12 This is a schematic bottom view of the semiconductor substrate 1 in a modified example 1 of the semiconductor device according to Embodiment 1. Figure 12 and Figure 2 correspond. Figure 13This is a schematic top view of the mounting substrate 2 in a modified example 1 of the semiconductor device 100a according to Embodiment 1. Figure 13 and Figure 3 correspond. Figure 12 as well as Figure 13 The semiconductor device 100a shown has substantially the same... Figures 1 to 6 The semiconductor device 100a shown has the same structure and can achieve the same effect, but as Figure 12 This differs from the previous case where a third electrode 11c is formed on the first surface 1s1 of the semiconductor substrate 1. Alternatively, at least one or more third electrodes 11c may be formed on the first surface 1s1 in addition to the first electrode 11a and the second electrode 11b. The number of third electrodes 11c can be one or more.

[0123] like Figure 12 As shown, a third electrode 11c is disposed on the first surface 1s1 at a distance from the first electrode 11a and the second electrode 11b. Therefore, when the potential of the third electrode 11c is the same as that of the first electrode 11a, which serves as the main electrode, the conductive portion 20 includes a third conductive portion 20c that can be wired parallel to the second electrode 11b, which serves as the control electrode. As a result, a semiconductor device 100a with improved noise immunity can be obtained.

[0124] As described above, when the third electrode 11c is formed on the first surface 1s1, such as Figure 13 As shown, the conductive part 20 also includes a third conductive part 20c. The third conductive part 20c is connected to the third electrode 11c via the joint 5 (not shown).

[0125] like Figure 13 As shown, a third conductive portion 20c is disposed at a distance from the first conductive portion 20a and the second conductive portion 20b. The first conductive portion 20a, the second conductive portion 20b, and the third conductive portion 20c are insulated from each other. The spaces between the first conductive portion 20a, the second conductive portion 20b, and the third conductive portion 20c are preferably filled with an insulating material such as silicone gel or epoxy resin. For example, the insulating material filled between the first conductive portion 20a, the second conductive portion 20b, and the third conductive portion 20c could also be... Figure 1 The sealing resin 7 shown.

[0126] In the third conductive portion 20c, the main surface 20s1 includes a third electrode side surface 20cs1 and a third wiring circuit side surface 20cs2. A recess 21 is formed between the third electrode side surface 20cs1 and the third wiring circuit side surface 20cs2.

[0127] When viewed from above in the z-direction, the third electrode 11c is positioned overlapping the third electrode side surface 20cs1 of the third conductive portion 20c. Alternatively, a current sensing line and a temperature sensing line, which are wirings from an on-chip diode, can be connected to the third wiring circuit side surface 20cs2. In this way, the third electrode 11c and the third conductive portion 20c can be electrically and mechanically connected.

[0128] <Effects>

[0129] In the semiconductor device 100a described above, electrode 11 includes at least one third electrode 11c. Conductive portion 20 includes a third conductive portion 20c. The third conductive portion 20c is connected to the third electrode 11c.

[0130] Therefore, the third conductive part 20c can be connected to either a current sensing line or a temperature sensing line, which is a wiring from an on-chip diode.

[0131] In the semiconductor device 100a described above, the potential of the third electrode 11c is the same as that of the first electrode 11a.

[0132] As a result, a semiconductor device 100a with improved noise immunity can be obtained.

[0133] <Structure of Variation Example 2>

[0134] Figure 14 This is a schematic bottom view of the mounting substrate 2 in a modified example 2 of the semiconductor device 100a according to Embodiment 1. Figure 14 and Figure 3 correspond. Figure 14 The mounting substrate 2 shown has substantially the same as Figures 1 to 6 The same structure as the mounting substrate 2 in the semiconductor device 100a shown can achieve the same effect, but as Figure 14 The semiconductor device 100a shown in Embodiment 1 has a plurality of semiconductor substrates 1, which is different.

[0135] exist Figures 1 to 6 In the semiconductor device 100a shown, the number of semiconductor substrates 1 is one, but the number of semiconductor substrates 1 in the semiconductor device 100a can also be multiple. The semiconductor device 100a can also have multiple semiconductor substrates 1 that are different from each other, and can also have multiple semiconductor substrates 1 that have different structures. As for the type of semiconductor substrate 1, as long as it is a vertical structure, there are no particular restrictions on the number of parallel connections and combinations.

[0136] In a variation 2 of the semiconductor device 100a according to Embodiment 1, the circuit structure of the semiconductor device 100a becomes a so-called 2-in-1 type for mounting two semiconductor substrates 1 on one module. Figure 14 This is the mounting base plate 2 that constitutes the half-bridge. For example... Figure 14 As shown, the four first electrode sides 20as1 disposed at the left and right ends of the mounting substrate 2 can also be connected to the semiconductor substrate 1 for transistors. The four first electrode sides 20as1 disposed at the center of the mounting substrate 2 can also be connected to the semiconductor substrate 1 for transistors.

[0137] Implementation method 2.

[0138] <Structure of Semiconductor Devices>

[0139] Figure 15 This is a schematic cross-sectional view of the semiconductor device 100b according to Embodiment 2. Figure 15 and Figure 1 correspond. Figure 16 This is a schematic top view of the mounting substrate 2 in the semiconductor device 100b according to Embodiment 2. Figure 16 and Figure 3 correspond. Figure 17 yes Figure 16 A schematic cross-section of line segment XVII-XVII. Figure 17 and Figure 4 correspond. Figures 15 to 17 The semiconductor device 100b shown has essentially the same Figure 1 as well as Figure 6 The semiconductor device 100a shown has the same structure and can achieve the same effect, but the difference is that the component connected to the back side 20s2 of the conductive part 20 is not the thermally conductive insulating layer 30 but the insulating substrate 31.

[0140] Specifically, in the semiconductor device 100b according to Embodiment 2, the mounting substrate 2 has a conductive portion 20, an insulating substrate 31, and a lower electrode 41. As described above, the insulating substrate 31 is connected to the back surface 20s2 of the conductive portion 20. The lower electrode 41 is connected to the side opposite to the side of the insulating substrate 31 to which the conductive portion 20 is connected. Regarding the lower electrode 41, the side opposite to the side of the insulating substrate 31 to which it is connected is exposed from the sealing resin 7.

[0141] The material constituting the insulating substrate 31 can be any material, such as a ceramic with Si-N or Al-N as the main component. The insulating substrate 31 insulates the conductive part 20 and the lower electrode 41.

[0142] In the semiconductor device 100b according to Embodiment 2, no current flows through the lower electrode 41. However, it is preferable to have high thermal conductivity. Furthermore, in order to suppress warping in the semiconductor device 100b, the coefficient of linear expansion of the lower electrode 41 is preferably the same as the coefficient of linear expansion of the conductive portion 20. That is, the material constituting the lower electrode 41 is preferably the same as the material constituting the conductive portion 20. The material constituting the lower electrode may, for example, include any material selected from aluminum (Al), aluminum alloys, copper (Cu), and copper alloys.

[0143] The conductive part 20, the insulating substrate 31, and the lower electrode 41 can each be joined by either a direct bonding method or an active metal brazing method. In this case, the direct bonding method joins the two constituent materials through a direct reaction. Alternatively, the active metal brazing method joins the two constituent materials using a brazing filler metal obtained by adding active metals such as titanium or zirconium.

[0144] like Figure 17 As shown, the conductive part 20, the insulating substrate 31, and the lower electrode 41 are integrated as a mounting substrate 2, thereby improving the handleability of the conductive part 20 in the manufacturing process of the semiconductor device 100b.

[0145] <Effects>

[0146] In the semiconductor device 100b described above, the mounting substrate 2 has an insulating substrate 31 and a lower electrode 41. The insulating substrate 31 is connected to the conductive portion 20. The lower electrode 41 is connected to the insulating substrate 31. The lower electrode 41 is disposed on the side opposite to the side where the conductive portion 20 is disposed when viewed from the insulating substrate 31.

[0147] Thus, the conductive part 20, the insulating substrate 31, and the lower electrode 41 are integrated as a mounting substrate 2. As a result, the handleability of the conductive part 20 in the manufacturing process of the semiconductor device 100b is improved.

[0148] Implementation method 3.

[0149] <Structure of Semiconductor Devices>

[0150] Figure 18 This is a schematic cross-sectional view of the semiconductor device 100c according to Embodiment 3. Figure 18 and Figure 1 correspond. Figure 18 The semiconductor device 100c shown has essentially the same Figure 1 as well as Figure 6The semiconductor device 100a shown has the same structure and achieves the same effect, but the difference lies in that a sealing resin 7 is formed by molding a housing. For example, a potting resin is used as the sealing resin 7. The material constituting the potting resin is, for example, silicone gel.

[0151] like Figure 18 As shown, a housing 8 is disposed on the support layer 40. The housing 8 is disposed in a manner that surrounds the semiconductor substrate 1. The housing 8 is fixed to the support layer 40 by an adhesive or the like. The housing 8 and the support layer 40, fixed by an adhesive or the like, are sealed.

[0152] The material constituting the housing 8 can be injection molded, and is preferably a material with high heat resistance and insulation. Any material can also be used as the material constituting the housing 8, such as engineering plastics like polyphenylene sulfide (PPS).

[0153] <Methods for Manufacturing Semiconductor Devices>

[0154] In the manufacturing method of the semiconductor device 100c according to Embodiment 3, a process (S1c) of preparing a semiconductor substrate 1 and a mounting substrate 2 is first performed. The mounting substrate 2 has a conductive portion 20, a thermally conductive insulating layer 30, and a support layer 40. A recess 21 is formed on the surface of the conductive portion 20.

[0155] Next, a process (S2c) is performed in which the semiconductor substrate 1 is mounted onto the conductive portion 20. Specifically, the electrode 11 formed on the first surface 1s1 of the semiconductor substrate 1 and the conductive portion 20 are connected via the bonding portion 5.

[0156] Next, the process of connecting the lead frame is performed (S3c). Specifically, the first wiring circuit 6a is connected to the first conductive part 20a via the joint 5. The second wiring circuit 6b is connected to the second conductive part 20b via the joint 5. The third wiring circuit 6c is connected to the upper electrode 11u of the semiconductor substrate 1 via the joint 5.

[0157] Next, the process of forming the sealing resin 7 is carried out (S4c). Specifically, the housing 8 is fixed to the support layer 40 by means of an adhesive or the like. Then, potting resin or the like is filled into the housing 8.

[0158] As a subsequent process, for example, a cover (not shown) may be mounted onto the semiconductor device 100c. Additionally, terminal processing such as bending may be performed on the wiring circuitry extending outwards from the sealing resin 7.

[0159] In this way, we can obtain Figure 18 The semiconductor device 100c shown in this embodiment 3.

[0160] <Effects>

[0161] The aforementioned semiconductor device 100c also includes a housing 8. The housing 8 surrounds a sealing resin 7.

[0162] Thus, a semiconductor device 100c with sealing resin 7 formed by housing molding can be obtained.

[0163] Implementation method 4.

[0164] <Structure of Semiconductor Devices>

[0165] Figure 19 This is a schematic cross-sectional view of the semiconductor device 100d according to Embodiment 4. Figure 19 and Figure 1 correspond. Figure 19 The semiconductor device 100d shown has essentially the same Figures 1 to 6 The semiconductor device 100a shown has the same structure and can achieve the same effect, but the difference is that it has a cooler 9.

[0166] Specifically, a cooler 9 is connected to the back side of the support layer 40 exposed from the sealing resin 7 via a sixth joint 5f. A flow path for allowing liquid, which serves as a refrigerant, to circulate is formed inside the cooler 9. The cooler 9 in the semiconductor device 100d according to this embodiment 4 is a liquid cooling cooler 9, but it could also be an air-cooled cooler 9. This improves the heat dissipation of the semiconductor device 100d.

[0167] Solder can be listed as a material constituting the sixth joint 5f, but it is particularly preferred to be a material with high thermal conductivity that can ensure long-term reliability even if the joint thickness is thin.

[0168] The material constituting the cooler 9 can be any material with high thermal conductivity. For example, the material constituting the cooler 9 can also include any material selected from aluminum (Al), aluminum alloys, copper (Cu), and copper alloys.

[0169] In the semiconductor device 100d according to this embodiment 4, when the sealing resin 7 is formed by housing molding, it is preferable to fill the housing 8 with the potting resin after the cooler 9 is bonded to the mounting substrate 2.

[0170] <Effects>

[0171] The aforementioned semiconductor device 100d also includes a cooler 9. The cooler 9 is connected to the mounting substrate 2.

[0172] This improves the heat dissipation of the semiconductor device 100d.

[0173] Implementation method 5.

[0174] <Structure of Semiconductor Devices>

[0175] Figure 20 This is a schematic cross-sectional view of the semiconductor device 100e according to Embodiment 5. Figure 20 and Figure 1 correspond. Figure 20 The semiconductor device 100e shown has essentially the same Figures 1 to 6 The semiconductor device 100a shown has the same structure and achieves the same effect, but the difference is that the sealing resin 7 seals a portion of the cooler 9.

[0176] The cooler 9 serves as a support layer 40 for mounting the substrate 2. Therefore, a thermally conductive insulating layer 30 is connected to the cooler 9. Thus, the cooler 9 can be installed without... Figure 19 The sixth junction 5f shown is connected to the thermally conductive insulating layer 30. This further improves the heat dissipation of the semiconductor device 100e.

[0177] Figure 21 This is a schematic cross-sectional view of a modified example of the semiconductor device 100e according to Embodiment 5. Figure 21 and Figure 1 correspond. Figure 21 The semiconductor device 100e shown has essentially the same Figure 20 The semiconductor device 100e shown has the same structure and achieves the same effect, but the difference is that the sealing resin 7 seals the entire cooler 9.

[0178] <Effects>

[0179] The aforementioned semiconductor device 100e seals at least a portion of the cooler 9 inside.

[0180] This further improves the heat dissipation of the semiconductor device 100e.

[0181] It should be understood that the embodiments disclosed herein are merely illustrative and not restrictive at all points. At least two embodiments of this disclosure may be combined, provided there are no contradictions. The basic scope of this disclosure is not limited to the foregoing description but is shown by the claims and is intended to include all modifications equivalent in meaning and scope to the claims.

[0182] Explanation of symbols

[0183] 1: Semiconductor substrate; 1s1: First surface; 1s2: Second surface; 1s3: Third surface; 2: Mounting substrate; 3: Insulating portion; 5: Bonding portion; 5a: First bonding portion; 5b: Second bonding portion; 5c: Third bonding portion; 5d: Fourth bonding portion; 5e: Fifth bonding portion; 5f: Sixth bonding portion; 6: Wiring circuit; 6a: First wiring circuit; 6b: Second wiring circuit; 6c: Third wiring circuit; 7: Sealing resin; 8: Housing; 9: Cooler; 11: Electrode; 11a: First electrode; 11b: Second electrode; 11c: Third electrode; 11u: Upper electrode; 12: Electric field intensity mitigation portion; 20: Conductive portion; 20a: First conductive portion; 20as1: Side of first electrode; 20a s2: Side of the first wiring circuit; 20b: Second conductive part; 20bs1: Side of the second electrode; 20bs2: Side of the second wiring circuit; 20c: Third conductive part; 20cs1: Side of the third electrode; 20cs2: Side of the third wiring circuit; 20s1: Main surface; 20s2: Back surface; 20s3: Side surface; 21: Recess; 21a: Opening; 21s1: Bottom surface; 21s2: Side surface; 30: Thermally conductive insulating layer; 31: Insulating substrate; 40: Support layer; 41: Lower electrode; 100a, 100b, 100c, 100d, 100e: Semiconductor device; d: Width; l: Distance; L: Straight part; R: Curved part; t1: Distance; w1: Width; w2: Width.

Claims

1. A semiconductor device comprising: A semiconductor substrate having a first surface; and The mounting substrate has a main surface opposite to the first surface. An electric field intensity mitigation portion and an electrode connected to the mounting substrate are formed on the first surface. A recess is formed on the main surface. The recess is positioned at a location that overlaps with the electric field intensity mitigation portion when viewed from above on the first surface.

2. The semiconductor device according to claim 1, wherein, When the direction perpendicular to the first surface is defined as the z-direction... The recess has an opening formed on the main surface and a bottom surface furthest from the first surface in the z-direction. The width of the bottom surface is smaller than the width of the opening.

3. The semiconductor device according to claim 2, wherein, The recess has a side surface connecting the main surface and the bottom surface. In a cross-section along the z-direction, the side surface has a straight portion.

4. The semiconductor device according to claim 2 or 3, wherein, The recess has a side surface that connects the main surface and the bottom surface. In a cross-section along the z-direction, the side surface has a curved portion.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The electrode includes a first electrode as the main electrode and a second electrode as the control electrode. The mounting substrate has a conductive portion. The conductive portion includes a first conductive portion connected to the first electrode and a second conductive portion connected to the second electrode. The first conductive part and the second conductive part are connected via an insulating part.

6. The semiconductor device according to claim 5, wherein, The electrode includes at least one or more third electrodes. The conductive portion includes a third conductive portion connected to the third electrode.

7. The semiconductor device according to claim 6, wherein, The potential of the third electrode is the same as that of the first electrode.

8. The semiconductor device according to any one of claims 5 to 7, wherein, The mounting substrate has a thermally conductive insulating layer connected to the conductive part.

9. The semiconductor device according to any one of claims 5 to 7, wherein, The mounting substrate has an insulating substrate connected to the conductive portion and a lower electrode connected to the insulating substrate. The lower electrode is disposed on the opposite side of the side where the conductive portion is disposed when viewed from the insulating substrate.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The semiconductor device also includes a sealing resin for sealing the semiconductor substrate inside.

11. The semiconductor device according to claim 10, wherein, The semiconductor device also includes a housing surrounding the sealing resin.

12. The semiconductor device according to claim 10 or 11, wherein, The semiconductor device also includes a cooler connected to the mounting substrate.

13. The semiconductor device according to claim 12, wherein, The sealing resin seals at least a portion of the cooler to the interior.

Images