Direct hybrid pad with tapered sidewalls

Abstract

An element, a bonding structure including the element, and a method of forming the same are disclosed. The element may include a non-conductive field region having a surface defining at least a portion of a bonding surface of the element. The surface of the non-conductive field region is prepared for direct bonding. The element may also include a conductive feature having an upper surface defining at least a portion of the engagement surface of the element, a lower surface opposite the upper surface, and a sidewall extending between the upper surface and the lower surface. An angle between the upper surface and the sidewall is about 75 DEG or less. The bonded structure includes an element and a second element that are directly bonded to each other without an intermediate adhesive.

Description

Technical Field

[0001] The art relates to components, bonding structures, and methods of forming components and bonding structures, and particularly to components and bonding structures having direct hybrid bonding pads, wherein the direct hybrid bonding pads have tapered sidewalls. Background Technology

[0002] Microelectronic components (such as integrated device dies or chips) can be mounted or stacked on top of other components to form bonding structures. Direct metal bonding can be performed at low temperatures without external pressure. For example, direct hybrid bonding involves directly bonding non-conductive features (e.g., inorganic dielectrics) of different components together without an intermediate binder, while simultaneously or subsequently directly bonding conductive features (e.g., metal pads or lines) of the components together. For example, microelectronic components can be mounted onto carriers (such as interposers, reconstituted wafers, or components). As another example, microelectronic components can be stacked on top of one microelectronic component; for example, a first integrated device die can be stacked on top of a second integrated device die. Each microelectronic component can have conductive pads for mechanical and electrical bonding of the components to each other. There is a continuing need for improved methods for forming bonding structures. Attached Figure Description

[0003] Specific embodiments will now be described with reference to the following figures, which are provided by way of example and not limitation.

[0004] Figure 1A This is a schematic cross-sectional side view of the two components before they are directly joined.

[0005] Figure 1B yes Figure 1A A schematic cross-sectional side view of the two components after direct joining.

[0006] Figure 2 This is a schematic cross-sectional side view of an element according to an embodiment.

[0007] Figure 3 This is a schematic cross-sectional side view of the joining elements (first element and second element) according to an embodiment, which at least partially defines the joining structure.

[0008] Figure 4A It is a schematic cross-sectional side view of a structure including an equipment section, a back-end process (BEOL) structure disposed above the equipment section, a dielectric layer disposed above the BEOL structure, and a patterned resist layer disposed above the dielectric layer.

[0009] Figure 4B yes Figure 4AA schematic cross-sectional side view of the structure in the first stage of forming the cavity.

[0010] Figure 4C yes Figure 4A A schematic cross-sectional side view of the structure in the second stage of forming the cavity, after the first stage.

[0011] Figure 4D yes Figure 4A A schematic cross-sectional side view of the structure after the cavity has been fully formed.

[0012] Figure 5A It is a schematic cross-sectional side view of a structure including an equipment section, a back-end process (BEOL) structure disposed above the equipment section, a dielectric layer disposed above the BEOL structure, and a patterned resist layer disposed above the dielectric layer.

[0013] Figure 5B yes Figure 5A A schematic cross-sectional side view of the structure after the cavity has been formed.

[0014] Figure 6A Showing an unpatterned resist layer Figure 4B or Figure 5B The structure.

[0015] Figure 6B It shows that after providing conductive material Figure 6A The structure.

[0016] Figure 6C The planarization process is shown. Figure 6B The structure.

[0017] Figure 7A This is a schematic cross-sectional side view of a portion of an element according to an embodiment.

[0018] Figure 7B This is a schematic cross-sectional side view of a portion of an element according to another embodiment. Detailed Implementation

[0019] The various embodiments disclosed herein relate to direct bonding (e.g., hybrid bonding) structures in which two or more elements can be directly bonded to each other (e.g., hybrid bonding) without the need for an intermediate adhesive. Figure 1A and Figure 1B The diagram schematically illustrates a process for forming a direct-bonded (e.g., hybrid-bonded) structure without an intermediate adhesive, according to some embodiments. Figure 1A and Figure 1BIn this configuration, the bonding structure 100 includes two elements 102 and 104 that can be directly bonded to each other at a bonding interface 118 (e.g., hybrid bonding) without an intermediate adhesive. Two or more microelectronic elements 102 and 104 (e.g., semiconductor elements, including, for example, integrated device dies, wafers, passive devices, independent active devices such as power switches, etc.) can be stacked or bonded to form the bonding structure 100. A conductive feature 106a of the first element 102 (e.g., contact pads, traces, vias through substrate electrodes, or exposed ends of vias) can be electrically connected to a corresponding conductive feature 106b of the second element 104. Any suitable number of elements can be stacked in the bonding structure 100. For example, a third element (not shown) can be stacked on top of the second element 104, a fourth element (not shown) can be stacked on top of the third element, and so on. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 102. In some embodiments, the laterally stacked additional elements may be smaller than the second element 104. In some embodiments, the horizontally stacked additional elements may be twice the size of the second element 104.

[0020] In some embodiments, elements 102 and 104 are directly bonded to each other (e.g., hybrid bonding) without intermediate adhesive. In various embodiments, a non-conductive field region comprising a non-conductive or dielectric material can be used as a first bonding layer 108a of the first element 102, which can be directly bonded to a corresponding non-conductive field region comprising a non-conductive or dielectric material, which serves as a second bonding layer 108b of the second element 104 without intermediate adhesive. Non-conductive bonding layers 108a and 108b can be disposed on respective front sides 114a and 114b of device portions 110a and 110b, such as semiconductor (e.g., silicon) portions of elements 102 and 104, or back-end process (BEOL) interconnect layers above these semiconductor portions. Active devices (e.g., transistors) and / or circuit arrangements can be patterned or otherwise disposed in or on device portions 110a and 110b. Active devices and / or circuitry may be disposed at or near the front sides 114a and 114b of device portions 110a and 110b, and / or at or near the opposite rear sides 116a and 116b of device portions 110a and 110b. Bonding layers may be provided on the front and / or rear sides of the components either at the wafer level during device fabrication or in subsequent processes, such as in redistribution layer (RDL) formation within a packaging facility. Non-conductive material may be referred to as a non-conductive bonding region or bonding layer 108a of the first component 102. In some embodiments, the non-conductive bonding layer 108a of the first component 102 may be directly bonded to a corresponding non-conductive bonding layer 108b of the second component 104 using a dielectric-to-dielectric bonding technique. For example, using bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, non-conductive or dielectric-to-dielectric bonding can be formed without intermediate adhesives, the entire contents of each of these patents being incorporated herein by reference in their entirety and for all purposes. It should be understood that, in various embodiments, bonding layers 108a and / or 108b may comprise non-conductive materials, such as dielectric materials (e.g., silicon oxide), or undoped semiconductor materials (e.g., undoped silicon). Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, including silicon (e.g., silicon oxide, silicon nitride, or silicon oxynitride) or carbon (e.g., silicon carbide, silicon oxynitride, low-k dielectric materials, SiCOH dielectrics, silicon carbonitride, diamond-like carbon, or materials comprising a diamond surface). Although containing carbon, such carbon-containing ceramic materials can be considered inorganic. In some embodiments, the dielectric material does not include polymeric materials, such as epoxy resins, resins, or molding materials.

[0021] In some embodiments, device portions 110a and 110b may have significantly different coefficients of thermal expansion (CTE) defining heterostructures. The CTE difference between device portions 110a and 110b, and particularly between the bulk semiconductors (typically single-crystal portions) of device portions 110a and 110b, may be greater than 5 ppm or greater than 10 ppm. For example, the CTE difference between device portions 110a and 110b may be in the range of 5 ppm to 100 ppm, 5 ppm to 40 ppm, 10 ppm to 100 ppm, or 10 ppm to 40 ppm. In some embodiments, one of device portions 110a and 110b may include a photoelectric single-crystal material, including a perovskite material that can be used for optical piezoelectric or thermoelectric applications, and the other device portion of device portions 110a and 110b may include a more conventional substrate material. For example, one of the device portions 110a and 110b includes lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other device portion includes silicon, quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the device portions 110a and 110b includes a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other device portion may include a non-group III-V semiconductor material, such as silicon, or may include other materials having a similar CTE, such as quartz, fused silica glass, sapphire, or glass.

[0022] In various embodiments, direct bonding (e.g., hybrid bonding) can be formed without an intermediate adhesive. For example, non-conductive bonding surfaces 112a and 112b can be polished to a highly smooth finish. Non-conductive bonding surfaces 112a and 112b can be polished using, for example, chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 112a and 112b can be less than 30. RMS. For example, the roughness of the mating surfaces 112a and 112b can be approximately 0.1. RMS up to 15 rms, 0.5 RMS to 10 rms or 1 RMS to 5 Within the range of rms. The bonding surfaces 112a and 112b can be cleaned and exposed to plasma and / or an etchant to activate the surfaces 112a and 112b. In some embodiments, surfaces 112a and 112b can be terminated with a substance after activation or during activation (e.g., during plasma and / or etching processes). Not limited by theory, in some embodiments, an activation process can be performed to disrupt the chemical bonding at the bonding surfaces 112a and 112b, and a termination process can provide additional chemicals at the bonding surfaces 112a and 112b, which increases the bonding energy during direct bonding (e.g., hybrid bonding). In some embodiments, activation and termination are provided in the same step; for example, plasma is provided to activate and terminate surfaces 112a and 112b. In other embodiments, bonding surfaces 112a and 112b can be terminated in separate processes to provide additional substances for direct bonding (e.g., hybrid bonding). In various embodiments, the terminating substance can include nitrogen. For example, in some embodiments, bonding surfaces 112a, 112b can be exposed to a nitrogen-containing plasma. In some embodiments, activation and / or termination can be achieved by exposure to oxygen-containing plasma. Furthermore, in some embodiments, the bonding surfaces 112a and 112b can be exposed to fluorine. For example, one or more fluorine peaks are present at or near the bonding interface 118 between the first element 102 and the second element 104. Therefore, in the bonding structure 100, the bonding interface 118 between the two non-conductive materials (e.g., bonding layers 108a and 108b) can include a very smooth interface with a high nitrogen content and / or fluorine peaks at the bonding interface 118. Additional examples of activation and / or termination treatments can be found in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. After the activation process, the roughness of the polished bonding surfaces 112a and 112b can be slightly rougher (e.g., about 1). RMS up to 30 rms, 3 RMS to 20 RMS, or perhaps even coarser.

[0023] In various embodiments, the conductive feature 106a of the first element 102 may also be directly bonded to the corresponding conductive feature 106b of the second element 104 without intermediate adhesives (e.g., without solder or other conductive adhesives between conductive features 106a and 106b). For example, direct bonding (e.g., hybrid bonding) techniques may be used to provide conductor-to-conductor direct bonding along a bonding interface 118 comprising covalently bonded non-conductive to non-conductive (e.g., dielectric to dielectric) surfaces prepared as described above. In various embodiments, direct bonding (e.g., hybrid bonding) techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988 may be used to form conductor-to-conductor (e.g., conductive feature 106a to conductive feature 106b) bonding and dielectric-to-dielectric bonding, the entire contents of each of these patents being incorporated herein by reference in their entirety and for all purposes. In the direct bonding (e.g., hybrid bonding) embodiments described herein, conductive features are provided within a non-conductive bonding layer, and both conductive and non-conductive features are prepared for direct bonding (e.g., hybrid bonding), such as through the planarization, activation, and / or termination processes described above. Therefore, the bonding surface prepared for direct bonding (e.g., hybrid bonding) includes both conductive and non-conductive features.

[0024] For example, as described above, non-conductive (e.g., dielectric) bonding surfaces 112a, 112b (e.g., inorganic dielectric surfaces) can be prepared and directly bonded to each other without intermediate adhesive. Conductive contact features (e.g., conductive features 106a and 106b, which may be at least partially surrounded by non-conductive dielectric field regions within bonding layers 108a and 108b) can also be directly bonded to each other without intermediate adhesive. In various embodiments, conductive features 106a, 106b may include discrete pads or traces at least partially embedded in non-conductive field regions. In some embodiments, conductive contact features may include exposed contact surfaces of vias (e.g., through-silicon vias (TSVs)) through the substrate. In some embodiments, the corresponding conductive features 106a and 106b may be recessed below the outer surface (e.g., the upper surface) (non-conductive bonding surfaces 112a and 112b) of the dielectric field region or non-conductive bonding layers 108a and 108b, for example, recessed to less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. The recess may be located in or near the center of a cavity in which the conductive features 106a and 106b are disposed, and additionally or alternatively, the recess may extend or be disposed along the side of the cavity in which the conductive features 106a and 106b are disposed. In various embodiments, prior to direct bonding (e.g., hybrid bonding), the size of the recess in the opposing elements may be set such that the total gap between opposing contact pads is less than 15 nm, or less than 10 nm. In some embodiments, non-conductive bonding layers 108a and 108b can be directly bonded to each other at room temperature without an intermediate adhesive, and the bonded structure 100 can subsequently be annealed. During annealing, conductive features 106a and 106b can expand and contact each other to form a direct metal-to-metal bond. Advantageously, high-density conductive features 106a and 106b can be achieved using Direct Bond Interconnect (DBI®) technology, available from Adeia of San Jose, CA, which will be connected across the bonding interface 118 (e.g., a regular array of small or fine-pitched patterns). In some embodiments, the spacing p of the conductive features 106a and 106b, such as conductive traces embedded in the bonding surface of one of the bonding elements, can be less than 100 μm, less than 10 μm, or even less than 2 μm. For some applications, the ratio of the spacing between conductive features 106a and 106b to one of the dimensions of the bonding pad (e.g., diameter) is less than 20, or less than 10, or less than 5, or less than 3, and sometimes preferably less than 2.In other applications, the width of the conductive trace in the bonding surface of one of the bonding elements embedded in the bonding element can range from about 0.3 µm to 50 µm, for example, from about 0.3 µm to 20 µm, about 0.3 µm to 3 µm, about 0.5 µm to 50 µm, about 0.75 µm to 25 µm, or about 1 µm to 5 µm. In various embodiments, conductive features 106a and 106b and / or the trace can comprise copper or a copper alloy, although other metals may also be suitable. For example, the conductive features disclosed herein (such as conductive features 106a and 106b) can comprise aluminum or a fine-grained metal (e.g., fine-grained copper). Furthermore, the primary lateral dimension (e.g., pad diameter) can also be small, for example, from about 0.25 µm to 30 µm, from about 0.25 µm to 5 µm, or from about 0.5 µm to 5 µm.

[0025] Therefore, in a direct bonding (e.g., hybrid bonding) process, the first element 102 can be directly bonded (e.g., hybrid bonded) to the second element 104 without intermediate adhesive. In some arrangements, the first element 102 may include a singlet-bonded element, such as a singlet-bonded integrated device die. In other arrangements, the first element 102 may include a carrier or substrate (e.g., a wafer) comprising multiple (e.g., dozens, hundreds, or more) device regions that, upon singlet-bonding, form multiple integrated device dies. Similarly, the second element 104 may include a singlet-bonded element, such as a singlet-bonded integrated device die. In other arrangements, the second element 104 may include a carrier or substrate (e.g., a wafer). Therefore, the embodiments disclosed herein can be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers can be directly bonded (e.g., hybrid bonded) to each other and singlet-bonded using a suitable singlet-bonding process. After unification, the side edges of the unified structure (e.g., the side edges of the two joining elements) can be substantially flush and can include markings indicating the common unification process of the joining structure (e.g., a sawing mark if a sawing unification process is used).

[0026] As illustrated herein, the first element 102 and the second element 104 can be directly bonded to each other (e.g., hybrid bonding) without intermediate binders, unlike deposition processes, and produce interfaces with different structures compared to deposition. In one application, the width of the first element 102 in the bonded structure is similar to the width of the second element 104. In some other embodiments, the width of the first element 102 in the bonded structure 100 is different from the width of the second element 104. Similarly, the width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Therefore, the first element 102 and the second element 104 can include non-deposited elements. Furthermore, unlike deposited layers, the bonded structure 100 can include defect regions along the bonded interface 118, where nanoscale voids (nanovoids) are present. The nanoovoids can be formed due to activation (e.g., exposure to plasma) of the bonded surfaces 112a and 112b. As explained above, the bonded interface 118 can include a certain concentration of material from the activation and / or final chemical processing processes. For example, in embodiments where activation is performed using nitrogen plasma, a nitrogen peak may be formed at the bonding interface 118. The nitrogen peak can be detected using secondary ion mass spectrometry (SIMS). In various embodiments, for example, nitrogen-end-capping treatment (e.g., exposing the bonding surface to nitrogen-containing plasma) may replace the OH groups on the hydrolyzed (OH-end-capped) surface with NH2 molecules to create a nitrogen-end-capped surface. In embodiments where activation is performed using oxygen plasma, an oxygen peak may be formed at the bonding interface 118. In some embodiments, the bonding interface 118 may comprise silicon oxynitride, silicon carbonitride, or silicon carbonitride. As illustrated herein, direct bonding may comprise covalent bonds, which are stronger than van der Waals bonds. Bonding layers 108a and 108b may also comprise polished surfaces planarized to a highly smooth finish.

[0027] In various embodiments, metal-to-metal bonding between conductive features 106a and 106b can be incorporated such that metal grains grow into each other across bonding interface 118. In some embodiments, the metal is copper or includes copper, which may have grains oriented along a 111 crystal plane for improved copper diffusion across bonding interface 118. In some embodiments, conductive features 106a and 106b may include a nanotwinned copper grain structure, which facilitates the incorporation of conductive features during annealing. Bonding interface 118 may extend substantially entirely to at least a portion of the bonded conductive features 106a and 106b, such that there are substantially no gaps between non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer (e.g., which may include copper) may be provided under and / or laterally surrounding conductive features 106a and 106b. However, in other embodiments, there may be no barrier layer under conductive features 106a and 106b, for example, as described in U.S. Patent No. 11,195,748, which is incorporated herein by reference in its entirety and for all purposes.

[0028] As described above, the non-conductive bonding layers 108a and 108b can be directly bonded without an intermediate adhesive, and the bonded structure 100 can subsequently be annealed. The annealing temperature can vary depending on the thermal budget of the device, the size of the conductive features 106a and 106b, the gap size between the conductive features 106a and 106b, the material of the conductive features 106a and 106b, the surrounding non-conductive layers 108a and 108b, and their relative CTE, etc. Example annealing temperatures include between about 50°C and 400°C, between about 100°C and 300°C, and between about 150°C and 250°C. During annealing, the conductive features 106a and 106b can expand and come into contact with each other to form a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 106a and 106b can diffuse into each other during the annealing process.

[0029] The embodiments described herein can reduce stress in conductive features 106a, 106b. Compared to conventional pads, the contact pads or bonding pads shaped as described below can reduce residual stress, thereby reducing wafer or die bending.

[0030] As described herein, the bonding surfaces 112a and 112b of the components can be polished in preparation for direct bonding (e.g., hybrid bonding). When the bonding surfaces 112a and 112b of the non-conductive bonding layers 108a and 108b are polished, dielectric rounding may occur in the regions of the bonding surfaces 112a and 112b adjacent to the conductive features 106a and 106b. Dielectric rounding can reduce the overall bonding strength and integrity. Over time, this can cause delamination or separation of the bonding layers, especially when the bonding structure is subjected to thermal or mechanical stress. Furthermore, dielectric rounding can create voids or air gaps between the bonding layers, which can negatively affect the electrical and optical properties of the device. The various embodiments disclosed herein relate to structures that prevent and / or reduce the formation of dielectric rounding during the polishing process by reducing stress at the edges of the conductive features 106a and 106b.

[0031] As described above, the direct bonding (e.g., hybrid bonding) technique described herein can achieve extremely fine spacing and / or small pad size between adjacent conductive features 106a and 106b. However, when the spacing between adjacent conductive features 106a and 106b is small, undesirable parasitic capacitances can exist between adjacent conductive features 106a and 106b, especially for higher frequency performance. The various embodiments disclosed herein relate to structures that can reduce such integrated capacitance without increasing the spacing.

[0032] Figure 2 This is a schematic cross-sectional side view of element 1 according to an embodiment. Element 1 may include: a device portion 10, a back-end process (BEOL) structure 12 including an interconnect structure 14, a dielectric layer 16, and conductive features (e.g., conductive pads 18). As is known in the art, for integrated circuits, the BEOL structure 12 may include multiple interconnect layers, including patterned traces and vias separated from each other by interlayer dielectrics (ILDs). However, those skilled in the art will understand that the principles and advantages taught herein are applicable to simpler structures, such as stand-alone surface mount devices, which may include simple contact leads without BEOL layers. The contact surfaces of element 1 include the surface 16a of the dielectric layer 16 and the upper surface 18a of the contact pads 18, which may also be referred to as the bonding surface or contact surface. The dielectric layer 16 may also be referred to as a non-conductive field region.

[0033] Device portion 10 may be a semiconductor (e.g., silicon) portion of element 1. Active devices (e.g., transistors) and / or circuit arrangements may be patterned and / or otherwise disposed in or on device portion 10. Although illustrated as landing pads, those skilled in the art will understand that interconnect structure 14 may take the form of wiring metal lines or traces, interlayer vias, vias through the substrate, or landing pads that may be electrically connected to conductive pads 18. As shown, interconnect structure 14 may be part of or on BEOL structure 12, or may be part of or on RDL. In some embodiments, vias of interconnect structure 14 may have widths in the range of, for example, about 0.1 µm to 0.5 µm, or about 0.2 µm to 0.4 µm.

[0034] The dielectric layer 16 has a bonding surface 16a, which can be polished to a highly smooth finish. The bonding surface 16a can be polished using, for example, CMP. The roughness of the bonding surface 16a can be less than 30. rms. For example, the roughness of the mating surface 16a can be approximately 0.1. RMS up to 15 RMS, approximately 0.5 RMS to 10 rms or about 1 RMS to 5 Within the range of rms.

[0035] Contact pad 18 (such as a copper pad) has an upper surface or mating surface 18a, a sidewall 18b, and a lower surface or bottom surface 18c. The sidewall 18b may extend between the upper surface 18a and the lower surface 18c. The interior angle δ1 between the mating surface 18a and the sidewall 18b is an acute angle and may be equal to or less than about 75°, less than about 70°, less than about 60°, or less than about 50°. For example, the angle δ1 between the mating surface 18a and the sidewall 18b may be in the range of about 30° to 75°, about 35° to 75°, about 30° to 70°, about 35° to 70°, about 30° to 60°, about 35° to 60°, about 30° to 50°, or about 35° to 50°. For example, the angle δ1 between the mating surface 18a and the sidewall 18b may be about 45°, such as 45° ± 5°. In some embodiments, an intermediate layer (not shown) exists between the contact pad 18 and the dielectric layer 16. The intermediate layer may include a seed layer and / or a barrier layer (e.g., a diffusion barrier layer). In some embodiments, the intermediate layer may have a multilayer structure.

[0036] In some embodiments, cavities formed in the dielectric layer 16 may be formed by means of dry etching (e.g., plasma etching) using a patterned photoresist (whether negative-directional) or by means of controlled isotropic etching (e.g., wet etching or certain dry vapor phase etching), in which contact pads 18 are disposed. To form conventional contact pads for components that are directly bonded (e.g., hybrid bonded), particularly for high-density pads, a skilled craftsman can avoid highly sloping sidewalls in order to form contact pads of precise size for direct bonding (e.g., hybrid bonded). Instead, contact pads for direct bonding (e.g., hybrid bonded) are conventionally arranged at an angle close to 90° relative to the horizontal contact surface of the component, or close to vertical sidewalls. However, in this disclosure, contact pads 18 are arranged with highly sloping sidewalls having a relatively small angle δ1.

[0037] As disclosed herein, forming cavities with sloping sidewalls in the dielectric layer 16 for the contact pads 18 can provide significant advantages because these angles can reduce stress and result in dielectric rounding during polishing (e.g., CMP).

[0038] The contact pad 18 has a bonding surface or upper surface 18a with a width w1, and the contact pad 18 contacts the lower side or lower surface 18c of the interconnect structure 14 with a width w2 smaller than the width w1. In some embodiments, the contact pad 18 may be formed at the wafer level, and the width w1 of the bonding surface 18a of the contact pad 18 may be in the range of about 0.5 µm to 20 µm, about 0.5 µm to 10 µm, about 0.5 µm to 5 µm, about 0.5 µm to 1 µm, about 1 µm to 5 µm, or about 1 µm to 10 µm. In some embodiments, the contact pad 18 may be formed at the package level, and the width w1 of the bonding surface 18a of the contact pad 18 may be in the range of 20 µm to 200 µm, 20 µm to 100 µm, 40 µm to 200 µm, or 400 µm to 100 µm. Due to its tapered shape, the width w1 can be adjusted during the polishing process—the width w1 of the contact pad 18 can be smaller when more of the contact pad 18 is polished.

[0039] The thickness of the contact pad 18 is t1. In some embodiments, the thickness of the dielectric layer 16 may be equal to or greater than the thickness t1. For example, the thickness t1 of the contact pad 18 may be in the range of 0.5 µm to 3 µm, 1 µm to 3 µm, or 1 µm to 2 µm. In some embodiments, the bonding surface 18a may be recessed relative to the bonding surface 16a of the dielectric layer 16. For example, the bonding surface 18a may be recessed relative to the bonding surface 16a of the dielectric layer 16 in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm.

[0040] Regardless of whether the contact pad 18 is recessed, the distance d1 between the contact surfaces 18a of adjacent contact pads 18 can be measured at the contact surface 16a. The average distance d2 is the average distance between the sidewalls 18b of adjacent contact pads 18. If the interior angle δ1 between the contact surface 18a and the sidewall 18b of the contact pad is 90°, then distance d1 and average distance d2 will be the same. However, because the sidewall 18b has an acute angle δ1 as disclosed herein, the average distance d2 is greater than the distance d1 at the upper surface. Therefore, as disclosed herein, parasitic capacitance can be reduced when the sidewall 18b is tilted inward.

[0041] Element 1 can be bonded to another element (second element) to form a bonded structure. In some embodiments, the second element may have the same or substantially similar structure as element 1. In some other embodiments, the second element may be configured to be directly bonded (e.g., hybrid bonded) to element 1, but with a different structure than element 1. As mentioned above, the bonded elements can be independently the same or different dies, wafers, passive or active components, etc.

[0042] Figure 3 This is a schematic cross-sectional side view of the joining elements (first element 1 and second element 2) that at least partially define the joining structure 3 according to an embodiment. Unless otherwise stated, Figure 3 Components that are similarly named or labeled in the text can be related to... Figure 2 The corresponding components are the same or roughly similar.

[0043] The first element 1 may include a first device portion 10, a first BEOL structure 12 including a first interconnect structure 14, a first dielectric layer 16, and a first conductive feature (e.g., a conductive pad 18). The second element 2 may include a second device portion 20, a second BEOL structure 22 including a second interconnect structure 24, a second dielectric layer 26, and a second conductive feature (e.g., a conductive pad 28). The first element 1 and the second element 2 may be directly bonded to each other along a bonding interface 30 (e.g., hybrid bonding) without intermediate adhesive. The first dielectric layer 16 and the second dielectric layer 26 may be directly bonded to each other along the bonding interface 30 without intermediate adhesive, and the first conductive pad 18 and the second conductive pad 28 may be directly bonded to each other along the bonding interface 30 without intermediate adhesive.

[0044] In some arrangements, the first element 1 may include a singlet-formed element, such as a singlet-formed integrated device die. In other arrangements, the first element 1 may include a carrier or substrate (e.g., a wafer) comprising a plurality (e.g., dozens, hundreds, or more) of device regions that, upon singlet-formation, form a plurality of integrated device dies. Similarly, the second element 2 may include a singlet-formed element, such as a singlet-formed integrated device die. In other arrangements, the second element 2 may include a carrier or substrate (e.g., a wafer). Therefore, the embodiments disclosed herein can be applied to wafer-to-wafer, die-to-die, or die-to-wafer bonding processes. In a wafer-to-wafer process, two or more wafers may be directly bonded to each other (e.g., hybrid bonding) and subsequently singlet-formed using a suitable singlet-formation process. After singlet-formation, the side edges of the singlet-formed structure (e.g., the side edges of two bonding elements) may be substantially flush and may include markings indicating a common singlet-formation process of the bonding structure (e.g., a sawing mark if a sawing singlet-formation process is used).

[0045] The first element 1 may include any suitable number of conductive pads 18. The conductive pads 18 may be distributed in or near the bonding surface of the first element 1 in any suitable manner. For example, the conductive pads 18 may be distributed uniformly or periodically, aperiodically, symmetrically, asymmetrically, and / or randomly along the bonding surface of the first element 1. Similarly, the second element 2 may include any suitable number of conductive pads 28. The conductive pads 28 may be distributed in or near the bonding surface of the second element 2 in any suitable manner. For example, the conductive pads 28 may be distributed uniformly or periodically, aperiodically, symmetrically, asymmetrically, and / or randomly along the bonding surface of the second element 2. In some embodiments, the conductive pads 18, 28 may be distributed to reduce or control parasitic capacitance between two or more conductive pads 18, 28 and / or reduce or control stress. At least some of the pads 18 of the first element 1 are positioned opposite the pads 28 of the second element, such that they can be aligned for mixed direct bonding. However, all pads 18 and 28 on non-components 1 and 2 need to be aligned with each other, especially when the component includes dummy pads.

[0046] Reference Figure 4A-6C To describe a method of forming a conductive pad, wherein the acute angle δ1 between the bonding surface and the sidewall is in the range of, for example, 30° to 75°, 35° to 75°, 30° to 70°, 35° to 70°, 30° to 60°, 35° to 60°, 30° to 50° or 35° to 50°. Figure 4A and Figure 4B The process of forming a plurality of cavities 40 according to an embodiment is shown. Figure 5A and Figure 5B Another process for forming a plurality of cavities 50 according to an embodiment is shown. Figures 6A to 6C The process of defining the bonding surface of element 1 according to an embodiment is shown.

[0047] Figure 4A It is a schematic cross-sectional side view of a structure including the device part 10, the BEOL structure 12 disposed above the device part, the dielectric layer 16 disposed above the BEOL structure 12, and the patterned resist layer 42 disposed above the dielectric layer 16. Figure 4B This is a schematic cross-sectional side view of the structure in the first stage of forming cavity 40. Figure 4C This is a schematic cross-sectional side view of the structure of the second stage forming cavity 40, which follows the first stage. Figure 4D This is a schematic cross-sectional side view of the structure after the cavity 40 is fully formed. The patterned resist layer 42 may have an opening 44, which is determined according to... Figure 4D The cavity 40 formed in the cavity is shaped to the desired shape.

[0048] The patterned resist layer 42 can be patterned using photolithography. The patterned resist layer 42 can be patterned by controlling the sidewall angle using different baking methods, or by using a multiple exposure (e.g., double exposure) method, which has a first exposure utilizing the pattern and a second blanket exposure, followed by a development process. Therefore, known techniques can provide a controlled tilt shape for the photoresist at the opening 44. The resist layer 42 can be used directly as a mask, or its pattern can be transferred to a hard mask layer before etching the dielectric layer 16. As those skilled in the art will understand, a similar effect can be achieved by providing a stepped profile for the resist.

[0049] The exposed areas of the dielectric layer 16 can be etched away using dry etching methods, such as reactive ion etching (RIE) or deep reactive ion etching (DRIE). The etching process can be guided by a patterned resist layer 42 to remove material from the dielectric layer 16 in a controlled manner. As etching proceeds, the formed photoresist is also etched away, and as the etching penetrates into the dielectric layer 16, the openings retract and widen (e.g., ...). Figure 4B and Figure 4C (As shown by the horizontal arrow in the image). Therefore, in the later stages of etching, the dielectric layer 16 at the outer edge of the opening 44 is re-exposed to etching and thus etched for a shorter time, while the central portion of the opening 44 is exposed from the beginning and thus etched for a longer time (generally in the later stages). Figure 4B and Figure 4C (In the direction indicated by the vertical arrow). Therefore, a tapered sidewall 40a of the cavity 40 can be formed. The etching process can be designed to be anisotropic. In addition to designing the shape of the resist, the shape of the etched cavity 40 is also affected by the selectivity between the resist and the exposed dielectric of any etching chemical component. Therefore, the slope of the opening can be controlled.

[0050] Figure 5A It is a schematic cross-sectional side view of a structure including device part 10, BEOL structure 12 disposed above device part, dielectric layer 16 disposed above BEOL structure 12 and patterned resist layer 52 disposed above dielectric layer 16. Figure 5B This is a schematic cross-sectional side view of the structure after cavity 50 has been formed. The patterned resist layer 52 can be patterned using photolithography. (Refer to reference...) Figures 4A to 4D The anisotropic etching process described is the opposite. Figure 5A and Figure 5B An isotropic etching process (e.g., isotropic wet etching or isotropic vapor phase etching) for forming cavity 50 is shown.

[0051] The exposed areas of the dielectric layer 16 can be etched away using a chemical etchant solution that selectively dissolves the dielectric material of the dielectric layer 16, thereby forming a cavity 50 with tapered sidewalls 50a. The etchant solution can be selected to have relatively high selectivity for the dielectric material above the patterned resist layer 52, such that the patterned resist layer 52 can serve as a mask to guide the etching process. In some embodiments, the etchant solution may include hydrofluoric acid. For example, the etchant solution may be a mixture of hydrofluoric acid and water, such as a 1:10 HF:H2O or buffered HF.

[0052] In some isotropic etching processes, tapered sidewalls naturally form within the cavity. Typically, such tapered sidewalls are avoided or minimized in metallization processes, particularly for fine dimensions, to achieve vertical sidewalls, resulting in better fidelity between the mask opening and the metal dimension. In the illustrated embodiment, the dielectric layer 16 is etched vertically and horizontally. In some embodiments, the rates of vertical and horizontal etching can be controlled. The rates of vertical and horizontal etching can be influenced at least in part by, for example, the resist adhesion and / or dielectric structuring properties of the dielectric layer 16. The horizontal component of the etching can occur for a longer duration at the top portion of the dielectric layer 16 closer to the bonding surface 16a compared to the lower portion of the BEOL structure 12, where the horizontal component of the bonding surface 16a is etched closer to the lower portion of the dielectric layer 16 than the lower portion of the BEOL structure 12. The duration of the horizontal component of the etching gradually decreases as it moves closer to the lower portion. Therefore, in the horizontal direction, the dielectric layer 16 is etched less in the lower portion than in the top portion, in order to define the tapered sidewall 50a. The outer edge of the cavity 50 thus extends under the resist 52, and those newly exposed dielectric surfaces are exposed to etching for less time than the central portion of the opening 54, and thus the cavity 50 has sloping sidewalls.

[0053] Figure 6A It shows Figure 4B and Figure 5B The structure without patterned resist layer 42 or 52. Figure 6B This shows the effect after providing conductive material 60. Figure 6A The structure. Conductive material 60 may be provided at least partially in the cavities 40, 50. In some embodiments, conductive material 60 may be provided to overfill the cavities 40, 50 such that at least a portion of the dielectric layer 16 above the mating surface 16a is covered by conductive material 60. Dashed line 62 indicates the target grinding or polishing stop line for forming the mating surface of element 1.

[0054] In some embodiments, an intermediate layer (not shown) may be provided between the contact pad 18 and the dielectric layer 16. The intermediate layer may include a seed layer and / or a barrier layer (e.g., a diffusion barrier layer). In some embodiments, the intermediate layer may have a multilayer structure.

[0055] Figure 6C The device 1 after a planarization process (e.g., CMP process) is shown. In the planarization process, at least a portion of the conductive material 60 and / or at least a portion of the dielectric layer 16 may be removed. The bonding surface 16a of the dielectric layer 16 may be polished to a highly smooth finish. The bonding surface 16a may be polished to have approximately 0.1... RMS up to 15 rms, 0.5 RMS to 10 rms or 1 RMS to 5 The surface roughness is within the range of rms. In some embodiments, the upper surface 18a of the contact pad 18 may be recessed (not shown) relative to the bonding surface 16a of the dielectric layer 16. For example, the bonding surface 18a may be recessed in the range of 2 nm to 20 nm or 4 nm to 10 nm relative to the bonding surface 16a of the dielectric layer 16.

[0056] The acute interior angle δ1 between the bonding surface 18a and the pad sidewall 18b can be equal to or less than 75°, 70°, 60°, or 50°. For example, the angle δ1 between the bonding surface 18a and the sidewall 18b can be in the range of 30° to 75°, 35° to 75°, 30° to 70°, 35° to 70°, 30° to 60°, 35° to 60°, 30° to 50°, or 35° to 50°. The obtuse exterior angle α1 between the dielectric bonding surface 16a and the sidewalls 40a and 50a of the cavities 40 and 50 can be approximately 180° minus the interior angle δ1 between the bonding surface 18a and the sidewall 18b. In the various embodiments disclosed herein, the exterior angle α1 between the dielectric bonding surface 16a and the sidewalls 40a and 50a can be greater than 100°, 105°, 110°, 120°, or 130°. For example, the angle α1 between the dielectric bonding surface 16a and the sidewalls 40a and 50a of the cavities 40 and 50 can be in the range of 105° to 150°, 105° to 145°, 110° to 150°, 110° to 145°, 120° to 150°, 120° to 145°, 130° to 150°, or 130° to 145°.

[0057] A known problem associated with planarization processes in conventional components (e.g., CMP processes) is dielectric rounding or etching at or near the junction surface of the dielectric layer and the junction surface of the conductive pad. During a CMP process, the material removal rate can vary depending on, for example, the local surface topology of the component and the stresses exposed to the polished dielectric and conductive materials. These stresses can cause the polishing pads to preferentially polish the dielectric material at the corners adjacent to the contact pads, resulting in dielectric corner rounding. Embodiments of this disclosure can prevent or mitigate dielectric rounding at or near the corner 64 between the junction surface 16a of the dielectric layer 16 and the junction surface 18a of the conductive pad 18. As disclosed herein, selecting angles α1, δ1 of the sidewalls 40a, 50a, 18b can provide this advantage.

[0058] In some embodiments, the sidewalls 40a, 50a of the cavities 40, 50 may have a generally straight and / or tapered profile. In some other embodiments, the sidewalls 40a, 50a of the cavities 40, 50 may have curvature (see [link to relevant documentation]). Figure 7A and Figure 7B () or steps. The sidewall 18b of the conductive pad 18 may be consistent with the sidewalls 40a and 50a of the cavities 40 and 50.

[0059] Figure 7A This is a schematic cross-sectional side view of a portion of an element according to an embodiment. Figure 7B This is a schematic cross-sectional side view of a portion of an element according to another embodiment. Unless otherwise stated, Figure 7A and Figure 7B Components with similar names or labels can be compared with Figure 2 The corresponding components are the same or roughly similar. Figure 7A In the middle, sidewalls 40a and 50a have convex curvature, and the sidewall 18b of the conductive pad 18 has concave curvature. Figure 7B In the process, sidewalls 40a and 50a have concave curvature, and pad sidewall 18b has convex curvature. The angles δ2 and δ3 between the mating surface 18a and the sidewall 18b can be the same or substantially the same as δ1 disclosed herein, and can be measured at corner 64, or can be the average slope of the sidewall 18b.

[0060] In one aspect, a first element is disclosed, configured to be directly bonded to a second element. The first element may include a non-conductive field region having a surface defining at least a portion of a bonding surface of the first element. The surface of the non-conductive field region is prepared for direct bonding to the second element. The first element may include a conductive feature having an upper surface defining at least a portion of the bonding surface of the first element, a lower surface opposite the upper surface, and a sidewall extending between the upper and lower surfaces. The angle between the upper surface and the sidewall is approximately 75° or less.

[0061] In one embodiment, the angle between the upper surface and the sidewall is in the range of about 30° to 70°.

[0062] In one embodiment, the angle between the upper surface and the sidewall is in the range of about 30° to 60°.

[0063] In one embodiment, the angle between the upper surface and the sidewall is in the range of about 35° to 50°.

[0064] In one embodiment, the conductive feature is a contact pad, and the thickness of the contact pad is in the range of about 1 μm to 2 μm. The width of the contact pad can be in the range of about 0.5 μm to 20 μm. The first element may also include a back-end process structure below a non-conductive field region. The back-end process structure may have vias electrically connected to the contact pad.

[0065] In one embodiment, the upper surface of the conductive feature is recessed by approximately 2 nm to 20 nm relative to the surface of the non-conductive field region.

[0066] In one aspect, a bonding structure is disclosed. The bonding structure may include a first element comprising a first non-conductive field region and a first conductive feature. The first non-conductive field region has a first surface defining at least a portion of a bonding surface of the first element. The first conductive feature has a first upper surface defining at least a portion of the bonding surface of the first element, a first lower surface opposite to the first upper surface, and a first sidewall extending between the first upper surface and the first lower surface. The angle between the first upper surface and the first sidewall is approximately 75° or less. The bonding structure may include a second element comprising a second non-conductive field region having a second surface directly bonded to the first surface of the first non-conductive field region, and the second conductive feature being directly bonded to the first conductive feature.

[0067] In one embodiment, the angle between the first upper surface and the first sidewall is in the range of about 30° to 70°.

[0068] In one embodiment, the angle between the first upper surface and the first sidewall is in the range of about 30° to 60°.

[0069] In one embodiment, the angle between the first upper surface and the first sidewall is in the range of about 35° to 50°.

[0070] In one embodiment, the first conductive feature is a contact pad, and the thickness of the contact pad is in the range of 1 µm to 2 µm, and the width of the contact pad is in the range of about 0.5 µm to 20 µm.

[0071] In one embodiment, the first upper surface of the first conductive feature is recessed by about 2 nm to 20 nm relative to the first surface of the first non-conductive field region.

[0072] In one embodiment, the second conductive feature has a second upper surface directly bonded to the first conductive feature, a second lower surface opposite to the second upper surface of the second conductive feature, and a second sidewall extending between the second upper surface and the second lower surface of the second conductive feature. The angle between the second upper surface and the second sidewall of the second conductive feature may be about 75° or less.

[0073] In one aspect, a method for forming conductive pads of an element is disclosed. The method may include: forming a patterned resist layer over at least a portion of the surface of a dielectric layer; removing a portion of the dielectric layer by etching to form a cavity having an angle between the sidewalls of the cavity and the surface of the dielectric layer; providing a conductive material to at least partially fill the cavity with the conductive material; and polishing at least the surface of the dielectric layer to prepare it for direct bonding. The angle is greater than about 105°.

[0074] In one embodiment, the patterned resist layer has a shape consistent with the shape of the cavity, and the etching includes dry etching.

[0075] In one embodiment, etching includes isotropic etching.

[0076] In one embodiment, the angle between the sidewall of the cavity and the surface of the dielectric layer is in the range of about 110° to 150°.

[0077] In one embodiment, the sidewalls of the cavity have curvature.

[0078] Unless the context explicitly requires otherwise, throughout the specification and claims, the terms "comprise," "comprising," "include," and "including" should be understood in an inclusive sense, rather than an exclusive or exhaustive sense; that is, they should be understood as "including, but not limited to." The term "coupled," as generally used herein, refers to two or more elements that are directly connected or connected by means of one or more intermediate elements. Similarly, the term "connected," as generally used herein, refers to two or more elements that are directly connected or connected by means of one or more intermediate elements. Additionally, when used in this application, the terms "herein," "above," "below," and similar terms should refer to the entire application and not any particular part of it. Where the context permits, the singular or plural terms used in the above embodiments may also include the plural or singular, respectively. When the word "or" refers to a list of two or more items, it encompasses all of the following interpretations: any one of the items in the list, all the items in the list, and any combination of the items in the list.

[0079] Furthermore, unless otherwise specifically stated or understood in the context of use, the conditional language used herein, such as “can,” “could,” “might,” “may,” “eg,” “for example,” “such as,” etc., is generally intended to convey that certain embodiments include features, elements, and / or states, while other embodiments do not include certain features, elements, and / or states. Therefore, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way.

[0080] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. For example, although the illustrated embodiments include preparation for direct hybrid bonding, those skilled in the art will understand that the techniques taught herein can be used for direct metal bonding even without direct dielectric bonding. In fact, the novel apparatuses, methods, and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functionality with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments can be made and still fall within the scope of the invention. The appended claims and their equivalents are intended to cover these forms or modifications that fall within the scope and spirit of this disclosure.

Claims

1. A first element configured to be directly coupled to a second element, the first element comprising: A non-conductive field region having a surface that defines at least a portion of the bonding surface of the first element, the surface of the non-conductive field region being prepared for direct bonding to the second element; as well as A conductive feature having: an upper surface defining at least a portion of the bonding surface of the first element; and a lower surface opposite to the upper surface; and a sidewall extending between the upper surface and the lower surface, wherein the angle between the upper surface and the sidewall is approximately 75° or less.

2. The first element according to claim 1, wherein the angle between the upper surface and the sidewall is in the range of about 30° to 70°.

3. The first element according to claim 1, wherein the angle between the upper surface and the sidewall is in the range of about 30° to 60°.

4. The first element according to claim 1, wherein the angle between the upper surface and the sidewall is in the range of about 35° to 50°.

5. The first element according to claim 1, wherein the conductive feature is a contact pad, and the thickness of the contact pad is in the range of about 1 μm to 2 μm.

6. The first element of claim 5, wherein the width of the contact pad is in the range of about 0.5 μm to 20 μm.

7. The first element of claim 6, further comprising a back-end process structure located below the non-conductive field region, the back-end process structure having a via electrically connected to the contact pad.

8. The first element of claim 1, wherein the upper surface of the conductive feature is recessed by about 2 nm to 20 nm relative to the surface of the non-conductive field region.

9. A joining structure, said joining structure comprising: A first element, the first element including a first non-conductive field region and a first conductive feature, the first non-conductive field region having a first surface defining at least a portion of a bonding surface of the first element, the first conductive feature having: a first upper surface defining at least a portion of the bonding surface of the first element; a first lower surface opposite to the first upper surface; and a first sidewall extending between the first upper surface and the first lower surface, wherein the angle between the first upper surface and the first sidewall is about 75° or less; as well as The second element includes a second non-conductive field region and a second conductive feature, the second non-conductive field region having a second surface directly bonded to the first surface of the first non-conductive field region, and the second conductive feature being directly bonded to the first conductive feature.

10. The joining structure of claim 9, wherein the angle between the first upper surface and the first sidewall is in the range of about 30° to 70°.

11. The joining structure of claim 9, wherein the angle between the first upper surface and the first sidewall is in the range of about 30° to 60°.

12. The joining structure of claim 9, wherein the angle between the first upper surface and the first sidewall is in the range of about 35° to 50°.

13. The bonding structure of claim 9, wherein the first conductive feature is a contact pad, and the thickness of the contact pad is in the range of 1 µm to 2 µm, and the width of the contact pad is in the range of about 0.5 µm to 20 µm.

14. The bonding structure of claim 9, wherein the first upper surface of the first conductive feature is recessed by about 2 nm to 20 nm relative to the first surface of the first non-conductive field region.

15. The joining structure of claim 9, wherein the second conductive feature has: a second upper surface directly joined to the first conductive feature; a second lower surface opposite to the second upper surface of the second conductive feature; and a second sidewall extending between the second upper surface and the second lower surface of the second conductive feature, wherein the angle between the second upper surface and the second sidewall of the second conductive feature is approximately 75° or less.

16. A method for forming conductive pads for a component, the method comprising: A patterned resist layer is formed over at least a portion of the surface of the dielectric layer; A cavity is formed by etching away a portion of the dielectric layer, the cavity having an angle greater than approximately 105° between its sidewall and the surface of the dielectric layer. Provide a conductive material to at least partially fill the cavity with the conductive material; and Polish the surface of at least the dielectric layer to prepare it for direct bonding.

17. The method of claim 16, wherein the patterned resist layer has a shape consistent with the shape of the cavity, and the etching comprises dry etching.

18. The method of claim 16, wherein the etching comprises isotropic etching.

19. The method of claim 16, wherein the angle between the sidewall of the cavity and the surface of the dielectric layer is in the range of about 110° to 150°.

20. The method of claim 16, wherein the sidewall of the cavity has curvature.

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