Pixel structure for improving poor pixel points
By optimizing the planar layout of the electronic paper pixel structure, ensuring a safe distance between the second metal layer and the data lines, and increasing the overlapping area of the storage capacitor, the pixel short circuit problem caused by semiconductor layer residue was solved, improving production yield and electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHU TOKEN SCI
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-21
AI Technical Summary
Existing electronic paper pixel structures suffer from display defects due to short circuits in pixel electrodes caused by semiconductor layer residue during manufacturing, affecting production yield and product reliability.
By optimizing the planar layout design of the pixel structure, the minimum spacing between the second metal layer and the adjacent data line is ensured to be ≥15μm. The design of the first metal layer covering the second metal layer is adopted to increase the overlapping area of the storage capacitor and cut off the parasitic conductive path.
It effectively reduces pixel short-circuit defects caused by semiconductor layer residue, improves the production yield and product reliability of electronic paper display panels, and optimizes electrical performance and process robustness.
Smart Images
Figure CN121900084A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic display device technology, specifically relating to a pixel structure for improving pixel defects, and more particularly to a pixel structure for improving pixel defects in electronic paper display devices. Background Technology
[0002] Electronic paper display technology, with its significant advantages such as paper-like visual experience, ultra-low power consumption, no need for backlight, and wide viewing angle, has been widely used in e-readers, electronic shelf labels, digital signage, and some wearable devices. Its core display unit is a microcapsule or microcup structure driven by a thin-film transistor (TFT) backplane, and the grayscale state of each pixel is maintained by charging the TFT circuit.
[0003] Existing electronic paper pixel structures, especially in backplanes using semiconductor layer TFT technology, have revealed some key issues affecting product yield and display performance.
[0004] During the manufacturing process of pixel structures, patterned residues in the semiconductor layer can cause problems. During the dry etching process of the semiconductor layer, due to the geometric steps at the edges of the first metal layer (typically used as gate lines and common electrodes), the etching gas can easily create a "shadowing effect," preventing the complete removal of semiconductor material and resulting in residues along the edge sidewalls of the first metal layer pattern. In the subsequent fabrication of the second metal layer (typically used as data lines and pixel capacitor electrodes), if the pattern of the second metal layer is too close to the edge of the underlying first metal layer pattern, this residual semiconductor layer may electrically connect the first and second metal layers, forming an unintended parasitic thin-film transistor (TFT) channel. This can cause a short circuit between the pixel capacitor electrode (second metal layer) and the common electrode (first metal layer), preventing the pixel from charging and maintaining its voltage properly. This manifests as "bright spots" or "dark spots" on the display panel, severely reducing product yield.
[0005] Therefore, there is an urgent need for an innovative pixel structure design that can effectively solve the pixel short circuit problem caused by semiconductor layer residue without increasing process complexity. Summary of the Invention
[0006] The purpose of this invention is to provide a pixel structure that improves pixel defects and solves the problem of short circuits in pixel electrodes caused by semiconductor layer residues during the manufacturing process, thereby improving the production yield and product reliability of electronic paper display panels.
[0007] Based on the above concept, the technical solution adopted by this invention is as follows: According to a first aspect of the present invention, a pixel structure for improving pixel defects is provided, comprising a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second metal layer, a first protective layer, a second protective layer, and a pixel electrode; The pixel electrode is connected to the second metal layer through the PAS holes in the first protective layer and the JAS holes in the second protective layer.
[0008] In some embodiments, the first metal layer includes a first capacitor plate and a first connecting line; the second metal layer includes a second capacitor plate, a connecting plate, and a connecting line.
[0009] In some embodiments, the projection of the first capacitor plate of the first metal layer onto the substrate covers the second capacitor plate of the second metal layer.
[0010] In some embodiments, the minimum distance between the edge of the first capacitor plate of the first metal layer and the edge of the second capacitor plate of the second metal layer is greater than or equal to 3 μm.
[0011] Furthermore, it also includes a first data line and a second data line for separating the pixel structure, the first data line and the second data line being intersected and connected to form a rectangle.
[0012] In some embodiments, the first data line is electrically connected to the first metal layer.
[0013] In some embodiments, the minimum spacing between the second data line and the second capacitor plate of the second metal layer is greater than or equal to 15 μm.
[0014] In some embodiments, the number of PAS holes and JAS holes is at least one.
[0015] In some embodiments, the projections of the PAS holes and JAS holes on the substrate are located inside the connecting plate.
[0016] In some embodiments, the diameter of the inscribed circle of the PAS hole is smaller than that of the JAS hole.
[0017] The beneficial effects of this invention are as follows: 1. This invention establishes a "safety isolation zone" by setting the minimum spacing between the second metal layer constituting the pixel capacitor and the adjacent data line to be greater than or equal to 15μm. This effectively ensures that the pattern edge of the second metal layer is far away from the potential risk area of semiconductor layer residue below the pattern edge of the first metal layer, thereby cutting off the possibility of the formation of the parasitic conductive path of "metal-residual semiconductor layer-metal". Therefore, it can reduce pixel short circuit defects caused by semiconductor layer residue, solve the problem of pixels not being able to charge properly, and ultimately improve the product yield of electronic paper display panels.
[0018] 2. The present invention adopts a design in which a first capacitor plate with a first metal layer covers a second capacitor plate with a second metal layer on the projection, and ensures that the minimum distance between the edges of the two is greater than or equal to 3μm, thereby effectively increasing the overlap area of the upper and lower plates of the storage capacitor (i.e., the first metal layer and the second metal layer) within a limited pixel area. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the electronic paper pixel structure of the present invention; Figure 2 This is a cross-sectional view of the electronic paper pixel structure of the present invention.
[0020] Figure label: Substrate 110, first metal layer 120, first capacitor plate 121, first connecting line 122, first insulating layer 130, semiconductor layer 140, second metal layer 150, second capacitor plate 151, connecting plate 152, connecting line 153, first protective layer 160, PAS hole 161, second protective layer 170, JAS hole 171, pixel electrode 180, first data line 191, second data line 192. Detailed Implementation
[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.
[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this invention pertains. The words “a” or “one” and similar terms used in this application specification and claims do not indicate a limitation of quantity, but rather indicate the presence of at least one. “A plurality” means two or more. The words “comprising” or “including” and similar terms mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. The words “connected” or “linked” and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. The words “above” and / or “below” and similar terms are for ease of description only and are not limited to a location or spatial orientation. The singular forms “a,” “the,” and “the” used in this application specification and appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0023] The technical concept of this invention includes: First, regarding the problem in the existing electronic paper pixel structure where the semiconductor layer is left at the edge of the first metal layer 120 during dry etching, causing a short circuit between the subsequently formed second metal layer 150 and the first metal layer 120, thus leading to the inability of the pixel to be charged, this invention recognizes that the root cause lies in the fact that the layout design has not fully considered this specific process defect.
[0024] Secondly, to address the aforementioned issues, this solution mandates a minimum spacing of 15μm or greater between the second capacitor plate 151 constituting the pixel capacitor in the second metal layer 150 and the adjacent second data line 192. This rule ensures that the effective graphic area of the second metal layer 150 is completely isolated from the edge risk area of the first metal layer 120, thereby physically blocking any parasitic conductive paths that may form in the residual semiconductor layer 140. Simultaneously, by optimizing the relative positions and overlap of the capacitor plates in the first metal layer 120 and the second metal layer 150, the capacitor area is maximized under the established rules, thus balancing electrical performance.
[0025] Therefore, this invention provides a pixel structure design scheme that avoids short-circuit risks caused by residual semiconductor layer 140 by optimizing the planar layout rules of the metal conductors inside the pixel. This concept, through a simple and reliable layout design modification, achieves the goal of improving product yield and reliability without increasing process complexity and cost.
[0026] This application provides a pixel structure for improving pixel defects, including a substrate 110, a first metal layer 120, a first insulating layer 130, a semiconductor layer 140, a second metal layer 150, a first protective layer 160, a second protective layer 170, and a pixel electrode 180 stacked sequentially. The pixel electrode 180 is connected to the second metal layer 150 through the PAS hole 161 of the first protective layer 160 and the JAS hole 171 of the second protective layer 170.
[0027] This invention establishes a "safe isolation zone" by setting the minimum distance between the second metal layer 150 constituting the pixel capacitor and the adjacent second data line 192 to be greater than or equal to 15μm. This effectively ensures that the pattern edge of the second metal layer 150 is far away from the potential risk area of residual semiconductor layer 140 below the pattern edge of the first metal layer 120, thereby cutting off the possibility of forming the parasitic conductive path of "metal-residual semiconductor layer-metal". Therefore, it can reduce pixel short circuit failure caused by semiconductor layer 140 residue, solve the problem of pixels not being able to charge normally, and ultimately improve the product production yield of electronic paper display panels. By adopting a design where the first capacitor plate 121 of the first metal layer 120 covers the second capacitor plate 151 of the second metal layer 150 on the projection, and ensuring that the minimum distance between their edges is greater than or equal to 3μm, the overlap area of the upper and lower plates of the storage capacitor (i.e., the first metal layer and the second metal layer) is effectively increased within a limited pixel area.
[0028] The following is in conjunction with the appendix Figures 1 to 2 This application provides a detailed description of a pixel structure for improving pixel defects.
[0029] In this embodiment, a pixel structure for improving pixel defects is provided, the top view of which is shown below. Figure 1 As shown, the area specifically includes a rectangular region formed by the intersection of two first data lines 191 and two second data lines 192. This rectangular region includes the stacked pixel structure provided in this application. The two first data lines 191 are arranged horizontally in parallel, and the two second data lines 192 are arranged vertically in parallel.
[0030] Furthermore, the horizontally arranged first data line 191 and the vertically arranged second data line 192 together form the wiring grid driving the pixel array. The first data line 191 typically serves as a gate line, responsible for applying scan signals row by row to control the on / off timing of the thin-film transistors (TFTs) in the entire row of pixels. The second data line 192 typically serves as a data line, responsible for writing specific voltage signals to each pixel in the corresponding row when the TFTs are turned on. This voltage is ultimately applied to the pixel electrode to control the display state of the electronic ink. The intersection of these two sets of data lines defines an independent pixel unit position, and the rectangular area formed by them is the boundary of a single pixel, ensuring that the signal can accurately address and drive each pixel, achieving overall image display.
[0031] In this embodiment, a cross-sectional view of a pixel structure that improves pixel defects is shown below. Figure 2 As shown, the structure, from bottom to top, includes a substrate 110, a first metal layer 120 formed on the substrate 110, a first insulating layer 130 covering the first metal layer 120, a semiconductor layer 140 formed on the first insulating layer 130, a second metal layer 150 formed on the first insulating layer 130, a first protective layer 160 covering the second metal layer 150, a second protective layer 170 formed on the first protective layer 160, and an uppermost pixel electrode 180.
[0032] Furthermore, the aforementioned functional layers can be sequentially fabricated using, for example, but not limited to, the following typical thin-film transistor array process steps. First, on the substrate 110 (typically a glass substrate), the first metal layer 120 is patterned and formed through processes such as deposition of a metal material (e.g., molybdenum, aluminum, or a stack thereof), photolithography, etching, and resist stripping. Next, the first insulating layer 130 (e.g., silicon nitride or silicon oxide) and the semiconductor layer 140 (e.g., an amorphous silicon layer) are sequentially deposited using methods such as chemical vapor deposition, and the semiconductor layer 140 is patterned using photolithography and dry etching processes. Subsequently, a metal material (such as the same material as the first metal layer) is deposited and patterned to form the second metal layer 150. Afterward, an inorganic material such as silicon nitride or silicon oxide is deposited to form the first protective layer 160, and PAS holes 161 penetrating this layer are formed through photolithography and etching processes. Next, an organic planarization material (e.g., acrylic resin) is coated and cured to form the second protective layer 170. Similarly, a larger JAS hole 171, aligned with the protective layer, is formed using photolithography and etching processes, exposing the underlying connection plate 152 area. Finally, a transparent conductive oxide (e.g., indium tin oxide, ITO) is deposited and patterned using methods such as sputtering to form the pixel electrode 180. This ITO material fills the JAS hole 171 and PAS hole 161, achieving ohmic contact with the connection plate 152 of the second metal layer 150, thus completing the fabrication of the entire pixel structure.
[0033] In this embodiment, the first metal layer 120 is patterned to form an electrically connected first capacitor plate 121 and a first connecting line 122. The first capacitor plate 121 serves as the common electrode (lower electrode) of the pixel storage capacitor, while the first connecting line 122 is used to transmit gate scan signals. The first connecting line 122 extends from the side of the first metal layer 120 and is electrically connected to the first data line 191. Similarly, the second metal layer 150 is patterned to form an interconnected second capacitor plate 151, a connecting plate 152, and a connecting line 153. The second capacitor plate 151 serves as the other electrode (upper electrode) of the pixel storage capacitor, the connecting line 153 is used to transmit data signals, and the connecting plate 152 serves as an intermediate conductor connecting the second capacitor plate 151 and the pixel electrode 180. The pixel electrode 180 achieves reliable physical contact and electrical connection with the underlying second metal layer 150 through the PAS hole 161 penetrating the first protective layer 160 and the JAS hole 171 of the second protective layer 170. That is, the first protective layer 160 is provided with the PAS hole 161 above the connecting plate 152, and the second protective layer 170 is also provided with a JAS hole 171 with a larger opening size above the PAS hole 161. During deposition, the area of the pixel electrode 180 located in the PAS hole 161 is in direct contact with the second metal layer 150.
[0034] In this embodiment, to achieve a larger storage capacitance and optimize the electric field distribution, the first capacitor plate 121 of the first metal layer 120 is designed to completely cover the second capacitor plate 151 of the second metal layer 150 in a direction perpendicular to the substrate 110 (i.e., its projection on the substrate plane), forming a planar layout of "lower plate wrapping upper plate". To ensure the capacitance of the storage capacitor while taking into account process alignment tolerances, the size of the overlapping area is specifically limited. The minimum horizontal distance between the edges of the first capacitor plate 121 and the second capacitor plate 151 in the overlapping area is set to be greater than or equal to 3 μm. This design ensures a sufficient and stable overlap area between the two, thereby obtaining a capacitance value that meets the design requirements.
[0035] In this embodiment, compared to the traditional design where the second metal layer 150 covers the first metal layer 120, the layout scheme of the first metal layer 120 wrapping the second metal layer 150 adopted in this invention exhibits a number of comprehensive advantages. In the traditional scheme, the pattern of the second metal layer 150 needs to extend in the air to cover the first metal layer 120 below. This makes the edge of the second metal layer 150 located directly above the step of the first metal layer 120, where the semiconductor layer 140 has the highest residual risk, which can easily form a short circuit. Moreover, in order to meet the safety spacing rules, the expansion of the second metal layer 150 is severely restricted, thereby compressing the capacitor area. However, this scheme uses the lower first metal layer 120 as a common electrode to wrap the upper electrode, transferring the risky edge area to the outer first metal layer 120. This effectively "protects" the core capacitor upper electrode (second metal layer 150) within a safe area, fundamentally isolating the risk of process defects. Under this safety architecture, the second metal layer 150 can be designed to be small and compact, strictly adhering to spacing rules. The task of increasing capacitance is undertaken by the first metal layer 120, which is not directly restricted by these rules and can be freely expanded, thus maximizing the capacitor area under the same safety constraints. Furthermore, this "base plate wrapping" structure has better tolerance for lithographic alignment errors between the upper and lower layers. When the second metal layer 150 experiences a slight shift within the area of the first metal layer 120, the change in overlap area is smaller, ensuring the stability of the capacitance value and the consistency of product performance. Therefore, this solution, through a clever role reversal in layout, achieves a shift from passively avoiding risks to actively building a safety architecture, optimizing electrical performance and process robustness while ensuring high yield.
[0036] In this embodiment, to address the residual short-circuit problem in the semiconductor layer, a key rule is established in the layout design: the minimum spacing between the edge of the second capacitor plate 151 of the second metal layer 150 and the edge of the adjacent second data line 192 is strictly defined as greater than or equal to 15 μm. This spacing creates a "safety barrier," ensuring that the pattern of the second capacitor plate 151 is far away from the residual semiconductor layer risk area below the edge of the first metal layer 120 pattern, thereby completely blocking the parasitic conductive path formed through the residual semiconductor layer.
[0037] Based on the core concept proposed in this invention, those skilled in the art will understand that the protection scope of the pixel structure for improving pixel defects is not limited to the specific values, shapes, and materials disclosed in the foregoing embodiments. As long as a pixel structure adopts the core design idea of avoiding short-circuit risks by setting a distance of ≥15μm between the second capacitor plate 151 constituting the capacitor in the second metal layer 150 and adjacent data lines, and / or by using the first capacitor plate 121 constituting the capacitor in the first metal layer 120 to cover and wrap the corresponding second capacitor plate 151 of the second metal layer 150 on the projection to increase the effective overlap area, then the technical solution falls within the protection scope of this invention. Regardless of the specific materials selected for each functional layer (e.g., the first metal layer and the second metal layer use the same or different metals or alloys, and the semiconductor layer 140 uses amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor), and regardless of how the specific values of the spacing and overlap width are adaptively adjusted according to the process node based on the threshold, such as setting the spacing to 10μm, 20μm, or the overlap width to 4μm, 5μm, etc., all are equivalent transformations or simple extensions of the technical solution described in this invention. This design fundamentally reconstructs the planar layout relationship between pixel capacitors and wires, optimizing capacitor performance while avoiding process-related short-circuit defects, and further improving the yield and reliability of electronic paper display panels. All of these should be covered by the patent scope of this invention.
[0038] Detailed implementation methods and principles: When the pixel structure of the present invention is in operation, the gate of its core functional unit, the thin-film transistor (TFT), is controlled by the first connection line 122 (i.e., the gate line) of the first metal layer 120. When an on-state voltage is applied to the first connection line 122, a conductive channel is formed in the semiconductor layer 140 (e.g., an amorphous silicon layer) located above it and separated by the first insulating layer 130. At this time, the data voltage signal from the connection line 153 (i.e., the data line) of the second metal layer 150 charges the storage capacitor (Cst) composed of the first capacitor plate 121 and the second capacitor plate 151 through the conductive channel. At the same time, the voltage is also transmitted to the pixel electrode 180 through the connection plate 152, the PAS hole 161, and the JAS hole 171. After charging is completed, even if the TFT is turned off, the charge stored in the storage capacitor can maintain the voltage stability on the pixel electrode 180 for a frame time, thereby driving the electronic paper display medium (such as microcapsule electrophoretic particles) to maintain the required display state.
[0039] During manufacturing, a semiconductor layer 140 (such as a-Si) located at the edge step of the first metal layer 120 may remain due to the "shadowing effect" of dry etching. In conventional designs that do not consider this issue, the edge of the second capacitor plate 151 of the second metal layer 150 may be too close to the edge of the first metal layer 120 in a horizontal layout. When the remaining semiconductor layer 140 is present in this area, a parasitic TFT channel may be formed between the first metal layer 120 and the second capacitor plate 151, causing a short circuit and preventing the storage capacitor from charging.
[0040] This invention mandates a minimum spacing of 15 μm between the second capacitor plate 151 and the adjacent second data line 192. This design rule ensures that the effective conductive pattern of the second capacitor plate 151 is horizontally distant from the edge of the first metal layer 120 pattern (particularly the portion of the first capacitor plate 121 that serves as the common electrode). Therefore, even if semiconductor layer residues exist at the edge of the first metal layer 120, these residues cannot form an electrical connection due to their significant distance from the second capacitor plate 151, thus completely severing parasitic conductive paths.
[0041] To achieve the largest possible storage capacitance within a limited pixel area while ensuring a safe spacing, this invention optimizes the layout of the upper and lower plates of the capacitor (i.e., the first capacitor plate 121 and the second capacitor plate 151). The design of the first capacitor plate 121 covering the second capacitor plate 151 on the projection with a minimum edge distance of 3μm or more achieves a "lower plate wrapping the upper plate" structure.
[0042] According to the parallel plate capacitor capacitance formula C=ε*A / d, where A is the overlapping area of the two plates and d is the thickness of the intermediate dielectric (i.e., the thickness of the first insulating layer 130), with a fixed dielectric thickness d, the capacitance C is directly proportional to the overlapping area A. This design maximizes the use of the available planar area to increase the overlapping area A by making the area of the first capacitor plate 121 (lower plate) larger than and completely covering the second capacitor plate 151 (upper plate). Simultaneously, a minimum overlap width of ≥3 μm is specified, providing the necessary tolerance space for photolithography and alignment processes. This ensures that even under the worst-case process deviations in actual production, sufficient effective overlap area is maintained between the two plates, thereby guaranteeing the stability and consistency of the capacitance value and meeting the requirements of electronic paper for maintaining capacitance size.
[0043] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. The invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.
[0044] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A pixel structure for improving pixel defects, characterized in that, It includes a substrate (110), a first metal layer (120), a first insulating layer (130), a semiconductor layer (140), a second metal layer (150), a first protective layer (160), a second protective layer (170), and a pixel electrode (180) stacked in sequence. The pixel electrode (180) is connected to the second metal layer (150) through the PAS hole (161) of the first protective layer (160) and the JAS hole (171) on the second protective layer (170).
2. The pixel structure for improving pixel defects according to claim 1, characterized in that, The first metal layer (120) includes a first capacitor plate (121) and a first connecting line (122); the second metal layer (150) includes a second capacitor plate (151), a connecting plate (152) and a connecting line (153).
3. The pixel structure for improving pixel defects according to claim 2, characterized in that, The projection of the first capacitor plate (121) of the first metal layer (120) onto the substrate (110) covers the second capacitor plate (151) of the second metal layer (150).
4. A pixel structure for improving pixel defects according to claim 2, characterized in that, The minimum distance between the edge of the first capacitor plate (121) of the first metal layer (120) and the edge of the second capacitor plate (151) of the second metal layer (150) is greater than or equal to 3 μm.
5. A pixel structure for improving pixel defects according to claim 1, characterized in that, It also includes a first data line (191) and a second data line (192) for separating the pixel structure, the first data line (191) and the second data line (192) are intersected and connected to form a rectangle.
6. A pixel structure for improving pixel defects according to claim 5, characterized in that, The first data line (191) is electrically connected to the first metal layer (120).
7. A pixel structure for improving pixel defects according to claim 5, characterized in that, The minimum spacing between the second data line (192) and the second capacitor plate (151) of the second metal layer (150) is greater than or equal to 15 μm.
8. A pixel structure for improving pixel defects according to claim 1, characterized in that, The number of PAS holes (161) and JAS holes (171) is at least one.
9. A pixel structure for improving pixel defects according to claim 8, characterized in that, The projections of the PAS holes (161) and JAS holes (171) on the substrate (110) are located inside the connecting plate (152).
10. A pixel structure for improving pixel defects according to claim 8, characterized in that, The diameter of the inscribed circle of the PAS hole (161) is smaller than that of the JAS hole (171).