High-voltage self-biased pre-starting LDO (low dropout regulator) circuit

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a high-voltage self-bias pre-start LDO circuit which comprises a feedback voltage division circuit, an operational amplifier circuit, a PMOS power tube, a self-bias circuit, a voltage reference generation circuit and a pre-start circuit. The bias circuit is used for providing bias voltage, the voltage reference generation circuit is used for generating reference voltage VREF weakly related to temperature, and the pre-starting circuit comprises an equivalent capacitor unit, a pre-starting branch and a pre-starting current source. According to the invention, a simple self-bias circuit design is introduced, and an additional bias voltage generation circuit is not needed; meanwhile, in the power-on process, the operational amplifier tail current is pre-started, and the problem of output overshoot is weakened. The circuit is suitable for a high-voltage power supply scene, rapid and stable starting of the circuit can be realized, and stable low-voltage output is provided for a load.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a high-voltage self-biased pre-start-up LDO circuit. Background Technology

[0002] As the core module for voltage conversion and regulation in power management integrated circuits, the low dropout linear regulator (LDO) is widely used in various electronic systems such as industrial control and communication equipment due to its advantages of simple structure, low output ripple, and low static power consumption. It is used to convert high voltage input into stable low voltage output and provide reliable power supply for sensitive loads such as microcontrollers and sensors.

[0003] In high-voltage, wide-input-range applications, PMOS transistors are often used as power transistors. However, these LDOs have a significant drawback: power-on output overshoot. The main reason is that the power supply to the operational amplifier before the power transistor and the establishment of its internal bias circuit require a certain amount of time. The source of the power transistor is directly connected to the power supply VDD. When VDD is rapidly powered on, the gate voltage Vgate of the power transistor rises slowly because the operational amplifier has not fully started up. This causes a momentary increase in the gate-source voltage Vgs of the power transistor, pulling the output voltage much higher than the normal output level. This overshoot phenomenon can not only damage the downstream load but also limits the application of LDOs in high-speed power-on systems, especially in designs where the feedback circuit resistance is increased to reduce power consumption.

[0004] Chinese patent application CN117170449A discloses an LDO circuit that adds an overshoot regulation circuit. During power-up, it utilizes the characteristic that the voltage of the lower plate of capacitor C1 increases with the voltage of the upper plate to turn on the control transistor M1, thereby pulling down the gate voltage of the MOS transistor M9 in the output stage of the operational amplifier. This controls the gate voltage of the PMOS power transistor Mp to be maintained at a high voltage, keeping Mp off until the reference voltage is established and exceeds the gate voltage of M1, at which point the normal feedback loop takes over the operation.

[0005] Chinese patent application CN118331367A discloses an LDO circuit that obtains the rate of change of the power supply voltage through a transient detection and compensation circuit. Specifically, it uses an RC network to detect the rising slope of the power supply VIN. When the rising slope is large enough, it triggers the Schmitt trigger G1 to flip, turns on the switching transistor M2, generates a compensation current, and applies it to the tail current of the error amplifier circuit to compensate for the tail current, thereby accelerating the transient response speed of the power transistor and suppressing overshoot.

[0006] The existing technologies described above have the following problems: the overshoot regulation circuit needs to ensure that the external voltage VN and bias current IB2 are established during power-up, otherwise the function will fail. Furthermore, directly pulling down the gate voltage of the MOSFET can easily lead to excessive gate-source voltage under high voltage power supply, causing device damage and resulting in poor reliability. In the tail current compensation technology, the compensation current needs to pass through a series switching transistor, introducing additional on-resistance, which weakens the timeliness and effectiveness of the compensation current. At the same time, if the power supply rise speed is slow, slower than the response threshold of capacitor C1 and Schmitt trigger but sufficient to cause output overshoot, the compensation circuit will fail. In addition, the capacitor C1 used in the existing technology is expensive, occupies a large area, and may even be impossible to implement in high voltage chip design. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention proposes a high-voltage self-biased pre-start-up LDO circuit, comprising a feedback voltage divider circuit, an operational amplifier circuit, and a PMOS power transistor, as well as a self-biasing circuit, a voltage reference generation circuit, and a pre-start-up circuit. The biasing circuit provides a bias voltage, the voltage reference generation circuit generates the temperature-dependent reference voltage VREF, and the pre-start-up circuit includes an equivalent capacitance unit, a pre-start-up branch, and a pre-start-up current source. This invention introduces a simple self-biasing circuit design, eliminating the need for an additional bias voltage generation circuit; simultaneously, during power-up, the pre-start-up op-amp tail current mitigates output overshoot. This invention is suitable for high-voltage power supply scenarios, enabling rapid and stable circuit startup and providing a stable low-voltage output to the load.

[0008] To achieve the above objectives, the present invention provides the following technical solution: A high-voltage self-biased pre-start-up LDO circuit includes a feedback voltage divider circuit, an operational amplifier circuit, and a PMOS power transistor. The feedback voltage divider circuit is composed of resistors R1 and R2, and obtains a feedback voltage VFB by dividing the output voltage VOUT. The first input terminal of the operational amplifier circuit is connected to a reference voltage VREF, and the second input terminal is connected to the feedback voltage VFB. The amplifier outputs an amplified signal to the gate of the power transistor M1. The circuit is characterized by further including a self-biasing circuit, a voltage reference generation circuit, and a pre-start-up circuit. One end of the self-biasing circuit is connected to the power supply voltage VDD, and the other end is grounded, providing a bias voltage V1 for the voltage reference generating circuit and the operational amplifier circuit. The input terminal of the voltage reference generating circuit is connected to the bias voltage V1, and the output terminal generates the reference voltage VREF, which is weakly correlated with temperature. The pre-start circuit is connected to the tail current source of the self-biasing circuit, the voltage reference circuit, and the operational amplifier circuit. The pre-start circuit includes an equivalent capacitor unit, a pre-start branch, and a pre-start current source. In the initial stage of power-on, the bias voltage V1 rises with the power supply voltage VDD, turns on the pre-start branch, and pulls up the voltage of the control node V3 through the equivalent capacitor unit to turn on the pre-start current source; when the reference voltage VREF stabilizes, the pre-start branch pulls down the voltage of the control node V3 to turn off the pre-start current source.

[0009] Specifically, the self-biasing circuit includes a resistor R3 and at least one NMOS transistor M12, M13, or M14 connected in a diode configuration; one end of the resistor R3 is connected to the power supply voltage VDD, and the other end of the resistor R3 is the output node of the bias voltage V1, and is connected to the drain and gate of the NMOS transistor M12; the source of the NMOS transistor M12 is connected to the drain and gate of the NMOS transistor M13, the source of the NMOS transistor M13 is connected to the drain and gate of the NMOS transistor M14, and the source of the NMOS transistor M14 is grounded.

[0010] Specifically, the voltage reference generation circuit includes a source follower M11, an enhancement-mode NMOS transistor M18, and at least one depletion-mode NMOS transistor M15, M16, and M17. The source follower M11 is a high-voltage depletion-mode NMOS transistor. Its gate is connected to the bias voltage V1, its drain and ISO_N terminal are connected to the power supply voltage VDD, and its source is connected to the Bulk terminal to output an intermediate voltage V2. The source of the enhancement-mode NMOS transistor M18 is grounded, its gate and drain are shorted, and it is connected to the reference voltage VREF. The depletion-mode NMOS transistor M15... The gates of the depletion-type NMOS transistor M16, M17, and M18 are connected; the source of the depletion-type NMOS transistor M17 is connected to the drain of the enhancement-type NMOS transistor M18; the source of the depletion-type NMOS transistor M16 is connected to the drain of the depletion-type NMOS transistor M17; the source of the depletion-type NMOS transistor M15 is connected to the drain of the depletion-type NMOS transistor M16; and the drain of the depletion-type NMOS transistor M15 is connected to the source of the source follower M11.

[0011] Specifically, the equivalent capacitance unit is composed of a high-voltage NMOS transistor M10; the drain and ISO_N terminal of the high-voltage NMOS transistor M10 are connected to the power supply voltage VDD, the gate and source are shorted and connected to the control node V3, and the Bulk terminal is connected to the source to form a PN junction barrier capacitor.

[0012] Specifically, the pre-start branch includes a switching transistor M19 and a discharge path; the gate of the switching transistor M19 is connected to the intermediate voltage V2, the source is connected to the control node V3, and the drain is connected to the discharge path; the discharge path includes at least one NMOS transistor M20, M21, and M22; the drain of the NMOS transistor M20 is connected to the drain of the switching transistor M19, and the source is connected to the drain of the NMOS transistor M21; the source of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22; the gates of the NMOS transistors M20, M21, and M22 are all connected to the reference voltage VREF, and the source of the NMOS transistor M22 is grounded.

[0013] Specifically, the pre-start branch is in the first state at the initial stage of power-on. After the reference voltage VREF is stably established, the pre-start branch is in the second state. The first state is when the switch M19 is turned on and the discharge path is turned off or presents a high resistance state. The second state is when both the switch M19 and the discharge path are turned on.

[0014] Specifically, the pre-start branch adjusts the number and width-to-length ratio of the NMOS transistors connected in series in the discharge path to regulate the time for switching from the first state to the second state, thereby controlling the operating time of the pre-start current source.

[0015] Specifically, the pre-start-up current source is composed of an NMOS transistor M9. The gate of the NMOS transistor M9 is connected to the drain of the switching transistor M19, the source is grounded, and the drain is connected to the tail current source of the operational amplifier circuit to provide the pre-start-up tail current.

[0016] Specifically, the tail current source of the operational amplifier circuit includes NMOS transistors M6, M7, and M8 in series; the drain of NMOS transistor M6 is connected to the drain of NMOS transistor M9, and the source is connected to the drain of NMOS transistor M7; the source of NMOS transistor M7 is connected to the drain of NMOS transistor M8; the gates of NMOS transistors M6, M7, and M8 are all connected to the reference voltage VREF; and the source of NMOS transistor M8 is grounded.

[0017] Specifically, the operational amplifier circuit further includes PMOS transistors M2 and M3 and NMOS transistors M4 and M5; the source of PMOS transistor M2 and the source of PMOS transistor M3 are connected to the power supply voltage VDD, the gate of PMOS transistor M2 is connected to the gate of PMOS transistor M3, and the drain of PMOS transistor M2 is connected to the gate of power transistor M1; the drain of PMOS transistor M3 is shorted to its gate and connected to the drain of NMOS transistor M5; the gate of NMOS transistor M5 is connected to the feedback voltage VFB, and its source is connected to the drain of NMOS transistor M9; the drain of NMOS transistor M4 is connected to the drain of PMOS transistor M2, its gate is connected to the reference voltage VREF, and its source is connected to the drain of NMOS transistor M9.

[0018] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention utilizes the inherent characteristics of high-voltage devices to construct a self-biasing circuit and source follower, enabling the generation of a stable bias voltage without the need for additional bias voltage or current sources. The use of a pre-startup tail current source enhances the operational amplifier's inherent control capability, avoiding the risk of directly pulling down the gate voltage of the operational amplifier's MOS transistor. The use of a high-voltage NMOS transistor to replace the traditional capacitor reduces production costs and implementation difficulty. This invention designs a pre-startup circuit that rapidly pulls up the gate voltage of the pre-startup current source through an equivalent capacitor during initial power-up, injecting additional startup circuitry into the operational amplifier circuit, helping to quickly establish the loop, and adapting to the power-up speed. Furthermore, by utilizing the temperature characteristics of a depletion-type NMOS transistor and an enhancement-type NMOS transistor connected in series to compensate for each other, the generated reference voltage VREF has a weak temperature correlation characteristic, providing a more stable comparison reference for the operational amplifier, thereby improving the output accuracy and stability of the LDO across the entire operating temperature range. In summary, this invention provides an LDO circuit that fundamentally suppresses output overshoot, is low-cost, and highly reliable, and is particularly suitable for high-voltage applications. Attached Figure Description

[0019] Figure 1 A schematic diagram of a high-voltage self-biased pre-start-up LDO circuit system architecture provided in an embodiment of the present invention; Figure 2 A circuit schematic diagram of a pre-start LDO circuit provided for the prior art; Figure 3 A circuit diagram of a high-voltage self-biased pre-start LDO circuit provided in an embodiment of the present invention; Figure 4 A schematic diagram of the vertical structure of the equivalent capacitor of a high-voltage NMOS provided in an embodiment of the present invention; Figure 5 This is a comparison diagram of voltage changes with and without a pre-start circuit in an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this invention, and not all embodiments. Therefore, the following detailed description of the embodiments of this invention is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort should fall within the scope of protection of this invention.

[0021] In embodiments of the present invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0022] Please see Figure 1 , Figure 1 A schematic diagram of a high-voltage self-biased pre-start-up LDO circuit system architecture is provided for an embodiment of the present invention, including a feedback voltage divider circuit, an operational amplifier circuit, and a PMOS power transistor; the feedback voltage divider circuit is composed of resistors R1 and R2, and obtains the feedback voltage VFB by dividing the output voltage VOUT; the first input terminal of the operational amplifier circuit is connected to the reference voltage VREF, the second input terminal is connected to the feedback voltage VFB, and the amplified signal is output to the gate of the power transistor M1; characterized in that it further includes a self-biasing circuit, a voltage reference generation circuit, and a pre-start-up circuit; One end of the self-biasing circuit is connected to the power supply voltage VDD, and the other end is grounded, providing a bias voltage V1 for the voltage reference generating circuit and the operational amplifier circuit. The input terminal of the voltage reference generating circuit is connected to the bias voltage V1, and the output terminal generates the reference voltage VREF, which is weakly correlated with temperature. Specifically, in this embodiment, the voltage reference generating circuit adopts a structure of depletion-mode NMOS transistors and enhancement-mode NMOS transistors connected in series. By utilizing the mutual compensation of their temperature characteristics and selecting the size and series ratio of the NMOS transistors, the absolute value of the temperature coefficient of the reference voltage VREF is less than 100 ppm / °C, which is weakly correlated. The pre-start circuit is connected to the tail current source of the self-biasing circuit, the voltage reference circuit, and the operational amplifier circuit. The pre-start circuit includes an equivalent capacitor unit, a pre-start branch, and a pre-start current source. In the initial stage of power-on, the bias voltage V1 rises with the power supply voltage VDD, turns on the pre-start branch, and pulls up the voltage of the control node V3 through the equivalent capacitor unit to turn on the pre-start current source; when the reference voltage VREF stabilizes, the pre-start branch pulls down the voltage of the control node V3 to turn off the pre-start current source.

[0023] First, please refer to Figure 2 , Figure 2 The circuit schematic of a pre-startup LDO circuit provided in the prior art is shown. The pre-startup mechanism is implemented through a coupling circuit based on MOS capacitors, including a five-transistor amplifier composed of MOS transistors M2-M6, and a bias network composed of feedback resistors R3 and R4, NMOS transistors M8 and M9, and capacitor C1. Its output is used to control a pre-startup NMOS current source M7. The specific working principle is as follows: When the power supply voltage VDD is initially applied, resistor R3 and NMOS transistor M8, connected in a diode configuration, form a voltage divider path. In the initial stage, when VDD is below the NMOS threshold voltage Vth, M8 is not turned on, and the potential of node V1 is approximately equal to VDD. Once VDD exceeds Vth, M8 turns on, clamping the voltage of node V1 at a level slightly higher than Vth, and it rises slowly with VDD. Simultaneously, one end of capacitor C1 is connected to VDD, and the other end is connected to node V2. Based on the characteristic that the voltage across a capacitor cannot change abruptly, the potential of node V2 is pulled up accordingly due to capacitive coupling as VDD rises.

[0024] As VDD continues to rise until the voltage at node V1 is sufficient to turn on NMOS transistor M9, the voltage at node V3 rises accordingly, thereby turning on the pre-startup current source M7. The additional current provided by M7 allows the amplifier to start up earlier, thereby regulating the gate voltage of power transistor M1 and preventing overshoot.

[0025] After the power-on process ends and the circuit enters a stable state, the charge stored in capacitor C1 is gradually released to ground through M9 as M9 continues to conduct. The voltages of nodes V2 and V3 eventually drop to ground potential. At this time, the pre-start current source M7 is turned off, and the tail current of the amplifier is completely taken over by M6. The circuit exits the pre-start mode and enters the steady-state operation state.

[0026] The above describes existing technologies that utilize MOM capacitors for pull-up and pre-startup operational amplifier current sources. While these technologies can address the output overshoot problem to some extent, they still have some shortcomings: the capacitors will withstand the full voltage difference between the power supply and ground in steady state, and conventional MOM capacitors have insufficient voltage withstand capability; to obtain sufficient coupling voltage, capacitor C1 needs to occupy a large area, and integrated circuit manufacturing processes require MOM capacitors to use multi-layer metal, forcing the circuit to add an additional photomask layer, significantly increasing manufacturing costs. To overcome these defects, embodiments of the present invention provide a high-voltage self-biased pre-startup LDO circuit, including a self-biasing circuit, a voltage reference generation circuit, and a pre-startup circuit. The pre-startup circuit further includes an equivalent capacitor unit, a pre-startup branch, and a pre-startup current source, wherein the equivalent capacitor unit is composed of a high-voltage NMOS transistor.

[0027] Further, please refer to Figure 3 , Figure 3 The circuit diagram of a high-voltage self-biased pre-start-up LDO circuit provided in this embodiment of the invention includes a resistor R3 and at least one NMOS transistor M12, M13, and M14 connected in diode configuration. One end of the resistor R3 is connected to the power supply voltage VDD, and the other end of the resistor R3 is the output node of the bias voltage V1 and is connected to the drain and gate of the NMOS transistor M12. The source of the NMOS transistor M12 is connected to the drain and gate of the NMOS transistor M13, and the source of the NMOS transistor M13 is connected to the drain and gate of the NMOS transistor M14. The source of the NMOS transistor M14 is grounded.

[0028] Specifically, in this embodiment, resistor R3 is a high-resistance resistor used to limit the static power consumption of the self-biased circuit within a preset range under high voltage. Resistor R3 is connected in series with at least one NMOS transistor connected in a diode configuration, and the bias voltage V1 is drawn from the common node of resistor R3 and the first NMOS transistor. In the initial power-on phase or when the power supply voltage VDD is low, the bias voltage V1 is insufficient to turn on the series-connected NMOS transistors, and the current flowing through this branch is extremely small, therefore V1 ≈ VDD. When the power supply voltage VDD exceeds the sum of the turn-on threshold voltages of the series-connected NMOS transistors, the NMOS transistors turn on, and the bias voltage V1 increases logarithmically and is limited to slightly above the sum of the threshold voltages. The voltage increase resulting from the continued rise of the power supply voltage VDD will be mainly distributed across the bias resistor R3.

[0029] By selecting a bias resistor R3 with a relatively large resistance, the quiescent current of this self-biased circuit can be limited to a low level, thereby effectively controlling the overall power consumption of the circuit and making it suitable for high-voltage power supply environments. Furthermore, by flexibly adjusting the number of NMOS transistors connected in series with the diode configuration, the stable level of the bias voltage V1 can be adjusted accordingly to adapt to different circuit design requirements. For example, in this embodiment, three NMOS transistors are connected in series; therefore, when the power supply voltage VDD is greater than 3Vth, the bias voltage V1 will remain at a voltage level slightly greater than 3Vth.

[0030] Further, the voltage reference generation circuit includes a source follower M11, an enhancement-mode NMOS transistor M18, and at least one depletion-mode NMOS transistor M15, M16, and M17; the source follower M11 is a high-voltage depletion-mode NMOS transistor, with its gate connected to the bias voltage V1, its drain and ISO_N terminal connected to the power supply voltage VDD, and its source connected to the Bulk terminal to output an intermediate voltage V2; the source of the enhancement-mode NMOS transistor M18 is grounded, its gate and drain are shorted and connected to the reference voltage VREF; the depletion-mode NMOS transistor M15, M16, and M17... The gates of transistor M15, M16, and M17 are connected to the gate of the enhancement-type NMOS transistor M18; the source of M17 is connected to the drain of M18; the source of M16 is connected to the drain of M17; the source of M15 is connected to the drain of M16; and the drain of M15 is connected to the source of source follower M11.

[0031] Specifically, in this embodiment, the gate of the source follower M11 receives a bias voltage V1, and the source outputs an intermediate voltage V2. The reference voltage VREF is drawn from the connection node of the series-connected depletion-mode NMOS transistor and the enhancement-mode NMOS transistor M18. The value of VREF is determined by the current flowing through this branch and the threshold voltage of the series-connected NMOS transistors. M15, M16, and M17 are series-connected depletion-mode NMOS transistors. Their temperature characteristics are opposite to those of the enhancement-mode NMOS transistors. The absolute values ​​of the threshold voltages of both depletion-mode and enhancement-mode NMOS transistors are negatively correlated with temperature, with the threshold voltage of the depletion-mode NMOS transistor being negative and the threshold voltage of the enhancement-mode NMOS transistor being positive. Therefore, as... Figure 3When M15, M16, M17, and M18 are connected in series, their effects on the reference voltage VREF level change in opposite directions with temperature, thus producing a certain neutralization effect. By adjusting the number of NMOS transistors in series and their width-to-length ratio, the temperature coefficient of the reference voltage VREF can be made close to zero, suppressing VREF's variation with temperature and meeting the operational amplifier circuit's requirements for reference voltage stability. This circuit structure, without requiring a complex bandgap reference architecture, utilizes the temperature characteristics of different types of MOS devices to achieve a simple, low-cost, and low-temperature-drift voltage reference suitable for high-voltage environments.

[0032] Furthermore, the equivalent capacitance unit is composed of a high-voltage NMOS transistor M10. The drain and ISO_N terminal of the high-voltage NMOS transistor M10 are connected to the power supply voltage VDD, the gate and source are shorted and connected to the control node V3, and the Bulk terminal is connected to the source, forming a PN junction barrier capacitor. In this embodiment, the gate and source of the equivalent capacitor M10 are connected, and it cannot conduct under normal operating conditions. However, it has its own isolation ring (ISO_N, NBL, or HVBN), and together with the substrate Pwell, it forms a body diode, which has a certain PN junction barrier capacitance, and can be equivalent to the MOM capacitor to a certain extent.

[0033] Further, the pre-start branch includes a switching transistor M19 and a discharge path; the gate of the switching transistor M19 is connected to the intermediate voltage V2, the source is connected to the control node V3, and the drain is connected to the discharge path; the discharge path includes at least one NMOS transistor M20, M21, and M22; the drain of the NMOS transistor M20 is connected to the drain of the switching transistor M19, and the source is connected to the drain of the NMOS transistor M21; the source of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22; the gates of the NMOS transistors M20, M21, and M22 are all connected to the reference voltage VREF, and the source of the NMOS transistor M22 is grounded.

[0034] Furthermore, the pre-start branch is in the first state at the initial stage of power-on. After the reference voltage VREF is stably established, the pre-start branch is in the second state. The first state is when the switch M19 is turned on and the discharge path is turned off or presents a high resistance state. The second state is when both the switch M19 and the discharge path are turned on.

[0035] Furthermore, the pre-start branch adjusts the number and width-to-length ratio of the NMOS transistors connected in series in the discharge path to regulate the time for switching from the first state to the second state, thereby controlling the operating time of the pre-start current source. Specifically, in this embodiment, by adjusting the number and width-to-length ratio of the NMOS transistors connected in series in the discharge path, the equivalent conduction threshold and discharge rate of the path can be changed, thereby precisely adjusting the turn-on duration of the pre-start current source M9, enabling the circuit to adapt to different power-on slopes and application scenario requirements.

[0036] Furthermore, the pre-start-up current source is composed of an NMOS transistor M9. The gate of the NMOS transistor M9 is connected to the drain of the switching transistor M19, the source is grounded, and the drain is connected to the tail current source of the operational amplifier circuit to provide the pre-start-up tail current.

[0037] Specifically, in this embodiment, when the power supply voltage VDD starts to power on and the voltage value is less than the series conduction threshold of M12, M13, and M14, the bias voltage V1 rises following the power supply voltage VDD; through the source follower M11, the intermediate voltage... Because the depletion-type NMOS transistors M15, M16, and M17 in the voltage reference generation circuit have negative threshold voltages and are always on, and there is always a certain Vds voltage drop, while NMOS transistor M22 is connected in diode mode and requires a threshold voltage drop to conduct, the reference voltage VREF has not been fully established in the early stage of power-on.

[0038] When the power supply voltage VDD reaches 2Vth, the intermediate voltage V2 is approximately Vth, which allows the switching transistor M19 to turn on. As the power supply voltage VDD continues to rise, M19 enters a fully on state. At this time, the rapid rise of VDD quickly raises the potential of control node V3 through the equivalent capacitor M10, thereby pulling up the potential of node V4. The rise in the potential of node V4 then turns on the NMOS pre-start-up current source M9, injecting additional startup current into the tail current node of the operational amplifier circuit. This current causes the operational amplifier circuit to enter the working state earlier during the rise of the power supply voltage VDD, thereby enabling rapid adjustment of the gate voltage of power transistor M1 and effectively suppressing output overshoot caused by rapid power-up.

[0039] As time progresses, the power supply voltage VDD continues to rise and stabilizes, the self-biasing circuit and voltage reference generation circuit are fully established, and the potential of node V2 reaches a stable value. At this time, the NMOS transistors connected in series in the discharge path are fully turned on due to sufficient gate-source voltage. The discharge path provides a low-impedance discharge path between control node V3 and ground, quickly dissipating the charge pulled up when the source of M10 was powered on, thereby pulling the potential of node V4 down to ground potential. As the potential of node V4 decreases, the pre-startup current source M9 turns off, and the pre-startup function ends; thereafter, the op-amp tail current source composed of series NMOS transistors begins to work normally, providing steady-state operating current for the operational amplifier.

[0040] Furthermore, the tail current source of the operational amplifier circuit includes NMOS transistors M6, M7, and M8 in series; the drain of NMOS transistor M6 is connected to the drain of NMOS transistor M9, and the source is connected to the drain of NMOS transistor M7; the source of NMOS transistor M7 is connected to the drain of NMOS transistor M8; the gates of NMOS transistors M6, M7, and M8 are all connected to the reference voltage VREF; the source of NMOS transistor M8 is grounded.

[0041] Specifically, in this embodiment, the tail current source of the operational amplifier circuit adopts a series structure of M6, M7, and M8, which is beneficial for flexibly adjusting the current value and withstand voltage in high-voltage applications, and optimizing power consumption and performance.

[0042] Furthermore, the operational amplifier circuit also includes PMOS transistors M2 and M3 and NMOS transistors M4 and M5; the source of PMOS transistor M2 and the source of PMOS transistor M3 are connected to the power supply voltage VDD, the gate of PMOS transistor M2 is connected to the gate of PMOS transistor M3, and the drain of PMOS transistor M2 is connected to the gate of power transistor M1; the drain of PMOS transistor M3 is shorted to its gate and connected to the drain of NMOS transistor M5; the gate of NMOS transistor M5 is connected to the feedback voltage VFB, and its source is connected to the drain of NMOS transistor M9; the drain of NMOS transistor M4 is connected to the drain of PMOS transistor M2, its gate is connected to the reference voltage VREF, and its source is connected to the drain of NMOS transistor M9.

[0043] Furthermore, the source of the PMOS power transistor M1 is connected to the power supply voltage VDD, and the drain is the output voltage VOUT; resistors R1 and R2 are connected in series between the output voltage and ground, and the feedback voltage VFB is drawn from the midpoint of the series connection.

[0044] In one optional implementation, the high-voltage NMOS transistors used in both the voltage reference generation circuit and the pre-start-up circuit have an isolation ring ISO_N structure, which can serve as an identifier for high-voltage devices. It should be noted that the specific vertical or horizontal structure of the high-voltage NMOS transistor can vary depending on the selected foundry process, as long as it possesses the required high-voltage withstand characteristics; the specific structure and type are not limited. Furthermore, since wide-input-range LDO designs themselves require the use of high-voltage devices, the selection of high-voltage NMOS transistors in the circuit of this invention eliminates the need for an additional mask layer, thereby avoiding increased manufacturing costs due to increased process complexity.

[0045] In one optional embodiment, the high-voltage NMOS transistor M10 of the equivalent capacitor unit can be, but is not limited to, a DENMOS, LDNMOS, or other high-voltage MOS transistors. This can be understood as any high-voltage metal-oxide-semiconductor field-effect transistor with a high-voltage vertical structure and usable internal parasitic capacitance, which can be used as the equivalent capacitor in this embodiment to achieve the same capacitive coupling and pull-up function. In this embodiment, the PN junction capacitance between the NBL layer and Bulk of the high-voltage NMOS transistor, and the body diode junction capacitance between the drain and the substrate, are used to equivalently replace the MOM capacitor.

[0046] Please see Figure 4 , Figure 4 This is a schematic diagram of the vertical structure of the equivalent capacitance of a high-voltage NMOS provided in an embodiment of the present invention. Figure 3 As can be seen from the connection method, the drain and ISO_N terminal of the equivalent capacitor M10 are connected to the power supply voltage VDD; the gate and Bulk terminal are shorted and connected to the source, serving as the other end of the capacitor. At this time, NBL, Psub, and Pwell where Bulk are located form a PN junction and are in a reverse-biased operating state; the barrier capacitance generated by the reverse-biased PN junction is used as the equivalent capacitor. Simultaneously, the buried NBL structure provides high withstand voltage capability to the substrate Psub, thereby ensuring that the equivalent capacitor unit can operate reliably in a high-voltage power supply environment.

[0047] like Figure 5 As shown, Figure 5 This diagram compares the voltage changes with and without a pre-start circuit in an embodiment of the present invention, simulating a power-on scenario and demonstrating the difference in output overshoot with and without the pre-start circuit. The diagram clearly shows that without the pre-start circuit, the output voltage exhibits a significant overshoot peak in the initial power-on phase, slowly decreasing as the power supply voltage VDD stabilizes, with substantial voltage fluctuations and recovery delays. With the pre-start circuit, the output voltage shows a smooth and controllable upward trend during the power-on phase and quickly stabilizes near the target value, effectively suppressing the output voltage overshoot.

[0048] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the claims. All of these variations are within the protection scope of the present invention.

Claims

1. A high-voltage self-biased pre-start-up LDO circuit, comprising a feedback voltage divider circuit, an operational amplifier circuit, and a PMOS power transistor; the feedback voltage divider circuit is composed of resistors R1 and R2, and obtains a feedback voltage VFB by dividing the output voltage VOUT; the first input terminal of the operational amplifier circuit is connected to a reference voltage VREF, the second input terminal is connected to the feedback voltage VFB, and the amplified signal is output to the gate of the power transistor M1; characterized in that, It also includes a self-biasing circuit, a voltage reference generation circuit, and a pre-startup circuit; One end of the self-biasing circuit is connected to the power supply voltage VDD, and the other end is grounded, providing a bias voltage V1 for the voltage reference generating circuit and the operational amplifier circuit. The input terminal of the voltage reference generating circuit is connected to the bias voltage V1, and the output terminal generates the reference voltage VREF, which is weakly correlated with temperature. The pre-start circuit is connected to the tail current source of the self-biasing circuit, the voltage reference circuit, and the operational amplifier circuit. The pre-start circuit includes an equivalent capacitor unit, a pre-start branch, and a pre-start current source. In the initial stage of power-on, the bias voltage V1 rises with the power supply voltage VDD, turns on the pre-start branch, and pulls up the voltage of the control node V3 through the equivalent capacitor unit to turn on the pre-start current source; when the reference voltage VREF stabilizes, the pre-start branch pulls down the voltage of the control node V3 to turn off the pre-start current source.

2. The high-voltage self-biased pre-start LDO circuit as described in claim 1, characterized in that, The self-biasing circuit includes a resistor R3 and at least one NMOS transistor M12, M13, or M14 connected in diode configuration. One end of the resistor R3 is connected to the power supply voltage VDD, and the other end of the resistor R3 is the output node of the bias voltage V1, and is connected to the drain and gate of the NMOS transistor M12. The source of the NMOS transistor M12 is connected to the drain and gate of the NMOS transistor M13, the source of the NMOS transistor M13 is connected to the drain and gate of the NMOS transistor M14, and the source of the NMOS transistor M14 is grounded.

3. The high-voltage self-biased pre-start LDO circuit as described in claim 2, characterized in that, The voltage reference generation circuit includes a source follower M11, an enhancement-type NMOS transistor M18, and at least one depletion-type NMOS transistor M15, M16, and M17. The source follower M11 is a high-voltage depletion-type NMOS transistor. The gate of the source follower M11 is connected to the bias voltage V1, the drain and ISO_N terminal are connected to the power supply voltage VDD, and the source is connected to the Bulk terminal and outputs an intermediate voltage V2. The source of the enhancement-mode NMOS transistor M18 is grounded, and its gate and drain are shorted together and connected to the reference voltage VREF. The gates of the depletion-type NMOS transistor M15, the depletion-type NMOS transistor M16, and the depletion-type NMOS transistor M17 are connected to the gate of the enhancement-type NMOS transistor M18. The source of the depletion-type NMOS transistor M17 is connected to the drain of the enhancement-type NMOS transistor M18, the source of the depletion-type NMOS transistor M16 is connected to the drain of the depletion-type NMOS transistor M17, the source of the depletion-type NMOS transistor M15 is connected to the drain of the depletion-type NMOS transistor M16, and the drain of the depletion-type NMOS transistor M15 is connected to the source of the source follower M11.

4. The high-voltage self-biased pre-start LDO circuit as described in claim 3, characterized in that, The equivalent capacitance unit is composed of a high-voltage NMOS transistor M10; The drain and ISO_N terminal of the high-voltage NMOS transistor M10 are connected to the power supply voltage VDD, the gate and source are shorted and connected to the control node V3, and the Bulk terminal is connected to the source to form a PN junction barrier capacitor.

5. The high-voltage self-biased pre-start LDO circuit as described in claim 4, characterized in that, The pre-start branch includes a switch M19 and a discharge path; The gate of the switching transistor M19 is connected to the intermediate voltage V2, the source is connected to the control node V3, and the drain is connected to the discharge path. The discharge path includes at least one NMOS transistor M20, M21, and M22; the drain of NMOS transistor M20 is connected to the drain of the switching transistor M19, and the source is connected to the drain of NMOS transistor M21; the source of NMOS transistor M21 is connected to the drain of NMOS transistor M22; the gates of NMOS transistor M20, NMOS transistor M21, and NMOS transistor M22 are all connected to the reference voltage VREF, and the source of NMOS transistor M22 is grounded.

6. The high-voltage self-biased pre-start LDO circuit as described in claim 5, characterized in that, The pre-start branch is in the first state at the initial power-on stage. After the reference voltage VREF is stably established, the pre-start branch is in the second state. The first state is when the switch M19 is turned on and the discharge path is turned off or presents a high resistance state. The second state is when both the switch M19 and the discharge path are turned on.

7. The high-voltage self-biased pre-start LDO circuit as described in claim 6, characterized in that, The pre-start branch adjusts the number and width-to-length ratio of the NMOS transistors connected in series in the discharge path to regulate the time for switching from the first state to the second state, thereby controlling the operating time of the pre-start current source.

8. The high-voltage self-biased pre-start LDO circuit as described in claim 7, characterized in that, The pre-start-up current source is composed of an NMOS transistor M9. The gate of the NMOS transistor M9 is connected to the drain of the switching transistor M19, the source is grounded, and the drain is connected to the tail current source of the operational amplifier circuit to provide the pre-start-up tail current.

9. The high-voltage self-biased pre-start LDO circuit as described in claim 8, characterized in that, The tail current source of the operational amplifier circuit includes NMOS transistors M6, M7, and M8 in series; the drain of NMOS transistor M6 is connected to the drain of NMOS transistor M9, and the source is connected to the drain of NMOS transistor M7; the source of NMOS transistor M7 is connected to the drain of NMOS transistor M8; the gates of NMOS transistors M6, M7, and M8 are all connected to the reference voltage VREF; the source of NMOS transistor M8 is grounded.

10. The high-voltage self-biased pre-start LDO circuit as described in claim 9, characterized in that, The operational amplifier circuit also includes PMOS transistors M2 and M3 and NMOS transistors M4 and M5; The source of PMOS transistor M2 and the source of PMOS transistor M3 are connected to the power supply voltage VDD. The gate of PMOS transistor M2 is connected to the gate of PMOS transistor M3. The drain of PMOS transistor M2 is connected to the gate of power transistor M1. The drain of the PMOS transistor M3 is shorted to the gate and connected to the drain of the NMOS transistor M5. The gate of the NMOS transistor M5 is connected to the feedback voltage VFB, and the source is connected to the drain of the NMOS transistor M9. The drain of the NMOS transistor M4 is connected to the drain of the PMOS transistor M2, the gate is connected to the reference voltage VREF, and the source is connected to the drain of the NMOS transistor M9.

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