Method and system for extending life of NAND flash memory

Abstract

A method of operating a NAND flash memory of a host device includes: detecting a temporary failure of a first NAND block of a plurality of NAND blocks; in response to the detected temporary fault of the first NAND block, determining a fault verification parameter of the first NAND block; assigning the first NAND block to a temporary bad block (TBB) list based on a fault verification parameter and a number of sets of the plurality of NAND blocks assigned to the TBB list; and determining that the NAND flash memory fails when the number of the sets allocated to the TBB list in the plurality of NAND blocks is greater than or equal to a threshold number of NAND blocks.

Description

Technical Field

[0001] This topic generally relates to NAND flash memory devices, and more specifically, but not exclusively, to a method and system for extending the lifespan of NAND flash memory having multiple NAND blocks performing read / write operations. Background Technology

[0002] Flash memory is typically an electronically non-volatile computer memory storage medium that can be electrically erased and reprogrammed. There are several types of flash memory, such as NOR flash and NAND flash. NOR and NAND flash may differ at the circuit level depending on whether the bit lines or word lines are pulled high or low. Specifically, in NAND flash, the relationship between bit lines and word lines is similar to or corresponds to a NAND gate. NAND types can be used in memory cards, USB flash drives, embedded multimedia cards (eMMC), universal flash drives (UFS), solid-state drives in smartphones, etc., for general data storage and transfer.

[0003] However, NAND flash memory can fail for various reasons. Errors in NAND flash memory can be divided into two main categories: permanent (uncorrectable) errors and temporary (correctable) errors. Temporary errors in NAND flash memory can include, but are not limited to, programming interference, read interference, overprogramming, and retention errors.

[0004] The information disclosed in the background section of this disclosure is only intended to enhance the understanding of the general background of this disclosure and should not be construed as an admission or representation in any form that such information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] This document discloses a method for enhancing or extending the lifespan of a NAND flash memory having multiple NAND blocks performing read / write operations. The method includes: detecting a fault in a first NAND block among the multiple NAND blocks; determining fault verification parameters for the first NAND block in response to detecting a fault in the first NAND block, wherein the fault verification parameters include at least one of a junction temperature of the first NAND block, one or more voltage levels of the first NAND block, or an ON / OFF cell count of the first NAND block; assigning the first NAND block to a TBB list based on the fault verification parameters and the number of sets of TBB lists among the multiple NAND blocks; and determining that the NAND flash memory has failed in response to the number of sets of TBB lists among the multiple NAND blocks being greater than or equal to a threshold number of NAND blocks.

[0006] Furthermore, this disclosure relates to a computing system for enhancing or extending the lifetime of NAND flash memory having multiple NAND blocks performing read / write operations. The computing system includes a processor and a memory communicatively coupled to the processor. The memory stores processor-executable instructions that, when executed, cause the processor to perform the following operations: detect a fault in a first NAND block among the multiple NAND blocks; in response to detecting a fault in the first NAND block, determine fault verification parameters for the first NAND block, wherein the fault verification parameters include at least one of a junction temperature of the first NAND block, one or more voltage levels of the first NAND block, and an ON / OFF cell count of the first NAND block; assign the first NAND block to a TBB list based on the fault verification parameters and the number of sets of TBB lists among the multiple NAND blocks; and determine that the NAND flash memory has failed in response to the number of sets of TBB lists among the multiple NAND blocks being greater than or equal to a threshold number of NAND blocks.

[0007] This disclosure provides a method for operating a NAND flash memory of a host device, the NAND flash memory having a plurality of NAND blocks configured to perform read / write operations, the method comprising: determining whether the number of read / write operation failures is greater than a threshold number of failures; in response to determining that the number of read / write operation failures is greater than the threshold number of failures, detecting a fault in a first NAND block among the plurality of NAND blocks, wherein the fault is one of a programming fault, an erase fault, or an uncorrectable error correction code; in response to detecting a fault in the first NAND block, determining fault verification parameters for the first NAND block, wherein the fault verification parameters include at least one of a junction temperature of the first NAND block, one or more voltage levels of the first NAND block, or an ON / OFF cell count of the first NAND block; determining whether the fault verification parameters correspond to a temporary fault condition; determining whether the number of sets of the plurality of NAND blocks allocated to a temporary bad block (TBB) list is less than a threshold number of NAND blocks; and in response to determining that the fault verification parameters correspond to a temporary fault condition, and in response to determining that the number of sets of the plurality of NAND blocks allocated to the TBB list is less than the threshold number of NAND blocks, allocating the first NAND block to the TBB list.

[0008] The foregoing description of the invention is merely illustrative and is not intended to be limiting in any way. Other aspects, embodiments, and features will become apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. In the drawings, the leftmost numeral of the reference numeral identifies the drawing for which that numeral first appears. Throughout the drawings, the same reference numerals are used to refer to the same features and components. Some embodiments of systems and / or methods according to this subject matter will now be described by way of example only and with respect to the accompanying drawings, in which:

[0010] Figure 1 A flowchart illustrating a temporary failure in NAND flash memory according to existing technology is shown;

[0011] Figure 2 An exemplary architecture of a NAND flash memory having multiple NAND blocks performing read / write operations is shown according to some embodiments of the present disclosure;

[0012] Figure 3 A detailed block diagram of an apparatus for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations, according to some embodiments of the present disclosure, is shown.

[0013] Figure 4 A flowchart is shown illustrating a method for detecting temporary faults using a three-stage verification process when the temporary fault is an erasure fault, according to some embodiments of the present disclosure;

[0014] Figure 5 A flowchart is shown of a method for detecting temporary faults using a three-stage verification process when the temporary fault is an uncorrectable error (UECC) according to some embodiments of the present disclosure;

[0015] Figure 6 A flowchart is shown illustrating a method for detecting temporary faults using a three-phase verification process when the temporary fault is a programming fault, according to some embodiments of the present disclosure;

[0016] Figure 7 A flowchart illustrating a method for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations, according to some embodiments of the present disclosure, is shown; and

[0017] Figure 8 A block diagram of an exemplary computing system according to some embodiments of the present disclosure is shown.

[0018] Those skilled in the art will understand that any block diagram herein represents a conceptual diagram of an illustrative system implementing the principles of this subject matter. Similarly, it should be recognized that arbitrary flow diagrams, flowcharts, state transition diagrams, pseudocode, etc., represent various processes that can be substantially represented in a computer-readable medium and executed by a computer or processor, regardless of whether such a computer or processor is explicitly shown. Detailed Implementation

[0019] In NAND flash memory systems, environmental factors such as temperature can affect both performance and reliability. When NAND flash memory operates at high temperatures, NAND cells may become difficult to program, erase, and read. Most NAND flash memory operates normally within a specified temperature range (e.g., 0 to 70°C), but the temperature range varies between different products (e.g., solid-state drives (SSDs), universal flash memory (UFS), or embedded multimedia cards (eMMC)). If a device operates outside its operating temperature range, there is a possibility of programming failures, erasure failures, and uncorrectable errors (UECC). Figure 1 Blocks S101 and S102 in the NAND flash memory. If any block fails, according to the bad block (BB) management policy, the NAND block may be replaced by a reserved block (RB). Figure 1 Blocks S103, S106, S107, and S108 in the diagram. Because the device is still operating at a relatively high temperature, there is a possibility of erase failures on the reserved blocks, and if this process continues, all RBs will be exhausted, causing the host device to enter read-only mode. Figure 1 (Blocks S104 and S105 in the diagram). In some respects, a mechanism can be provided to extend the lifespan of NAND flash memory devices and prevent or suppress NAND flash memory devices from entering read-only mode. Furthermore, in some respects, a method and system can address one or more shortcomings of existing systems.

[0020] In this document, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or implementation of the subject matter described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0021] Although this disclosure can be modified in various variations and alternatives, specific embodiments thereof have been shown by way of example in the accompanying drawings and will be described in detail below. However, it should be understood that this is not intended to limit this disclosure to the specific forms disclosed, but rather that this disclosure should cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

[0022] The terms “comprising,” “including,” “include,” or any other variation thereof are intended to cover non-exclusive inclusion, which includes not only those components or steps in a list of components or steps, but also other components or steps not expressly listed or inherent to such a setup, device, or method.

[0023] In other words, without further restrictions, the inclusion of one or more elements in a system or apparatus that begin with "comprising..." does not preclude the presence of other elements or additional elements in the system or method.

[0024] Embodiments of this disclosure relate to a method for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations. NAND flash memory is a non-volatile storage technology that can retain data without power. One goal of NAND flash memory devices is to reduce the cost per bit and increase the maximum chip capacity, allowing flash memory to compete with magnetic storage devices such as hard drives. In NAND flash memory, the relationship between bit lines and word lines is similar to or corresponds to NAND gates. NAND types can be used in memory cards, USB flash drives, solid-state drives in smartphones, etc., for general data storage and transfer.

[0025] When a NAND flash memory device is operated outside its operating temperature and voltage range, erase failures, programming failures, or UECC may occur during read operations. Furthermore, if the device continues to operate under the same conditions, each reserved block (RB) of the host device may be exhausted, and it will become or enter read-only mode. Figure 1 As shown. In this case, the present disclosure provides a method including detecting faults within one or more NAND blocks among a plurality of NAND blocks and determining whether the nature of the fault is temporary or permanent. Temporary faults can be detected using a three-stage verification process based on the junction temperature of the NAND block (e.g., the temperature of the transistor junction of the NAND block), voltage levels (e.g., the power supply voltage (VCCQ) of the input / output interface of the NAND flash memory device and / or the power supply voltage (VCC) of the memory cells used to operate the NAND block), and ON / OFF cell counts (e.g., the number of times the NAND block switches between a programming state (ON) and an erase state (OFF)). Furthermore, the method includes transferring the NAND block with the temporary fault to a temporary bad block (TBB) list. If the temporary fault persists for multiple NAND blocks before the TBB list is full (e.g., the number of sets of NAND blocks allocated to the TBB list is less than a threshold number of NAND blocks), the steps described above of detecting the temporary fault and transferring the NAND block to the TBB are performed. Therefore, preventing the use of reserved blocks (RBs) can prevent or prohibit the device from entering read-only mode. Furthermore, the method may include setting an exception bit such that when the TBB list is full (e.g., the number of sets of multiple NAND blocks allocated to the TBB list is greater than or equal to a threshold number of NAND blocks), the host device with NAND flash memory is reset. In other words, RB block usage may be rapid, and if the host device continues to operate in an exception environment, the host device can enter read-only mode.

[0026] Therefore, this disclosure can be used to extend the lifespan of NAND flash memory with multiple NAND blocks performing read / write operations or to operate the NAND flash memory. Because this disclosure initially detects temporary EF, PF, and UECC errors, unnecessary RB remapping can be avoided. Use cases for this disclosure include, but are not limited to, automotive UFS or SSDs. In the aforementioned scenarios, NAND flash memory devices may be used in various geographical environments and may operate at different high or low temperatures, which may cause temporary failures. In such scenarios, when the device (NAND flash memory) is operating in an abnormal host environment, this disclosure enables the host device to reset the device.

[0027] In the following detailed description of embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of this disclosure, in which specific embodiments in which the disclosure may be practiced are illustrated by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it should be understood that other embodiments may be utilized and changes may be made without departing from the scope of the disclosure. Therefore, the following description should not be considered limiting.

[0028] Figure 2 Example diagrams of NAND flash memory configured in an apparatus for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations, according to some embodiments of the present disclosure, are shown. In some embodiments, the NAND flash memory apparatus may include a block decoder, NAND blocks 0, 1, 2, ... n-1, a ground select transistor GST, a ground select line GSL, a source line SL, a bit line BL, a floating gate transistor FGT, a word line WL, and a page decoder.

[0029] The hierarchical structure of NAND flash memory begins at the cell level, establishing strings, pages, blocks, planes, and dies. A string is a series of connected NAND cells, where the source of one cell is connected to the drain of the next cell. In other words, NAND flash memory cells are organized into an array, block, and page hierarchy, such as... Figure 2 As shown, a NAND flash memory array can be divided into multiple NAND blocks, and each block contains multiple pages. Furthermore, each NAND block can include 16 to 64 memory cells, such as... Figure 2As shown. All memory cells within the same block can be erased simultaneously, and data can be programmed and retrieved on a page-by-page basis. All memory cell blocks can share bit lines and on-chip page buffers for storing the data being programmed. However, if the host environment is not within the 0 to 70°C range, NAND flash memory may malfunction. Accordingly, it is desirable to detect temporary faults within the NAND block. Temporary faults within the NAND block can be identified via a three-stage verification process by the device's processor. The three-stage verification process is performed based on the junction temperature of the NAND block, one or more voltage levels (e.g., VCC / VCCQ), and the ON / OFF cell count. A temporary fault can be one of a programming fault (PF), an erase fault (EF), or an uncorrectable error correction code (UECC). Based on the detection of temporary faults within the NAND block, the processor can assign the NAND block with the temporary fault to a temporary bad block (TBB) list. Furthermore, if the temporary fault persists, the detection of temporary faults and the allocation of NAND blocks can be repeated until the TBB list is full (e.g., the number of sets of multiple NAND blocks allocated to the TBB list is greater than or equal to a threshold number of NAND blocks). In addition, the processor can set an exception bit to reset the host device with NAND flash memory when the TBB list is full.

[0030] Figure 3 A detailed block diagram of an apparatus for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations, according to some embodiments of the present disclosure, is shown.

[0031] Figure 3 The device shown may include, but is not limited to, various hardware components such as processor 302, I / O interface 304, memory 306, and sensor circuitry 308. Processor 302, memory 306, I / O interface 304, and sensor circuitry 308 may be communicatively coupled to each other via wired or wireless communication channels. Furthermore, processor 302 may be configured to execute instructions stored in memory 306 and perform various processes, such as determining the junction temperature and / or voltage level of a NAND block based on electrical and / or thermal data output by sensor circuitry 308 (e.g., a temperature sensor, a voltage / current sensor, a resistive sensor that correlates resistance measurements with temperature, etc.). I / O interface 304 may be configured to couple internal hardware components to external devices via one or more networks. Memory may also store instructions to be executed by the processor. Memory may include random access memory (RAM) cells and / or non-volatile memory cells, such as read-only memory (ROM), optical disc drives, disk drives, flash memory, electrically erasable read-only memory (EEPROM), storage space on servers or in the cloud, etc. The memory 306 can also store data processed by the processor and obtained via the I / O interface 304.

[0032] In some embodiments, processor 302 can be configured to use a three-stage verification process to detect temporary faults within NAND blocks in a plurality of NAND blocks. Initially, processor 302 may receive read / write requests from a host device. Furthermore, processor 302 may perform read / write operations in response to receiving a read / write request. Processor 302 may detect temporary faults within NAND blocks in a plurality of NAND blocks. A temporary fault may be one of a programming fault (PF), an erase fault (EF), or an uncorrectable error correction code (UECC). Then, during the execution of a read / write operation, processor 302 may detect whether the fault has occurred beyond a threshold number of faults (e.g., three times). When the fault in a NAND block has occurred beyond the threshold number of faults, a three-stage verification process is performed based on junction temperature, voltage level (e.g., VCC / VCCQ), and ON / OFF cell counts. However, if the three-stage verification process determines that the junction temperature, voltage level (VCC / VCCQ), and ON / OFF cell counts are within a predefined range, processor 302 may classify the fault as a permanent fault of the NAND flash memory, as described in further detail below.

[0033] If any of the junction temperature, voltage level (VCC / VCCQ), and ON / OFF cell count exceeds the corresponding threshold range, processor 302 determines the fault to be a temporary fault, and processor 302 may add the NAND block with the detected temporary fault to the Temporary Bad Block (TBB) list. For example, when the junction temperature exceeds the threshold junction temperature range (0 to 70°C), processor 302 may not check the voltage level (VCC / VCCQ) and ON / OFF cell count. Processor 302 may allocate a NAND block to the TBB when it is determined that the TBB is not full (e.g., the number of NAND blocks in the set allocated to the TBB list is less than the threshold number of NAND blocks). Furthermore, when the host device is operating under normal conditions (i.e., when the junction temperature is within 0 to 70°C and the voltage level VCC / VCCQ is within the corresponding voltage threshold range), processor 302 may perform an erase operation on the NAND blocks listed in the TBB list during standard operating conditions, as described in further detail below.

[0034] In another example, when the junction temperature is within the threshold junction temperature range, processor 302 can determine whether the voltage level (VCC / VCCQ) exceeds the threshold operating voltage range. In other words, when the host environment temperature is within the operating range, processor 302 can check the operating voltage level. If the voltage level is not within the threshold operating voltage range, processor 302 can determine whether the TBB is full (e.g., whether the number of sets of multiple NAND blocks allocated to the TBB list is greater than or equal to the threshold number of NAND blocks). When processor 302 determines that the TBB is not full, processor 302 can allocate NAND blocks to the TBB and perform an erase operation on the NAND blocks listed in the TBB list during standard operating conditions, as described in further detail below.

[0035] As another example, when both the junction temperature and voltage level are within the corresponding threshold range, the processor 302 can compare the ON / OFF cell count with the threshold count value. When the ON / OFF cell count exceeds the threshold count value, the processor 302 can allocate the NAND block to the TBB list. Furthermore, if the processor 302 determines that the ON / OFF cell count is less than or equal to the threshold count value, the processor 302 can notify the host that the NAND flash memory failure is not temporary in nature and can be considered a permanent failure.

[0036] Figure 4 A flowchart is shown of a method for detecting temporary faults using three-stage verification according to some embodiments of the present disclosure.

[0037] A three-stage verification process is performed independently for junction temperature, voltage level (VCC / VCCQ), and ON / OFF cell count. As an example, processor 302 can receive write requests from the host device and select an available NAND block (S401 and S402). Based on the received write request, processor 302 can perform an erase operation before the write operation (S403, S404, S405, and S406). Furthermore, processor 302 can detect the presence of faults and determine whether the number of write operation failures exceeds a threshold number of failures (e.g., 3) (S405 and S406). If the number of write operation failures exceeds the threshold number of failures, processor 302 can determine whether the junction temperature exceeds the operating temperature range (e.g., whether the junction temperature is greater than HTL or less than LTL, as shown in S407 and S408) based on temperature data obtained from sensor circuit 308. If the junction temperature exceeds the threshold junction temperature range, the processor 302 may allocate NAND blocks to the TBB when it determines that the TBB is not full (e.g., the number of sets of NAND blocks allocated to the TBB list is less than the threshold number of NAND blocks) (S409 and S410), and perform erase operations on the NAND blocks listed in the TBB list during standard operating conditions (S411, S412, S413, S414, S415, S416, S417 and S430, which will be referred to below). Figure 7 (Further detailed description). When the junction temperature is within the operating temperature range, the processor 302 can determine whether the voltage level is within the threshold voltage range (e.g., determine whether VCC and VCCQ are greater than the corresponding upper limit voltage (HVCC and HVCCQ) or less than the lower limit voltage (LVCC and LVCCQ)) (S418 and S419), and when the voltage level (VCC / VCCQ) exceeds the threshold operating voltage range, determine whether the TBB list is full in response to the voltage level exceeding the threshold voltage range (S409). When the voltage level is within the threshold operating voltage range, the processor 302 can compare the ON / OFF cell count with the threshold count value, and if the ON / OFF cell count is greater than the threshold count value, allocate NAND blocks to the TBB list (S420 and S421).

[0038] As another example and reference Figure 5When the temporary fault is UECC, the processor 302 can first receive a read request from the host device (S501). Based on the received read request, the processor can perform a read operation (S502, S503, S504, and S505). When the number of read operation failures is less than the threshold number of failures (e.g., 3), the processor 302 can execute the read request (S502, S503, and S504). In other words, when the temporary fault is UECC (S504), the processor 302 can determine whether the junction temperature exceeds the threshold junction temperature range based on the temperature data obtained from the sensor circuit 308 (e.g., determine whether the junction temperature is greater than HTL or less than LTL, as shown in S506 and S507). If the junction temperature exceeds the threshold junction temperature range, the processor 302 may allocate NAND blocks to the TBB when it determines that the TBB is not full (e.g., the number of sets of NAND blocks allocated to the TBB list is less than the threshold number of NAND blocks) (S508 and S509), and perform erase operations on the NAND blocks listed in the TBB list during standard operating conditions (S510, S511, S512, S513, S514, S516, and S517, which will be referred to below). Figure 7 (Further detailed description). When the junction temperature is within the threshold junction temperature range, processor 302 can determine whether the voltage level is within the threshold voltage range (e.g., determine whether VCC and VCCQ are greater than the corresponding upper limit voltage (HVCC and HVCCQ) or less than the lower limit voltage (LVCC and LVCCQ)) (S518 and S519), and when the voltage level (VCC / VCCQ) exceeds the threshold operating voltage range, determine whether the TBB list is full in response to the voltage level exceeding the threshold voltage range (S508). When both the junction temperature and the voltage level are within the corresponding threshold operating range, processor 302 can compare the ON / OFF cell count with the threshold count value, and if the ON / OFF cell count is greater than the threshold count value, allocate a NAND block to the TBB list (S520 and S521).

[0039] As another example and reference Figure 6When the temporary fault is a programming fault, the processor 302 can first receive a write request from the host device (S601). Based on the received write request, the processor 302 can perform a write operation (S602, S603, S604, and S605). When the number of write operation failures is less than the threshold number of failures (e.g., 3), the processor 302 can execute the write request (S602, S603, and S604). In other words, when the temporary fault is a programming fault (S604), the processor 302 can determine whether the junction temperature exceeds the threshold junction temperature range based on the temperature data obtained from the sensor circuit 308 (e.g., determine whether the junction temperature is greater than HTL or less than LTL, as shown in S606 and S607). If the junction temperature exceeds the threshold junction temperature range, the processor 302 may allocate NAND blocks to the TBB when it determines that the TBB is not full (e.g., the number of sets of NAND blocks allocated to the TBB list is less than the threshold number of NAND blocks) (S608 and S609), and perform erase operations on the NAND blocks listed in the TBB list during standard operating conditions (S610, S611, S612, S613, S614, S615, and S616, which will be referred to below). Figure 7 (Further detailed description below). If the TBB list is full, the processor 302 can set an exception bit and reset the device (S617), which will be described in further detail below. When the junction temperature is within the threshold junction temperature range, the processor 302 can determine whether the voltage level is within the threshold voltage range (e.g., determine whether VCC and VCCQ are greater than the corresponding upper limit voltage (HVCC and HVCCQ) or less than the lower limit voltage (LVCC and LVCCQ)) (S618 and S619), and when the voltage level (VCC / VCCQ) exceeds the threshold operating voltage range, determine whether the TBB list is full in response to the voltage level exceeding the voltage range (S608). When both the junction temperature and the voltage level are within the corresponding threshold operating range, the processor 302 can compare the ON / OFF cell count with the threshold count value, and if the ON / OFF cell count is greater than the threshold count value, allocate a NAND block to the TBB list (S620, S621).

[0040] Figure 7 A flowchart is shown of a method for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations, according to some embodiments of the present disclosure.

[0041] like Figure 7As shown, method 700 includes one or more blocks, illustrating a method for extending the lifetime of a NAND flash memory having multiple NAND blocks performing read / write operations. Method 700 can be described in the general context of computer-executable instructions. Typically, computer-executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions that perform functions or implement abstract data types.

[0042] The order in which method 700 is described should not be construed as a limitation, and any number of the described method blocks can be combined in any order to implement method 700. Furthermore, individual blocks may be removed from the method without departing from the spirit and scope of the subject matter described herein. Moreover, method 700 can be implemented in any suitable hardware, software, firmware, or a combination thereof.

[0043] At block 701, method 700 may include the processor 302 detecting a temporary fault in or within a first NAND block of a plurality of NAND blocks. A temporary fault may be one of a programming fault (PF), an erase fault (EF), or an uncorrectable error correction code (UECC). At block 703, in response to detecting a temporary fault in the first NAND block, the processor 302 determines fault verification parameters for the first NAND block, wherein the fault verification parameters include at least one of the junction temperature of the first NAND block, one or more voltage levels (e.g., VCC / VCCQ) of the first NAND block, or the ON / OFF cell count of the first NAND block. To determine the fault verification parameters, the processor 302 may perform the three-stage verification process described herein. At block 705, the processor 302 assigns the first NAND block to a list of temporarily bad blocks (TBBs) based on the fault verification parameters (e.g., when the fault verification parameters satisfy a temporary fault condition) and the number of sets of the plurality of NAND blocks assigned to a TBB list.

[0044] As an example implementation of blocks 701, 703, and 705, when the number of detected fault occurrences exceeds a threshold number of faults (e.g., three), processor 302 can determine whether the junction temperature exceeds the threshold junction temperature range. If the junction temperature exceeds the threshold junction temperature range, processor 302 can allocate NAND blocks to the TBB if it is determined that the TBB is not full (e.g., the number of sets of NAND blocks allocated to the TBB list is less than the threshold number of NAND blocks), and perform an erase operation on the NAND blocks listed in the TBB list during standard operating conditions, as described in further detail below. However, if the fault does not occur three times, processor 302 can perform a read / write operation because the temperature is within the threshold junction temperature range. Since the junction temperature is within the operating temperature range, processor 302 can check the voltage level and allocate NAND blocks to the TBB list based on whether the TBB list is full and the voltage value. When both the junction temperature and the voltage level are within the corresponding threshold range, processor 302 can compare the ON / OFF cell count with the threshold count value and allocate NAND blocks to the TBB list based on the ON / OFF cell count and the determination that the TBB list is full.

[0045] At block 707, method 700 may include determining that a NAND flash memory device has failed when the number of sets of multiple NAND blocks allocated to the TBB list is greater than or equal to a threshold number of NAND blocks. As an example implementation of block 707, processor 302 may set an exception bit such that the host device having NAND flash memory is reset when the TBB list is full.

[0046] In some embodiments, during standard operating conditions and when the number of NAND blocks allocated to the TBB list is less than a threshold number of NAND blocks, processor 302 may perform an erase operation on the NAND blocks listed in the TBB list. As an example, the erase operation may be initiated on the NAND blocks listed in the TBB list after an idle time and within a threshold junction temperature range and a threshold operating voltage range. Furthermore, after a successful erase operation, the NAND blocks may be transferred from the TBB list to the Free Block (FB) list. However, if the erase operation is unsuccessful, processor 302 may transfer the NAND blocks from the TBB list to the Runtime Bad Block (RTBB) list.

[0047] This disclosure can be used to extend the lifespan of NAND flash memory with multiple NAND blocks performing read / write operations. This disclosure initially detects temporary EF, PF, and UECC errors, which can prevent unnecessary RB remapping. Use cases for this disclosure include, but are not limited to, automotive UFS or SSDs. In the aforementioned scenarios, NAND flash memory devices may be used in various geographical environments and may operate at different high or low temperatures, potentially leading to temporary failures. In such scenarios, when the device (NAND flash memory) is operating in an abnormal host environment, this disclosure helps to reset the device.

[0048] Computing System

[0049] In some embodiments, Figure 8 A block diagram of an exemplary computing system 800 for implementing embodiments of the present disclosure is shown. In some embodiments, the computing system 800 is used to extend the lifetime of NAND flash memory having multiple NAND blocks performing read / write operations. The computing system 800 may include a central processing unit (“CPU” or “processor”) 802. The processor 802 may include at least one data processor 802 for executing program components to perform user- or system-generated business processes. The processor 802 may include dedicated processing units, such as an integrated system (bus) controller, a memory management control unit, a floating-point unit, a graphics processing unit, a digital signal processing unit, etc. In some embodiments, processor 302 may be implemented by processor 802.

[0050] Processor 802 can be configured to communicate with input device 811 and output device 812 via I / O interface 801. I / O interface 801 can employ various communication protocols / methods, such as, but not limited to, audio, analog, digital, stereo, IEEE-1394, serial bus, Universal Serial Bus (USB), infrared, PS / 2, BNC, coaxial, component, composite, digital video interface (DVI), high-definition multimedia interface (HDMI), radio frequency (RF) antenna, S-video, video graphics array (VGA), IEEE 802.n / b / g / n / x, Bluetooth, cellular (e.g., Code Division Multiple Access (CDMA), High Speed ​​Packet Access (HSPA+), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), WiMax, etc.). Using I / O interface 801, computing system 800 can communicate with input device 811 and output device 812.

[0051] In some embodiments, processor 802 may be configured to communicate with communication network 809 via network interface 803. Network interface 803 can communicate with communication network 809. Network interface 803 may employ various connection protocols, including but not limited to direct connection, Ethernet (e.g., twisted pair 10 / 100 / 1000 Base T), Transmission Control Protocol / Internet Protocol (TCP / IP), Token Ring, IEEE 802.11a / b / g / n / x, etc. Communication network 809 may be implemented as one of different types of networks within the vehicle, such as an intranet or local area network (LAN), Controller Area Network (CAN), etc. Communication network 809 may be a private network or a shared network, representing an association of different types of networks communicating with each other using various protocols such as Hypertext Transfer Protocol (HTTP), CAN protocol, Transmission Control Protocol / Internet Protocol (TCP / IP), Wireless Application Protocol (WAP), etc. Furthermore, communication network 809 may include various network devices, including routers, bridges, servers, computing devices, storage devices, etc. These one or more computing devices may include, but are not limited to, mobile phones, tablet phones, laptops, etc. In some embodiments, the processor 802 may be configured to connect to the memory 805 (e.g., via the storage interface 804) Figure 8 (RAM, ROM, etc., not shown) communicate. Storage interface 804 can be connected to memory 805 using various connection protocols such as Serial Advanced Technology Attachment (SATA), Integrated Drive Electronics (IDE), IEEE-1394, Universal Serial Bus (USB), Fibre Channel, Small Computer System Interface (SCSI), etc. Memory 805 includes, but is not limited to, memory drives, removable disk drives, etc. Memory drives may further include magnetic drums, disk drives, magneto-optical drives, optical disc drives, redundant arrays of independent disks (RAID), solid-state storage devices, solid-state drives, etc. Memory 805 can store a collection of program or database components, including, but not limited to, user interface 806, operating system 807, web browser 808, etc. In some embodiments, computing system 800 can store user / application data, such as data, variables, records, etc., as described in this disclosure. Such a database can be implemented as a fault-tolerant, relational, scalable, and secure database, such as Oracle or Sybase.

[0052] Operating system 807 facilitates resource management and operation of computing system 800. Examples of operating systems include, but are not limited to, Apple. ® MACINTOSH ® OS X ® UNIX ® UNIX-like system distributions (e.g., BERKELEY SOFTWARE EDISTRIBUTION)® (BSD), FreeBSD ® NETBSD ® (such as OpenBSD) LINUX ® Disciplinations (e.g., Red Hat) ® UBUNTU ® KUBUNTU ® etc.), IBM ® OS / 2 ® MICROSOFT ® WINDOWS ® (XP) ® VISTA ® / 7 / 8, 10, etc.), APPLE ® iOS ® Google TM ANDROID TM BLACKBERRY ® Operating system, etc. The user interface 806 can facilitate the display, execution, interaction, manipulation, or operation of program components through text or graphical means. For example, the user interface can provide computer interaction interface elements, such as cursors, icons, checkboxes, menus, scroll bars, windows, widgets, etc., on a display system operatively connected to the computing system 800. A graphical user interface (GUI) can be used, including but not limited to Apple's... ® Macintosh ® Aqua operating system ® IBM ® OS / 2 ® Microsoft ® Windows ® (e.g., Aero, Metro, etc.), Web interface libraries (e.g., ActiveX) ® Java ® Javascript ® AJAX, HTML, Adobe ® Flash ® etc.

[0053] In some embodiments, the computing system 800 may implement program components stored in the web browser 808. The web browser 808 may be a hypertext viewing application, such as Microsoft. ® INTERNET EXPLORER ® Google TM CHROME TM MOZILLA ®FIREFOX ® APPLE ® SAFARI ® Secure web browsing can be provided using protocols such as Hypertext Transfer Protocol Secure (HTTPS), Secure Sockets Layer (SSL), and Transport Layer Security (TLS). Web browser 808 can utilize technologies such as AJAX, DHTML, and Adobe... ® FLASH ® JAVASCRIPT ® JAVA ® Facilities such as application programming interfaces (APIs) are included. In some embodiments, the computing system 800 may implement program components stored in the mail client. The mail server may be an Internet mail server such as Microsoft Exchange. The mail server may use technologies such as Active Server Pages (ASP) and ActiveX. ® ANSI ® C++ / C#, Microsoft ® .NET, CGI SCRIPTS, JAVA ® JAVASCRIPT ® PERL ® PHP, Python ® WEBOBJECTS ® Facilities such as mail servers. Mail servers can utilize various communication protocols, such as Internet Message Access Protocol (IMAP), Message Application Programming Interface (MAPI), and Microsoft. ® Email exchange, Post Office Protocol (POP), Simple Mail Transfer Protocol (SMTP), etc. In some embodiments, the computing system 800 may implement a program component for storing an email client. The email client may be an email viewing application, such as Apple's... ® MAIL, MICROSOFT ® ENTOURAGE ® MICROSOFT ® OUTLOOK ® MOZILLA ® THUNDERBIRD ® wait.

[0054] Furthermore, one or more computer-readable storage media may be utilized in implementing embodiments of this disclosure. A computer-readable storage medium refers to any type of physical memory capable of storing information or data readable by processor 802. Therefore, a computer-readable storage medium may store instructions for execution by one or more processors 802, including instructions for causing processor 802 to perform steps or stages of the embodiments described herein. The term "computer-readable medium" should be understood to include tangible articles and exclude carrier waves and transient signals, i.e., non-transitory signals. Examples include random access memory (RAM), read-only memory (ROM), volatile memory, non-volatile memory, hard disk drives, optical disc (CD) ROMs, digital video discs (DVDs), flash drives, magnetic disks, and any other known physical storage media.

[0055] Unless otherwise expressly stated, the terms “an embodiment,” “an embodiment,” “multiple embodiments,” “the embodiment,” “the multiple embodiments,” “one or more embodiments,” “some embodiments,” and “an embodiment” mean “one or more (but not all) embodiments of this disclosure.”

[0056] Unless otherwise expressly stated, the terms “including,” “comprising,” “having,” and variations thereof mean “including, but not limited to.” Unless otherwise expressly stated, the listed items do not imply that any or all of the items are mutually exclusive.

[0057] Unless otherwise expressly stated, the terms "a," "an," and "the" mean "one or more." The description of embodiments in which multiple components communicate with each other does not imply that all of these components are necessary. Rather, a variety of optional components are described to illustrate various possible embodiments of this disclosure.

[0058] When a single device or item is described herein, it is apparent that multiple devices / items (whether they cooperate or not) may be used in place of the single device / item. Similarly, in cases where multiple devices or items (whether they cooperate or not) are described herein, it is apparent that a single device / item may be used in place of these multiple devices or items, or that a different number of devices / items may be used in place of the number of devices or programs shown. The functionality and / or features of a device may be alternatively embodied by one or more other devices not explicitly described as having such functionality / features. Therefore, other embodiments of this disclosure do not necessarily need to include the device itself.

[0059] Finally, the language used in this specification has been chosen primarily for readability and instructional purposes, and not for defining or limiting the subject matter of the invention. Therefore, the scope of this disclosure should not be limited by the specific description, but rather by the claims issued based on this application. Accordingly, the embodiments of this disclosure are intended to illustrate, rather than limit, the scope of which is set forth in the appended claims.

[0060] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The aspects and embodiments disclosed herein are for illustrative purposes and not restrictive, and the true scope and spirit are indicated by the appended claims.

Claims

1. A method for operating NAND flash memory of a host device, the NAND flash memory having a plurality of NAND blocks configured to perform read / write operations, the method comprising: Detecting a fault in the first NAND block among the plurality of NAND blocks; In response to detecting a fault in the first NAND block, fault verification parameters for the first NAND block are determined, wherein the fault verification parameters include at least one of the junction temperature of the first NAND block, one or more voltage levels of the first NAND block, or the ON / OFF cell count of the first NAND block. Based on the fault verification parameters and the number of sets of TBB lists allocated to temporary bad blocks in the plurality of NAND blocks, the first NAND block is assigned to the TBB list; and In response to the fact that the number of sets of the plurality of NAND blocks allocated to the TBB list is greater than or equal to a threshold number of NAND blocks, it is determined that the NAND flash memory has failed.

2. The method according to claim 1, wherein, The fault is one of a programming fault, an erasure fault, or an uncorrectable error code.

3. The method according to claim 1, further comprising: Receive read / write requests from the host device; In response to receiving the read / write request, a read / write operation is initiated on the first NAND block; Determine if the number of read / write operation failures exceeds the threshold number of failures; as well as In response to the number of read / write operation failures exceeding the threshold number of failures, a fault is detected in the first NAND block.

4. The method according to claim 3, further comprising: In response to detecting a fault in the first NAND block, the junction temperature of the first NAND block is determined; as well as Determine whether the junction temperature of the first NAND block is within the threshold junction temperature range.

5. The method according to claim 4, further comprising: In response to determining that the junction temperature of the first NAND block is not within the threshold junction temperature range, the first NAND block is assigned to the TBB list.

6. The method according to claim 4, further comprising: In response to determining that the junction temperature of the first NAND block is within the threshold junction temperature range, the one or more voltage levels of the first NAND block are determined; as well as Determine whether the one or more voltage levels are within the threshold voltage range.

7. The method according to claim 6, further comprising: In response to determining that at least one of the one or more voltage levels is not within the threshold voltage range, the first NAND block is assigned to the TBB list.

8. The method according to claim 6, further comprising: In response to determining that the one or more voltage levels are within the threshold voltage range, the ON / OFF cell count of the first NAND block is determined; Determine whether the ON / OFF unit count is greater than the threshold ON / OFF unit count value; and In response to determining that the ON / OFF cell count is greater than the threshold ON / OFF cell count value, the first NAND block is allocated to the TBB list.

9. The method according to claim 1, further comprising: In response to performing an erase operation on the first NAND block, the first NAND block is transferred from the TBB list to the free block list.

10. An apparatus for operating NAND flash memory of a host device, the NAND flash memory having a plurality of NAND blocks configured to perform read / write operations, the apparatus comprising: The processing unit is configured as follows: Detecting a fault in the first NAND block among the plurality of NAND blocks; In response to detecting a fault in the first NAND block, fault verification parameters for the first NAND block are determined, wherein the fault verification parameters include at least one of the junction temperature of the first NAND block, one or more voltage levels of the first NAND block, and the ON / OFF cell count of the first NAND block. Based on the fault verification parameters and the number of sets of the TBB lists allocated to the plurality of NAND blocks, the first NAND block is assigned to the TBB list; In response to the fact that the number of sets of the plurality of NAND blocks allocated to the TBB list is greater than or equal to a threshold number of NAND blocks, it is determined that the NAND flash memory has failed.

11. The apparatus according to claim 10, wherein, The fault is one of a programming fault, an erasure fault, or an uncorrectable error code.

12. The apparatus according to claim 10, wherein, The processing unit is configured as follows: Receive read / write requests from the host device; In response to receiving the read / write request, a read / write operation is initiated on the first NAND block; Determine if the number of read / write operation failures exceeds the threshold number of failures; as well as In response to the number of read / write operation failures exceeding the threshold number of failures, a fault is detected in the first NAND block.

13. The apparatus according to claim 12, wherein, The processing unit is further configured to: In response to detecting a fault in the first NAND block, the junction temperature of the first NAND block is determined; and Determine whether the junction temperature of the first NAND block is within the threshold junction temperature range.

14. The apparatus according to claim 13, wherein, The processing unit is further configured to: in response to determining that the junction temperature of the first NAND block is not within the threshold junction temperature range, allocate the first NAND block to the TBB list.

15. The apparatus according to claim 13, wherein, The processing unit is configured as follows: In response to determining that the junction temperature of the first NAND block is within the threshold junction temperature range, the one or more voltage levels of the first NAND block are determined; as well as Determine whether the one or more voltage levels are within the threshold voltage range.

16. The apparatus according to claim 15, wherein, The processing unit is configured to allocate the first NAND block to the TBB list in response to determining that at least one of the one or more voltage levels is not within the threshold voltage range.

17. The apparatus according to claim 15, wherein, The processing unit is configured as follows: In response to determining that the one or more voltage levels are within the threshold voltage range, the ON / OFF cell count of the first NAND block is determined; Determine whether the ON / OFF unit count is greater than the threshold ON / OFF unit count value; and In response to determining that the ON / OFF cell count is greater than the threshold ON / OFF cell count value, the first NAND block is allocated to the TBB list.

18. The apparatus according to claim 10, wherein, The processing unit is configured to: in response to performing an erase operation on the first NAND block, transfer the first NAND block from the TBB list to the free block list.

19. A method of operating NAND flash memory of a host device, the NAND flash memory having a plurality of NAND blocks configured to perform read / write operations, the method comprising: Determine if the number of read / write operation failures exceeds the threshold number of failures; In response to determining that the number of read / write operation failures is greater than the threshold number of failures, a fault is detected in the first NAND block among the plurality of NAND blocks, wherein the fault is one of a programming fault, an erase fault, or an uncorrectable error correction code; In response to detecting a fault in the first NAND block, fault verification parameters for the first NAND block are determined, wherein the fault verification parameters include at least one of the junction temperature of the first NAND block, one or more voltage levels of the first NAND block, or the ON / OFF cell count of the first NAND block. Determine whether the fault verification parameters correspond to temporary fault conditions; Determine whether the number of sets of the TBB (Temporarily Bad Block) list allocated to the plurality of NAND blocks is less than a threshold number of NAND blocks; and In response to determining that the fault verification parameter corresponds to the temporary fault condition, and in response to determining that the number of sets of the plurality of NAND blocks allocated to the TBB list is less than the threshold number of NAND blocks, the first NAND block is allocated to the TBB list.

20. The method according to claim 19, wherein, In response to one of the following: the junction temperature of the first NAND block is within a threshold junction temperature range, the one or more voltage levels are within a threshold voltage range, or the ON / OFF cell count is greater than a threshold ON / OFF cell count value, the fault verification parameter corresponds to the temporary fault condition.

Images