Thread scheduling method and device, electronic equipment and storage medium

Abstract

The invention discloses a thread scheduling method and device, electronic equipment and a storage medium, and belongs to the technical field of operating systems. The method comprises the steps that a DSM PF event of a virtual machine is monitored, and the DSM PF event is triggered when a plurality of threads access the same shared memory page in a cross-node mode; according to the DSM PF events, an inter-thread incidence matrix is constructed, and the inter-thread incidence matrix is used for quantifying the number of times of triggering the DSM PF events between any two threads; the thread graph structure is divided to generate a thread grouping scheme with the aim of minimizing the number of DSM PF events between different grouping threads, the vertex of the thread graph structure represents the threads, and the adjacency matrix of the thread graph structure is the incidence matrix between the threads.

Description

Technical Field

[0001] This application belongs to the field of operating system technology, specifically relating to a thread scheduling method, device, electronic device, and storage medium. Background Technology

[0002] Virtualization technology abstracts underlying hardware resources, virtualizing a single physical server into multiple virtual machines, significantly improving server resource utilization and system flexibility. As an equivalent isolated copy of a real computer, a virtual machine can support the parallel execution of operating systems and applications in an independent virtual environment, enabling unified resource allocation and efficient management. However, the computing resources of traditional virtual machines are limited by the hardware capacity of a single server, making it difficult to meet the ever-increasing demands for large-scale CPU and memory resources in applications such as big data analytics and image processing.

[0003] To overcome the bottleneck of single-machine resources, resource over-allocation strategies have been widely adopted. However, resource over-allocation can easily lead to fierce competition for physical resources among multiple tasks, resulting in a decline in application performance. Against this backdrop, distributed virtualization technology has emerged, aggregating the physical resources of multiple servers across nodes to build ultra-large-scale aggregated virtual machines. By distinguishing between local and remote CPU resources and leveraging interrupt forwarding and communication interception mechanisms, cross-node CPU collaboration is achieved. Simultaneously, distributed shared memory technology is used to maintain the consistency of memory data across multiple nodes, enabling applications to transparently use virtual computing resources across nodes.

[0004] Nevertheless, the DSM mechanism in distributed virtualization introduces significant data synchronization overhead, leading to frequent contention for memory pages across nodes, which severely restricts overall performance. Summary of the Invention

[0005] The purpose of this application is to provide a thread scheduling method, apparatus, electronic device, and storage medium that can solve the problem of frequent contention for memory pages across nodes, which severely restricts overall performance.

[0006] In a first aspect, embodiments of this application provide a thread scheduling method applied to a distributed virtualization server. The distributed virtualization server includes multiple server nodes, each server node running a virtual machine, and the virtual machine containing multiple threads. The method includes: Monitor the Distributed Shared Memory Page Fault (DSM PF) events of virtual machines. DSM PF events are triggered when multiple threads access the same shared memory page across nodes. Based on the DSM PF events, construct an inter-thread association matrix. The inter-thread association matrix is ​​used to quantify the number of times the DSM PF event is triggered between any two threads. With the goal of minimizing the number of DSM PF events between different grouped threads, the thread graph structure is divided to generate a thread grouping scheme, where the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix.

[0007] Secondly, embodiments of this application provide a thread scheduling device applied to a distributed virtualization server. The distributed virtualization server includes multiple server nodes, each server node running a virtual machine, and the virtual machine containing multiple threads. The device includes: The monitoring module is used to monitor Distributed Shared Memory Page Fault (DSM PF) events of virtual machines. DSM PF events are triggered when multiple threads access the same shared memory page across nodes. The building module is used to construct an inter-thread association matrix based on DSM PF events. The inter-thread association matrix is ​​used to quantify the number of times DSM PF events are triggered between any two threads. The generation module is used to divide the thread graph structure and generate a thread grouping scheme with the goal of minimizing the number of DSM PF events between different grouped threads. In this scheme, the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix.

[0008] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, the memory storing programs or instructions executable on the processor, the programs or instructions, when executed by the processor, implementing the steps of the method described in the first aspect.

[0009] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0010] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0011] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method described in the first aspect.

[0012] In the embodiments of this application, by monitoring the Distributed Shared Memory Page Fault (DSMPF) events of the virtual machine, which are triggered when multiple threads access the same shared memory page across nodes, an inter-thread association matrix is ​​constructed based on the DSMPF events. This matrix quantifies the number of times DSMPF events are triggered between any two threads, transforming complex thread behavior relationships into a structured mathematical model, thus providing a basis for scheduling decisions. With the goal of minimizing the number of DSMPF events between different thread groups, the thread graph structure is partitioned to generate a thread grouping scheme. Here, the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix. By formulating the scheduling problem as a clear combinatorial optimization objective and obtaining an approximate optimal solution through graph partitioning, highly correlated thread groups can be adaptively bundled for scheduling, reducing data synchronization communication latency and network bandwidth consumption in the distributed shared memory environment, and improving the overall computational efficiency and overall operating performance of the aggregated virtual machine. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a distributed virtualization framework provided in an embodiment of this application; Figure 2 This is a schematic diagram illustrating a distributed virtualization memory page contention method provided in an embodiment of this application; Figure 3 This is a flowchart of a thread scheduling method provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating a thread scheduling optimization provided in an embodiment of this application; Figure 5 This is a structural diagram of a thread scheduling device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0015] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0016] The technical terms used in the embodiments of this application will be introduced below.

[0017] Distributed virtualization is a technical architecture that aggregates the computing resources of multiple physical servers into a unified resource pool through software definition, supporting virtual machines to run across nodes and breaking through the limitations of single-machine physical resources.

[0018] Distributed Shared Memory (DSM) provides logically shared, physically distributed memory access abstractions for upper-layer applications by building a globally unified address space in a distributed system. This technology utilizes memory mapping and consistency protocols to achieve cross-node data synchronization.

[0019] A Distributed Shared Memory Page Fault (DSM PF) refers to the exception handling process triggered in a DSM architecture when a thread accesses a memory page that is not located on the local node. This process involves remote page fetching, state synchronization, and consistency maintenance operations.

[0020] An Aggregate Virtual Machine (AVM) is a special virtual machine instance built on distributed virtualization technology. Its virtual resources are provided by the hardware resources of multiple physical nodes, and it can present computing resources that exceed the specifications of a single machine.

[0021] The Extended Berkeley Packet Filter (eBPF) is a programmable framework provided by the Linux kernel that allows users to safely execute custom bytecode in kernel space. It is widely used in scenarios such as network packet processing, system tracing, and performance monitoring.

[0022] The thread scheduling method provided in this application embodiment can be applied to at least the following application scenarios, which will be described below.

[0023] Distributed virtualization (DVR) is an emerging technology that allows virtual machines to utilize physical computing resources across multiple servers, aggregating them into large-scale aggregated virtual machines. To aggregate Central Processing Unit (CPU) resources across nodes, DVR distinguishes between local and remote CPU resources, intercepts message transmissions between them, and uses an interrupt forwarding mechanism to send request information to the corresponding server's Advanced Programmable Interrupt Controller (APIC), enabling normal communication between the local and remote CPUs. Therefore, applications within the aggregated virtual machine can allocate threads to any virtual CPU (vCPU) across nodes without needing to consider the underlying hardware topology. For memory resource aggregation, DVR typically employs distributed shared memory technology, achieving cross-node memory data consistency through memory copying and memory page state transitions.

[0024] The framework of distributed virtualization technology, such as Figure 1 As shown, a distributed virtualization server interconnects multiple independent physical server nodes via a network and integrates them into a unified, resource-pooled supercomputer through a software layer. In this architecture, the server nodes are the physical servers that make up this resource pool, each possessing local hardware resources such as CPU and memory.

[0025] On top of this aggregated resource pool, a special type of virtual machine can be created, called an aggregated virtual machine. The key difference between an aggregated virtual machine and a regular virtual machine is that an aggregated virtual machine sees virtual resources aggregated from all or multiple server nodes. That is, an aggregated virtual machine's vCPU might come from node A, and its memory might come from nodes A, B, and C simultaneously. For the operating system and applications running inside the aggregated virtual machine, they are unaware of the underlying hardware distribution; they still see a unified logical computer with massive computing resources.

[0026] When an application runs in an aggregated virtual machine, it creates multiple threads to execute tasks in parallel. A thread is the basic unit of task scheduling in the operating system and can be understood as the context of an execution flow. In an aggregated virtual machine, these threads can be scheduled to execute on any vCPU provided by the underlying resource pool, regardless of which server node the physical CPU core behind that vCPU resides on. This embodies the flexibility of distributed virtualization, but it also introduces technical challenges.

[0027] To ensure that these threads, which may be distributed across different server nodes, can work together correctly and efficiently, they need to communicate and exchange data through shared memory. In a distributed environment, this is achieved through Distributed Shared Memory (DSM) technology. DSM constructs a globally unified virtual memory address space at the software level, allowing all threads to access this space as if it were local memory.

[0028] However, distributed shared memory technology in distributed virtualization introduces significant data synchronization overhead. Inappropriate thread scheduling strategies can lead to frequent distributed shared memory accesses and cross-node contention for memory pages. For example... Figure 2 As shown, the thread scheduling system in a distributed virtual machine is unaware of the underlying hardware physical topology, potentially distributing multiple threads across different servers. Threads may read and write data on the same memory page, triggering cross-node data synchronization overhead. For example, if thread 1 modifies data in a memory page, and thread 2 reads that memory page, DSM technology is needed to copy the modified memory data from the corresponding server to the server where thread 2 resides to achieve cross-node consistency of memory data. If the thread scheduling mechanism is inadequate, it will trigger frequent contention for cross-node memory pages, introducing high data synchronization overhead and impacting application performance.

[0029] In response to the problems in related technologies, embodiments of this application provide a thread scheduling method, apparatus, electronic device, and storage medium, which can solve the problem of frequent contention for memory pages across nodes, which seriously restricts overall performance.

[0030] The thread scheduling method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0031] Figure 3 A flowchart of a thread scheduling method provided in an embodiment of this application.

[0032] like Figure 3 As shown, the thread scheduling method may include steps 110-130. This method is applied to a distributed virtualization server, which includes multiple server nodes. Each server node runs a virtual machine, and the virtual machine contains multiple threads, as detailed below: Step 110: Monitor the Distributed Shared Memory Page Fault (DSM PF) event of the virtual machine. The DSM PF event is triggered when multiple threads access the same shared memory page across nodes. A virtual machine (VM) can run across multiple server nodes, with its virtual CPU and memory resources shared by the physical resources on different nodes. To ensure consistent memory access, distributed shared memory (DSM) technology is used to maintain a globally unified memory address space for the VM. When threads running on different server nodes access the same memory page, a DSM page fault event (PF) is triggered. A DSM PF event is essentially an exception caused by the target memory page not being on the thread's local node, requiring a data copy to be obtained from a remote node over the network or state synchronization to be performed.

[0033] These DSM PF events are dynamically intercepted and monitored using an extended Berkeley packet filter program, eBPF, deployed within the virtual machine kernel. Because eBPF can hook into the virtual machine's page fault handling path, it captures detailed information about each page fault event.

[0034] By leveraging eBPF, monitoring programs can be deployed in user space to directly capture and analyze page fault scenarios. This non-intrusive approach not only maintains the original integrity and stability but also allows for precise tracking of the relationship between page fault events and thread execution contexts, quickly pinpointing the specific thread pairs causing cross-node data contention. This provides accurate data support for subsequent scheduling optimizations.

[0035] Step 120: Based on the DSM PF events, construct the inter-thread association matrix. The inter-thread association matrix is ​​used to quantify the number of times the DSM PF event is triggered between any two threads. The inter-thread association matrix (IPM) is a mathematical modeling tool that describes the memory access relationships between threads. The element values ​​in this symmetric matrix quantitatively represent the frequency of cross-node memory page contention between any two threads. The IPM is a square matrix where the rows and columns correspond to all active threads within the virtual machine. Each element represents the number of times the corresponding row and column threads trigger a DSM PF event within a specific time window due to contention for the same memory page.

[0036] This approach quantifies the interactions between threads into numerical values, transforming the vague notion of "interaction strength" into a computable data structure. By collecting distributed shared memory page fault events within the virtual machine, an inter-thread correlation matrix is ​​constructed to quantify the degree of interaction between threads through memory access.

[0037] Step 130: With the goal of minimizing the number of DSM PF events between different grouped threads, the thread graph structure is divided to generate a thread grouping scheme, where the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix.

[0038] The thread scheduling problem is transformed into a graph partitioning optimization problem. A thread graph structure is constructed, where each vertex represents a thread, and the weights of edges connecting two vertices are taken from the corresponding elements of the inter-thread association matrix constructed in step 120. This makes the matrix the adjacency matrix of the graph. The goal of partitioning is very clear: to find a way to divide the vertices in the graph into K subsets. Therefore, minimizing this partitioning value means grouping the threads with the most frequent memory access interactions within the same server node as much as possible, thereby minimizing the high cost of cross-node data synchronization caused by threads being scattered across different nodes.

[0039] By abstracting each thread within the virtual machine as vertices in a graph structure, and using the interaction frequency represented by DSM PF events as the weights of the connecting edges in the graph, a complete inter-thread association matrix is ​​constructed as the adjacency matrix of the graph. In other words, based on the number of times distributed shared memory page faults are triggered due to threads accessing the same memory page, a thread topology graph structure representing the strength of inter-thread associations is built.

[0040] Based on this, the thread graph structure can be divided into K subgraphs using a spectral clustering algorithm, where K equals the number of server nodes in the distributed environment. Each resulting subgraph corresponds to a physical server node, and the thread members within it are constrained to be scheduled and executed within that node through an affinity mask. This mathematical model-based partitioning method effectively ensures that memory-intensive threads are clustered on the same node, fundamentally reducing the frequency of cross-node data synchronization.

[0041] In one possible embodiment, step 110 may specifically include the following steps: Deploy the extended Berkeley packet filter eBPF program in the virtual machine kernel. The eBPF program is used to intercept page fault events triggered by distributed shared memory. For each intercepted page fault event, extract the memory page address associated with the page fault event and the thread identifier of the currently executing thread; Based on the memory page address and thread identifier, determine whether two consecutive DSM PF events targeting the same memory page are triggered by threads on different server nodes; If so, it is recorded as a DSM PF event.

[0042] eBPF, as a kernel-mode programmable technology, allows the safe execution of user-defined programs in kernel space, providing a foundation for high-performance system monitoring. Leveraging eBPF's ability to safely and efficiently execute user-defined programs in kernel mode, this method mounts custom programs to the kernel's page fault handling path, enabling real-time interception of page fault events triggered by distributed shared memory. This kernel-level monitoring approach ensures complete data acquisition while minimizing performance impact.

[0043] When an eBPF program successfully intercepts a page fault event, it captures two key metadata from the event context: the first is the virtual memory address that triggered the exception, which can be converted into a specific memory page identifier through address alignment and page table lookup; the second is the thread identifier of the current execution context, which uniquely identifies the execution unit that triggered the exception during operation, providing a basis for subsequent analysis of the relationship between threads and memory page access.

[0044] After obtaining the memory page address and thread identifier, the access sequence of each individual memory page is traced, with particular attention paid to two consecutive page fault events targeting the same memory page. When a new access is detected, it is compared to whether the thread that triggered the exception is located on a different physical server node than the thread that triggered the exception previously. This node information is typically obtained based on the mapping relationship between virtual CPUs and physical CPUs, as well as the topological location of the physical CPUs in the distributed system.

[0045] By analyzing two consecutive page fault sequences targeting the same memory page, a valid DSM PF event is defined as when the two exceptions are triggered by threads on different server nodes. For example, for a specific memory page, if a page fault triggered by thread T2 immediately follows a page fault triggered by thread T1, and the two threads are located on different physical nodes, a DSM PF event will be recorded between threads T1 and T2. This event statistics provide a crucial data foundation for subsequently constructing an inter-thread correlation matrix.

[0046] If, after comparison, it is confirmed that the threads accessing the same memory page twice consecutively belong to different nodes, then this event is officially recorded as a valid distributed shared memory page fault event. This record not only includes the event itself, but also associates it with the identifiers of the two involved threads and the specific memory page information, providing data support for subsequently constructing the relationship between threads.

[0047] Specifically, if multiple threads share memory pages across nodes, thread read and write operations will trigger a Page Fault Exception (PF) in the Data Management System (DSM). Data copying and memory page state transitions are needed to achieve cross-node data consistency. This process introduces high cross-node data synchronization overhead, and subsequent access to the same memory page by threads on other nodes will also trigger page faults again. The Global Thread Scheduling System (GPTS) utilizes eBPF technology to monitor page fault activity in the underlying memory pages within the virtual machine, accurately recording the memory page address corresponding to each page fault and the thread identifier that triggered the exception.

[0048] Therefore, a kernel-level eBPF program was used to achieve non-intrusive monitoring of distributed shared memory page fault events, providing a precise data source for optimization. By analyzing continuous access sequences and node location information, the actual contention scenarios causing cross-node data synchronization can be accurately identified. This fine-grained monitoring mechanism lays a reliable data foundation for subsequent thread correlation analysis and scheduling optimization, enabling the targeted reduction of unnecessary cross-node memory accesses, thereby improving overall performance.

[0049] In one possible embodiment, step 120 may specifically include the following steps: An initialization matrix is ​​generated based on the identifiers of all active threads in the virtual machine, and all elements of the initialization matrix are zero. Within a preset time window, monitor two consecutive DSM PF events for each memory page; If two consecutive DSM PF events are triggered by the first thread and the second thread, then the count is incremented in the matrix elements corresponding to the first and second threads in the initialization matrix; the first thread and the second thread correspond to different server nodes; By accumulating the counts of all memory pages, the inter-thread correlation matrix is ​​obtained.

[0050] An initialization matrix is ​​generated based on the identifiers of all active threads in the executable state within the virtual machine. The initialization matrix can be an N×N square matrix, where N represents the total number of active threads, and the row and column indices correspond to the unique identifier of each thread. Initially, all matrix elements are set to zero. This zero-based initialization ensures that subsequent counting operations begin from a clean baseline.

[0051] Within a pre-defined fixed time window, continuous access monitoring is performed on each individual memory page. The time window setting needs to strike a balance between data accuracy and responsiveness. For each monitored memory page, special attention is paid to two consecutively triggered DSM PF events, because consecutive accesses often better reflect real-time data dependencies between threads.

[0052] The construction process begins by initializing a matrix with all elements set to zero. For each pair of threads that generate a DSM PF (Distributed Memory Page Activation) due to the same memory page, the counts at their corresponding intersections in the matrix are accumulated. For example, assuming threads T1 and T2 access memory page P1 sequentially and trigger a DSM PF once, and threads T1 and T3 trigger two DSM PFs due to memory page P2, then in the inter-thread association matrix, the element value corresponding to T1 and T2 will increase by 1, while the element value corresponding to T1 and T3 will increase by 2. The inter-thread association matrix clearly depicts the coupling strength between any two threads in shared memory access within the virtual machine, effectively quantifying the interaction strength between any two threads caused by shared memory access.

[0053] As the time window progresses, the access sequences of all memory pages are continuously monitored and statistically analyzed, accumulating the number of DSM PF events between all cross-node thread pairs. When the preset time window ends, the fully accumulated matrix constitutes a complete inter-thread association matrix. Each element of the inter-thread association matrix intuitively reflects the frequency with which the corresponding two threads share memory data in a distributed environment, providing precise data support for subsequent optimization decisions.

[0054] In one possible embodiment, step 130 may specifically include the following steps: The degree matrix is ​​calculated based on the inter-thread association matrix. The degree matrix is ​​a diagonal matrix, and the diagonal elements of the degree matrix are the sum of the elements in each row of the inter-thread association matrix. Construct a Laplace matrix based on the inter-thread correlation matrix and degree matrix; Calculate the eigenvalues ​​and eigenvectors of the Laplacian matrix; Select the eigenvectors corresponding to the first K smallest eigenvalues ​​to form an eigenvector matrix, where K is the number of server nodes and K is a positive integer; Based on the feature vector matrix, a clustering algorithm is used to group threads and generate a thread grouping scheme.

[0055] In graph theory, the Laplacian matrix is ​​defined as the difference between the degree matrix and the adjacency matrix. This linear algebraic tool effectively reveals the spectral characteristics of graph structures and is commonly used for graph partitioning and clustering analysis. The degree matrix is ​​a diagonal matrix, with its diagonal elements corresponding to the connectivity of each vertex in the graph structure. In spectral graph theory, it is used as a normalization factor to characterize the importance of vertices. K-means clustering is a classic partitioning clustering algorithm that iteratively optimizes the distribution of data points into K clusters, minimizing the squared error within each cluster. It is characterized by its simplicity and fast convergence.

[0056] Calculate the degree matrix corresponding to the inter-thread association matrix. The degree matrix is ​​a special diagonal matrix where all off-diagonal elements are zero, and the value of each diagonal element is equal to the sum of all elements in the corresponding row of the inter-thread association matrix. This is equivalent to calculating an association degree index for each thread, which reflects the total strength of interaction between that thread and all other threads in the matrix.

[0057] After obtaining the degree matrix, the Laplace matrix is ​​constructed based on the degree matrix and the inter-thread affinity matrix. The Laplace matrix has a clear physical meaning in graph theory, characterizing the topological structure and connectivity properties of the graph. The standard method for constructing the Laplace matrix is ​​to subtract the inter-thread affinity matrix from the degree matrix, transforming the original affinity strength data into a mathematical representation that reflects the essential characteristics of the graph structure. The properties of the Laplace matrix determine the accuracy and effectiveness of subsequent analyses.

[0058] Eigenvalues ​​and corresponding eigenvectors are calculated by performing eigendecomposition on the Laplacian matrix. Eigenvalues ​​reflect the cutting structure of the graph, while eigenvectors provide the most discriminative dimensional information for graph partitioning. In particular, eigenvectors corresponding to smaller eigenvalues ​​often contain the most important connection patterns of the graph, and these vectors can map closely connected vertices closer together in the lower-dimensional space.

[0059] The eigenvectors corresponding to the top K smallest eigenvalues ​​are selected, where K equals the number of available server nodes in the distributed environment. These eigenvectors are combined to form a new eigenvector matrix, where each row of the matrix corresponds to the coordinate representation of a thread in the reduced-dimensional space. This transforms the partitioning problem, which is difficult to handle in high-dimensional graph space, into a relatively simple clustering problem in low-dimensional Euclidean space.

[0060] Based on the eigenvector matrix, a clustering algorithm is used to group threads. Specifically, a clustering algorithm can be used to group threads. Spectral clustering is a clustering method based on spectral graph theory. It performs dimensionality reduction by analyzing the eigenvectors of the data similarity matrix, and is particularly suitable for discovering non-convex cluster structures.

[0061] Specifically, each thread is now represented by its coordinates in the new feature space. By analyzing the distribution pattern of these coordinate points, they are divided into K distinct groups. For example, the K-means clustering algorithm is used to iteratively optimize the allocation of coordinate points into K clusters, making points within the same cluster as similar as possible and points between different clusters as dissimilar as possible. The grouping results directly generate the final thread grouping scheme, clarifying which threads should be scheduled to run on the same server node.

[0062] Specifically, such as Figure 4As shown, threads T1 and T2 read from and write to the same memory page P0. GPTS records the thread ID of the previous and next PFs for each memory page; if the thread IDs are different, the count in the corresponding DSM matrix is ​​incremented by 1. DSM matrix The definition is shown in formula (1).

[0063]

[0064] in and Representing different thread numbers, It is a DSM matrix The elements in. At the initial moment. GPTS will compile statistics. The number of DSM PFs within the time window is recorded, and the DSM matrix is ​​reset to 0 in the next stage. If the number of DSM PFs between some threads in the DSM matrix increases significantly, it indicates that thread scheduling needs to be used to migrate them to the same server to avoid the cross-node data synchronization overhead of DSM PFs.

[0065] Through DSM matrix This can measure the tightness of the relationship between threads. Merging threads that closely share the same memory pages into the same server can reduce the synchronization of data across nodes. However, the number of threads in a virtual machine is large, and the relationships between threads are complex, making it impossible to directly divide threads into different groups using control lines. As shown in formula (2), It naturally describes the number of interactions between threads. Each non-zero line in Represents thread They will access the same memory page. This represents the number of threads currently in the process.

[0066]

[0067] From a graph theory perspective, each thread can be represented as a topological graph. One of the points, Represents a thread in the topology graph. The DSM matrix represents the number of DSM PFs that occur between threads. Then it can correspond to the current The adjacency matrix.

[0068] For the graph The goal of GPTS is to integrate its threads Divide into several unconnected subgraphs ,satisfy Each subgraph corresponds to a different server. Therefore, by obtaining the subgraph partitioning scheme, a corresponding thread migration strategy can be generated.

[0069] To reduce the number of cross-node reads and writes of the same memory page, the graph partitioning strategy needs to minimize the number of DSM PFs between subgraphs, i.e., the weights of subgraph partitioning. As shown in formula (3). If divided into For each subgraph, the corresponding weights are as shown in formula (4).

[0070]

[0071] in, represent The complement, that is, except The remaining threads in the subgraph. According to the spectral clustering algorithm, It can be done through the DSM matrix The matrix decomposition is obtained as shown in formula (5).

[0072]

[0073] Introduce an indicator vector in formula (5) , This can be further deduced as Laplace matrix Solving for eigenvectors.

[0074]

[0075] Among them, the indicator vector The definition is shown in formula (7). Adjacency matrix The degree matrix. The Laplace matrix. .

[0076]

[0077] for The objective of GPTS is transformed into solving The eigenvector corresponding to the smallest eigenvalue, thus the subgraph partitioning makes... Minimum, that is The number of DSM PFs between threads within a subgraph is minimized. For partitioning multiple subgraphs, the objective function transformation of GPTS is accumulated across all subgraphs. As shown in formula (9), this is equivalent to solving... smallest The feature values ​​and their corresponding feature vectors are used to obtain the mapping relationship of the server to which each thread belongs.

[0078]

[0079] By constructing an inter-thread association matrix, the originally discrete and complex thread interaction events are transformed into computable and analyzable structured data. This quantitative description of associations enables an objective assessment of the coupling degree between threads, avoiding subjective judgments based on experience or assumptions. The introduction of a time window mechanism ensures both the statistical significance of the data and provides a temporal basis for dynamic optimization. The resulting inter-thread association matrix serves as direct input to subsequent graph partitioning algorithms, laying a solid foundation for data-driven intelligent thread scheduling.

[0080] By transforming the complex thread scheduling problem into a computable feature space clustering problem, and leveraging the mathematical property of graph cut minimization in spectral clustering theory, the optimal grouping method among threads can be effectively identified. This ensures that memory-intensive threads are reasonably clustered, thereby mathematically guaranteeing the minimization of cross-node communication overhead. This solution, based on graph theory and linear algebra, provides a theoretical guarantee for resource scheduling in distributed environments.

[0081] The clustering algorithm is the K-means clustering algorithm, and the number of clusters in the clustering algorithm is equal to the number of server nodes.

[0082] The clustering algorithm specifically employs K-means clustering, with the number of clusters explicitly set to the number of physical server nodes K in the distributed virtualization environment. K-means clustering effectively handles low-dimensional data points composed of feature vectors, finding the optimal cluster centers through iterative calculations and grouping threads with similar feature vector coordinates into the same cluster. Fixing the number of clusters to the number of server nodes has clear physical significance; each generated cluster directly corresponds to a schedulable physical server, allowing the mathematical grouping scheme to be seamlessly mapped to actual infrastructure resources.

[0083] Determining the number of clusters to be K, the number of server nodes, ensures the rationality of resource allocation and the feasibility of the solution. For example, in a distributed environment consisting of four servers, the number of clusters is set to 4. This way, the final thread grouping scheme will divide all threads into four non-overlapping groups. Each group can be fully scheduled to run on a specific server, avoiding scheduling conflicts or resource waste caused by a mismatch between the number of groups and physical resources.

[0084] Based on graph partitioning theory, the thread topology graph is divided into multiple subgraphs, each corresponding to a server node. A spectral clustering algorithm is used to aggregate densely associated threads, ensuring a high probability of memory page sharing among threads within the same subgraph, while minimizing thread interactions between different subgraphs. This partitioning mechanism uses affinity settings to schedule threads to their corresponding server nodes, effectively reducing the frequency of cross-node data synchronization.

[0085] By transforming the abstract graph partitioning problem into a concrete K-way partitioning problem and employing the mature K-means algorithm for solution, both computational efficiency and the perfect correspondence between the grouping scheme and the physical infrastructure are guaranteed. This correspondence allows for precise implementation of subsequent thread affinity settings, providing a technical guarantee for truly reducing the overhead of cross-node memory access.

[0086] In one possible embodiment, after step 130, the following steps may also be included: Based on the thread grouping scheme, set the affinity parameters of the threads for each server node; Threads are scheduled to the corresponding server nodes based on the affinity parameter value.

[0087] The generated thread grouping scheme is parsed, which specifies the target server node to which each thread is assigned. Based on this mapping, an affinity parameter is set for each thread; at the operational level, this is typically represented by a thread affinity mask. An affinity mask is a bitmask data structure, where each bit represents an available logical processor. By precisely setting these bits, the execution scope of a thread can be limited to the set of logical processors corresponding to a specific server node.

[0088] By setting these parameters through the standard thread control interface provided by the operator, it is ensured that each thread can only be scheduled among the processor cores on its target node, and will not be assigned to processors on other nodes by the operator's default scheduler.

[0089] After the affinity parameters are set, the actual scheduling and execution phase begins. The kernel scheduler strictly adheres to the preset affinity parameters when allocating CPU time slices. For example, when a thread in a thread group assigned to node one becomes ready, the scheduler will only select one logical processor from the set of logical processors on node one to execute that thread, even if processors on other nodes are idle. This mandatory scheduling constraint ensures that thread groups with high memory affinity always run together on the same physical server node.

[0090] Topology awareness of thread execution is achieved through the standard scheduling mechanism of the operation. This affinity-based scheduling control ensures that thread groups with intensive shared memory access are confined to the same node, allowing their data interaction to be completed through the high-speed bus within the node, completely avoiding cross-node network communication overhead. Furthermore, since this solution directly utilizes the affinity control mechanism natively supported by the operation, no modification to the underlying scheduler code is required, resulting in excellent compatibility and ease of deployment. This fine-grained thread placement strategy effectively reduces data synchronization latency in distributed shared memory environments, improving overall resource utilization efficiency.

[0091] Specifically, based on the thread grouping scheme, affinity parameters for each thread to each server node are set, including: Analyze the thread grouping scheme to determine the target server node to which each thread is assigned; For each thread, the affinity mask is set to allow it to run only on the target server node by manipulating the provided thread control interface.

[0092] Affinity mask is a bitmap data structure used by the operating system scheduler. It restricts the execution location of threads or processes by setting the corresponding bits of the processor core, thereby binding threads to the processor.

[0093] The resolution process involves reading the grouping scheme's data structure and identifying the mapping between each thread's unique identifier and its assigned target server node. This resolution allows for the precise determination of the specific physical server to which each thread should be scheduled, providing an accurate basis for subsequent affinity settings.

[0094] After obtaining the mapping relationship between threads and target nodes, the execution constraints for each thread are set individually. This step is accomplished by calling the standard thread control interface provided by the kernel, which involves the precise configuration of the thread affinity mask. The affinity mask is a bitmap data structure where each bit represents a logical processor. By setting this mask, it is possible to precisely control which processors a thread is allowed to execute on.

[0095] Specifically, a corresponding bitmask can be constructed based on the physical processor information contained in the target server node. For example, in a system with two server nodes, node one may contain logical processors 0 to 15, and node two may contain logical processors 16 to 31. When it is necessary to bind a thread to node one, a bitmask is constructed, where bits 0 to 15 are set to 1 and the remaining bits are set to 0. This bitmask is then used to set the target thread.

[0096] This setup ensures that each thread can only be scheduled and executed within the processor set on its specified target server node. It guarantees that thread groups with high memory access dependencies always run together on the same physical node, allowing memory access between them to be completed via high-speed interconnects within the node without triggering cross-node data synchronization.

[0097] By leveraging the processor affinity mechanism natively supported by the operating system, the underlying kernel scheduling algorithm does not need to be modified, ensuring the versatility and portability of the solution. Simultaneously, by precisely controlling the execution location of threads, cache invalidation and memory access latency issues caused by thread migration between nodes are effectively avoided, providing a fundamental guarantee for improving the overall performance of the distributed virtualization environment.

[0098] In the embodiments of this application, by monitoring the Distributed Shared Memory Page Fault (DSMPF) events of the virtual machine, which are triggered when multiple threads access the same shared memory page across nodes, an inter-thread association matrix is ​​constructed based on the DSMPF events. This matrix quantifies the number of times DSMPF events are triggered between any two threads, transforming complex thread behavior relationships into a structured mathematical model, thus providing a basis for scheduling decisions. With the goal of minimizing the number of DSMPF events between different thread groups, the thread graph structure is partitioned to generate a thread grouping scheme. Here, the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix. By formulating the scheduling problem as a clear combinatorial optimization objective and obtaining an approximate optimal solution through graph partitioning, highly correlated thread groups can be dynamically and adaptively bundled for scheduling. This reduces data synchronization communication latency and network bandwidth consumption in the distributed shared memory environment, improving the overall computational efficiency and overall operating performance of the aggregated virtual machine.

[0099] The thread scheduling method provided in this application can be executed by a thread scheduling device. This application uses the example of a thread scheduling device executing the thread scheduling method to illustrate the thread scheduling device provided in this application.

[0100] Figure 5 This is a block diagram of a thread scheduling device provided in an embodiment of this application. The device 500 includes: Monitoring module 510 is used to monitor the Distributed Shared Memory Page Fault (DSM PF) event of the virtual machine, which is triggered when multiple threads access the same shared memory page across nodes; The construction module 520 is used to construct an inter-thread association matrix based on the DSM PF event, wherein the inter-thread association matrix is ​​used to quantify the number of times the DSM PF event is triggered between any two threads; The generation module 530 is used to divide the thread graph structure and generate a thread grouping scheme with the goal of minimizing the number of DSM PF events between different grouped threads. The vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix.

[0101] In one possible embodiment, the monitoring module 510 is specifically used for: Deploy the extended Berkeley packet filter eBPF program in the virtual machine kernel. The eBPF program is used to intercept page fault events triggered by distributed shared memory. For each intercepted page fault event, extract the memory page address associated with the page fault event and the thread identifier of the currently executing thread; Based on the memory page address and the thread identifier, determine whether two consecutive DSMPF events targeting the same memory page are triggered by threads on different server nodes; If so, it is recorded as the DSM PF event.

[0102] In one possible embodiment, the construction module 520 is specifically used for: An initialization matrix is ​​generated based on the identifiers of all active threads in the virtual machine, and all elements of the initialization matrix are zero. Within a preset time window, monitor two consecutive DSM PF events for each memory page; If the two consecutive DSM PF events are triggered by the first thread and the second thread, then the count is incremented in the matrix elements corresponding to the first thread and the second thread in the initialization matrix; the first thread and the second thread correspond to different server nodes; The inter-thread correlation matrix is ​​obtained by accumulating the counts of all memory pages.

[0103] In one possible embodiment, the generation module 530 is specifically used for: The degree matrix is ​​calculated based on the inter-thread association matrix. The degree matrix is ​​a diagonal matrix, and the diagonal elements of the degree matrix are the sum of the elements in each row of the inter-thread association matrix. Construct a Laplace matrix based on the inter-thread correlation matrix and the degree matrix; Calculate the eigenvalues ​​and eigenvectors of the Laplacian matrix; Select the eigenvectors corresponding to the first K smallest eigenvalues ​​to form an eigenvector matrix, where K is the number of server nodes and K is a positive integer; Based on the feature vector matrix, a clustering algorithm is used to group the threads to generate a thread grouping scheme.

[0104] The clustering algorithm is K-means clustering, and the number of clusters in the clustering algorithm is equal to the number of server nodes.

[0105] In one possible embodiment, the device 500 further includes: The configuration module is used to set the affinity parameters of the threads for each server node according to the thread grouping scheme; The scheduling module is used to schedule the thread to the corresponding server node according to the affinity parameter value.

[0106] In one possible embodiment, the setting module is specifically used for: Analyze the thread grouping scheme to determine the target server node to which each thread is assigned; For each thread, the affinity mask of the thread is set to allow it to run only on the target server node through the thread control interface provided by the operating system.

[0107] In the embodiments of this application, by monitoring the Distributed Shared Memory Page Fault (DSMPF) events of the virtual machine, which are triggered when multiple threads access the same shared memory page across nodes, an inter-thread association matrix is ​​constructed based on the DSMPF events. This matrix quantifies the number of times DSMPF events are triggered between any two threads, transforming complex thread behavior relationships into a structured mathematical model, thus providing a basis for scheduling decisions. With the goal of minimizing the number of DSMPF events between different thread groups, the thread graph structure is partitioned to generate a thread grouping scheme. Here, the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix. By formulating the scheduling problem as a clear combinatorial optimization objective and obtaining an approximate optimal solution through graph partitioning, highly correlated thread groups can be dynamically and adaptively bundled for scheduling. This reduces data synchronization communication latency and network bandwidth consumption in the distributed shared memory environment, improving the overall computational efficiency and overall operating performance of the aggregated virtual machine.

[0108] The thread scheduling device provided in this application embodiment can implement the various processes implemented in the above method embodiments, and will not be described again here to avoid repetition.

[0109] Optionally, Figure 6 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application is shown.

[0110] An electronic device may include a processor 401 and a memory 402 storing computer program instructions.

[0111] Specifically, the processor 401 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0112] Memory 402 may include a large-capacity memory for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 402 is a non-volatile solid-state memory. In a particular embodiment, memory 402 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0113] The processor 401 implements any of the thread scheduling methods in the embodiment shown in the figure by reading and executing computer program instructions stored in the memory 402.

[0114] In one example, the electronic device may also include a communication interface 404 and a bus 410. Wherein, as... Figure 6 As shown, the processor 401, memory 402, and communication interface 404 are connected through bus 410 and complete communication with each other.

[0115] Communication interface 404 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0116] Bus 410 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 410 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0117] The electronic device can execute the thread scheduling method in the embodiments of this application, thereby achieving the combination Figure 2 Describes the thread scheduling method.

[0118] Furthermore, in conjunction with the thread scheduling method in the above embodiments, this application embodiment can provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; these computer program instructions are implemented when executed by a processor. Figure 1 The thread scheduling method.

[0119] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0120] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0121] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0122] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A thread scheduling method, characterized in that, Applied to a distributed virtualization server, the distributed virtualization server includes multiple server nodes, each server node runs a virtual machine, and the virtual machine contains multiple threads; the method includes: Monitor the Distributed Shared Memory Page Fault (DSM PF) events of the virtual machine, which are triggered when multiple threads access the same shared memory page across nodes; Based on the DSM PF event, an inter-thread association matrix is ​​constructed, which is used to quantify the number of times the DSM PF event is triggered between any two threads; With the goal of minimizing the number of DSM PF events between different grouped threads, the thread graph structure is divided to generate a thread grouping scheme, wherein the vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix.

2. The method according to claim 1, characterized in that, The monitoring of the distributed shared memory page fault (DSM) PF events of the virtual machine includes: Deploy the extended Berkeley packet filter eBPF program in the virtual machine kernel. The eBPF program is used to intercept page fault events triggered by distributed shared memory. For each intercepted page fault event, extract the memory page address associated with the page fault event and the thread identifier of the currently executing thread; Based on the memory page address and the thread identifier, determine whether two consecutive DSM PF events targeting the same memory page are triggered by threads on different server nodes; If so, it is recorded as the DSM PF event.

3. The method according to claim 1, characterized in that, The step of constructing the inter-thread association matrix based on the DSM PF event includes: An initialization matrix is ​​generated based on the identifiers of all active threads in the virtual machine, and all elements of the initialization matrix are zero. Within a preset time window, monitor two consecutive DSM PF events for each memory page; If the two consecutive DSM PF events are triggered by the first thread and the second thread, then the count is incremented in the matrix elements corresponding to the first thread and the second thread in the initialization matrix; the first thread and the second thread correspond to different server nodes; The inter-thread correlation matrix is ​​obtained by accumulating the counts of all memory pages.

4. The method according to claim 1, characterized in that, The process of generating a thread grouping scheme based on the thread graph structure includes: The degree matrix is ​​calculated based on the inter-thread association matrix. The degree matrix is ​​a diagonal matrix, and the diagonal elements of the degree matrix are the sum of the elements in each row of the inter-thread association matrix. Construct a Laplace matrix based on the inter-thread correlation matrix and the degree matrix; Calculate the eigenvalues ​​and eigenvectors of the Laplacian matrix; Select the eigenvectors corresponding to the first K smallest eigenvalues ​​to form an eigenvector matrix, where K is the number of server nodes and K is a positive integer; Based on the feature vector matrix, a clustering algorithm is used to group the threads to generate a thread grouping scheme.

5. The method according to claim 4, wherein the clustering algorithm is a K-means clustering algorithm, and the number of clusters in the clustering algorithm is the number of server nodes.

6. The method according to claim 1, characterized in that, After generating the thread grouping scheme based on the graph structure, the method further includes: Based on the thread grouping scheme, set the affinity parameters of the thread for each server node; The thread is scheduled to the corresponding server node based on the affinity parameter value.

7. The method according to claim 6, characterized in that, The step of setting the affinity parameters of the threads for each server node according to the thread grouping scheme includes: Analyze the thread grouping scheme to determine the target server node to which each thread is assigned; For each thread, the affinity mask of the thread is set to allow it to run only on the target server node through the thread control interface provided by the operating system.

8. A thread scheduling device, characterized in that, An apparatus for use in a distributed virtualization server, wherein the distributed virtualization server comprises multiple server nodes, each server node running a virtual machine, the virtual machine containing multiple threads, the apparatus comprising: The monitoring module is used to monitor the Distributed Shared Memory Page Fault (DSM PF) events of the virtual machine, which are triggered when multiple threads access the same shared memory page across nodes; A construction module is used to construct an inter-thread association matrix based on the DSM PF event, wherein the inter-thread association matrix is ​​used to quantify the number of times the DSM PF event is triggered between any two threads; The generation module is used to divide the thread graph structure and generate a thread grouping scheme with the goal of minimizing the number of DSM PF events between different grouped threads. The vertices of the thread graph structure represent threads, and the adjacency matrix of the thread graph structure is the inter-thread association matrix.

9. An electronic device, characterized in that, The electronic device includes: a processor and a memory storing computer program instructions; the processor implements the thread scheduling method as described in any one of claims 1-7 when executing the computer program instructions.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the thread scheduling method as described in any one of claims 1-7.

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