Information processing method of electronic equipment, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an information processing method of electronic equipment, the electronic equipment and a storage medium, the electronic equipment comprises a mainboard, and the mainboard is provided with a device interface and a specified memory; the method comprises the steps that power supply amplitude information, interface state information and timestamp information are obtained, and a signal amplitude indicated by the power supply amplitude information and an interface state indicated by the interface state information are matched with time indicated by the timestamp information; under the condition that the signal amplitude indicated by the power supply amplitude information is larger than or equal to the preset signal amplitude, interface reference information is stored in a specified storage, the interface reference information comprises interface state information and timestamp information, and the interface reference information is used for conducting fault analysis on a power supply device on the mainboard. According to the invention, the problem of poor fault positioning accuracy of the power supply device of the electronic equipment in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an information processing method for an electronic device, an electronic device, and a storage medium. Background Technology

[0002] In related technologies, when a power supply failure occurs on the motherboard of electronic devices such as laptops and tablets (i.e., the power supply device fails), repair personnel usually remove the faulty device (i.e., the faulty device) from the motherboard, perform a preliminary analysis on the faulty device, and then send the faulty device to the manufacturer for multi-level analysis in order to locate the fault.

[0003] However, most power supply device failures result in internal or external cracks or burns, and the final analysis conclusion is always classified as Electrical Over Stress (EOS). At this point, the analysis stops, and the true cause of the failure cannot be determined.

[0004] This shows that the relevant technologies suffer from poor accuracy in locating faults in the power supply components of electronic devices. Summary of the Invention

[0005] This application provides an information processing method for an electronic device, an electronic device, and a storage medium to at least solve the problem of poor accuracy in locating faults in the power supply devices of electronic devices in related technologies.

[0006] According to one aspect of the embodiments of this application, an information processing method for an electronic device is provided. The electronic device includes a motherboard, on which device interfaces and a designated memory are provided. The method includes: acquiring power amplitude information, interface status information, and timestamp information, wherein the power amplitude information is used to indicate the signal amplitude of a power signal of the device interface, the interface status information is used to indicate the interface status of the device interface, and the signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information match the time indicated by the timestamp information; when the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, saving interface reference information to the designated memory, wherein the interface reference information includes the interface status information and the timestamp information, and the interface reference information is used for fault analysis of power devices on the motherboard.

[0007] According to another aspect of the embodiments of this application, an electronic device is also provided, including: a motherboard, wherein the motherboard is provided with a controller, a device interface, and a designated memory; wherein the controller is used to acquire power amplitude information, interface status information, and timestamp information, wherein the power amplitude information is used to indicate the signal amplitude of the power signal of the device interface, the interface status information is used to indicate the interface status of the device interface, and the signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information match the time indicated by the timestamp information; when the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, interface reference information is saved to the designated memory, wherein the interface reference information includes the interface status information and the timestamp information, and the interface reference information is used for fault analysis of the power device on the motherboard; the designated memory is used to store the interface reference information.

[0008] In an exemplary embodiment, the motherboard is further provided with an analog-to-digital converter chip, and the device interface is connected to an input pin of the analog-to-digital converter chip; the analog-to-digital converter chip is used to convert the power signal of the device interface into a digital signal to obtain the power amplitude information, and transmit the power amplitude information to the control device.

[0009] In an exemplary embodiment, the controller is configured to acquire state information of a set of signal lines of the device interface, and determine the interface state of the device interface based on the state information of the set of signal lines to obtain the interface state information, wherein the set of signal lines includes at least one of the following: a detection line, a data line, and a status line; and acquire the timestamp information matching the interface state information.

[0010] In an exemplary embodiment, the controller is further configured to determine the interface state of the device interface from a set of interface states based on the state information of the set of signal lines, and obtain the interface state information, wherein the set of interface states includes at least one of the following: not connected state, connected state.

[0011] In one exemplary embodiment, the control device includes a first controller and a second controller. The first controller is a microcontroller, and the second controller includes at least one of the following: an embedded controller and a central processing unit. The first controller is configured to acquire the power amplitude information; receive the interface status information and the timestamp information transmitted by the second controller; and save the interface reference information to the designated memory. The second controller is configured to acquire the interface status information and the timestamp information matching the interface status information, and transmit the interface status information and the timestamp information to the first controller. The interface reference information is saved to the designated memory by the first controller.

[0012] In one exemplary embodiment, the first controller is further configured to send the power amplitude information to the second controller for storage.

[0013] In an exemplary embodiment, the controller is further configured to save the combination of the power amplitude information, the interface status information, and the timestamp information as the interface reference information into the designated memory.

[0014] In an exemplary embodiment, the control device is further configured to: after saving the interface reference information to the designated memory, in the event of a power device failure, read the interface reference information from the designated memory; if the time indicated by the timestamp information does not match the time of the power device failure, mark the power device failure as a non-electrical overstress (EOS) failure; if the time indicated by the timestamp information matches the time of the power device failure, and the interface status indicated by the interface status information is in an unconnected state, mark the power device failure as a non-EOS failure; if the time indicated by the timestamp information matches the time of the power device failure, and the interface status indicated by the interface status information is in a connected state, mark the power device failure as an EOS failure.

[0015] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed by a processor.

[0016] According to another aspect of the embodiments of this application, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, causing the computer device to perform the steps in any of the method embodiments described above.

[0017] In the embodiments provided in this application, the EOS signal typically enters the electronic device through the device interface. The power supply device can be directly or indirectly connected to the device interface, and the signal amplitude of the power supply signal at the device interface also represents the power supply amplitude through the power supply device. Therefore, an EOS fault is characterized by an abnormal signal amplitude in the power supply signal of the device interface (i.e., an abnormal power supply amplitude of the power supply device), and by a connection status in the interface state (i.e., an external device needs to be connected to the device interface, and the signal amplitude needs to be abnormal; only under these circumstances can an EOS signal enter the electronic device). For the electronic device, power amplitude information, interface status information, and timestamp information can be acquired during device operation. Since the signal amplitude of the power supply signal can characterize the power supply voltage of the external device connected to the device interface, and the interface status can characterize the connection relationship between the device interface and the external device, if the signal amplitude is greater than or equal to a preset signal amplitude, the interface reference information can be saved to a designated memory. Since the interface reference information includes interface status information and timestamp information, it can characterize the interface status and time when the signal amplitude of the power signal of the device interface exceeds the signal amplitude threshold. Therefore, saving it as on-site information when the power device on the motherboard fails can lock the analysis direction based on the matching of interface status and time (e.g., analyzing whether the power device failure is an EOS failure). After locking the analysis direction, corresponding measures can be taken to improve the accuracy of fault location of power devices in electronic devices in related technologies, thereby achieving the technical effect of improving the accuracy of fault location. Attached Figure Description

[0018] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0019] Figure 1 This is a hardware structure block diagram of a laptop computer according to an embodiment of the present application of an information processing method for an electronic device;

[0020] Figure 2 This is a schematic flowchart of an optional information processing method for an electronic device according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of an optional information processing method for an electronic device according to an embodiment of this application;

[0022] Figure 4 This is a structural block diagram of an optional electronic device according to an embodiment of this application;

[0023] Figure 5 This is a structural block diagram of another optional electronic device according to an embodiment of this application;

[0024] Figure 6 This is a structural block diagram of another optional electronic device according to an embodiment of this application. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] According to one aspect of the embodiments of this application, an information processing method for an electronic device is provided. Optionally, the method embodiments provided in this application can be executed in a laptop computer or similar computing device. Taking running on a laptop computer as an example, Figure 1 This is a hardware structure block diagram of a laptop computer according to an embodiment of an electronic device information processing method of this application. Figure 1 As shown, a laptop computer may include one or more ( Figure 1Only one is shown in the image. A processor 102 (which may include, but is not limited to, a central processing unit (CPU) or a field-programmable gate array (FPGA)) and a memory 104 for storing data are also shown. The laptop computer may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned laptop computer. For example, a laptop computer may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0028] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the information processing method of the electronic device in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a laptop computer via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0029] In one example, transmission device 106 includes a network interface controller (NIC) that can connect to other network devices via a base station to communicate with the Internet. In another example, transmission device 106 may be a radio frequency (RF) module for wireless communication with the Internet.

[0030] The information processing method for electronic devices provided in this embodiment can be applied to electronic devices, such as the aforementioned laptops and tablets. When a power supply component on the motherboard of an electronic device malfunctions, repair personnel typically remove the faulty component from the motherboard, perform a preliminary analysis, and then send the faulty component to the manufacturer for multi-level analysis to locate the fault. However, most power supply component failures result in internal or external cracks or burns, and the final analysis conclusion is classified as an EOS (Effective Novel Coronavirus). After this, the analysis stops, and the true cause of the malfunction cannot be determined.

[0031] Taking laptops as an example, when the power supply components on the motherboard fail, after-sales analysis can be performed. The typical after-sales analysis of power supply components on the motherboard involves removing the faulty component from the motherboard after the malfunction occurs. A motherboard repair technician first performs a preliminary analysis to determine the possible causes of the failure. Then, the component is sent to the manufacturer for multi-level analysis, including visual inspection, X-ray examination, current-voltage characteristic curve (IV curve) analysis, scanning acoustic microscopy (SAM), and decapsulation.

[0032] However, the initial analysis by motherboard repair technicians usually doesn't provide much valuable information, while the manufacturer's analysis, although more in-depth, often only presents the symptom of the component's failure. Neither of these analytical methods can recreate the fault scene or match it to the cause of the failure. Especially when looking at power supply-related fault statistics, issues like component cracking / burning / melting are the most difficult to analyze. This is because such burning could be caused by an EOS (Effective Loss of Components), a flaw in the circuit design, or micro-damage to the component during manufacturing, leading to high current heating under normal operating conditions. Experience shows that if the analysis indicates a power supply component failure due to cracking / burning / melting, the final conclusion is always categorized as an EOS cause, and further analysis is stopped. However, this doesn't actually pinpoint the true cause of the failure. In this situation, no matter how much EOS protection is strengthened, the problem may not be solved.

[0033] To at least partially solve the aforementioned technical problems, in this embodiment, during the operation of the electronic device, power amplitude information, interface status information, and timestamp information are acquired. When the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, interface reference information is saved. The interface reference information includes at least interface status information and timestamp information. Since one manifestation of an EOS fault is an abnormal signal amplitude of the power signal at the device interface, when the signal amplitude of the power signal at the device interface is greater than or equal to the preset signal amplitude, the interface status information and timestamp information are saved. This information can serve as on-site information when the power device malfunctions. Combining this on-site information, it is possible to clarify whether it is an EOS fault, thereby locking in the direction of analysis, such as locking in whether it is an EOS fault or not. Based on the locked direction, corresponding measures can be taken to improve the accuracy of fault location.

[0034] Electronic devices may include motherboards, also known as main circuit boards, system boards, or motherboards. The motherboard is a core component within a computer or electronic device. It acts as a platform, connecting and supporting all hardware components such as the processor (CPU), memory, storage devices, input / output interfaces, and other expansion cards. The motherboard is the nervous system of the electronic device; it not only provides the physical connections between these components but also manages their data communication and power distribution.

[0035] The motherboard can have device interfaces and designated memory. Device interfaces are used to connect external devices (i.e., devices connected to electronic devices, such as mobile phones, USB flash drives, etc.). Device interfaces can be directly or indirectly connected to the power supply via power cables. Power signals can be transmitted through the power cables; these signals can be power signals transmitted to power devices on the motherboard or power signals output by the motherboard to external devices. Designated memory can be non-volatile memory, including but not limited to at least one of the following: Electrically Erasable Programmable Read-Only Memory (EEPROM); Read-Only Memory (ROM); Flash Memory; Ferroelectric Random Access Memory (FRAM); Magnetoresistive Random Access Memory (MRAM).

[0036] In addition to the aforementioned components, the motherboard may also include control devices. These control devices may include one or more components, including but not limited to at least one of the following: a Platform Controller Hub (PCH); a Super Input / Output chip; a power management controller; a Voltage Regulator Module (VRM); an Embedded Controller (EC); a Northbridge Chip (Memory Controller Hub, MCH); a Southbridge Chip (I / O Controller Hub, ICH); a network controller; a sound card controller; a graphics processing unit controller; a storage controller; and a peripheral controller. The information processing method of the electronic device in this embodiment can be executed by the control devices located on the motherboard.

[0037] Here, the motherboard can be powered by a power supply, and a power management circuit can be installed on the motherboard. This power management circuit distributes power to various components, such as the CPU, memory, and chipset. The power management circuit can include various power modules, such as voltage regulator modules (VRMs). These modules further convert and adjust the input DC voltage to the specific voltage and current levels required by each component on the motherboard, ensuring that every electronic component on the motherboard can operate stably at its rated voltage and current, which is fundamental to the normal operation of the hardware system. The motherboard can have one or more device interfaces, each of which can transmit power signals via a single power line. The information processing method for the electronic device in this embodiment is described for one device interface. It is understood that, for cases where the motherboard has multiple device interfaces, the information processing method for the electronic device in this embodiment is applicable to each device interface.

[0038] Figure 2 This is a schematic flowchart of an optional information processing method for an electronic device according to an embodiment of this application, as shown below. Figure 2 As shown, the process includes the following steps:

[0039] Step S202: Obtain power amplitude information, interface status information and timestamp information. The power amplitude information is used to indicate the signal amplitude of the power signal of the device interface, the interface status information is used to indicate the interface status of the device interface, and the signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information match the time indicated by the timestamp information.

[0040] Step S204: If the signal amplitude indicated by the power amplitude information is greater than or equal to the preset signal amplitude, save the interface reference information to the specified memory. The interface reference information includes interface status information and timestamp information. The interface reference information is used for fault analysis of the power devices on the motherboard.

[0041] The controller can periodically or by event triggering to acquire time-matched power amplitude information, interface status information, and timestamp information. Power amplitude information can be obtained by monitoring the power signal transmitted to the device interface, and it can be used to indicate the signal amplitude of the power signal at the device interface. Here, the EOS signal can only enter the electronic device's system through the physical interface (i.e., the device interface). The power device can be directly or indirectly connected to the device interface, and the signal amplitude of the power signal at the device interface also represents the power amplitude passing through the power device. Correspondingly, an EOS fault is represented by an abnormal signal amplitude in the power signal at the device interface (i.e., an abnormal power amplitude of the power device); and by a connected state in the interface status (i.e., an external device is connected to the device interface, thus allowing an EOS signal to enter the electronic device's system through the device interface). Therefore, the power signal at the device interface can be processed. Interface status information can be obtained by monitoring the device interface, and it can be used to characterize the interface status, which can represent the connection status between the device interface and the external device.

[0042] When the control device consists of a single controller, that single controller can perform all information acquisition operations. When the control device consists of multiple controllers, power amplitude information, interface status information, and timestamp information can be acquired by different controllers. The acquired power amplitude information, interface status information, and timestamp information can be aggregated to one of the controllers (either the controller acquiring power amplitude information or the controller acquiring interface status information), or it can be aggregated to the other controllers.

[0043] It should be noted that power amplitude information and interface status information can be acquired simultaneously. The signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information must match the time indicated by the timestamp information. The time indicated by the timestamp information can be the physical world time for acquiring the power amplitude information or interface status information, or it can be the physical world time of a preset time interval (or no longer than the preset time interval) between acquiring the power amplitude information or interface status information. For example, when power amplitude information is acquired, the first interface status information acquired subsequently can be used as the matching interface status information. Similarly, when interface status information is acquired, the first power amplitude information acquired subsequently can be used as the matching power amplitude information. The timestamp information can be a physical world timestamp acquired after acquiring the power amplitude information or interface status information, or it can be acquired at other times, as long as it matches the power amplitude information and interface status information.

[0044] The controller can directly save the acquired power amplitude information, interface status information, and timestamp information as interface reference information to a designated memory. Considering the possibility of extremely low signal amplitude (i.e., no power supply) or signal amplitude within a reasonable range (in which case, the power supply device failure is usually not an EOS failure), to save storage resources, the interface reference information can be saved to the designated memory only if the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude. The interface reference information may include interface status information and timestamp information, or it may include power amplitude information, interface status information, and timestamp information.

[0045] In this embodiment, the preset signal amplitude can be the upper limit of a reasonable amplitude range, which can be the maximum reasonable amplitude of the power signal of the device interface specified by the designer. The preset signal amplitude can be set based on experience, or it can be a reasonable value obtained based on the analysis of historical data, or it can be designed based on other factors. This embodiment does not limit this.

[0046] Power supply devices can be directly or indirectly connected to a device interface. Interface reference information indicates whether an external device is connected to the device interface when the power supply amplitude of the power supply device is abnormal. Therefore, interface reference information can be used for fault analysis of power supply devices on the motherboard. Fault analysis is usually performed after a power supply device on the motherboard fails. Fault analysis of power supply devices can be performed by electronic devices (e.g., the aforementioned control devices) or by other devices. Other devices can read the interface reference information stored in a designated memory and then perform fault analysis on the power supply devices connected to the device interface based on the read interface reference information.

[0047] For example, when analyzing the possible causes of after-sales damage to power components on a laptop motherboard, the faulty component to be analyzed can be removed, and some field information (i.e., interface reference information) related to the fault can be found in the ROM (an example of a specified memory). By combining this field information, the direction of analysis can be locked, and corresponding measures can be taken to improve the analysis based on the analysis and judgment after locking the direction.

[0048] It should be noted that, considering the time-varying characteristics of the power signal amplitude and interface status of the device interface, the interface status information can be stored together with timestamp information in a designated memory. Multiple interface reference information entries can be stored in the designated memory; each entry can be stored once the power signal amplitude of the device interface reaches a preset amplitude.

[0049] According to the embodiments provided in this application, an electronic device includes a motherboard with device interfaces and a designated memory. It acquires power amplitude information, interface status information, and timestamp information. The power amplitude information indicates the signal amplitude of the power signal of the device interface, and the interface status information indicates the interface status of the device interface. The signal amplitude indicated by the power amplitude information and the interface status information match the time indicated by the timestamp information. When the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, interface reference information is saved to the designated memory. The interface reference information includes interface status information and timestamp information. The interface reference information is used for fault analysis of power devices on the motherboard, solving the problem of poor accuracy in fault location of power devices in related technologies and improving the accuracy of fault location.

[0050] In an exemplary embodiment, the motherboard may also include an analog-to-digital converter (ADC) chip and a controller. One input pin of the ADC chip may be connected to the device interface, and the controller is the same as or similar to that in the previous embodiment, and will not be described in detail here. Correspondingly, obtaining power amplitude information, interface status information, and timestamp information includes: converting the power signal (analog signal) of the device interface into a digital signal through the ADC chip to obtain the power amplitude information, and transmitting the power amplitude information to the controller.

[0051] An analog-to-digital converter (ADC) chip is an electronic device that converts continuously changing analog signals into digital signals. It acts as a bridge, enabling analog signals from the real world (such as sound, temperature, pressure, and voltage) to be processed and analyzed by digital systems (such as microprocessors and computers). The ADC chip's tasks are sampling and quantization. Sampling involves capturing the instantaneous values ​​of analog signals, while quantization converts these instantaneous values ​​into binary digital form, thus transforming continuous analog signals into discrete digital data.

[0052] In this embodiment, the device interface is connected to an input pin of the analog-to-digital converter (ADC). The ADC can sample the amplitude of the power signal from the device interface, quantize the sampled analog signal, and convert it into a digital signal (i.e., binary digital form), thus obtaining the power amplitude information. This power amplitude information can then be transmitted to the controller by the ADC.

[0053] In this embodiment, the power signal of the device interface is converted into a digital signal by an analog-to-digital converter chip and transmitted to the controller for processing. This can improve the accuracy and efficiency of interface power monitoring and facilitate subsequent data processing.

[0054] In an exemplary embodiment, a controller may also be provided on the motherboard. Acquiring power amplitude information, interface status information, and timestamp information includes: acquiring the status information of a set of signal lines of the device interface through the controller; and determining the interface status of the device interface based on the status information of the set of signal lines to obtain interface status information.

[0055] In this embodiment, the device interface may have a set of signal lines, which may include at least one of the following: a detection line, a data line, and status lines. The controller can acquire the status information of this set of signal lines. By parsing the status information of this set of signal lines, the interface status of the device interface can be determined, thus obtaining interface status information. The interface status of the device interface may be matched from a set of interface statuses, which may include at least one of the following: not connected, inserted, connected, unplugged, unplugged, or may include more, fewer, or different interface statuses than those mentioned above; this embodiment does not limit this.

[0056] Detection lines can be used to monitor or detect specific events or states on a circuit board or interface. For example, detection lines can detect whether an external device is being inserted or has been removed from the device interface, and can also report these events to the controller so that the device or system can respond promptly and perform corresponding operations. Data lines can be used to transmit actual data signals between devices. For example, data lines can handle bidirectional data transmission, such as file transfer, video signals, and audio signals. Status lines convey the current operating status or configuration information of a device or component, and can provide feedback such as whether the device or component is ready, busy, or in error. Based on at least some of these signal lines, the interface status of the device interface can be determined. It should be noted that there are multiple ways to set up a set of signal lines. For example, the three types of signal lines mentioned above can be set up separately, or at least two signal lines can be combined into one signal line. For example, detection lines and status lines can be the same signal line. Therefore, as long as the status information of the acquired signal lines can be parsed to determine the corresponding interface status, it is acceptable.

[0057] In this embodiment, the controller can acquire timestamp information, which can be obtained based on interface status information or power supply amplitude information. For example, after acquiring interface status information or the status information of a set of signal lines, the current time can be acquired to obtain the timestamp information. Alternatively, after acquiring power supply amplitude information, the current time can be acquired to obtain the timestamp information.

[0058] Through this embodiment, the controller can acquire the status information of a set of signal lines and determine the interface status of the device interface accordingly. It can accurately track the status changes during the interface operation process, identify the interface environment when a fault occurs, and improve the accuracy of fault location. Furthermore, by acquiring matching timestamp information based on the interface status information, the timeliness and accuracy of information acquisition can be improved.

[0059] In an exemplary embodiment, determining the interface state of a device interface based on the state information of a set of signal lines to obtain interface state information includes: determining the interface state of the device interface from a set of interface states based on the state information of a set of signal lines to obtain interface state information, wherein the set of interface states includes at least one of the following: unconnected state, connected state.

[0060] For a controller, the interface state can be determined from a set of interface states based on the state information of a set of signal lines, thus obtaining interface state information. A set of interface states includes at least one of the following: not connected, connected. In addition, a set of interface states may also include at least one of the following: inserted, unplugged, unplugged, or may include more, fewer, or different interface states. The type of interface state can be configured according to the needs of fault analysis, and this embodiment does not limit this.

[0061] For example, the state of a device interface can be categorized into four types: insertion, fully connected, removal, and complete removal. The CPU or EC can determine the current state of the interface based on the signals on the device interface.

[0062] In this embodiment, the controller determines the interface state of the device interface from a set of interface states, which can meet the needs of different usage scenarios and help identify abnormal states during specific operations, thereby enabling more accurate classification and analysis of faults.

[0063] In one exemplary embodiment, a controller is also provided on the motherboard. To facilitate information acquisition, interface reference information can be acquired through multiple controllers. The controller may include multiple controllers, for example, a first controller and a second controller. The first controller may be a microcontroller unit (MCU), and the second controller may include at least one of the following: an embedded controller (EC), or a CPU. The second controller and the second controller may also be other controller types, which are not limited in this embodiment.

[0064] Correspondingly, obtaining power amplitude information, interface status information, and timestamp information includes: obtaining power amplitude information through the first controller; obtaining interface status information and timestamp information matching the interface status information through the second controller, and transmitting the interface status information and timestamp information to the first controller.

[0065] The power amplitude information can be obtained by a first controller, which can acquire the power amplitude information in the same or different ways as in the aforementioned embodiments. For example, a device interface is connected to an input port of an ADC chip via a voltage divider circuit, and the first controller can be connected to the output port of the ADC chip. The ADC chip transmits the power amplitude information to the first controller. Here, the device interface and voltage divider circuit can be located on the motherboard or independently of the motherboard, as long as the connection relationship with the ADC chip and the first controller (e.g., MCU) is maintained.

[0066] For example, an ADC chip can be used to convert analog power signals into digital signals in real time, an MCU can be used to receive and process the power amplitude data (i.e., power amplitude information) converted by the ADC chip, and a ROM chip can be used to store the useful data.

[0067] like Figure 3 As shown, the motherboard can have N device interfaces (i.e., interface 1 to interface N) and N power lines (i.e., power line 1 to power line N), where N is a positive integer greater than or equal to 1. The N power lines can be connected to the input pins of the ADC chip via a voltage divider circuit. The ADC chip can be connected to the MCU, and the MCU can be connected to the ROM. The ADC chip converts the analog power signal into a digital power signal and transmits it to the MCU.

[0068] Taking interface 1 as an example, the power line 1 on interface 1 can be connected to an input pin of the ADC chip through a voltage divider network. The ADC chip converts the analog power signal at the input pin into a digital power signal and transmits it to the MCU.

[0069] For interface status information, the process involves acquiring power amplitude information, interface status information, and timestamp information, including: acquiring interface status information through a second controller. Here, the second controller (e.g., EC, CPU, etc.) can acquire the status information of a set of signal lines and determine the interface status information based on this acquired set of signal line status information. For timestamp information, the process involves acquiring power amplitude information, interface status information, and timestamp information, including: acquiring timestamp information that matches the interface status information through the second controller.

[0070] The first and second controllers can be connected via a bidirectional communication interface. To aggregate power amplitude and interface status information, the second controller can send interface status and timestamp information to the first controller, or the first controller can send power amplitude information to the second controller. When the second controller sends interface status and timestamp information to the first controller, the first controller matches the power amplitude, interface status, and timestamp information. When the first controller sends power amplitude information to the second controller, the second controller matches the power amplitude, interface status, and timestamp information.

[0071] Optionally, the interface reference information is saved to the designated memory by the first controller. Correspondingly, saving the interface reference information to the designated memory includes: saving the interface reference information to the designated memory via the first controller. Here, the first controller may be connected to the designated memory, and the interface reference information may be saved to the designated memory by the first controller.

[0072] Optionally, when the first controller sends the power amplitude information to the second controller, saving the interface reference information to a designated memory includes: saving the interface reference information to the designated memory via the second controller. Here, the second controller can be connected to the designated memory, and the interface reference information can be saved to the designated memory by the second controller. When other controllers aggregate the two types of information, the interface reference information can be saved to the designated memory by the other controllers.

[0073] For example, an MCU can be connected to an EC chip and a CPU via a bidirectional communication interface, facilitating the transmission of relevant data. Figure 3 The MCU and CPU or EC can be connected via a bidirectional interface. In addition, the control device (e.g., MCU, CPU, EC, etc.) can be powered by a power supply.

[0074] The CPU or EC can determine the current state of the device interface through signals on the device interface and send the interface status information and timestamp information to the MCU. The MCU can receive the current timestamp information (indicating the current physical world time) and the real-time interface status information of the device interface (e.g., interface 1) from the CPU or EC in real time, and based on the timing of information reception, store the time-matched power amplitude information, timestamp information and interface status information together (i.e., combine the digital signal transmitted by the ADC with the information obtained from the CPU / EC) in the ROM.

[0075] For interface 1, considering that interface power supplies with signal amplitudes below the design amplitude will not be considered EOS, the MCU will only process signals exceeding the maximum reasonable design amplitude of power line 1 as determined by the designer (an example of a preset signal amplitude). This avoids excessive data storage and transmission. In this way, power amplitude information exceeding the reasonable design amplitude at each moment can be recorded.

[0076] Through this embodiment, the collaborative work of the first controller and the second controller integrates power amplitude information and interface status information, which can construct detailed and comprehensive fault site data. At the same time, the bidirectional data transmission between the first controller and the second controller can improve the speed and reliability of data processing.

[0077] In one exemplary embodiment, after obtaining the power amplitude information through the first controller, the method further includes: sending the power amplitude information to the second controller for storage through the first controller.

[0078] To ensure data security and prevent the inability to read interface reference information due to a specified memory malfunction, the first controller can send power amplitude information to the second controller. The second controller can then save the power amplitude information or interface reference information, for example, by saving it to a memory connected to the second controller. For instance, the MCU can simultaneously send the power amplitude signal to the EC or CPU for saving.

[0079] In this embodiment, the first controller not only saves data to local storage, but also forwards the data to the second controller for storage. This allows for data backup in multiple locations, enhancing data security and recovery capabilities, and preventing data loss due to a single storage point failure.

[0080] In one exemplary embodiment, saving interface reference information to a designated memory includes saving a combination of power amplitude information, interface status information, and timestamp information as interface reference information to the designated memory.

[0081] Interface reference information may not include power supply amplitude information. Considering that there is a certain difference between the set signal amplitude threshold (i.e., the preset signal amplitude) and the actual signal amplitude that causes the power supply device to have an EOS fault, in order to facilitate maintenance personnel to obtain the recorded interface reference information, a combination of power supply amplitude information, interface status information and timestamp information can be saved as interface reference information in a designated memory.

[0082] Here, based on the recorded power supply amplitude information, the rationality of the preset signal amplitude setting can be judged, and the preset signal amplitude can be adjusted based on the judgment result. In addition, the recorded power supply amplitude information can facilitate the analysis of problems in circuit structure, etc., and facilitate circuit design improvements.

[0083] In this embodiment, the combination of power amplitude information, interface status information, and timestamp information is saved as interface reference information in a designated memory, which can improve the convenience of information acquisition and also help to judge the rationality of the preset signal amplitude setting.

[0084] In an exemplary embodiment, after saving the interface reference information to a designated memory, the method further includes: in the event of a power device failure, reading the interface reference information from the designated memory; if the time indicated by the timestamp information does not match the time of the power device failure, marking the power device failure as a non-EOS failure; if the time indicated by the timestamp information matches the time of the power device failure, marking the power device failure as a non-EOS failure when the interface status indicated by the interface status information is in an unconnected state; and marking the power device failure as an EOS failure when the interface status indicated by the interface status information is in a connected state.

[0085] In this embodiment, if a power supply device on the motherboard fails, the failure can be triggered by maintenance personnel or performed autonomously by the electronic device. To this end, interface reference information can be read from a designated memory, and the time indicated by the timestamp information can be analyzed to see if it matches the time of the power supply device failure. If they do not match, it indicates that no abnormal power signal was detected at the device interface at the time of the power supply device failure (i.e., no EOS signal input was detected). Therefore, it can be determined that the power supply device failure is not an EOS failure, and the power supply device failure can be marked as a non-EOS failure.

[0086] If the time indicated by the timestamp information matches the time of the power device failure, it can be further determined whether the interface status indicated by the interface status information is a connected state. Here, if the interface status of the device interface is an unconnected state (e.g., unplugged, not plugged in, etc.), it means that no external device was connected to the device interface when the power device failed, and the device failure was not caused by EOS. Therefore, it can be determined that the device failure of the power device is not an EOS failure, and the device failure of the power device is marked as a non-EOS failure. If the interface status of the device interface is a connected state, it can be determined that the device failure of the power device is an EOS failure, and the device failure of the power device is marked as an EOS failure.

[0087] For example, if an EOS (Effective Loss) is generated at a certain moment on interface 1, causing damage to a power supply device, then as long as the ADC and MCU are still working, they can record this power supply amplitude information, interface status information, and timestamp information. Generally, when a power supply device is damaged by an EOS, it usually manifests as a short circuit, and the system cannot function properly. If the system can function normally, the MCU, EC (Electronic Control Unit), or CPU can perform fault analysis. If the system cannot function normally, the laptop motherboard will be sent for repair.

[0088] When the motherboard is sent for repair, the technician can retrieve three pieces of information from the MCU's ROM: power supply amplitude information, interface status information, and timestamp information. The timestamp information allows the technician to confirm if the time of the fault matches the given information. The interface status information tells the technician what was being done with the interface at the time—whether it was being plugged in / out, connected to an external device, or not connected at all. The power supply amplitude information tells the technician the EOS (Electronic Energy Level) status at the time. By using these three pieces of information, the key information about the fault scene can be completely reconstructed, facilitating the technician's correct diagnosis.

[0089] For example, after matching the on-site timestamp information at the time of the fault, if the interface is in an unconnected state and abnormal power amplitude information is not recorded, but the power supply device still fails, then the maintenance personnel can clearly determine that the device failure is not caused by an EOS (Effective Loss of Power). This requires looking for the cause in the circuit design and the device itself. Conversely, the maintenance personnel can determine that an EOS has occurred, and in this case, corresponding EOS-enhanced protection needs to be implemented for the device interface.

[0090] The above analysis reveals whether the damage originates externally or internally, a crucial step in fault analysis. Data from after-sales surveys of laptops shows that over 70% of component damage / failure is caused by electrical disturbances (EOS). However, the source and energy level of EOS cannot be determined using conventional analysis methods. The electronic device information processing method provided in this application, through hardware and software collaboration, records key factors such as the power signal amplitude and interface status at the fault location in real time. This provides objective data support for subsequent analysis, preventing errors in the analysis direction and facilitating the identification of effective solutions, thereby improving motherboard quality. For maintenance personnel, based on the recorded power amplitude information and other key information, it is possible to clearly determine whether the fault is caused by external interference and to ascertain the magnitude of the interference, facilitating product improvements and ultimately enhancing product quality.

[0091] Furthermore, the motherboards of electronic devices are distributed across the circuitry, allowing full utilization of existing hardware design resources. For example, the ADC can use the EC or the CPU's built-in ADC interface, the MCU can be implemented using the EC controller itself, and the ROM can utilize the system's Basic Input Output System (BIOS) ROM resources, thereby reducing additional cost investment and enabling the recording of critical information with almost no increase in hardware costs.

[0092] Optionally, to facilitate maintenance personnel in obtaining the actual signal amplitude, the power supply amplitude information can be saved to a designated memory. To save storage space, the power supply amplitude information can also be acquired as a separate piece of information, and the acquired power supply amplitude information will not be saved to the designated memory. Correspondingly, the power supply amplitude information of the device interface and the interface reference information of the device interface can be acquired. The interface reference information includes interface status information. If the signal amplitude indicated by the power supply amplitude information is greater than or equal to a preset signal amplitude, the interface reference information is saved to the designated memory. The acquired power supply amplitude information and interface reference information are time-matched. Optionally, the interface reference information may also include timestamp information. The methods for acquiring power supply amplitude information and interface reference information are similar to those in the previous embodiments and have been described, so they will not be repeated here.

[0093] This embodiment analyzes and saves interface reference information after a fault occurs, and marks the fault type by combining timestamp comparison and interface status. It can automatically distinguish whether the fault is caused by EOS or other reasons, which helps to quickly eliminate EOS protection design defects, guide subsequent fault investigation and circuit optimization, and improve the overall stability and maintenance efficiency of the hardware system.

[0094] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0095] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / Random Access Memory (RAM), magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0096] According to another aspect of the embodiments of this application, an electronic device is also provided, which can be used to implement the information processing method of the electronic device provided in the above embodiments, and will not be repeated hereafter. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0097] Figure 4 This is a structural block diagram of an optional electronic device according to an embodiment of this application, such as... Figure 4 As shown, the electronic device includes a motherboard 402, on which a controller 404, a device interface 406, and a designated memory 408 may be configured. The controller 404 is used to acquire power amplitude information, interface status information, and timestamp information. The power amplitude information indicates the signal amplitude of the power signal of the device interface 406, and the interface status information indicates the interface status of the device interface 406. The signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information match the time indicated by the timestamp information. When the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, interface reference information is saved to the designated memory 408. The interface reference information includes interface status information and timestamp information, and is used for fault analysis of the power devices on the motherboard. The designated memory 408 is used to store the interface reference information.

[0098] It should be noted that the controller 404 in this embodiment can be used to execute the above steps S202 and S204, which have already been described and will not be repeated here.

[0099] According to the embodiments provided in this application, an electronic device includes a motherboard with device interfaces and a designated memory. It acquires power amplitude information, interface status information, and timestamp information. The power amplitude information indicates the signal amplitude of the power signal of the device interface, and the interface status information indicates the interface status of the device interface. The signal amplitude indicated by the power amplitude information and the interface status information match the time indicated by the timestamp information. When the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, interface reference information is saved to the designated memory. The interface reference information includes interface status information and timestamp information. The interface reference information is used for fault analysis of power devices on the motherboard, solving the problem of poor accuracy in fault location of power devices in related technologies and improving the accuracy of fault location.

[0100] In one exemplary embodiment, such as Figure 5 As shown, the motherboard 402 is also equipped with an analog-to-digital converter chip 502, and the device interface 406 is connected to one input pin of the analog-to-digital converter chip 502. The analog-to-digital converter chip 502 is used to convert the power signal of the device interface 406 into a digital signal to obtain the power amplitude information, and transmit the power amplitude information to the controller 404.

[0101] In an exemplary embodiment, the controller 404 is configured to acquire state information of a set of signal lines of the device interface 406, and determine the interface state of the device interface 406 based on the state information of the set of signal lines to obtain interface state information, wherein the set of signal lines includes at least one of the following: a detection line, a data line, and a status line; and acquire timestamp information that matches the interface state information.

[0102] In an exemplary embodiment, the controller 404 is further configured to determine the interface state of the device interface from a set of interface states based on the state information of a set of signal lines, and obtain interface state information, wherein the set of interface states includes at least one of the following: unconnected state, connected state.

[0103] In one exemplary embodiment, such as Figure 6As shown, the control device 404 includes a first controller 602 and a second controller 604. The first controller 602 can be a microcontroller. The second controller 604 can include at least one of the following: an embedded controller, a central processing unit. The first controller 602 is used to acquire power amplitude information; receive interface status information and timestamp information transmitted by the second controller 604; and save interface reference information to a designated memory 408. The second controller 604 is used to acquire interface status information and timestamp information matching the interface status information, and transmit the interface status information and timestamp information to the first controller 602. The interface reference information is saved to the designated memory 408 by the first controller 602.

[0104] In one exemplary embodiment, the first controller 602 is further configured to send power amplitude information to the second controller 604 for storage.

[0105] In an exemplary embodiment, the controller 404 is further configured to save a combination of power amplitude information, interface status information and timestamp information as interface reference information into a designated memory 408.

[0106] In one exemplary embodiment, the controller 404 is further configured to, after saving the interface reference information to the designated memory 408, read the interface reference information from the designated memory 408 in the event of a power device failure; if the time indicated by the timestamp information does not match the time of the power device failure, mark the power device failure as a non-electrical overstress (EOS) failure; if the time indicated by the timestamp information matches the time of the power device failure, mark the power device failure as a non-EOS failure when the interface status indicated by the interface status information is in an unconnected state; and if the time indicated by the timestamp information matches the time of the power device failure, mark the power device failure as an EOS failure when the interface status indicated by the interface status information is in a connected state.

[0107] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0108] According to another aspect of the embodiments of this application, a computer-readable storage medium is provided, the computer-readable storage medium including a stored program, wherein the program executes the steps in any of the above method embodiments when it is run.

[0109] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, ROMs, RAMs, portable hard drives, magnetic disks, or optical disks.

[0110] According to another aspect of the embodiments of this application, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps in the information processing method embodiments of any of the above-described electronic devices.

[0111] According to another aspect of the embodiments of this application, there is also a computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the information processing method embodiments of any of the above-described electronic devices.

[0112] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0113] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. An information processing method for an electronic device, characterized in that, The electronic device includes a motherboard, on which device interfaces and designated memory are provided; the method includes: Acquire power amplitude information, interface status information, and timestamp information, wherein the power amplitude information is used to indicate the signal amplitude of the power signal of the device interface, the interface status information is used to indicate the interface status of the device interface, and the signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information match the time indicated by the timestamp information. If the signal amplitude indicated by the power amplitude information is greater than or equal to the preset signal amplitude, the interface reference information is saved to the designated memory. The interface reference information includes the interface status information and the timestamp information. The interface reference information is used to analyze the power devices on the motherboard for fault analysis.

2. The method according to claim 1, characterized in that, The motherboard also includes an analog-to-digital converter chip and a controller, wherein the controller interface is connected to an input pin of the analog-to-digital converter chip; The acquisition of power amplitude information, interface status information, and timestamp information includes: The analog-to-digital converter chip converts the power signal of the device interface into a digital signal to obtain the power amplitude information, and then transmits the power amplitude information to the control device.

3. The method according to claim 1, characterized in that, The motherboard is also equipped with control devices; the acquisition of power amplitude information, interface status information, and timestamp information includes: The controller acquires the status information of a set of signal lines of the device interface, and determines the interface status of the device interface based on the status information of the set of signal lines to obtain the interface status information. The set of signal lines includes at least one of the following: a detection line, a data line, and a status line. The timestamp information that matches the interface status information is obtained through the controller.

4. The method according to claim 3, characterized in that, The process of determining the interface state of the device interface based on the state information of the set of signal lines, and obtaining the interface state information, includes: Based on the status information of the set of signal lines, the interface status of the device interface is determined from a set of interface statuses to obtain the interface status information, wherein the set of interface statuses includes at least one of the following: not connected, connected.

5. The method according to claim 1, characterized in that, The motherboard is also equipped with a control device, which includes a first controller and a second controller. The first controller is a microcontroller, and the second controller includes at least one of the following: an embedded controller and a central processing unit. The acquisition of power amplitude information, interface status information, and timestamp information includes: The power amplitude information is obtained through the first controller; The interface status information and the timestamp information matching the interface status information are obtained through the second controller, and the interface status information and the timestamp information are transmitted to the first controller. The interface reference information is stored in the designated memory by the first controller.

6. The method according to claim 5, characterized in that, After obtaining the power amplitude information through the first controller, the method further includes: The power amplitude information is sent from the first controller to the second controller for storage.

7. The method according to claim 1, characterized in that, Saving the interface reference information to the designated memory includes: The combination of the power amplitude information, the interface status information, and the timestamp information is saved as the interface reference information to the designated memory.

8. The method according to any one of claims 1 to 7, characterized in that, After saving the interface reference information to the designated memory, the method further includes: In the event of a power supply device failure, the interface reference information is read from the designated memory; If the time indicated by the timestamp information does not match the time of the power supply device failure, the power supply device failure is marked as a non-electrical overstress EOS failure. If the time indicated by the timestamp information matches the time of the power device failure, and the interface status indicated by the interface status information is in an unconnected state, the power device failure is marked as a non-EOS failure. If the time indicated by the timestamp information matches the time of the power supply device failure, and the interface status indicated by the interface status information is in the connected state, the power supply device failure is marked as an EOS failure.

9. An electronic device, characterized in that, Includes: a motherboard, on which control devices, device interfaces, and designated memory are provided; wherein, The control device is used to acquire power amplitude information, interface status information, and timestamp information. The power amplitude information indicates the signal amplitude of the power signal of the device interface, and the interface status information indicates the interface status of the device interface. The signal amplitude indicated by the power amplitude information and the interface status indicated by the interface status information match the time indicated by the timestamp information. If the signal amplitude indicated by the power amplitude information is greater than or equal to a preset signal amplitude, interface reference information is saved to the designated memory. The interface reference information includes the interface status information and the timestamp information, and is used for fault analysis of the power devices on the motherboard. The designated memory is used to store the interface reference information.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 8.

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