Frequency multiplication code pattern interference self-calibration system and communication system

Abstract

The invention discloses a frequency multiplication code pattern interference self-calibration system and a communication system, and relates to the technical field of high-speed signal transmission, and the system comprises a first calibration unit which carries out the initial calibration of a positive signal of a to-be-calibrated differential signal to obtain a first calibration signal, a second calibration unit which carries out the complex calibration of the first calibration signal to obtain a second calibration signal, and a third calibration unit which carries out the complex calibration of the second calibration signal. The calibration triggering unit outputs a third calibration signal under the condition that a preset calibration condition is met, the fourth calibration unit obtains a fourth calibration signal according to the third calibration signal and the second calibration signal, and finally the third calibration unit carries out final calibration on the positive signal according to the second calibration signal and the fourth calibration signal to obtain a calibrated positive signal. Therefore, the problem of frequency multiplication code pattern crosstalk between the high-speed serial signals is solved, and the frequency multiplication code pattern crosstalk between the high-speed serial signals can be effectively eliminated through the self-calibration system built by discrete components, so that the reliability and the stability of system operation are improved.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal transmission technology, and in particular to a frequency-doubled code interference self-calibration system and communication system. Background Technology

[0002] With the continuous improvement of high-speed signal transmission rates, crosstalk between signals has become particularly prominent, especially in high-speed serial systems, where the interference of data signals on clock signals is particularly significant.

[0003] In related technologies, electromagnetic coupling is typically reduced by increasing the distance between signal lines during the PCB (Printed Circuit Board) design phase, thereby reducing crosstalk. However, this method has space limitations and cannot completely solve the crosstalk problem between high-speed signals, which can lead to errors in system code acceptance and judgment. Furthermore, if crosstalk occurs frequently, it may cause the entire system to malfunction.

[0004] No effective solutions have yet been proposed for technical issues such as frequency-multiplication code crosstalk between high-speed serial signals in related technologies. Summary of the Invention

[0005] This invention provides a frequency-doubling pattern interference self-calibration system to at least solve the problem of frequency-doubling pattern crosstalk between high-speed serial signals in related technologies.

[0006] This invention provides a frequency-multiplying code pattern interference self-calibration system, comprising: a positive signal calibration circuit and a negative signal calibration circuit. The positive signal calibration circuit includes first to third calibration units, and the negative signal calibration circuit includes a calibration trigger unit and a fourth calibration unit.

[0007] The first calibration unit performs initial calibration on the positive signal of the differential signal to be calibrated to obtain the first calibration signal;

[0008] The second calibration unit performs recalibration on the first calibration signal to obtain the second calibration signal;

[0009] The calibration trigger unit outputs a third calibration signal when the preset calibration conditions are met.

[0010] The fourth calibration unit obtains the fourth calibration signal based on the third and second calibration signals;

[0011] The third calibration unit performs final calibration on the positive signal based on the second and fourth calibration signals to obtain the calibrated positive signal.

[0012] The present invention also provides a communication system, including a frequency multiplication code pattern interference self-calibration system as described in any of the above claims.

[0013] This invention involves a first calibration unit performing initial calibration on the positive signal of the differential signal to be calibrated to obtain a first calibration signal. A second calibration unit then performs recalibration on the first calibration signal to obtain a second calibration signal. A calibration trigger unit outputs a third calibration signal when preset calibration conditions are met. A fourth calibration unit obtains a fourth calibration signal based on the third and second calibration signals. Finally, the third calibration unit performs final calibration on the positive signal based on the second and fourth calibration signals to obtain the calibrated positive signal. This solves the problem of frequency-multiplication crosstalk between high-speed serial signals. The self-calibration system, built with discrete components, can effectively eliminate frequency-multiplication crosstalk between high-speed serial signals, thereby improving the reliability and stability of the system. Attached Figure Description

[0014] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a frequency multiplication code pattern interference processing scheme for related technologies;

[0016] Figure 2 This is a schematic diagram of a frequency multiplication code interference processing scheme provided in one embodiment of the present invention;

[0017] Figure 3 This is a block diagram of a frequency-doubling code pattern interference self-calibration system provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0019] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0020] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The present invention provides a frequency-doubled pattern interference self-calibration system, and the system is described in detail below in conjunction with the execution system of the frequency-doubled pattern interference self-calibration system.

[0022] Specifically, before introducing the embodiments of the present invention, we will first introduce the frequency multiplication code interference processing method in related technologies. High-speed serial signals are generally composed of differential signals, which are composed of two single-ended signals P and N. The interference of the frequency multiplication code mainly comes from the disturbance of the clock signal by the data signal in the serial system. In a typical serial system, the data signal rate is twice that of the clock signal, and in the board-level layout, there are many data signal traces distributed around the clock signal. Therefore, the clock signal is more susceptible to external data interference. One typical type of interference is that at the high level, the clock signal is superimposed with the interference of the data signal. This superposition will greatly increase the high-level amplitude of the signal. Excessively high levels will damage the passive components of the system, causing breakdown or shortening the lifespan. Generally, the interference occurs in the first half or the second half of a high-level UI (Unit Interval) of the clock signal.

[0023] Crosstalk, or code interference, is an important consideration in the development of high-speed signals. If the crosstalk between signals is large and exceeds the system's tolerance, and the crosstalk reaches the signal receiver during signal transmission without being effectively eliminated, it will have disastrous consequences for the entire system, leading to errors in code recognition. Furthermore, if crosstalk occurs frequently, it may also cause the entire system to fail to operate.

[0024] In existing technical solutions for frequency-multiplication code interference processing Figure 1 This is a schematic diagram of a frequency multiplication code interference processing scheme for related technologies, such as... Figure 1 As shown, during the PCB design phase, the distance between serial signal traces is typically increased to reduce electromagnetic coupling and crosstalk. However, with technological advancements, the speed of high-speed signals will continue to rise. Therefore, simply increasing the distance between signal traces to eliminate crosstalk will place increasingly stringent requirements on the spacing, as PCB trace space is limited and cannot be infinitely increased. This is especially true in BGA (Ball Grid Array) package areas, where the trace paths are fixed within the package area, making it impossible to increase the trace distance. Consequently, the aforementioned technical solutions cannot meet the demands of future higher-speed signals.

[0025] Therefore, eliminating the excessively high voltage caused by the crosstalk superposition of frequency-harmonic signals in the system, and ensuring that it can stably recover to the normal signal level at the receiving end, has become a major challenge and key point in high-speed signal design. Figure 2 This is a schematic diagram of a frequency multiplication code interference processing scheme provided in one embodiment of the present invention, as shown below. Figure 2 As shown, the present invention is constructed from discrete components to automatically eliminate interference between frequency multiplication codes of high-speed serial differential signals, thereby ensuring that the receiving end can simultaneously receive the correct differential signals without strict requirements on the spacing of the traces. It features high reliability, strong versatility, and low cost.

[0026] Specifically, Figure 3 This is a block diagram of a frequency-doubling code interference self-calibration system provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the frequency-doubled code interference self-calibration system 10 mainly includes a positive signal calibration circuit 100 and a negative signal calibration circuit 200. The positive signal calibration circuit 100 includes a first calibration unit 101, a second calibration unit 102, and a third calibration unit 103, while the negative signal calibration circuit 200 includes a calibration trigger unit 201 and a fourth calibration unit 202. During the frequency-doubled code interference self-calibration process, the first calibration unit 101 first performs initial calibration on the positive signal of the differential signal to be calibrated to obtain a first calibration signal; secondly, the second calibration unit 102 performs recalibration on the first calibration signal to obtain a second calibration signal; thirdly, the calibration trigger unit 201 outputs a third calibration signal when the preset calibration conditions are met; finally, the fourth calibration unit 202 obtains a fourth calibration signal based on the third and second calibration signals, and the third calibration unit 103 performs final calibration on the positive signal based on the second and fourth calibration signals to obtain the finally calibrated positive signal.

[0027] The preset calibration conditions can be set by those skilled in the art based on the real-time signal calibration requirements, and are not specifically limited here.

[0028] Specifically, to solve the crosstalk problem between high-speed signals, this embodiment of the invention provides an automatic self-calibration system for eliminating frequency-multiplied code interference of high-speed serial differential signals based on discrete components. This system can eliminate the interference of frequency-multiplied codes between high-speed serial differential signals, thereby ensuring that the receiving end can receive the correct differential signals simultaneously. It does not require strict requirements on the spacing of the traces, making it highly reliable, versatile, and low-cost.

[0029] Specifically, such as Figure 3As shown in this embodiment of the invention, if the clock differential signal PN (PN Junction, P-type-N-type junction) in the input high-speed serial system is interfered with by the adjacent data signal, since the data signal has twice the speed of the clock signal, there will be two typical phenomena in the crosstalk: one is that the crosstalk is superimposed on the T1 time period, that is, the first half of a UI time, and the other is that it is superimposed on the T4 time period, that is, the second half of a UI time. Therefore, the interference of the data signal will cause the level at these two points to rise abnormally, that is, the high level is twice the normal level. Therefore, in order to solve the above problems, this embodiment of the invention uses a series of operational amplifiers (such as U1, U2, U3 and U4) and NPN (Negative-Positive-Negative Transistor) type transistors (such as Q1), identifies the time interval of interference occurrence (such as T1 to T5), and then adjusts the affected P signal according to different time intervals. That is, according to the interference characteristics of different time intervals, different resistor values ​​and circuit configurations are used respectively, and the output signal is adjusted by combining operational amplifiers and transistors to ensure that the output level meets expectations.

[0030] The specific circuit connections for each calibration unit will be explained in detail below.

[0031] According to one embodiment of the present invention, a first calibration unit 101 includes: a first resistor, one end of which is electrically connected to a positive signal input terminal; a second resistor, one end of which is electrically connected to the other end of the first resistor, and the other end of which is electrically connected to an input terminal of a second calibration unit 102; a first amplifier, the inverting input terminal of which is electrically connected to a connection node between the first and second resistors, the non-inverting input terminal of which is electrically connected to a ground node, the power input terminal of which is electrically connected to a power access node, the ground terminal of which is electrically connected to a ground node, and the output terminal of which is electrically connected to the other end of the second resistor and the connection node between the input terminal of the second calibration unit 102.

[0032] The preset multiplier can be set by those skilled in the art based on the real-time signal calibration blood requirements, and is not specifically limited here.

[0033] Specifically, such as Figure 3As shown, the first calibration unit 101 includes a first resistor R1, a second resistor R2, and a first amplifier U1. One end of the first resistor R1 is electrically connected to the positive signal input terminal, one end of the second resistor R2 is electrically connected to the other end of the first resistor R1, and the other end of the second resistor R2 is electrically connected to the input terminal of the second calibration unit 102. The inverting input terminal of the first amplifier U1 is electrically connected to the connection node between the first resistor R1 and the second resistor R2. The non-inverting input terminal of the first amplifier U1 is electrically connected to the ground node. The power input terminal of the first amplifier U1 is electrically connected to the power access node. The ground terminal of the first amplifier U1 is electrically connected to the ground node. The output terminal of the first amplifier U1 is electrically connected to the connection node between the other end of the second resistor R2 and the input terminal of the second calibration unit 102. The resistance value of the second resistor R2 is the product of the resistance value of the first resistor R1 and a preset multiple.

[0034] For example, such as Figure 3 As shown, at time T1, the input signal P (Vin_P) is 2 × VCC (Voltage Common Collector, power supply voltage). The P signal is interfered with by the data signal, while the N signal (Vin_N) is a low logic level 0, serving as a reference signal. The first resistor R1 is used to introduce the input P signal into the first amplifier U1, and the second resistor R2 serves as the feedback resistor for the first amplifier U1. Therefore, the first amplifier U1 is in a linear amplification state. At this time, the signal P is amplified in reverse and output to node a, satisfying the virtual short and virtual open properties. Therefore, U1+=U1-=0. Due to the virtual open property, the current flowing through the first resistor R1 is equal to the current flowing through the second resistor R2. The expression can then be obtained: Combining U1+=U1-=0, we can obtain If we take R2 = 0.5 × R1, then the output of the first amplifier U1 is a = -0.5 × 2 × VCC = -VCC. At this time, the signal P after being processed by the first amplifier U1 is output at node a. Since the signal P has been inverted and amplified, it is equivalent to halving the noise amplitude of the P signal and inverting it once, so that the positive interference that was originally superimposed on the P signal is now turned into negative interference.

[0035] Therefore, by introducing the P signal into the first amplifier U1 and adjusting the output using the negative feedback mechanism, if the resistor R2 is set to half of R1, then the output a of the first amplifier U1 will be the negative half of the input signal. At this time, the amplitude of the original interference signal is halved and the phase is reversed, which means that the positive interference originally superimposed on the P signal has now become negative interference, thereby effectively canceling the original interference components.

[0036] According to one embodiment of the present invention, the second calibration unit 102 includes: a third resistor, one end of which is electrically connected to the other end of the second resistor and the output terminal of the first amplifier; a fourth resistor, one end of which is electrically connected to the other end of the third resistor, and the other end of which is electrically connected to the input terminal of the second calibration unit 102 and the input terminal of the fourth calibration unit 202; a second amplifier, the inverting input terminal of which is electrically connected to the connection node between the third and fourth resistors, the non-inverting input terminal of which is electrically connected to a ground node, the power input terminal of which is electrically connected to a power access node, the ground terminal of which is electrically connected to a ground node, and the output terminal of which is electrically connected to the connection node between the other end of the fourth resistor and the input terminal of the fourth calibration unit 202.

[0037] Specifically, such as Figure 3 As shown, the second calibration unit 102 includes a third resistor R3, a fourth resistor R4, and a second amplifier U2. One end of the third resistor R3 is electrically connected to the other end of the second resistor and the output terminal of the first amplifier. One end of the fourth resistor R4 is electrically connected to the other end of the third resistor R3. The other end of the fourth resistor R4 is electrically connected to the input terminal of the second calibration unit 102 and the input terminal of the fourth calibration unit 202. The inverting input terminal of the second amplifier U2 is electrically connected to the connection node between the third resistor R3 and the fourth resistor R4. The non-inverting input terminal of the second amplifier U2 is electrically connected to the ground node. The power input terminal of the second amplifier U2 is electrically connected to the power access node. The ground terminal of the second amplifier U2 is electrically connected to the ground node. The output terminal of the second amplifier U2 is electrically connected to the connection node between the other end of the fourth resistor R4 and the input terminal of the fourth calibration unit 202.

[0038] For example, after the signal P flows through the first amplifier U1, it continues to flow through the second amplifier U2. The second amplifier U2 further processes the signal P from the first amplifier U1 and outputs the signal P to node b. Similarly, the fourth resistor R4 serves as the feedback resistor for the second amplifier U2, so the second amplifier U2 is in a linear amplification state. At this time, the signal P is amplified in reverse and output to node b, satisfying the virtual short and virtual open properties. Therefore, we can obtain U2+=U2-=0. Thus, the current flowing through the third resistor R3 is equal to the current flowing through the fourth resistor R4. At this point, we can obtain the expression: Combining this with U² + = U² - = 0, we can obtain... If R3=R4, then the output of the second amplifier U2 is b=-a, that is, b=VCC. At this time, the amplitude and phase of the signal are further adjusted.

[0039] Therefore, after signal P is processed by the first amplifier U1, the noise amplitude of signal P has been halved and the phase has been reversed. When the signal enters the second amplifier U2, since the second amplifier U2 also has a negative feedback resistor, the second amplifier U2 is also in a linear amplification state and satisfies the characteristics of virtual short and virtual open. Through the operation of the second amplifier U2, the signal that was originally distorted by interference is not only restored to the correct amplitude, but also the phase is corrected, so that the signal returns to normal, thereby ensuring that the receiver can accurately identify the signal.

[0040] According to one embodiment of the present invention, the calibration trigger unit 201 includes: a thirteenth resistor, one end of which is electrically connected to the negative signal input terminal of the differential signal to be calibrated; a fourteenth resistor, one end of which is electrically connected to a power supply access node; a transistor, the base of which is electrically connected to the other end of the thirteenth resistor, the collector of which is electrically connected to the other end of the fourteenth resistor and one end of the ninth resistor, and the emitter of which is electrically connected to a ground node.

[0041] Specifically, such as Figure 3 As shown, the calibration trigger unit 201 includes a thirteenth resistor R13, a fourteenth resistor R14, and a transistor Q1. One end of the thirteenth resistor R13 is electrically connected to the negative signal input terminal of the differential signal to be calibrated, one end of the fourteenth resistor R14 is electrically connected to the power supply access node, the base of the transistor Q1 is electrically connected to the other end of the thirteenth resistor R13, the collector of the transistor Q1 is electrically connected to the other end of the fourteenth resistor R14 and one end of the ninth resistor, and the emitter of the transistor Q1 is electrically connected to the ground node.

[0042] Specifically, at time T1, because the polarities of PN are opposite, the N signal Vin_N is 0. Since transistor Q1 is an NPN transistor, the base of transistor Q1 is in the cutoff state due to insufficient forward bias voltage. At this time, when transistor Q1 is cut off, the current cannot flow from the collector to the emitter. This means that the output node e will be maintained at the VCC level through the pull-up resistor. That is, when transistor Q1 is cut off, the value of the output node e is VCC, i.e., e=VCC.

[0043] Therefore, in this state, even if the P signal is disturbed, the other part of the system (i.e., the N signal path) can still provide a stable reference point, which helps subsequent circuits to process the signal accurately.

[0044] According to one embodiment of the present invention, the fourth calibration unit 202 includes: a ninth resistor, one end of which is electrically connected to the output terminal of the calibration trigger unit 201; a tenth resistor, one end of which is electrically connected to the output terminal of the second amplifier; an eleventh resistor, one end of which is electrically connected to the other end of the ninth resistor; a twelfth resistor, one end of which is electrically connected to a ground node; a fourth amplifier, the inverting input terminal of which is electrically connected to the connection node between the ninth and eleventh resistors, the non-inverting input terminal of which is electrically connected to the other end of the twelfth resistor, the power input terminal of which is electrically connected to a power access node, the ground terminal of which is electrically connected to a ground node, and the output terminal of which is electrically connected to the other end of the eleventh resistor and one end of the seventh resistor, respectively.

[0045] Specifically, such as Figure 3 As shown, the fourth calibration unit 202 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a fourth amplifier U4. One end of the ninth resistor R9 is electrically connected to the output terminal of the calibration trigger unit 201. One end of the tenth resistor R10 is electrically connected to the output terminal of the second amplifier U2. One end of the eleventh resistor R11 is electrically connected to the other end of the ninth resistor R9. One end of the twelfth resistor R12 is electrically connected to the ground node. The inverting input terminal of the fourth amplifier U4 is electrically connected to the connection node between the ninth resistor R9 and the eleventh resistor R11. The non-inverting input terminal of the fourth amplifier U4 is electrically connected to the other end of the twelfth resistor R12. The power input terminal of the fourth amplifier U4 is electrically connected to the power input node. The ground terminal of the fourth amplifier U4 is electrically connected to the ground node. The output terminal of the fourth amplifier U4 is electrically connected to the other end of the eleventh resistor R11 and one end of the seventh resistor R7, respectively.

[0046] For example, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 in the fourth calibration unit 202 constitute the bias network of transistor Q1, thereby ensuring that transistor Q1 operates in a suitable state. Combined with the operating principle of the fourth amplifier U4, the fourth amplifier U4 is also in a linear amplification state, satisfying the characteristics of virtual short and virtual open circuits. Therefore, we can obtain U4+ = U4-, that is... When R12=R10 and R9=R11, the output of the fourth amplifier U4 is d=e-b. Since the fourth amplifier U4 receives inputs from two different paths, namely e=VCC from the output of transistor Q1 and b=VCC from the output of the second amplifier U2, and the output of the fourth amplifier U4 is d=e-b, the output of the fourth amplifier U4 at this time is d=e-b=VCC-VCC=0. This means that although the P signal is interfered with, the design of part of the circuit of the fourth amplifier U4 effectively cancels out this interference, so that the final output Vout_P returns to the normal VCC level.

[0047] Therefore, at time T1, the main benefit of the N signal flowing through the fourth amplifier U4 for signal calibration is that it helps the system effectively identify and eliminate the frequency multiplication pattern interference in the P signal, ensuring the correct logic level of the output signal, enhancing the stability and reliability of the system, and providing high design flexibility and cost-effectiveness.

[0048] According to one embodiment of the present invention, the third calibration unit 103 includes: a fifth resistor, one end of which is electrically connected to the other end of a fourth resistor and the output terminal of a second amplifier; a sixth resistor, one end of which is electrically connected to the other end of a fourth resistor and the other end of which is electrically connected to the output terminal of a frequency-doubling code interference self-calibration system; a seventh resistor, one end of which is electrically connected to the output terminal of the fourth calibration unit 202; an eighth resistor, one end of which is electrically connected to a grounding node; a third amplifier, the inverting input terminal of which is electrically connected to the other ends of the seventh resistor and the fifth resistor, the non-inverting input terminal of which is electrically connected to the other end of the eighth resistor, the power input terminal of which is electrically connected to a power access node, the grounding terminal of which is electrically connected to a grounding node, and the output terminal of which is electrically connected to the output terminal of the frequency-doubling code interference self-calibration system.

[0049] Specifically, such as Figure 3As shown, the third calibration unit 103 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a third amplifier U3. One end of the fifth resistor R5 is electrically connected to the other end of the fourth resistor and the output of the second amplifier. One end of the sixth resistor R6 is electrically connected to the other end of the fourth resistor and the other end of the sixth resistor R6 is electrically connected to the output of the frequency multiplication pattern interference self-calibration system. One end of the seventh resistor R7 is electrically connected to the output of the fourth calibration unit 202. One end of the eighth resistor R8 is electrically connected to the grounding node. The inverting input of the third amplifier U3 is electrically connected to the other ends of the seventh resistor R7 and the fifth resistor R5. The non-inverting input of the third amplifier U3 is electrically connected to the other end of the eighth resistor R8. The power input of the third amplifier U3 is electrically connected to the power access node. The grounding terminal of the third amplifier U3 is electrically connected to the grounding node. The output of the third amplifier U3 is electrically connected to the output of the frequency multiplication pattern interference self-calibration system. At this time, the resistance values ​​of the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are all equal.

[0050] For example, the main function of the third amplifier U3 is to amplify and shape the signal processed by the previous stage, and output the signal P to node c, ultimately outputting to Vout_P. Similarly, the third amplifier U3 is in a virtual open / virtual short state, at which time U3+=U3-=0. The current flowing through the seventh resistor R7 is equal to the sum of the currents flowing through the fifth resistor R5 and the sixth resistor R6. At this point, if R5=R6=R7, we can obtain the output of the third amplifier U3: c=b+d=VCC, and the output Vout_P=VCC. Therefore, the interference-affected input P signal at time T1 changes from the original 2×VCC to the normal VCC.

[0051] Therefore, the main benefit of the P signal flowing through the third amplifier U3 for signal calibration is that it can help the system effectively identify and eliminate the frequency multiplication pattern interference in the P signal, ensure the correct logic level of the output signal, and enhance the stability and reliability of the system.

[0052] Furthermore, based on the design of the aforementioned circuit components, at time T2, the magnitude of Vin_P is the normal VCC (the interference received at this time is 0), and the magnitude of the Vin_N signal is also low, 0. At this time, the entire circuit uses the same resistance values ​​as at time T1. Similarly, the output a of the first amplifier U1 can be obtained as a = -0.5 × Vin_P = -0.5 × VCC. The output b of the second amplifier U2 is -a = 0.5 × VCC. Transistor Q1 is still in the off state, therefore, the output e = VCC. The output d of the fourth amplifier U4 is d = e - b = VCC - 0.5 × VCC = 0.5 × VCC. The output c of the third amplifier U3 is c = b + d = 0.5 × VCC + 0.5 × VCC = VCC. In summary, throughout the entire T2-T1 interval, the output P signal becomes a normal amplitude level signal, eliminating the interference of the frequency multiplication pattern.

[0053] Furthermore, similarly, the situation at times T3 and T4 is similar to that at times T1 and T2 analyzed above. The difference is that the UI affected by the interference at times T3 and T4 changes from the first half to the second half. The entire system can still eliminate this type of interference. To avoid redundancy, this will not be discussed in detail here.

[0054] Furthermore, at time T5, Vin_P=0, Vin_N=VCC, therefore b=a=0, transistor Q1 is turned on, therefore e=0, so d=e-b=0V, and the output Vout_P=b+d=0. Therefore, it can be seen that the entire system can still ensure that the normal output Vout_P is low, without affecting the normal logic function of the system.

[0055] In summary, from time T1 to T5, the output Vout_P can maintain a normal amplitude level, which can eliminate the serialized frequency multiplication code pattern, thereby ensuring the accuracy of the amplitude and logic level. The entire scheme of this embodiment utilizes the characteristics of the PN signal to automatically eliminate interference on the P signal.

[0056] To facilitate a clearer understanding of the technical solution of this invention by those skilled in the art, a detailed description will be provided below based on specific embodiments:

[0057] This invention uses VCC as 3.3V, R2 to R14 as 10K, R1 as 20K, U1, U2, U3, and U4 as LM307 amplifiers, and Q1 as a 9013 NPN transistor. Specific details are as follows:

[0058] (1) At times T1 and T4, the differential signal P is 2×VCC=6.6V and N is 0V. At this time, the output of U1 is a=-0.5×Vin_P=-3.3V; the output of U2 is b=-a=3.3V; the output of U4 is d=e-b=3.3-3.3=0V. The output of the whole system is Vout_P=b+d=3.3+0=3.3V. Therefore, the system voltage has been reduced from the original 6.6V due to crosstalk to 3.3V, and the system has completed the elimination of crosstalk.

[0059] (2) At times T2 and T3, the P signal is VCC=3.3V and the N signal is 0V. At this time, the output of U1 is a=-0.5×Vin_P=-1.65V; the output of U2 is b=-a=1.65V; the output of U4 is d=e-b=3.3-1.65=1.65V. The output of the whole system is Vout_P=b+d=1.65+1.65=3.3V. Therefore, in the half-UI interval that is not disturbed, the whole system can maintain the output normally and is not affected, thus completing the function of adaptive crosstalk elimination.

[0060] (3) At time T5, the P signal is VCC=0V and the N signal is 3.3V. At this time, the output of U1 is a=-0.5×Vin_P=-0V; the output of U2 is b=-a=0V. At this time, Q1 is turned on, so e=0V; the output of U4 is d=e-b=0V. The output of the whole system is Vout_P=b+d=0V. Therefore, during the low-level T5 time period without interference, the whole system can maintain normal output.

[0061] In summary, during the entire T1 to T5 time period, if P in the high-speed signal is interfered with by the frequency multiplication pattern of the adjacent trace, resulting in amplitude distortion, the system will adaptively judge the entire signal and eliminate crosstalk. Therefore, the entire system completes the function of automatically calibrating the frequency multiplication pattern crosstalk.

[0062] Therefore, based on the above specific embodiments, the circuit of the present invention has strong versatility. Utilizing discrete components, it can detect crosstalk when one signal line in a differential signal is subjected to crosstalk of a code pattern with a frequency multiplication rate from adjacent traces. By utilizing the opposite polarity of PN signals, it can accurately eliminate the crosstalk signal without affecting the transmission of the original normal signal, thereby ensuring the stable and reliable operation of the system. It can also quickly eliminate high-amplitude crosstalk in a timely manner, reducing the harm of high amplitude to the system. This self-calibrating system for eliminating frequency multiplication code pattern crosstalk has strong versatility, high reliability, and low cost. At the same time, the technical solution of the present invention can also be used in other high-speed differential signal systems for crosstalk calibration systems with multiple frequency multiplication code pattern relationships.

[0063] The frequency-multiplied code pattern interference self-calibration system proposed in this embodiment of the invention comprises the following steps: a first calibration unit performs initial calibration on the positive signal of the differential signal to be calibrated to obtain a first calibration signal; a second calibration unit performs recalibration on the first calibration signal to obtain a second calibration signal; a calibration trigger unit outputs a third calibration signal when preset calibration conditions are met; a fourth calibration unit obtains a fourth calibration signal based on the third and second calibration signals; and finally, the third calibration unit performs final calibration on the positive signal based on the second and fourth calibration signals to obtain the calibrated positive signal. This solves the problem of frequency-multiplied code pattern crosstalk between high-speed serial signals. The self-calibration system, built with discrete components, can effectively eliminate frequency-multiplied code pattern crosstalk between high-speed serial signals, thereby improving the reliability and stability of system operation.

[0064] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0065] Embodiments of the present invention also provide a communication system, which includes a frequency multiplication code pattern interference self-calibration system as described in any of the above claims.

[0066] According to the communication system proposed in this embodiment of the invention, a first calibration unit performs initial calibration on the positive signal of the differential signal to be calibrated to obtain a first calibration signal. A second calibration unit performs recalibration on the first calibration signal to obtain a second calibration signal. A calibration trigger unit outputs a third calibration signal when preset calibration conditions are met. A fourth calibration unit obtains a fourth calibration signal based on the third and second calibration signals. Finally, the third calibration unit performs final calibration on the positive signal based on the second and fourth calibration signals to obtain the calibrated positive signal. This solves the problem of frequency-multiplication crosstalk between high-speed serial signals. The self-calibration system built with discrete components can effectively eliminate frequency-multiplication crosstalk between high-speed serial signals, thereby improving the reliability and stability of system operation.

[0067] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0068] The above provides a detailed description of the frequency multiplication code interference self-calibration system provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A frequency-doubling code interference self-calibration system, characterized in that, include: The system includes a positive signal calibration circuit and a negative signal calibration circuit. The positive signal calibration circuit includes first to third calibration units, and the negative signal calibration circuit includes a calibration trigger unit and a fourth calibration unit. The first calibration unit performs initial calibration on the positive signal of the differential signal to be calibrated to obtain the first calibration signal; The second calibration unit performs recalibration on the first calibration signal to obtain the second calibration signal; The calibration triggering unit outputs a third calibration signal when the preset calibration conditions are met. The fourth calibration unit obtains a fourth calibration signal based on the third calibration signal and the second calibration signal; The third calibration unit performs final calibration on the positive signal based on the second calibration signal and the fourth calibration signal to obtain the calibrated positive signal.

2. The frequency multiplication code pattern interference self-calibration system according to claim 1, characterized in that, The first calibration unit includes: A first resistor, one end of which is electrically connected to the input terminal of the positive signal; The second resistor has one end electrically connected to the other end of the first resistor, and the other end of the second resistor is electrically connected to the input terminal of the second calibration unit. A first amplifier, wherein the inverting input terminal of the first amplifier is electrically connected to the connection node between the first resistor and the second resistor, the non-inverting input terminal of the first amplifier is electrically connected to the ground node, the power input terminal of the first amplifier is electrically connected to the power access node, the ground terminal of the first amplifier is electrically connected to the ground node, and the output terminal of the first amplifier is electrically connected to the connection node between the other end of the second resistor and the input terminal of the second calibration unit.

3. The frequency multiplication code interference self-calibration system according to claim 2, characterized in that, The resistance of the second resistor is the product of the resistance of the first resistor and a preset multiple.

4. The frequency multiplication code interference self-calibration system according to claim 2 or 3, characterized in that, The second calibration unit includes: A third resistor, one end of which is electrically connected to the other end of the second resistor and the output terminal of the first amplifier; A fourth resistor, one end of which is electrically connected to the other end of the third resistor, and the other end of which is electrically connected to the input terminal of the third calibration unit and the input terminal of the fourth calibration unit, respectively. The second amplifier has its inverting input terminal electrically connected to the connection node between the third and fourth resistors, its non-inverting input terminal electrically connected to the ground node, its power input terminal electrically connected to the power access node, its ground terminal electrically connected to the ground node, and its output terminal electrically connected to the connection node between the other end of the fourth resistor and the input terminal of the fourth calibration unit.

5. The frequency multiplication code pattern interference self-calibration system according to claim 4, characterized in that, The resistance value of the third resistor is equal to the resistance value of the fourth resistor.

6. The frequency multiplication code interference self-calibration system according to claim 5, characterized in that, The third calibration unit includes: The fifth resistor, one end of which is electrically connected to the other end of the fourth resistor and the output terminal of the second amplifier; The sixth resistor, one end of which is electrically connected to the other end of the fourth resistor, and the other end of which is electrically connected to the output terminal of the frequency multiplication code interference self-calibration system; The seventh resistor, one end of which is electrically connected to the output terminal of the fourth calibration unit; The eighth resistor, one end of which is electrically connected to the grounding node; The third amplifier has its inverting input terminal electrically connected to the other ends of the seventh resistor and the fifth resistor, respectively, its non-inverting input terminal electrically connected to the other end of the eighth resistor, its power input terminal electrically connected to the power access node, its ground terminal electrically connected to the ground node, and its output terminal electrically connected to the output terminal of the frequency multiplication code interference self-calibration system.

7. The frequency multiplication code interference self-calibration system according to claim 6, characterized in that, The resistance values ​​of the fifth resistor, the sixth resistor, and the seventh resistor are all equal.

8. The frequency multiplication code pattern interference self-calibration system according to claim 6, characterized in that, The fourth calibration unit includes: The ninth resistor, one end of which is electrically connected to the output terminal of the calibration trigger unit; The tenth resistor, one end of which is electrically connected to the output terminal of the second amplifier; The eleventh resistor, one end of which is electrically connected to the other end of the ninth resistor; The twelfth resistor, one end of which is electrically connected to the grounding node; The fourth amplifier has its inverting input terminal electrically connected to the connection node between the ninth and eleventh resistors, its non-inverting input terminal electrically connected to the other end of the twelfth resistor, its power input terminal electrically connected to the power access node, its ground terminal electrically connected to the ground node, and its output terminal electrically connected to the other end of the eleventh resistor and one end of the seventh resistor.

9. The frequency multiplication code interference self-calibration system according to claim 8, characterized in that, The calibration trigger unit includes: The thirteenth resistor, one end of which is electrically connected to the negative signal input terminal of the differential signal to be calibrated; The fourteenth resistor, one end of which is electrically connected to the power supply access node; The transistor has its base electrically connected to the other end of the thirteenth resistor, its collector electrically connected to the other end of the fourteenth resistor and one end of the ninth resistor, and its emitter electrically connected to the ground node.

10. A communication system, characterized in that, include: The frequency multiplication code pattern interference self-calibration system as described in any one of claims 1 to 9.

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