Extensible, reconfigurable and interchangeable method and device for information processing system

Abstract

The invention relates to an extensible, reconfigurable and interchangeable method and device for an information processing system, and belongs to the technical field of information processing systems. The device comprises an FPGA (Field Programmable Gate Array) platform case, a CPU (Central Processing Unit) platform case, a network switching board card and a rear plug-in board card, all the board cards meet the VITA standard protocol, and all the board cards can obtain the case number and the slot position number on the VPX connector; all executable files of board cards of the same type in the current working mode are placed in an SATA disk, and the program executable files are named according to the case number and the slot position number; the network address of the board card is electrified to automatically obtain an IP address, and the IP address is bound with the case number and the slot number corresponding to the case where the current board card is located. According to the invention, random exchange of similar board cards can be realized, the operation and maintenance cost is reduced, and the reliability of the system is improved.

Description

Technical Field

[0001] This invention belongs to the field of information processing system technology, and specifically relates to a method and apparatus for an information processing system that is scalable, reconfigurable and interchangeable. Background Technology

[0002] Scalability, reconfigurability, and interchangeability are emerging trends in information processing systems. Hardware expansion allows for the rapid construction of information processing systems of varying scales, while reconfiguration enables existing hardware to perform different functions, resulting in completely different system forms. Reconfigurability is a crucial technology for achieving multi-functional integration, significantly expanding system utilization scenarios and reducing hardware costs. Furthermore, in large-scale information processing systems, the interchangeability of similar components is a particularly important requirement; therefore, information processing systems have a practical need for component versatility.

[0003] Information processing systems with heterogeneous architectures are difficult to dynamically configure using software. While single-board-level reconfiguration is relatively easy, and there are related research and engineering implementations in the field, how to efficiently achieve system-level scalability, reconfigurability, and interchangeability is an urgent engineering problem that needs to be solved. Summary of the Invention (a) Technical problems to be solved The technical problem to be solved by the present invention is how to provide a method and apparatus for scalable, reconfigurable and interchangeable information processing systems to solve the problem of system-level scalability, reconfigurability and interchangeability.

[0004] (II) Technical Solution To address the aforementioned technical problems, this invention proposes a scalable, reconfigurable, and interchangeable device for an information processing system, comprising: an FPGA-type platform chassis, a CPU-type platform chassis, a network switching board, and a rear-mounted board; FPGA-based platform chassis include: general-purpose signal processing boards that use FPGA as the main processor to perform signal processing; CPU-based platform chassis include: a general-purpose data processing board that uses the CPU as the main processor to perform data processing; at the same time, the CPU-based platform chassis also has reserved installation positions for network switching boards and rear-mounted boards. Network switching boards are used to achieve interconnection and interoperability of Gigabit Ethernet and to realize a fully switched high-speed network based on RapidIO. Gigabit Ethernet is used to transmit system reconfiguration commands, and RapidIO fully switched high-speed network is used to transmit system service layer data. General-purpose data processing boards are connected to network switching boards through Gigabit Ethernet and RapidIO. The rear-mounted board is used to implement fiber-to-RapidIO full switching; the FPGA platform chassis is connected to the rear-mounted board of the CPU platform chassis via fiber optic cable, and the rear-mounted board is connected to the network switching board via RapidIO. All boards comply with the VITA standard protocol, and the chassis number and slot number can be obtained from the VPX connector of all boards. All executable files of the same type of board in the current working mode are placed on the SATA disk, and the program executable files are named in the format of chassis number + slot number. The network address of the board is obtained automatically by power-on, and the IP address is bound to the chassis number and slot number of the current chassis where the board is located.

[0005] The present invention also provides a method for an information processing system to be scalable, reconfigurable, and interchangeable, the method comprising the following steps: S1. All boards meet the VITA standard protocol, and the chassis number and slot number are obtained from the VPX connector of all boards; S2. The board automatically obtains its IP address upon power-up, and this IP address is bound to the chassis number and slot number corresponding to the chassis where the board is located. S3. Place all executable files of the same type of board in the current working mode into the SATA disk. The program executable files should be named according to the chassis number + slot number. S4. Based on the processing capacity of the current information processing system, determine the number of fully switchable, scalable heterogeneous data processing hardware boards. If the number is insufficient, add the corresponding boards and then use fiber optic cables to extend the connection between the chassis.

[0006] (III) Beneficial Effects This invention proposes a scalable, reconfigurable, and interchangeable method and apparatus for information processing systems. This method enables the rapid construction of information processing systems with different modalities through software configuration of hardware. All boards within the apparatus can be updated and loaded simultaneously, significantly improving system reconfiguration efficiency compared to single-board updates in traditional solutions. The method allows for rapid connection of FPGA and CPU boards via fiber optic cables and rear-mounted boards, meeting the scalability requirements of large systems. By ensuring all boards comply with the VITA standard protocol, binding chassis and slot numbers via IP addresses, and placing all executable files for the same type of board in its current operating mode on a SATA disk, the method improves the versatility of FPGA and CPU boards, enabling arbitrary interchangeability of similar boards, reducing maintenance costs, and improving system reliability. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the hardware architecture of the general signal processing board described in this invention; Figure 2This is a schematic diagram of the hardware architecture of the general data processing board described in this invention; Figure 3 This is a schematic diagram of the hardware architecture of the rear insert board described in this invention; Figure 4 This is the fully switched, integrated heterogeneous processing architecture described in this invention; Figure 5 This is a reconstructed architecture for the information processing system described in this invention. Detailed Implementation

[0008] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0009] This invention belongs to the field of engineering implementation technology for information processing system expansion, reconstruction, and component interchangeability. It involves large-scale system reconstruction engineering implementation, board component generalization technology, and algorithm online update technology, which can meet the needs of reconfigurable system working mode, scalable system hardware resources, and interchangeability of similar boards.

[0010] The reconfigurable information processing system method proposed in this invention is applicable to the expansion and reconfiguration of large-scale systems. Large-scale signal processing may include multiple information processing chassis.

[0011] The present invention provides a scalable, reconfigurable and interchangeable device for an information processing system, the device comprising: an FPGA-type platform chassis, a CPU-type platform chassis, a network switching board, and a rear-mounted board; FPGA-based platform chassis include: general-purpose signal processing boards that use FPGA as the main processor to perform signal processing; CPU-based platform chassis include: a general-purpose data processing board that uses the CPU as the main processor to perform data processing; at the same time, the CPU-based platform chassis also has reserved installation positions for network switching boards and rear-mounted boards. Network switching boards are used to achieve interconnection and interoperability of Gigabit Ethernet and to realize a fully switched high-speed network based on RapidIO. Gigabit Ethernet is used to transmit system reconfiguration commands, and RapidIO fully switched high-speed network is used to transmit system service layer data. General-purpose data processing boards are connected to network switching boards through Gigabit Ethernet and RapidIO. The rear-mounted board is used to implement fiber-to-RapidIO full switching; the FPGA platform chassis is connected to the rear-mounted board of the CPU platform chassis via fiber optic cable, and the rear-mounted board is connected to the network switching board via RapidIO. All boards comply with the VITA standard protocol, and the chassis number and slot number can be obtained from the VPX connector of all boards. All executable files of the same type of board in the current working mode are placed on the SATA disk, and the program executable files are named in the format of chassis number + slot number. The network address of the board is obtained automatically by power-on, and the IP address is bound to the chassis number and slot number of the current chassis where the board is located.

[0012] Example 1: This invention provides a scalable, reconfigurable, and interchangeable device for an information processing system, wherein both the FPGA-type platform chassis and the CPU-type platform chassis include multiple information processing hardware components. The information processing hardware components of this invention include: a general-purpose signal processing board that uses an FPGA as the main processor and a general-purpose data processing board that uses a CPU as the main processor. The information processing system runs on the device of this invention.

[0013] The general-purpose signal processing board architecture designed in this invention, which uses an FPGA as the main processor, is as follows: Figure 1 As shown, it includes: two FPGA chips, one ZYNQ chip, and a SATA disk; The FPGA chip used is the XC7VX690T chip, or a chip with similar performance and hardware resources to the XC7VX690T model; ZYNQ chips use the XC7Z030 chip, or a chip with similar performance to the XC7Z030 chip; SATA drives must have a capacity of at least 512GB.

[0014] The general-purpose signal processing board adopts the standard VPX architecture. The ZYNQ chip's PS side has a gigabit network interface, and the PL side has an LVDS interface and a GTX high-speed interface. Each of the two FPGAs has 6 pairs of LVDS interfaces and 1 pair of GTX interfaces with the ZYNQ's PL side. The two FPGAs have 96 pairs of transceiver fiber optic connections. A schematic diagram of this general-purpose signal processing board is shown below. Figure 1 As shown. Two FPGAs are used to implement the main signal processing algorithms, and 96 pairs of transceiver optical fibers are used to transmit massive amounts of data from the information processing system, providing a high-bandwidth channel for the reconfigurability of the information processing system. The ZYNQ chip PL end reads the chassis number and slot number through the VPX connector. The ZYNQ chip PL end has a GTX high-speed interface and an LVDS interface with the two FPGAs; the ZYNQ chip PS end handles network data reception and transmission. A 512GB SATA disk is mounted on the PS end, which runs a Linux embedded system.

[0015] The architecture of the general-purpose data processing board designed in this invention, which uses the CPU as the main processor, is as follows: Figure 2As shown, the hardware resources consist of: two CPU processors, one FPGA chip, one MCU chip, and two SATA disks.

[0016] Two CPU processors are simultaneously connected to an FPGA chip via Local bus, UART, and I2C. Both CPU processors are connected to a network switching board via Gigabit Ethernet and RapidIO. Each CPU processor is connected to a SATA hard drive.

[0017] The board consists of two FT-1500A / 16 CPU processors, one JFM7K325T FPGA chip, and one TMS320F28335 MCU chip, all with a clock speed of 80MHz. External interfaces include 6 RS232 ports, 16 GPIO ports, and 2 Gigabit Ethernet ports. It uses two DDR3 channels, with each channel employing four 16-bit wide, 8Gb DDR3 chips to form a 64-bit bus width, resulting in a 4GB capacity per channel and a total of 16GB across all four channels.

[0018] This invention employs a fully switched network topology. A network switching card conforming to the VPX standard is inserted inside the CPU-based platform chassis. This card enables gigabit Ethernet interconnection and a fully switched high-speed network based on RapidIO. Gigabit Ethernet is used to transmit system reconfiguration commands, while the RapidIO fully switched high-speed network is used to transmit system service layer data. Figure 2 As shown, the two CPU processors are connected to the network switching board via Gigabit Ethernet and RapidIO.

[0019] To enhance the scalability of information processing systems, this invention designs a fiber-to-optical-to-RapidIO full-switch back-plug card, such as... Figure 3 As shown, this rear-mounted board completes the conversion from fiber optic protocol to RapidIO and data routing. It includes a main control chip and a 24-in-1 optical module. The main control chip is an XC7VX690T chip. The 24-in-1 optical module is used for fiber optic communication with general-purpose signal processing boards, supporting transmission rates of over 10Gbps. The main control chip connects to the optical module and the VPX connector. There are four 4XSRIO interfaces between the main control chip and the VPX connector to complete the interconnection of the general-purpose data processing board's RapidIO high-speed network. At the same time, this rear-mounted board has a gigabit Ethernet interface for dynamic configuration and control command communication.

[0020] Utilizing a fiber-to-RapidIO fully switched backplane, this invention innovatively proposes a fully switched, scalable heterogeneous data processing hardware architecture, such as... Figure 4As shown, optical fibers are used as the transmission medium between chassis, and RapidIO networks are used inside the chassis for massive data exchange. Currently, the hardware architecture can support the expansion of up to 48 chassis, which can meet the computing resources of ultra-large-scale information processing systems.

[0021] The above invention describes the basic hardware architecture of the entire information processing system. Based on this hardware architecture, a reconfigurable and interchangeable software process and method adapted to this hardware were invented. This invention proposes three requirements for the information processing system architecture. First, all boards proposed in this invention must meet the VITA 46.0 standard protocol, and all boards must be able to obtain their chassis number and slot number from the VPX connector. Second, this invention requires that all executable files of the same type of system-level boards in their current operating mode be placed on a SATA disk, and the executable files should be named according to the chassis number + slot number. Third, this invention requires that the network address of the boards automatically obtains its IP address upon power-on, and this IP address is bound to the chassis number and slot number corresponding to the chassis where the board is located.

[0022] To enable the information processing system to be reconfigured, the device of this invention also includes a display and control computer, which incorporates an algorithm resource library, algorithm decision-making and deployment scripts, and an FTP server. The algorithm resource library contains all executable files for different operating modes of the information processing system. These executable files must have unique names, named according to the operating mode + function. The system designer configures the algorithm decision-making and deployment scripts according to the operating modes of the information processing system. When the operating mode is changed on the display and control computer, the FTP server is used to send the executable file data to a SATA drive in a designated IP address and slot, according to the decision-making and deployment scripts. The information processing system reconfiguration architecture is shown below. Figure 5 As shown, this invention enables system mode reconstruction through configuration on the display and control computer. To ensure interchangeability between the two main types of processing boards in the information processing system, this invention provides designs for general-purpose signal processing boards and general-purpose data processing boards.

[0023] The general-purpose signal processing board uses the ZYNQ's PL (Plain Oldest Link) terminal to obtain the chassis number and slot number of the board. These chassis and slot numbers are unique identifiers within the information processing system. The PL terminal then sends these information to the ZYNQ's PS (Power Supply) terminal. The PS terminal processor reads the corresponding executable file from the SATA disk based on these unique chassis and slot numbers. This method satisfies the interchangeability requirements of general-purpose signal processing boards.

[0024] The general data processing board uses the FPGA chip inside the board to obtain the chassis number and slot number of the current board. The chassis number and slot number are unique identifiers in the information processing system. The FPGA sends the chassis number and slot number to the MCU chip. The MCU chip modifies the startup script of the general data processing board, and then the CPU processor is started by the FPGA to begin its work.

[0025] This method can satisfy the interchangeability of general data processing boards.

[0026] Example 2: This invention discloses a method for a scalable, reconfigurable, and interchangeable information processing system. The specific implementation steps include three parts: a scalable implementation method 1, a reconfigurable implementation method 2, and an interchangeable implementation method 3. The information processing system satisfies scalability, reconfigurability, and interchangeability, specifically including: S1. All boards comply with the VITA 46.0 standard protocol, and the chassis number and slot number can be obtained from the VPX connector of each board. Each chassis is assigned a unique chassis number and slot number as its physical address at the factory.

[0027] S2. This invention requires the board to automatically obtain an IP address upon power-up. This IP address is bound to the chassis number and slot number corresponding to the chassis where the board is located. Note: This IP address is bound to the chassis number and slot number, not to the board itself. This step prepares the board for reconfiguration.

[0028] S3. This invention requires all executable files of the same type of board in the current working mode to be placed on the SATA disk. The program executable files are named according to the chassis number + slot number.

[0029] In conjunction with S1-S3, the general-purpose signal processing board and the general-purpose data processing board perform the following operations, specifically, The general-purpose signal processing board uses the ZYNQ's PL terminal to obtain the chassis number and slot number of the current board. This chassis number and slot number have unique identification in the information processing system. The PL terminal sends the obtained chassis number and slot number to the ZYNQ's PS terminal. The PS terminal processor automatically obtains the IP address and retrieves all executable files of the same type of board in the current working mode from the display control computer and stores them on the SATA disk. Then, it reads the corresponding executable file from the SATA disk according to the unique chassis number and slot number.

[0030] The general-purpose data processing board uses the FPGA chip within the board to obtain the chassis number and slot number of the current board location. This chassis number and slot number are unique identifiers in the information processing system. The FPGA sends the chassis number and slot number to the CPU processor and MCU chip. The CPU processor automatically obtains the IP address and retrieves all executable files of the same type of board in the current working mode from the display and control computer and stores them on the SATA disk. Then, it reads the corresponding executable file from the SATA disk based on the unique chassis number and slot number. The MCU chip modifies the startup script of the general-purpose data processing board, and then the FPGA starts the CPU processor to begin its operation.

[0031] S4. Based on the processing capacity of the current information processing system, determine the number of fully switchable, scalable heterogeneous data processing hardware boards. If the number is insufficient, add the corresponding boards and extend the connection between the chassis using optical fibers.

[0032] When the display and control computer changes the working mode, it uses an FTP server to send the executable file data to the SATA disk in the specified IP chassis and slot according to the decision deployment script.

[0033] Beneficial effects: This invention proposes a scalable, reconfigurable, and interchangeable method and apparatus for information processing systems. This method enables the rapid construction of information processing systems with different modalities through software configuration of hardware. All boards within the apparatus can be updated and loaded simultaneously, significantly improving system reconfiguration efficiency compared to traditional single-board updates. The method allows for rapid connection of FPGA-type boards and CPU-type boards via optical fiber and a rear-mounted board, meeting the scalability requirements of large systems. This method improves the versatility of FPGA-type and CPU-type boards, enabling arbitrary interchangeability of similar boards, reducing maintenance costs, and improving system reliability.

[0034] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A scalable, reconfigurable, and interchangeable device for an information processing system, characterized in that, The device includes: an FPGA platform chassis, a CPU platform chassis, a network switching board, and a rear-mounted board; FPGA-based platform chassis include: general-purpose signal processing boards that use FPGA as the main processor to perform signal processing; CPU-based platform chassis include: a general-purpose data processing board that uses the CPU as the main processor to perform data processing; at the same time, the CPU-based platform chassis also has reserved installation positions for network switching boards and rear-mounted boards. Network switching boards are used to achieve interconnection and interoperability of Gigabit Ethernet and to realize a fully switched high-speed network based on RapidIO. Gigabit Ethernet is used to transmit system reconfiguration commands, and RapidIO fully switched high-speed network is used to transmit system service layer data. General-purpose data processing boards are connected to network switching boards through Gigabit Ethernet and RapidIO. The rear-mounted board is used to implement fiber-to-RapidIO full switching; the FPGA platform chassis is connected to the rear-mounted board of the CPU platform chassis via fiber optic cable, and the rear-mounted board is connected to the network switching board via RapidIO. All boards comply with the VITA standard protocol, and the chassis number and slot number can be obtained from the VPX connector of all boards. All executable files of the same type of board in the current working mode are placed on the SATA disk, and the program executable files are named in the format of chassis number + slot number. The network address of the board is obtained automatically by power-on, and the IP address is bound to the chassis number and slot number of the current chassis where the board is located.

2. The scalable, reconfigurable, and interchangeable device for the information processing system as described in claim 1, characterized in that, The general-purpose signal processing board includes: two FPGA chips, one ZYNQ chip, and a SATA disk; The general-purpose signal processing board adopts the standard VPX architecture; the ZYNQ chip's PS end has a gigabit network interface, and the PL end has an LVDS interface and a GTX high-speed interface; both FPGAs and the ZYNQ's PL end are equipped with LVSD interfaces and GTX high-speed interfaces, and both FPGAs have external transceiver optical fibers; the two FPGAs are used to implement signal processing algorithms, and the transceiver optical fibers are used to transmit massive amounts of data from the information processing system, providing a high-bandwidth channel for the reconfigurability of the information processing system; the ZYNQ chip's PL end completes the reading of the chassis number and slot number through the VPX connector, and the ZYNQ chip's PS end completes the receiving and sending of network data, with SATA disks mounted to the PS end.

3. The scalable, reconfigurable, and interchangeable device for the information processing system as described in claim 1, characterized in that, The general-purpose data processing board includes: two CPU processors, one FPGA chip, one MCU chip, and two SATA disks; Two CPU processors are simultaneously connected to an FPGA chip via Local bus, UART, and I2C. Both CPU processors are connected to a network switching board via Gigabit Ethernet and RapidIO. Each CPU processor is connected to a SATA hard drive.

4. The scalable, reconfigurable, and interchangeable device for the information processing system as described in claim 1, characterized in that, The rear-mount card is used to complete the conversion of fiber optic protocol to RapidIO and data routing. It includes a main control chip and a 24-in-1 optical module. The optical module is used for fiber optic communication with a general signal processing board. The main control chip connects the optical module and the VPX connector. There are 4 4XSRIO interfaces between the main control chip and the VPX connector for interconnection with the RapidIO high-speed network. At the same time, the rear-mount card has a gigabit Ethernet interface for dynamic configuration and control command communication.

5. The scalable, reconfigurable, and interchangeable apparatus for the information processing system as described in claim 1, characterized in that, Optical fiber is used as the transmission medium between chassis, and RapidIO network is used inside the chassis for the exchange of massive amounts of data.

6. The scalable, reconfigurable, and interchangeable apparatus for the information processing system as described in claim 1, characterized in that, The device also includes a display and control computer, which contains an algorithm resource library, algorithm decision deployment scripts, and an FTP server. The algorithm resource library contains all executable files for different working modes of the information processing system. Each executable file name is unique and is named according to the working mode + function. The algorithm decision deployment script is configured according to the working mode of the information processing system. When the working mode is changed on the display and control computer, the executable file data is sent to the SATA disk in the designated IP chassis and slot according to the decision deployment script via the FTP server.

7. The scalable, reconfigurable, and interchangeable apparatus for the information processing system as described in claim 6, characterized in that, The general-purpose signal processing board uses the ZYNQ's PL terminal to obtain the chassis number and slot number of the current board. This chassis number and slot number have unique identification in the information processing system. The PL terminal sends the obtained chassis number and slot number to the ZYNQ's PS terminal. The PS terminal processor reads the executable file corresponding to the SATA disk based on the unique chassis number and slot number.

8. The scalable, reconfigurable, and interchangeable apparatus for the information processing system as described in claim 6, characterized in that, The general data processing board uses the FPGA chip inside the board to obtain the chassis number and slot number of the current board. The chassis number and slot number are unique identifiers in the information processing system. The FPGA sends the chassis number and slot number to the MCU chip. The MCU chip modifies the startup script of the general data processing board, and then the FPGA starts the CPU processor to begin its work.

9. A method for making an information processing system based on the apparatus of any one of claims 1-8 scalable, reconfigurable, and interchangeable, characterized in that, The method includes the following steps: S1. All boards meet the VITA standard protocol, and the chassis number and slot number are obtained from the VPX connector of all boards; S2. The board automatically obtains its IP address upon power-up, and this IP address is bound to the chassis number and slot number corresponding to the chassis where the board is located. S3. Place all executable files of the same type of board in the current working mode into the SATA disk. The program executable files should be named according to the chassis number + slot number. S4. Based on the processing capacity of the current information processing system, determine the number of fully switchable, scalable heterogeneous data processing hardware boards. If the number is insufficient, add the corresponding boards and then use fiber optic cables to extend the connection between the chassis.

10. The scalable, reconfigurable, and interchangeable apparatus for the information processing system as described in claim 9, characterized in that, The general signal processing board uses the ZYNQ's PL terminal to obtain the chassis number and slot number of the current board. This chassis number and slot number have unique identification in the information processing system. The PL terminal sends the obtained chassis number and slot number to the ZYNQ's PS terminal. The PS terminal processor automatically obtains the IP address and retrieves all executable files of the same type of board in the current working mode from the display control computer and stores them on the SATA disk. Then, it reads the corresponding executable file from the SATA disk according to the unique chassis number and slot number. The general-purpose data processing board uses the FPGA chip within the board to obtain the chassis number and slot number of the current board location. This chassis number and slot number are unique identifiers in the information processing system. The FPGA sends the chassis number and slot number to the CPU processor and MCU chip. The CPU processor automatically obtains the IP address and retrieves all executable files of the same type of board in the current working mode from the display and control computer and stores them on the SATA disk. Then, it reads the corresponding executable file from the SATA disk based on the unique chassis number and slot number. The MCU chip modifies the startup script of the general-purpose data processing board, and then the FPGA starts the CPU processor to begin its operation.

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