Wafer chip defect detection method, device, equipment and medium

Abstract

The application relates to the technical field of chip defect identification, and discloses a wafer chip defect detection method, device, equipment and medium. In the method, a Mamba space modeling network is used, so that when a high-resolution original gray image of a wafer chip is processed, the calculation complexity is reduced from a square level of an existing method to a linear level, the inference speed is improved, and the demand of real-time detection of an industrial production line is met. The spatial propagation mechanism of the Mamba space modeling network effectively captures the spatial propagation characteristics of wafer chip defects, improves the identification accuracy and spatial consistency of systematic defects and continuous defects, the learnable spline base function of the KAN network enhances the interpretability of the feature transformation process, the decision basis of the detection result is transparent and traceable, and quality auditing and process improvement are facilitated.

Description

Technical Field

[0001] This application relates to the technical field of chip defect identification, and in particular to a method, apparatus, equipment and medium for detecting defects in wafer chips. Background Technology

[0002] Wafer chips are the key substrate for integrated circuit manufacturing, and their surface quality directly affects the chip's electrical performance, reliability, and production yield. During wafer manufacturing, multiple processes such as photolithography, etching, thin film deposition, and chemical mechanical polishing can easily introduce surface defects such as particle contamination, scratches, pattern breaks, and residues. If these defects are not detected and removed in a timely manner, they can lead to large-scale device failures, causing significant economic losses. Therefore, establishing an efficient, stable, and accurate automated wafer defect detection system has become a crucial step in the semiconductor manufacturing process.

[0003] Currently, wafer defect detection technologies are mainly divided into two categories: traditional image processing methods and deep learning-based intelligent detection methods. Traditional image processing methods rely on manually set thresholds and rules, combined with grayscale segmentation, edge detection (such as Sobel and Canny operators), morphological operations, and other techniques for defect identification. However, they are highly dependent on manually set parameters and are very sensitive to changes in imaging lighting conditions, surface texture complexity, and environmental noise. This results in large fluctuations in detection results under different batches or complex process conditions, poor generalization ability, and a tendency to produce false positives and false negatives.

[0004] With the development of deep learning technology, defect detection methods based on convolutional neural networks (CNNs) have gradually become mainstream. These methods construct multi-layer feature extraction networks and train classifiers on large-scale labeled samples to achieve end-to-end automatic defect identification. Compared with traditional methods, the aforementioned deep learning-based detection methods have achieved significant improvements in detection accuracy, but certain limitations remain. First, many methods employ standard convolutional networks or Transformer architectures. When processing high-resolution wafer images (typically containing hundreds to thousands of chip cells), the computational complexity increases quadratically, resulting in slow inference speeds and high memory consumption, making it difficult to meet the real-time inspection needs of production lines. Second, most existing methods process each chip cell independently, failing to fully utilize the spatial propagation characteristics of defects in the wafer manufacturing process—the same process anomaly may lead to contiguous defects in adjacent or specific areas of chips; ignoring this spatial correlation may reduce the accuracy and consistency of detection. Third, the "black box" nature of deep neural networks makes the detection results lack interpretability, making it difficult to provide clear evidence for process improvement and quality auditing, which places high demands on traceability in the semiconductor manufacturing environment.

[0005] In summary, existing wafer defect detection technologies struggle to balance computational complexity, spatial correlation modeling, and interpretability. These issues have become bottlenecks in improving detection accuracy and robustness in actual semiconductor manufacturing. Summary of the Invention

[0006] This application provides a method, apparatus, device, and medium for detecting defects in wafer chips. The method utilizes the Mamba spatial modeling network to reduce the computational complexity from quadratic to linear levels when processing high-resolution raw grayscale images of wafer chips, thereby improving inference speed and meeting the real-time detection needs of industrial production lines. The spatial propagation mechanism of the Mamba spatial modeling network effectively captures the spatial propagation characteristics of wafer chip defects, improving the accuracy and spatial consistency of identifying systematic and contiguous defects. Furthermore, the learnable spline basis functions of the KAN network enhance the interpretability of the feature transformation process, making the decision-making basis for the detection results transparent and traceable, facilitating quality auditing and process improvement.

[0007] In a first aspect, embodiments of this application provide a method for detecting defects in a wafer chip, including:

[0008] Obtain the original grayscale image of the wafer;

[0009] The original grayscale image is sequentially subjected to contrast enhancement, Gaussian filtering, sharpening enhancement, and zero-mean normalization to obtain the preprocessed image.

[0010] The preprocessed image is sequentially subjected to chip center localization, geometric correction, and ROI extraction to obtain all chip regions; all chip regions are sequence encoded to obtain chip sequence indexes; and position encoding is performed based on the chip sequence indexes to obtain position encoding vectors.

[0011] Based on the chip region and the location encoding vector, a KAN network is used to locally encode the chip region to obtain the vectorized features of the chip.

[0012] Based on the chip feature sequence composed of vectorized features of all the chips, the Mamba output features are determined using the Mamba spatial modeling network.

[0013] The vectorized features of the chip and the output features of Mamba are fused to obtain the final fused features;

[0014] Based on the final fusion features, the chip defect category corresponding to the chip region is determined.

[0015] In some embodiments, the KAN network includes multiple KAN layers; the step of using the KAN network to locally encode the chip region based on the chip region and the location encoding vector to obtain the vectorized features of the chip includes:

[0016] Initial feature mapping is performed on the chip region to generate an initial feature vector;

[0017] The initial feature vector is input into a multi-layer KAN layer to perform nonlinear transformation using spline basis functions to obtain the corresponding output vector for each layer, and the output vector is then normalized.

[0018] The result of normalizing the output vector corresponding to the last layer is determined as the vectorized feature.

[0019] In some embodiments, the step of determining the Mamba output features using a Mamba spatial modeling network based on the chip feature sequence composed of vectorized features of all the chips includes:

[0020] The vectorized features of the chip are mapped to SSM input vectors through linear projection;

[0021] Based on the SSM input vector, the selectivity coefficient vector of the chip is generated;

[0022] Based on the selectivity coefficient, the input matrix corresponding to the chip is generated, and the output matrix is ​​determined;

[0023] Based on the vectorization features of the chip, a time step is generated; based on the input matrix, output matrix and time step, discretization calculation is performed to obtain the discretized state transition matrix and the discretized input matrix;

[0024] Based on the discretized state transition matrix and the discretized input matrix, state recursion is performed to obtain the spatial relationship between all chips;

[0025] A bidirectional Mamba spatial modeling network is used to perform reverse sequence propagation to obtain the SSM output of the chip;

[0026] Based on the SSM output of the chip, multi-head parallel processing and residual enhancement are performed to obtain the Mamba output characteristics of the chip.

[0027] In some embodiments, the step of fusing the vectorized features of the chip and the Mamba output features to obtain the final fused features includes:

[0028] The vectorized features of the chip and the Mamba output features are linearly mapped to obtain the aligned vectorized features and aligned Mamba output features.

[0029] Based on the aligned vectorized features and aligned Mamba output features, the gate weight vector is determined;

[0030] The aligned vectorized features and the aligned Mamba output features are weighted and fused based on the gated weight vector to obtain the fused features;

[0031] The fused features are normalized and nonlinearly activated to obtain the final fused features.

[0032] In some embodiments, the step of determining the chip defect category corresponding to the chip region based on the final fusion feature includes:

[0033] The final fused features are mapped to the category space through a linear transformation to obtain the unnormalized scores for different defect categories;

[0034] Based on the unnormalized scores of the chip in different defect categories, the category probability of different defect categories is determined;

[0035] The defect category corresponding to the highest probability of the aforementioned category is determined as the final defect category of the chip.

[0036] In some embodiments, the method further includes:

[0037] Based on the contribution of each feature dimension of the final fused feature, the contribution value of the feature dimension to the defect category is determined;

[0038] Back projection is performed based on the contribution value of the defect category to generate a region map of defects inside the chip.

[0039] In some embodiments, the method further includes:

[0040] For a defective chip, the gradient of the maximum class probability used to determine the final defect category with respect to the input features of each of the KAN layers is calculated.

[0041] Each KAN layer is sorted according to the absolute value of its gradient, and the top K neurons that have the greatest impact on defect determination are identified.

[0042] The input-output mapping relationship of the neuron is obtained by combining the spline basis function coefficients and spline basis functions corresponding to the first K neurons.

[0043] By utilizing the input-output mapping relationship of the neurons, a chip-level attribution heatmap is generated.

[0044] Secondly, embodiments of this application also provide a wafer chip defect detection device, comprising:

[0045] The acquisition unit is used to acquire the original grayscale image of the wafer;

[0046] The preprocessing unit is used to sequentially perform contrast enhancement, Gaussian filtering, sharpening enhancement and zero-mean normalization on the original grayscale image to obtain the preprocessed image;

[0047] The extraction unit is used to sequentially perform chip center localization, geometric correction, and ROI extraction on the preprocessed image to obtain all chip regions; perform sequence encoding on all the chip regions to obtain chip sequence indexes; and perform position encoding based on the chip sequence indexes to obtain position encoding vectors.

[0048] A local coding unit is used to locally encode the chip region based on the chip region and the position coding vector using a KAN network to obtain the vectorized features of the chip.

[0049] The first determining unit is used to determine the Mamba output features based on the chip feature sequence composed of vectorized features of all the chips, using the Mamba spatial modeling network.

[0050] A fusion unit is used to fuse the vectorized features of the chip and the output features of Mamba to obtain the final fused features;

[0051] The second determining unit is used to determine the chip defect category corresponding to the chip region based on the final fusion features.

[0052] Thirdly, embodiments of this application also provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the wafer chip defect detection method described above.

[0053] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the wafer chip defect detection method.

[0054] The above embodiments provide a wafer chip defect detection method, apparatus, device, and medium. This method uses a Mamba spatial modeling network to reduce the computational complexity from quadratic to linear levels when processing high-resolution raw grayscale images of wafer chips, thereby improving inference speed and meeting the real-time detection needs of industrial production lines. The spatial propagation mechanism of the Mamba spatial modeling network effectively captures the spatial propagation characteristics of wafer chip defects, improving the accuracy and spatial consistency of identifying systematic and contiguous defects. The learnable spline basis functions of the KAN network enhance the interpretability of the feature transformation process, making the decision-making basis for the detection results transparent and traceable, facilitating quality auditing and process improvement. Attached Figure Description

[0055] Figure 1 An exemplary flowchart of a wafer chip defect detection method provided according to some embodiments is shown;

[0056] Figure 2 An exemplary schematic diagram of a raw grayscale image of a wafer provided according to some embodiments is shown;

[0057] Figure 3 An exemplary schematic diagram of a chip region in a corrected image is shown;

[0058] Figure 4 An exemplary schematic diagram of a wafer chip defect detection device provided according to some embodiments is shown. Detailed Implementation

[0059] To make the objectives and implementation methods of this application clearer, the exemplary implementation methods of this application will be clearly and completely described below with reference to the accompanying drawings of the exemplary embodiments of this application. Obviously, the exemplary embodiments described are only some embodiments of this application, and not all embodiments.

[0060] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0061] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.

[0062] The terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device that includes a range of components is not necessarily limited to all of the components that are clearly listed, but may include other components that are not clearly listed or that are inherent to such product or device.

[0063] To address the aforementioned technical problems, embodiments of this application provide a wafer chip defect detection method, apparatus, device, and medium. This method utilizes a Mamba spatial modeling network to reduce the computational complexity from quadratic to linear levels when processing high-resolution raw grayscale images of wafer chips, thereby improving inference speed and meeting the real-time detection needs of industrial production lines. The spatial propagation mechanism of the Mamba spatial modeling network effectively captures the spatial propagation characteristics of wafer chip defects, improving the accuracy and spatial consistency of identifying systematic and contiguous defects. Furthermore, the learnable spline basis functions of the KAN network enhance the interpretability of the feature transformation process, making the decision-making basis for the detection results transparent and traceable, facilitating quality auditing and process improvement.

[0064] Figure 1 A flowchart of a wafer chip defect detection method provided according to some embodiments is shown, the method including S100-S700.

[0065] S100: Obtain the raw grayscale image of the wafer. For example, such as... Figure 2 As shown, Figure 2 The image displayed is a raw grayscale image of the wafer.

[0066] S200. The original grayscale image is sequentially subjected to contrast enhancement, Gaussian filtering, sharpening enhancement, and zero-mean normalization to obtain the preprocessed image.

[0067] In this embodiment, the original grayscale image is sequentially subjected to contrast enhancement, Gaussian filtering, sharpening enhancement, and zero-mean normalization. Correspondingly, brightness equalization, noise suppression, edge enhancement, and grayscale normalization can be achieved on the original grayscale image to obtain a stable input suitable for subsequent chip segmentation and feature extraction.

[0068] In this embodiment, contrast enhancement can be achieved using the following steps:

[0069] The gray values ​​of the pixels in the original grayscale image are denoted as... x and y represent the column and row coordinates of a pixel in a two-dimensional coordinate system, respectively, with the origin of the two-dimensional coordinate system being the top-left corner of the image. The image is divided into... Each sub-block, among which This represents the number of sub-blocks in the row direction. Let be the number of sub-blocks in the column direction, and perform histogram equalization independently on each sub-block. Let the gray level of the pixels within the sub-block be denoted as . The grayscale histogram count is , The number of pixels with gray level i within the identifier sub-block;

[0070] The normalized cumulative distribution function (CDF) within a sub-block is defined as:

[0071] ;

[0072] in, It is a grayscale index, with a value range of 0 ≤ p ≤ i; grayscale level is Histogram count; number of pixels within a sub-block: ,in and These are the width and height of the sub-block, respectively. grayscale The corresponding normalized cumulative distribution function value.

[0073] The grayscale value after equalization is: ;

[0074] in, This represents the equalized gray value corresponding to gray level i. This represents the number of gray levels.

[0075] In some embodiments, to avoid amplifying local noise, the histogram is contrast-limited. Specifically, when the grayscale histogram count... If the limit is exceeded, the excess portion will be redistributed to all gray levels in a uniform proportion. Then determine. and By employing the contrast limiting process described above, local noise amplification can be effectively suppressed, allowing the final preprocessed image to maintain visual quality while enhancing contrast.

[0076] In some embodiments, bilinear interpolation is used to fuse adjacent sub-blocks to update the equalized grayscale values ​​and ensure the continuity of brightness changes across the entire image.

[0077] In this embodiment, after performing contrast enhancement processing on the original grayscale image, the grayscale value of each pixel in the original grayscale image can be changed to the grayscale value after equalization. At this time, the original grayscale image is converted into a contrast-enhanced image, and the grayscale value of the pixel in the contrast-enhanced image is denoted as... .

[0078] In this embodiment, Gaussian filtering can suppress high-frequency noise in the contrast-enhanced image while preserving the main contour structure. In this embodiment, a Gaussian filter is used to smooth the contrast-enhanced image, resulting in a Gaussian-filtered image. The grayscale values ​​of the pixels in the Gaussian-filtered image are denoted as... .

[0079] The Gaussian filtering result is expressed as:

[0080] ;

[0081] in, where is the grayscale value of a pixel in the Gaussian-filtered image; x and y represent the column and row coordinates of the pixel in the two-dimensional coordinate system, respectively, with values ​​ranging from 1 ≤ x ≤ W to 1 ≤ y ≤ H; W and H are the width and height of the image after contrast enhancement, respectively; u and v are the local offsets of the Gaussian kernel in the column and row directions, respectively, that is, the offsets of the weight positions within the kernel relative to the pixels, where u and v are integer values, satisfying -r ≤ u ≤ r and -r ≤ v ≤ r; r is the radius of the Gaussian filter kernel, which can be set according to the image noise level, for example, it can be set to . scope; The two-dimensional Gaussian kernel function is defined as follows: ;in, >0 represents the Gaussian kernel standard deviation;

[0082] This represents the grayscale value of a pixel in the contrast-enhanced image. In the contrast-enhanced image, the offset in the column direction relative to pixel (x, y) , line direction offset The gray values ​​of the neighboring pixels; the traversal range is u,v∈{-r,-r+1,…,r}; and it satisfies the normalization condition:

[0083] .

[0084] In some embodiments, before performing Gaussian filtering on the contrast-enhanced image, a mirror-filling method is used for augmentation to avoid artifacts at the edges caused by the Gaussian filtering convolution operation.

[0085] In this embodiment, to enhance edge gradients and local texture features, Laplacian enhancement can be added after Gaussian filtering to sharpen the image. This processing can highlight the texture and edge structure in the wafer image, which is helpful for subsequent feature extraction.

[0086] A sharpened image can be represented as:

[0087] ;

[0088] in, This represents the grayscale value of a pixel in the sharpened image. represents the grayscale value of a pixel in the Gaussian-filtered image; To sharpen the intensity coefficient and control the extent of Laplacian enhancement, we can take... ; This is the discrete Laplacian value calculated for each pixel in the Gaussian-filtered image.

[0089] The Laplace operator is defined as:

[0090] ;

[0091] Where s and t are the column direction component and row direction component of the eight-neighbor offset, respectively, and all possible values ​​of s and t are given by the set enumerate; It is an eight-neighbor offset set, containing offset pairs in eight directions around the center pixel;

[0092] ;

[0093] In some embodiments, to ensure the stability of edge pixels, symmetric expansion or mirror filling can be used to perform boundary processing on the Gaussian filtered image before calculating the Laplacian value.

[0094] In this embodiment of the application, in order to eliminate the overall brightness difference caused by different batches and different exposure conditions, zero-mean normalization is performed on the sharpened and enhanced image.

[0095] Normalization is defined as follows:

[0096] ;

[0097] in, The gray values ​​of pixels in the image after zero-mean normalization, i.e., the preprocessed image; σ represents the grayscale value of a pixel in the sharpened image; μ is the mean of all pixels in the image based on the sharpened image statistics; σ is the standard deviation of all pixels in the image based on the sharpened image statistics. To prevent division by zero, the constant can be taken as... Magnitude;

[0098] ;

[0099] ;

[0100] In this embodiment, the zero-mean normalized image has a stable brightness distribution, which is used for chip region analysis in the next step and helps to improve the robustness of subsequent modules to the input.

[0101] S300: Perform chip center localization, geometric correction, and ROI extraction sequentially on the preprocessed image to obtain all chip regions; perform sequence encoding on all chip regions to obtain chip sequence indexes; perform position encoding based on the chip sequence indexes to obtain position encoding vectors.

[0102] In this embodiment, the chip center positioning step includes: obtaining the layout structure of the chip in the wafer; and determining the chip center coordinates in the preprocessed image based on the layout structure of the chip in the wafer. Specifically, the step of obtaining the layout structure of the chip in the wafer includes: determining the layout structure of the chip in the wafer based on wafer mask design or equipment calibration data. In this embodiment, the wafer mask design or equipment calibration data refers to wafer data from the design stage.

[0103] It should be noted that a wafer contains several chips. The layout structure of the chips on a wafer includes the geometric layout parameters of the chips on the wafer, specifically including the chip width. ,high , number of rows Column number and the center coordinates of the first chip .

[0104] The chip center distance can be expressed as:

[0105] ;

[0106] ;

[0107] in, The spacing between the chip centers along the column direction; The column spacing between chips; The spacing between the chip centers in the row direction; This refers to the row spacing between chips.

[0108] In the first line, number The coordinates of the chip center in the column can be represented as:

[0109] ;

[0110] ;

[0111] in, In the first line, number The column coordinates in the chip center coordinates; For being in the first line, number The row coordinates in the chip center coordinates of the column.

[0112] In some embodiments, the method further includes determining whether the chip falls completely within the effective range of the wafer based on the chip center coordinates, chip width, and chip height; if it does not fall completely within the effective range of the wafer, the chip is determined to be an invalid chip and deleted from the preprocessed image.

[0113] In one example, the step of determining whether the chip falls completely within the effective range of the wafer based on the chip center coordinates, chip width, and chip height may include:

[0114] Determine the distances from the four vertices of the chip to the center of the wafer. If all four distances are less than the wafer radius, the chip is considered to be completely within the valid range. If at least one of the four vertices is more than the wafer radius, the chip is considered not to be completely within the wafer's valid range.

[0115] In some embodiments, the method further includes: determining whether there is rotation and / or translation between the chip layout structure in the wafer and the preprocessed image; if there is rotation and / or translation, determining an affine transformation matrix based on a template matching method or a Hough transform method; and correcting the preprocessed image based on the affine transformation matrix to obtain a corrected image.

[0116] In this embodiment of the application, the corrected image is:

[0117] ;

[0118] in, The grayscale values ​​of pixels in the corrected image; It is the affine transformation matrix; The image is after preprocessing; The rotation angle; The translation amount is in the column direction. This represents the translation amount in the row direction.

[0119] In this way, global geometric correction is performed on the processed image, and ROI extraction can be performed on the corrected image to improve the accuracy of chip positioning.

[0120] In this embodiment of the application, ROI extraction is performed on the corrected image to obtain all chip regions in the corrected image. Figure 3 An exemplary schematic diagram of a chip region in a corrected image is shown. Figure 3 It includes 40 chip regions.

[0121] ;

[0122] in, For the first line, number The chip area corresponding to the chip in the column; It refers to the range of column coordinates from the left boundary coordinate to the right boundary coordinate of the chip region in the column direction; It refers to the range of row coordinates from the upper boundary coordinate to the lower boundary coordinate of the chip region in the row direction; This refers to the image within the row and column coordinate ranges of the corrected image, i.e., the chip area.

[0123] In this embodiment of the application, the step of sequentially encoding all chip regions to obtain a chip sequence includes: converting a two-dimensional chip array composed of all the chip regions into a one-dimensional sequence index according to a preset strategy. This facilitates the subsequent construction and processing of Mamba spatial modeling networks.

[0124] Each element of the two-dimensional chip array corresponds to a chip, which is indexed by row. and column indexes Composed of two-dimensional coordinates express.

[0125] In this embodiment of the application, the preset strategy can be one of the following three scanning strategies.

[0126] The first scanning strategy is row-first serialization, specifically:

[0127] ;

[0128] Where k is a one-dimensional sequence index, derived from two-dimensional coordinates. Mapped to obtain; , ; For column numbers.

[0129] The second scanning strategy is column-first serialization, specifically:

[0130] ;

[0131] Where k is a one-dimensional sequence index, derived from two-dimensional coordinates. Mapped to obtain; , ; The number of rows.

[0132] The third scanning strategy is other serialization, specifically: to enhance spatial structure alignment, a diagonal sequence, serpentine sequence, or circular sequence can be selected based on prior information about the spatial distribution of defects, thereby enhancing the model's ability to express spatial structure. The prior information referred to here is empirical knowledge about the spatial distribution patterns of defects on the wafer known before model training. For example, if historical data shows that defects are mainly distributed in a ring shape along the wafer edge, a circular sequence is preferable to ensure that adjacent sequence elements are also spatially adjacent; if defects mainly propagate in a strip-like pattern along a certain direction, row-first or column-first priority better preserves the continuity of that direction; if the defect distribution has no obvious directional pattern, row-first or column-first priority is sufficient.

[0133] This application does not limit the specific scanning strategy, but still uses the above-mentioned row priority and column priority as the preferred embodiments.

[0134] In this embodiment of the application, the step of performing position encoding based on the chip sequence index to obtain a position encoding vector includes: performing position encoding based on the chip sequence index using a standard sine-cosine position encoding method to obtain a position encoding vector.

[0135] In this embodiment of the application, in order to preserve the spatial location information of the chip in the wafer, a one-dimensional sequence index is used. The standard sine-cosine position coding method is used to map the position code to a continuous position code, which is the position code vector.

[0136] The standard sine-cosine position encoding method is as follows:

[0137] ;

[0138] in, For the first The second position encoding vector of the chip One component; For the first The second position encoding vector of the chip +1 component; The total dimension of the positional encoding vector is even; 2 Even-numbered dimensions (0th, 2nd, 4th, ...) are represented by the sine function; 2 +1 indicates an odd-numbered dimension (1st, 3rd, 5th, ... dimension), which corresponds to the use of the cosine function; For indexes of dimension pairs, , each pair (2 ,2 +1) Shares the same frequency base .

[0139] PE(k) is the position encoding vector. (Its dimensions are given by the sine / cosine formula above, and it is a fixed vector that is independent of the chip content and is determined only by the sequence position k, used to inject the spatial position information of each chip on the wafer into the model.) It can be compared with the initial feature vector of the kth chip. Add or splice them together to enhance the Mamba spatial modeling network's ability to express spatial structures.

[0140] It should be noted that the dimension of the initial feature vector is the same as... Consistency or alignment after concatenation: Specifically, consistency is required when adding to the initial feature vector, and alignment is required after concatenation when concatenating with the initial feature vector.

[0141] In this embodiment, through preprocessing in S200 and chip region serialization in S300, wafer images from different batches, different acquisition devices, or different orientation conditions can be aligned to a consistent reference coordinate system, making the input distribution more stable and providing a reliable foundation for subsequent feature encoding. This standardized input process is well-adapted to situations where edge regions are susceptible to illumination fluctuations and the noise distribution in the central region is uneven.

[0142] S400. Based on the chip region and the position encoding vector, a KAN network is used to locally encode the chip region to obtain the vectorized features of the chip.

[0143] In this embodiment of the application, the purpose of step S400 is to perform local encoding on the image of each chip region, extract interpretable and stable high-dimensional features such as texture, pattern, and brightness structure, and obtain an interpretable vectorized feature representation.

[0144] In some embodiments, the KAN network includes multiple KAN layers; the step of using the KAN network to locally encode the chip region based on the chip region and the location encoding vector to obtain the vectorized features of the chip includes:

[0145] Initial feature mapping is performed on the chip region to generate an initial feature vector;

[0146] In this embodiment of the application, the chip area Performing initial feature mapping involves inputting chip regions into shallow convolutional or linear mapping structures to generate initial feature vectors.

[0147] The initial feature vector can be represented as:

[0148] ;

[0149] in, For the first The initial feature vector of each chip; This is the feature dimension of layer 0 (the input layer of the KAN network), which is the dimension of the initial feature vector. for 3D real space.

[0150] The position encoding vector and the initial feature vector are concatenated to update the initial feature vector.

[0151] The initial feature vector is input into a multi-layer KAN layer to perform nonlinear transformation using spline basis functions to obtain the corresponding output vector for each layer, and the output vector is then normalized.

[0152] In this embodiment of the application, the connection between each pair of adjacent nodes in each layer of the multi-layer KAN layer is replaced by a B-spline basis function (spline basis function) instead of scalar weights.

[0153] In this embodiment, the Kolmogorov–Arnold network (KAN) is used to construct a nonlinear mapping through B-spline basis functions, replacing the activation function in the traditional neural network, in order to improve interpretability and local function fitting ability.

[0154] For the Layers, feature dimensions With input node Its output features are defined as:

[0155] ;

[0156] in, For the first The first feature vector output by the layer There are 1 component; e is the dimension index of the output feature; For the layer index of the KAN network; For the first The feature dimension of the layer; For the first The feature dimension of the layer; For the first In the layer, connect the first The linear mapping weights from the input nodes to the e-th output node; For the first The first layer outputs the feature vector. One portion, When equal to 1, The first eigenvector of the initial feature vector There are 1 component, and the corresponding dimension is 1. ; The index of the spline basis functions is m=1,2,…,M; This represents the total number of spline basis functions, which is set according to the task, for example, it can be 8 or 16; For the first In the layer, connect the first The coefficients of the m-th spline basis function from the e-th input node to the e-th output node; For the first indivual order spline basis functions; The order of the spline, for example, using cubic spline basis functions, i.e. .

[0157] In this embodiment, the Cox-deBoor recursive formula is used to calculate the spline basis functions. Its zeroth-order basis function is:

[0158] ;

[0159] in, For the first Defined at the interval of each node B-spline basis functions of order B; For the node sequence Each node value can be generated using an equidistant or learnable method; For the node sequence Each node value;

[0160] Higher-order basis functions are passed through:

[0161] ;

[0162] in, It is the first Defined at the interval of each node B-spline basis functions of order B can be derived from this. and The meaning; For the value of the b-th node, given the node sequence { , ,…, Given, it must satisfy the non-decreasing condition. ≤ The zero-order basis formula [ , () represents the interval of the m-th node, when the input x falls within this interval. =1, otherwise 0; in higher-order recursive formulas , These are the normalized distance weights, and and Correspondingly, when the denominator is zero, the term is taken as 0 according to convention (Cox-deBoor division rule).

[0163] In this embodiment of the application, since each dimension of the KAN network output is composed of several spline basis functions Weighted combination (i.e.) This mechanism, derived from the analysis of the shape and coefficient changes of each basis function, traces the mapping relationship between input and output features. This allows the influence of features such as texture variations and brightness structures in the chip region on high-dimensional space to be clearly presented, facilitating the generation of defect attribution maps in subsequent modules.

[0164] In this embodiment, the introduction of spline basis functions enables each feature dimension to have a visual mapping relationship in the input domain, which is helpful for subsequent defect attribution and interpretability analysis.

[0165] The result of normalizing the output vector corresponding to the last layer is determined as the vectorized feature.

[0166] In this embodiment of the application, to avoid excessive differences in feature distribution between different levels, layer normalization can be performed on the output of each layer. The normalization process of a layer can be represented as:

[0167] ;

[0168] ;

[0169] ;

[0170] in, For the first The result after layer normalization; For the first Feature vectors output by the layer; For the first Layer feature vectors in The mean of each component; For the first Layer feature vectors in Standard deviation of each component; To prevent division by zero of extremely small constants; For the first The feature dimension of the layer.

[0171] In some embodiments, the normalized result can also be standardized and subjected to affine transformation:

[0172] ;

[0173] ;

[0174] in, For the first The first layer outputs the feature vector. One component; This is the final output value after the learnable affine transformation; For the first Layer The learnable scaling parameters corresponding to the dimension (initialization) ); For the first Layer The learnable translation parameters corresponding to the dimension (initialization) ).

[0175] In this embodiment of the application, after... After layer KAN encoding, the first The vectorized features of a chip can be represented as:

[0176] ;

[0177] in, For the first The local feature vector of a chip, i.e. the vectorized features of the chip; For the first Each chip passed through The feature vectors after layer KAN encoding and layer normalization; D is the dimension of the vectorized features (equal to...). ).

[0178] In this embodiment, the KAN network is used to capture local texture, edge, and fine structural changes in the chip while maintaining model compactness, enabling more explicit representation of point-like, line-like, and small-scale diffusion defects. The structure of the differentiable spline basis functions allows the model to maintain a stable response when facing features with small defects or approximate noise, which helps to improve the quality of local feature representation.

[0179] S500: Based on the chip feature sequence composed of vectorized features of all the chips, the Mamba (Selective SSM) spatial modeling network is used to determine the Mamba output features.

[0180] In this embodiment, step S500 performs spatial dependency modeling on the chip feature sequence composed of vectorized features of each chip to capture defect patterns within the wafer. Step S500 is completed by the Mamba spatial modeling network module.

[0181] In this embodiment, the Mamba spatial modeling network can establish dependencies on long chip feature sequences, enabling the spatial consistency between adjacent chips on the wafer, defect aggregation patterns in local areas, and overall center-edge variation trends to be comprehensively expressed in a unified state space. Later, through the introduction of bidirectional propagation and a multi-head structure, the model exhibits a more balanced modeling capability for spatial variations in different directions, making it suitable for handling various patterns such as process anomaly propagation, repetitive defects, and overall anomalies.

[0182] In some embodiments, the step of determining the Mamba output features using a Mamba spatial modeling network based on the chip feature sequence composed of vectorized features of all the chips includes:

[0183] The vectorized features of the chip are mapped to SSM input vectors through linear projection.

[0184] In this embodiment, the basic dynamic structure of the selective state-space model can be a continuous-time state-space model, which can effectively model the dependencies of long sequences, and takes the form of:

[0185] ;

[0186] ;

[0187] Among them, h( () represents the continuous-time hidden state vector. ; It is a continuous-time variable; Here is the state transition matrix. ; For the input projection matrix, ; For continuous-time input vectors, ; For continuous time output; To output the projection matrix ; , and All are learnable matrices; To hide the state dimension; Input dimensions for SSM.

[0188] In this embodiment of the application, the vectorized features of the chip can be... Projected as SSM input vector:

[0189] ;

[0190] ;

[0191] in, For the first SSM input vectors of each chip; For the input projection matrix, You can choose according to the needs of the task. Size; ∈ , where is the corresponding bias; d is the input dimension of the SSM.

[0192] Based on the SSM input vector, the selectivity coefficient vector of the chip is generated.

[0193] In this embodiment of the application, a selectivity coefficient is introduced to adaptively adjust the model dynamic parameters according to different chip locations and local structures:

[0194] ;

[0195] Where s(k) is the selectivity coefficient vector of the k-th chip; For learnable projection matrices, ; For the first Vectorized features of each chip; For the selectivity coefficient bias, ∈ ; Sigmoid(·) is the Sigmoid activation function, with an output range of (0,1).

[0196] Based on the selectivity coefficient, the input matrix corresponding to the chip is generated, and the output matrix is ​​determined.

[0197] Input projection matrix Scaling by the selectivity coefficient vector generates the k-th input matrix:

[0198] ;

[0199] in, Let be the input matrix corresponding to the k-th chip. Diag(s(k)) is based on A diagonal matrix with diagonal elements. .

[0200] The output matrix can be defined as:

[0201] ;

[0202] in, This is the output matrix of the k-th chip; The projection matrix is ​​the output matrix. This is used to bias the output matrix.

[0203] In this embodiment, the structure of the input matrix and the output matrix can be adapted to the characteristics of different chip regions, thereby improving the model's ability to model spatial variations.

[0204] Based on the vectorization features of the chip, a time step is generated; based on the input matrix, output matrix, and time step, discretization calculation is performed to obtain the discretized state transition matrix. and the discretized input matrix .

[0205] In this embodiment, the time step is generated based on the vectorized features of the chip:

[0206]

[0207] , The time step is the k-th chip; The time step projection vector (learnable projection vector). ; The time step is the bias; Softplus(·) is the Softplus activation function;

[0208] In this embodiment of the application, the continuous model is discretized using zero-order hold (ZOH) to obtain:

[0209]

[0210] ;

[0211] in:

[0212]

[0213]

[0214] in, Let be the hidden state vector of the k-th chip; This is the discretized state transition matrix; For the kth The hidden state of a chip; The input matrix is ​​the discretized form. Let be the SSM input vector of the k-th chip; This is the SSM output of the k-th chip; This is the output matrix of the k-th chip; The time step is the k-th chip; It is a continuous state transition matrix; Let be an N×N identity matrix; exp(·) is the matrix exponent.

[0215] when When the value is small, Taylor expansion can be used for approximate calculation. :

[0216]

[0217] In some embodiments, it is preferable :

[0218]

[0219] in, This represents the time step of the k-th chip; Bk is the discretized input matrix; Bk is the input matrix of the k-th chip.

[0220] In implementation, higher-order approximation or numerical methods, such as the Krylov subspace method, can be selected depending on the device capabilities.

[0221] The discrete form described above is similar to a recurrent neural network, but by designing a specific matrix structure, the gradient vanishing problem is avoided.

[0222] Based on the discretized state transition matrix and the discretized input matrix By performing state recursion, the spatial relationships between all chips can be obtained.

[0223] In this embodiment of the application, for chip feature sequences Perform initialization:

[0224]

[0225] in, This is the initial hidden state.

[0226] Begin recursive calculation:

[0227]

[0228] ;

[0229] in, Let be the hidden state vector of the k-th chip; This is the discretized state transition matrix; For the kth The hidden state of a chip; The input matrix is ​​the discretized form. Let be the SSM input vector of the k-th chip.

[0230] In this embodiment of the application, the output sequence Characterizes the spatial relationship between global chips on a wafer. This represents the total number of chips.

[0231] A bidirectional Mamba spatial modeling network is used to perform reverse sequence propagation to obtain the SSM output of the chip.

[0232] In this embodiment of the application, to simultaneously capture forward and backward dependencies, a bidirectional Mamba spatial modeling network can be used to perform reverse sequence propagation:

[0233]

[0234] Its final output is:

[0235] ;

[0236] in, This is the SSM output result for the k-th chip; This is the forward Mamba output of the k-th chip; For the reverse Mamba output of the k-th chip; Concat( , ) represents a vector concatenation operation.

[0237] Based on the SSM output of the chip, multi-head parallel processing and residual enhancement are performed to obtain the Mamba output characteristics of the chip.

[0238] In this embodiment, to improve model capacity, the input features can be projected onto multiple heads for parallel modeling. Let the number of heads be... , No. The output of the head is After piecing them together, we get:

[0239]

[0240] in, oh(k) is the output of the multi-head splicing of the k-th chip; oh(k) is the output of the h-th head.

[0241] Subsequently, the expressive power is further enhanced through residual enhancement, namely residual connections and feedforward networks:

[0242] ;

[0243] in: The Mamba output characteristics of the k-th chip; LayerNorm( ) is feature-wise normalization; MLP( The ) is a multilayer perceptron, which consists of two linear transformations and an intermediate activation function.

[0244] In this embodiment, by leveraging the efficient parameter characteristics of KAN and the structural inductive bias of Mamba, model parameter redundancy is reduced, the risk of overfitting under small sample conditions is lowered, and the generalization ability across batches and machines is improved. At the same time, the overall architecture of the algorithm remains simple, the computational overhead is controllable, and it is easy to integrate with existing wafer inspection equipment. It is suitable for real-time or near real-time online defect detection in industrial production line environments, promoting the intelligent upgrade of semiconductor manufacturing quality control.

[0245] S600. The vectorized features of the chip and the output features of Mamba are fused to obtain the final fused features.

[0246] This step is performed by the adaptive fusion module. In this embodiment, vectorized features (local feature vectors) and Mamba output features (global sequence features) are dynamically fused, enabling the model to simultaneously utilize detailed information such as chip internal texture and wafer-level spatial dependency information. To enhance the model's adaptability to different modal features, a learnable gated fusion structure is adopted.

[0247] In some embodiments, the step of fusing the vectorized features of the chip and the Mamba output features to obtain the final fused features includes:

[0248] The vectorized features of the chip and the Mamba output features are linearly mapped to obtain the aligned vectorized features and aligned Mamba output features.

[0249] In this embodiment of the application, the vectorized features of the k-th chip , Equal to D, Mamba output features ,in = × , The number of heads operating in parallel. This refers to the output dimension of a single head, i.e., the number of output channels per head in a multi-head design. This is due to the dimension of vectorized features. Dimensions of Mamba output features They may differ, requiring a linear mapping to ensure dimensionality consistency and feature fusion. Let the aligned vectors be:

[0250]

[0251]

[0252] in, The aligned vectorized features; The feature projection matrix of KAN; For KAN projection bias; Features of the aligned Mamba output; This is the Mamba eigenprojection matrix; Features for Mamba output; For Mamba projection bias; These are common feature dimensions, which are hyperparameters and need to be pre-defined during implementation. , , and Acquired through training.

[0253] Based on the aligned vectorized features and the aligned Mamba output features, the gating weight vector is determined.

[0254] In this embodiment, a gating mechanism is introduced to generate a weight vector in order to adaptively select local and global information based on the characteristics of a specific chip region. To automatically determine the relative importance of local and global features.

[0255] In the gating vector formula: ;

[0256] in, Let be the gate weight vector of the k-th chip. Each component independently controls the local / global bias ratio of the corresponding dimension of the fused feature; Use the Sigmoid activation function to ensure the output range is within... and between; Let be the gated weight matrix, ∈ (Input is to combine two) The 2-dimensional vector concatenation results in (a dimensional vector), which is a learnable projection matrix; The aligned vectorized features; For feature concatenation vectors; Features of the aligned Mamba output; For the gated bias vector, ∈ .

[0257] In this embodiment, the gating weight vector can adaptively adjust the fusion ratio between different chip regions.

[0258] When the local texture information of certain chip regions better reflects defect characteristics The component tends to be larger, causing the fusion to be biased towards local features. When the spatial relationship of certain chip regions within the overall wafer structure is more important, The component tends to be smaller, causing the fusion to favor the global features generated by Mamba. .

[0259] The aligned vectorized features and the aligned Mamba output features are weighted and fused based on the gated weight vector to obtain the fused features.

[0260] In this embodiment of the application, after obtaining the gating weight vector, the aligned vectorized features and the aligned Mamba output features are weighted and fused according to the gating weight vector, which can be expressed as:

[0261] ;

[0262] in," " indicates element-wise multiplication; Features of fusion; This is the gating weight vector; The aligned vectorized features; This refers to the aligned Mamba output characteristics.

[0263] The above formula ensures that when the local texture features of a certain chip region are more critical, the model automatically increases the weight of KAN features; when the overall spatial pattern of the wafer is more sensitive to defects, it can favor Mamba features.

[0264] The fused features are normalized and nonlinearly activated to obtain the final fused features.

[0265] In this embodiment of the application, in order to maintain the stability of the feature numerical range and improve the trainability of the model, the fused features are normalized and nonlinearly activated to obtain the final fused features:

[0266] ;

[0267] in, For layer normalization operation; ReLU, GELU, or other monotonic activation functions can be used; Features of fusion; This is the final fusion feature.

[0268] In this embodiment, the adaptive fusion module utilizes dimensional gating coefficients and feature interaction terms to merge local fine-grained features and global spatial features, enabling the model to simultaneously utilize both types of information for defect judgment. In cases of complex defect types or irregular spatial layouts, this fusion design allows the model to adaptively select more reliable feature sources, thereby improving judgment stability.

[0269] S700. Based on the final fusion features, determine the chip defect category corresponding to the chip region.

[0270] In this embodiment, the final fusion features of the chip are used for classification to generate a chip defect category corresponding to each chip region. A fully connected classification model is used to determine the chip defect category.

[0271] In some embodiments, the step of determining the chip defect category corresponding to the chip region based on the final fusion feature includes:

[0272] The final fused features are mapped to the category space through a linear transformation to obtain the unnormalized scores for different defect categories;

[0273] This is accomplished using the following formula:

[0274] ;

[0275] in, For the first Unnormalized scores for different defect categories of each chip; For the classification weight matrix, ∈ , which are parameters that can be learned; For the final fusion feature, ; To fuse feature dimensions; For the classification bias vector, ∈ , which are parameters that can be learned; The preset number of defect types, such as surface particles, linear scratches, stains, and localized brightness abnormalities. and It is obtained through training.

[0276] Based on the unnormalized scores of the chip in different defect categories, the category probabilities of different defect categories are determined.

[0277] In this embodiment of the application, Softmax normalization is used to convert the above logits into class probabilities:

[0278] ;

[0279] in, For the first The chip belongs to the first The probability of a class of defects; For the first The chip belongs to the first Unnormalized score of class defects; The number of preset defect types.

[0280] The defect category corresponding to the highest probability of the aforementioned category is determined as the final defect category of the chip.

[0281] In this embodiment, the defect category corresponding to the highest category probability is the defect category of the chip region:

[0282] ;

[0283] in, Let k be the final defect category of the k-th chip; For the first The chip belongs to the first The probability of a class of defects.

[0284] In this embodiment of the application, in order to indicate the defect source region, the contribution of each dimension of the fused feature vector can be reverse-mapped. The method further includes:

[0285] Based on the contribution of each feature dimension of the final fused feature, the contribution value of the feature dimension to the defect category is determined;

[0286] Specifically, the contribution value can be calculated by multiplying the weight vector and the feature:

[0287] ;

[0288] in, For the first The contribution value of each feature dimension to the defect category; For the k-th final fused feature 1≤ ≤ ); To fuse feature dimensions; Classification weight matrix The corresponding final defect category The first line The element, that is, the category for the first element. Weights of dimensional features.

[0289] Back projection is performed based on the contribution value of the defect category to generate a region map of defects inside the chip.

[0290] In this embodiment of the application, back-projection of the contribution value can generate a region map of internal defects in the chip, enabling interpretable defect localization.

[0291] In some embodiments, the method further includes wafer-level defect aggregation to obtain a set of prediction results for all chips on the wafer, specifically:

[0292] The final defect category for all chips on the entire wafer can be represented as:

[0293] ;

[0294] in, This is the set of prediction results for all chips on the wafer; Let be the final defect category of the k-th chip.

[0295] In some embodiments, if it is necessary to generate a wafer-level defect distribution map, the category label of each chip can be mapped back to the original two-dimensional array position to form a defect distribution matrix:

[0296] ;

[0297] in, t represents the defect distribution matrix; t is the row index of the chip. For the column index of the chip; The value of the mapping function from two-dimensional coordinates to one-dimensional indices; For located The final defect category of the chip at the location.

[0298] This defect distribution matrix can be used to statistically analyze the proportion of defect categories, spatial distribution patterns, and to conduct process backtracking analysis.

[0299] Alternatively, in some embodiments, average pooling is used to determine the set of predictions for all chips across the entire wafer:

[0300] ;

[0301] in, This represents the global feature vector at the wafer level. This represents the total number of chips on the wafer. This represents the final fusion feature of the k-th chip.

[0302] In this embodiment, the wafer-level global feature vector can be used for wafer-level defect pattern recognition, such as annular defects, stripe defects, edge anomalies, etc., to determine the set of prediction results for all chips on the wafer.

[0303] In this embodiment of the application, to facilitate manual review of defect determination results and process backtracking, the method further includes:

[0304] For a defective chip, the gradient of the maximum class probability used to determine the final defect class with respect to the input features of each of the KAN layers is calculated.

[0305] In this embodiment of the application, the first defect is identified as a defect. For each chip, the gradient of the model output (e.g., the unnormalized score of the defect category or the maximum probability of the stated category) with respect to the input features of each layer of the KAN is calculated to reflect the influence of each layer's features on the final decision. Let the i-th chip be denoted as... Layer features are The gradient is then expressed as:

[0306] ;

[0307] in, The decision metric output by the model (e.g., the unnormalized score of the defect category or the maximum probability of the stated category). The number of layers in the KAN.

[0308] Each KAN layer is sorted according to the absolute value of its gradient, and the top K neurons that have the greatest impact on defect determination are identified.

[0309] In this embodiment, based on the aforementioned gradient information, each layer can be sorted by its absolute gradient value, and several neurons with the greatest impact on the output can be identified. For ease of implementation and description, let the number of neurons be 1. For example, it is advisable ;certainly It can be adjusted appropriately according to the complexity of the task.

[0310] The input-output mapping relationship of the neuron is obtained by combining the spline basis function coefficients and spline basis functions corresponding to the first K neurons.

[0311] For the identified dominant neuron, its corresponding spline function coefficients and spline basis function combinations are extracted, and then the input-output mapping curve of the neuron is reconstructed. This mapping can be used as part of the interpretability description to characterize the neuron's response pattern to feature changes.

[0312] By utilizing the input-output mapping relationship of the neurons, a chip-level attribution heatmap is generated.

[0313] Specifically, the activation intensity or gradient value of each dominant neuron is mapped back to its corresponding input channel and spatial location to form a chip-level attribution heatmap. The mapping process can employ back-projection from the feature map to the pixel space or interpolation techniques, specifically through methods such as spline function support intervals and deconvolution of convolution kernels (or gradient-weighted mapping). This attribution heatmap visually demonstrates which image regions (e.g., edges, textures, grains, etc.) significantly contribute to defect detection, thus providing a reference for quality review and process improvement.

[0314] Interpretable outputs can be generated solely based on the spline function and gradient information of the KAN layer, or they can be weighted by combining the spatial context information provided by Mamba to reflect the relative importance of local features within the global wafer structure.

[0315] In this embodiment, the interpretable output process provides clear, structured evidence for defect identification. By analyzing the critical spline basis function nodes, the local regions constituting the determination criteria are mapped back to the original wafer image, forming a visualized attribution map. This result can be used by process debugging personnel to locate the defect formation stage, determine whether anomalies have spatial correlation, and provide support for production line decisions.

[0316] In this embodiment, during the inference phase, steps S100-S700 are executed. The inference phase does not involve parameter updates; all weights are derived from fixed parameters obtained during training.

[0317] The inference process first performs preprocessing and chip region extraction steps S200 and S300 on the original grayscale image of the input wafer. The resulting chip sequence is then sequentially input into the KAN network in step S400 to generate local features. Subsequently, the local feature sequence is input into the Mamba spatial modeling network module in step S500 to calculate the global spatial representation and generate residual-enhanced feature vectors. Next, the S600's adaptive fusion module generates fused features. It serves as the input to the defect classification module, and ultimately outputs the chip-level defect category probability and prediction results.

[0318] When interpretable output is required, a corresponding attribution heatmap can be generated based on the gradient and spline function mapping of the KAN layer. The attribution heatmap displays local regions that significantly contribute to the chip's defect assessment and can be further explained at the global wafer structure level in conjunction with the S500's spatial features. All outputs during the inference phase can be recorded or displayed by the inspection system to support engineering analysis and quality auditing.

[0319] In this embodiment, the training of the KAN network and the Mamba spatial modeling network is also included. Specifically, this includes phased training and joint training.

[0320] In this embodiment of the application, in order to enable the KAN network and the Mamba spatial modeling network to obtain stable initial parameters respectively, staged training is performed first, and then the convergence of the overall architecture is achieved through joint training.

[0321] In the first stage (phased training), the parameters of the Mamba spatial modeling network are kept fixed, and only the encoder and classifier heads of the KAN network are trained, enabling the encoder to learn local texture features of different defect types. A relatively large initial learning rate can be used for this stage, for example, approximately [value missing]. The algorithm iterates through several rounds using batch training to gradually and effectively represent local features. To further improve stability, gradient pruning can be incorporated into the optimization process to suppress extreme updates.

[0322] In the second phase (joint training), the Mamba spatial modeling network is unfrozen (i.e., the parameters of the Mamba spatial modeling network are unfixed) and the adaptive fusion module is unfrozen, and the entire network is jointly trained. The learning rate in this phase typically uses a small initial value, for example, approximately [value missing]. It can also be used in conjunction with a cosine annealing strategy for gradual decay. The learning rate increases with the first... The iteration change can be represented as:

[0323] in, For the first The learning rate for each iteration; This represents the current iteration number; Minimum learning rate; The maximum learning rate; This represents the total number of iterations. In one example, it can be taken as... Approximately .

[0324] During parameter optimization, the AdamW optimizer with a weight decay mechanism can be used to simultaneously control model complexity and training stability. The weight decay coefficient can be, for example, approximately... To improve training speed and memory utilization efficiency, a mixed precision training method can be adopted.

[0325] In some embodiments, training data preparation and enhancement strategies are specifically designed to enable the model to adapt to the diversity of wafer defects under illumination, process variations, and imaging differences.

[0326] In terms of data organization, training, validation, and test sets are divided on a wafer-by-wafer basis to avoid mixing samples from the same wafer across different sets. For cases of significant defect class imbalance, sample distribution can be improved through resampling or by introducing class weights into the loss function.

[0327] In terms of data augmentation, various perturbations are applied to the chip image or the corresponding extracted local region to expand the coverage of the input distribution. These perturbations may include: small-angle random rotation, horizontal or vertical flipping, slight deformation perturbations, brightness and contrast fluctuations, and small-amplitude Gaussian noise injection. The augmentation magnitude can be, for example, a rotation range of approximately ±15 degrees, a brightness perturbation range of approximately ±20%, and a noise standard deviation of approximately 0.02. These augmentation methods enable the model to adapt to imaging changes during the manufacturing process without altering the essential characteristics of the defects.

[0328] To further enhance the robustness of the global spatial structure, enhancements such as size scaling and slight rotation can be applied to the entire wafer image, and the corresponding regions can be synchronized after chip partitioning. This embodiment is not limited to this.

[0329] In this embodiment, to balance classification accuracy, spatial consistency, and the sparsity constraint of KAN spline coefficients, a multi-task joint loss function is used during training, the overall form of which is:

[0330] ;

[0331] in, This represents the total loss function value. For classification loss; This represents a loss of spatial consistency. For spline coefficient sparsity loss, and These are the corresponding weighting coefficients;

[0332] In one example and For example, we can take approximately [number] for each. With the agreement However, this value is not the only limit; adjustments should be made based on the actual task and the verification set.

[0333] Classification loss We employ cross-entropy with class weights to address the class imbalance problem. Let the total number of samples be... , No. The true labels (i.e., true defect categories) of each sample are vectors. (one-hot representation), the model for the first The predicted probability of the class is ,but:

[0334] ;

[0335] in, For classification loss; is the total number of samples (wafer chips) in the training set; n is the sample index; The category weights are the actual labels; The g-th component of the true label (1 if the n-th sample belongs to the g-th class, otherwise 0); g is the class index (g=1,…,C); Let g be the probability that the nth sample belongs to the gth class.

[0336] Spatial consistency loss This is used to encourage spatial consistency in the prediction results of adjacent chips on a wafer, thereby utilizing spatial correlation information of defects on the wafer.

[0337] Define adjacent sets Given the neighbor set of the chip (e.g., four-neighbor or eight-neighbor areas can be used as examples), the spatial consistency loss can be expressed as:

[0338] ;

[0339] in, This represents a loss of spatial consistency. For neighboring chip indexes; The set of neighbors of the chip; Let be the probability distribution vector of the nth chip; Let be the probability distribution vector of the neighboring chips.

[0340] sparsity loss Constraining the sparsity of spline basis function coefficients in a KAN network reduces the risk of overfitting and enhances interpretability. Let... For the first The first in the layer The output dimension, the first The input dimension, the first The sparsity loss can be expressed as the sum of the absolute values ​​of the coefficients of the spline basis functions:

[0341] ;

[0342] in, This represents the sparsity loss value. is the layer index of the KAN network; e is the dimension index of the output feature; a is the dimension index of the input feature; m is the spline basis function index; For the first The coefficients of the m-th spline basis function connecting input node a to output node e in the layer.

[0343] In the embodiments of this application, and (L1 norm) regularization combined with and through Adjust its strength; in some embodiments, the coefficients may be truncated or a sparsity training strategy may be employed to facilitate the visualization and interpretation of subsequent spline basis functions.

[0344] The weights of the above multi-task loss , and category weights The optimal values ​​can be determined by common hyperparameter search methods such as grid search or Bayesian optimization on the validation set to ensure training stability and generalization.

[0345] In this embodiment, a multi-task joint loss consisting of classification loss, spatial consistency loss, and sparsity loss can be used to simultaneously constrain the model's local discriminative ability, wafer spatial structure consistency, and sparsity of the KAN layer spline function.

[0346] This allows the model to have a more stable gradient when dealing with class-imbalanced defect samples; enables the spatial sequence modeling module to fully utilize the structural correlation between adjacent chips on the wafer during learning; and ensures that the spline coefficients maintain reasonable sparsity during training, thereby facilitating subsequent interpretability generation.

[0347] In each training iteration, the aforementioned loss term is calculated based on the current input chip region features, its neighborhood structure, and the spline coefficients of the KAN layer. The parameters of KAN, Mamba, and the fusion module are simultaneously updated via backpropagation. Throughout the training cycle, if the joint loss of the model on the validation set shows an increasing trend, an early stopping strategy can be used as an optional implementation to avoid overfitting.

[0348] Through the above-mentioned joint optimization steps, the model parameters trained in the embodiments of this application can effectively take into account local defect modes, global wafer structural features, and interpretability constraints, making the final model suitable for industrial-grade detection and diagnosis of wafer chip defects.

[0349] In this embodiment, the model can be deployed on wafer defect detection equipment or detection software systems, and used in conjunction with online or offline detection processes. Deployment methods may include service-oriented deployment, modular deployment, or embedded deployment, depending on the architecture design of the detection production line.

[0350] The model can be integrated with front-end acquisition systems, defect databases, manufacturing execution systems (MES), or yield analysis systems via standard communication interfaces. During integration, it can provide chip-level defect prediction results, attribution heatmaps, and overall wafer defect structure information. It can also output JSON, binary structured data, or image format data as needed for back-end system access or storage. This embodiment does not limit specific communication protocols or hardware platforms, nor does it limit inference throughput parameters; it can be flexibly configured according to the production line environment.

[0351] The method described in this application has a compact overall structure and clearly defined dependent modules, allowing for deployment on different hardware platforms depending on actual equipment conditions. Because the network design employs serialization modeling and lightweight local feature encoding, it exhibits good adaptability in industrial applications and can complete detection tasks under real-time or near-real-time conditions.

[0352] In this embodiment, the training phase adopts a phased training strategy and a multi-task loss joint optimization mechanism to ensure the stable convergence of the local coding network and the spatial sequence modeling network; the inference phase outputs chip defect judgment results and interpretability information according to a unified execution process.

[0353] This application's embodiments achieve a unified representation of local details and global spatial correlation in wafer defect detection scenarios, ensuring good stability and interpretability of defect determination even under complex process conditions. A relatively complete structured characterization system is formed in wafer defect detection scenarios, enabling unified modeling of local and global information and providing interpretable output, thus providing reliable technical support for process quality management. The method in this application's embodiments has good engineering applicability and can be widely used for wafer defect detection tasks under different batches and process conditions.

[0354] The key aspects of the method in this application's embodiments are mainly reflected in three aspects: input normalization, joint modeling of "local interpretable features-global spatial structure," and construction of interpretable structures. First, through preprocessing operations such as contrast enhancement, smoothing filtering, and brightness normalization, illumination differences and random noise in the wafer image are effectively suppressed, and defect edges and local textures are made clearer, providing a stable input foundation for subsequent feature extraction. Based on this, this application's embodiments utilize the regularity of wafer arrangement to divide the entire image into a structured chip sequence, enabling two-dimensional spatial relationships to be expressed sequentially in subsequent models, reducing the computational burden of directly modeling on the original high-resolution image.

[0355] In the feature encoding stage, this embodiment employs a KAN network based on differentiable spline functions to extract local fine-grained features. This allows the local structures of point-like, line-like, and texture-like defects to be represented by more flexible function mappings, reducing the limitations of traditional convolutional activation on complex defect morphologies. Simultaneously, to capture the spatial correlation of wafer chips within the array structure, this embodiment introduces a Mamba spatial modeling network. This network uses a linearly complex sequence propagation mechanism to encode the dependencies between the center and edges, row and column directions, and local clustering regions, enabling a unified expression of systematic defect patterns and global structural changes in the feature space.

[0356] The adaptive feature fusion module in this embodiment integrates local texture features and global spatial features in a dimension-wise gating manner, and combines feature interaction terms to construct a more consistent fusion representation, thus making it suitable for dealing with complex defect scenarios that are difficult to cover with a single feature. Finally, leveraging the traceability of the KAN spline structure, this application constructs an interpretable output process based on gradient backtracking. By generating an attribution graph through the activation mapping of key spline nodes, the defect judgment criteria can be presented intuitively, facilitating process engineers to analyze the causes of defect formation.

[0357] In summary, a complete wafer chip defect detection system was constructed through input normalization, local-global joint modeling, and interpretable output mechanism. It is suitable for various process conditions and defect types and has good engineering implementation value.

[0358] In this embodiment, while ensuring the accuracy of wafer chip defect detection, the detection speed is improved, the spatial correlation modeling capability of defects is enhanced, the traceability of the decision-making process is provided, and good generalization performance is guaranteed under small sample conditions.

[0359] The above embodiments provide a wafer chip defect detection method, apparatus, device, and medium. This method uses a Mamba spatial modeling network to reduce the computational complexity from quadratic to linear levels when processing high-resolution raw grayscale images of wafer chips, thereby improving inference speed and meeting the real-time detection needs of industrial production lines. The spatial propagation mechanism of the Mamba spatial modeling network effectively captures the spatial propagation characteristics of wafer chip defects, improving the accuracy and spatial consistency of identifying systematic and contiguous defects. The learnable spline basis functions of the KAN network enhance the interpretability of the feature transformation process, making the decision-making basis for the detection results transparent and traceable, facilitating quality auditing and process improvement.

[0360] This application also provides a wafer chip defect detection device. Figure 4 An exemplary schematic diagram of a wafer chip defect detection device provided according to some embodiments is shown.

[0361] The device includes:

[0362] Acquisition unit 401 is used to acquire the original grayscale image of the wafer;

[0363] The preprocessing unit 402 is used to sequentially perform contrast enhancement, Gaussian filtering, sharpening enhancement and zero-mean normalization on the original grayscale image to obtain the preprocessed image;

[0364] Extraction unit 403 is used to sequentially perform chip center localization, geometric correction, and ROI extraction on the preprocessed image to obtain all chip regions; perform sequence encoding on all chip regions to obtain chip sequence index; and perform position encoding based on the chip sequence index to obtain position encoding vector;

[0365] Local coding unit 404 is used to locally encode the chip region based on the chip region and the position coding vector using a KAN network to obtain the vectorized features of the chip.

[0366] The first determining unit 405 is used to determine the Mamba output features based on the chip feature sequence composed of vectorized features of all the chips, using the Mamba spatial modeling network.

[0367] The fusion unit 406 is used to fuse the vectorized features of the chip and the output features of Mamba to obtain the final fused features;

[0368] The second determining unit 407 is used to determine the chip defect category corresponding to the chip region based on the final fusion features.

[0369] In this embodiment of the application, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of wafer chip defect detection as described above.

[0370] In this embodiment of the application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of wafer chip defect detection as described above.

[0371] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platform, or it can be implemented by hardware.

[0372] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the units or processes shown in the drawings are not necessarily essential for implementing this application. Those skilled in the art will understand that the units in the apparatus of the embodiment can be distributed within the apparatus of the embodiment as described, or can be located in one or more apparatuses different from this embodiment, with corresponding changes. The units of the above-described embodiment can be combined into one unit, or further divided into multiple sub-units.

[0373] The serial numbers in this application are for descriptive purposes only and do not represent the superiority or inferiority of any particular implementation scenario. The above disclosures are merely a few specific implementation scenarios of this application; however, this application is not limited thereto, and any variations conceived by those skilled in the art should fall within the protection scope of this application.

Claims

1. A method for detecting defects in a wafer chip, characterized in that, include: Obtain the original grayscale image of the wafer; The original grayscale image is sequentially subjected to contrast enhancement, Gaussian filtering, sharpening enhancement, and zero-mean normalization to obtain the preprocessed image. The preprocessed image is sequentially subjected to chip center localization, geometric correction, and ROI extraction to obtain all chip regions; all chip regions are sequence encoded to obtain chip sequence indexes; and position encoding is performed based on the chip sequence indexes to obtain position encoding vectors. Based on the chip region and the location encoding vector, a KAN network is used to locally encode the chip region to obtain the vectorized features of the chip. Based on the chip feature sequence composed of vectorized features of all the chips, the Mamba output features are determined using the Mamba spatial modeling network. The vectorized features of the chip and the output features of Mamba are fused to obtain the final fused features; Based on the final fusion features, the chip defect category corresponding to the chip region is determined.

2. The method according to claim 1, characterized in that, The KAN network includes multiple KAN layers; the step of using the KAN network to locally encode the chip region based on the chip region and the location encoding vector to obtain the vectorized features of the chip includes: Initial feature mapping is performed on the chip region to generate an initial feature vector; The initial feature vector is input into a multi-layer KAN layer to perform nonlinear transformation using spline basis functions to obtain the corresponding output vector for each layer, and the output vector is then normalized. The result of normalizing the output vector corresponding to the last layer is determined as the vectorized feature.

3. The method according to claim 1, characterized in that, The step of determining the Mamba output features using a Mamba spatial modeling network based on the chip feature sequence composed of vectorized features of all the chips includes: The vectorized features of the chip are mapped to SSM input vectors through linear projection; Based on the SSM input vector, the selectivity coefficient vector of the chip is generated; Based on the selectivity coefficient, the input matrix corresponding to the chip is generated, and the output matrix is ​​determined; Based on the vectorization features of the chip, a time step is generated; based on the input matrix, output matrix and time step, discretization calculation is performed to obtain the discretized state transition matrix and the discretized input matrix; Based on the discretized state transition matrix and the discretized input matrix, state recursion is performed to obtain the spatial relationship between all chips; A bidirectional Mamba spatial modeling network is used to perform reverse sequence propagation to obtain the SSM output of the chip; Based on the SSM output of the chip, multi-head parallel processing and residual enhancement are performed to obtain the Mamba output characteristics of the chip.

4. The method according to claim 1, characterized in that, The step of fusing the vectorized features of the chip and the Mamba output features to obtain the final fused features includes: The vectorized features of the chip and the Mamba output features are linearly mapped to obtain the aligned vectorized features and aligned Mamba output features. Based on the aligned vectorized features and aligned Mamba output features, the gate weight vector is determined; The aligned vectorized features and the aligned Mamba output features are weighted and fused based on the gated weight vector to obtain the fused features; The fused features are normalized and nonlinearly activated to obtain the final fused features.

5. The method according to claim 2, characterized in that, The step of determining the chip defect category corresponding to the chip region based on the final fusion features includes: The final fused features are mapped to the category space through a linear transformation to obtain the unnormalized scores for different defect categories; Based on the unnormalized scores of the chip in different defect categories, the category probability of different defect categories is determined; The defect category corresponding to the highest probability of the aforementioned category is determined as the final defect category of the chip.

6. The method according to claim 5, characterized in that, Also includes: Based on the contribution of each feature dimension of the final fused feature, the contribution value of the feature dimension to the defect category is determined; Back projection is performed based on the contribution value of the defect category to generate a region map of defects inside the chip.

7. The method according to claim 5, characterized in that, The method further includes: For a defective chip, the gradient of the maximum class probability used to determine the final defect category with respect to the input features of each of the KAN layers is calculated. Each KAN layer is sorted according to the absolute value of its gradient, and the top K neurons that have the greatest impact on defect determination are identified. The input-output mapping relationship of the neuron is obtained by combining the spline basis function coefficients and spline basis functions corresponding to the first K neurons. By utilizing the input-output mapping relationship of the neurons, a chip-level attribution heatmap is generated.

8. A wafer chip defect detection device, characterized in that, include: The acquisition unit is used to acquire the original grayscale image of the wafer; The preprocessing unit is used to sequentially perform contrast enhancement, Gaussian filtering, sharpening enhancement and zero-mean normalization on the original grayscale image to obtain the preprocessed image; The extraction unit is used to sequentially perform chip center localization, geometric correction, and ROI extraction on the preprocessed image to obtain all chip regions; perform sequence encoding on all the chip regions to obtain chip sequence indexes; and perform position encoding based on the chip sequence indexes to obtain position encoding vectors. A local coding unit is used to locally encode the chip region based on the chip region and the position coding vector using a KAN network to obtain the vectorized features of the chip. The first determining unit is used to determine the Mamba output features based on the chip feature sequence composed of vectorized features of all the chips, using the Mamba spatial modeling network. A fusion unit is used to fuse the vectorized features of the chip and the output features of Mamba to obtain the final fused features; The second determining unit is used to determine the chip defect category corresponding to the chip region based on the final fusion features.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the wafer chip defect detection method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the wafer chip defect detection method as described in any one of claims 1 to 7.

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