Pixel circuit, display panel and electronic equipment

Abstract

The invention relates to the technical field of display, and discloses a pixel circuit, a display panel and electronic equipment. The pixel circuit comprises a write-in module and a driving transistor, the write-in module at least comprises two capacitors connected in series, any one of a grid electrode, a source electrode and a drain electrode of the driving transistor is connected to a series connection point between the two capacitors, and meanwhile the write-in module further receives data voltage. Thus, when the brightness of the light-emitting device is adjusted, for example, in the process of increasing or decreasing the data voltage according to the fixed variation amplitude, the brightness of the light-emitting device can be adjusted according to the value smaller than the variation amplitude, so that the pixel circuit can display finer brightness control.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit, display panel, and electronic device. Background Technology

[0002] The main component that enables display functions in electronic devices is the display panel. The display panel includes a pixel array and a display driver IC (DDIC). The DDIC is used to output data voltage to the pixel circuit of each pixel in the pixel array to control the brightness of the light-emitting device in the pixel circuit.

[0003] Currently, pixel circuits can adjust brightness (grayscale) by changing the current flowing through the light-emitting device based on the amplitude of data voltage changes. For example, during the brightening process of the light-emitting device, the data voltage can be increased or decreased, such as decreasing the data voltage from 3V to 2V, or increasing the data voltage from 2V to 3V. However, current pixel circuits can only adjust the light-emitting device based on a fixed amplitude of data voltage change (e.g., 1V), causing the light-emitting device to exhibit abrupt brightness fluctuations. This results in poor display panel refresh performance. Therefore, there is an urgent need for a pixel circuit that can achieve more precise brightness adjustment. Summary of the Invention

[0004] To address the aforementioned issues, embodiments of this application provide a pixel circuit, a display panel, and an electronic device.

[0005] In a first aspect, embodiments of this application provide a pixel circuit, including a first light-emitting transistor, a first driving transistor, a first writing transistor, a first capacitor, a second capacitor, and a light-emitting device; a first terminal of the first driving transistor is connected to one terminal of the first light-emitting transistor, the other terminal of the first light-emitting transistor is connected to a first power supply, and a second terminal of the first driving transistor is connected to the light-emitting device; a first terminal of the first writing transistor is used to receive a data voltage, and a second terminal of the first writing transistor is connected to one terminal of the first capacitor; the other terminal of the first capacitor is connected in series with the second capacitor, and the other terminal of the first capacitor is also connected to the second terminal of the first driving transistor; wherein, the first terminal is the source and the second terminal is the drain; or, the first terminal is the drain and the second terminal is the source.

[0006] Based on the above scheme, the data voltage written via the first write transistor can be divided by a first capacitor and a second capacitor connected in series. The voltage divided by the first capacitor can be written to the source or drain of the first driving transistor, thereby changing the current flowing through the light-emitting device to adjust the brightness. Thus, when adjusting the brightness of the light-emitting device, for example, to reduce its brightness, the data voltage needs to be increased. The pixel circuit can then gradually reduce the brightness of the light-emitting device based on voltage changes smaller than the data voltage change, enabling the pixel circuit to achieve more precise brightness control.

[0007] In some possible implementations of the first aspect described above, a second light-emitting transistor is also included; the second terminal of the first driving transistor is connected to the light-emitting device through the second light-emitting transistor.

[0008] It is understood that a pixel circuit can use only one light-emitting transistor to control the light emission of the light-emitting device, or it can use two light-emitting transistors to control the light emission of the light-emitting device. This application does not limit this.

[0009] In some possible implementations of the first aspect described above, the following are also included: a first reset transistor, wherein a first terminal of the first reset transistor is used to receive a first reset voltage, and a second terminal of the first reset transistor is connected to the control terminal of the first driving transistor; a third capacitor and a second reset transistor, wherein one end of the third capacitor is connected to the control terminal of the first driving transistor, and the other end of the third capacitor is connected to the second capacitor, and the third capacitor, the second capacitor, and the first capacitor are connected in series in sequence; a first terminal of the second reset transistor is connected to the other end of the third capacitor, and a second terminal of the second reset transistor is used to receive the first reset voltage; a third reset transistor, wherein a first terminal of the third reset transistor is connected to one end of the first capacitor, and a second terminal of the third reset transistor is used to receive a second reset voltage; and a fourth reset transistor, wherein a first terminal of the fourth reset transistor is used to receive the second reset voltage, and a second terminal of the fourth reset transistor is connected to a light-emitting device.

[0010] It is understandable that the first reset transistor, the second reset transistor, the third reset transistor, and the fourth reset transistor are mainly used to realize the initialization and compensation stages of the pixel circuit, ensuring the normal operation of the pixel circuit.

[0011] In some possible implementations of the first aspect above, the control terminal of the first light-emitting transistor is used to receive the first light-emitting signal, the control terminal of the second light-emitting transistor is used to receive the second light-emitting signal, and the first light-emitting transistor and the second light-emitting transistor are turned on simultaneously or sequentially based on the first light-emitting signal and the second light-emitting signal.

[0012] It is understood that this application does not limit the turn-on order of the first light-emitting transistor and the second light-emitting transistor. Specifically, in the first light-emitting transistor (e.g.,Figure 4 Transistor T12 (shown) precedes the second light-emitting transistor (e.g., Figure 4 When transistor T13 is turned on, it can prevent the formation of a path between node N6 and power supply VSS when transistor T13 is turned on first, thus avoiding interference with the normal light emission of the light-emitting device L.

[0013] In some possible implementations of the first aspect above, the first light-emitting transistor and the second light-emitting transistor are turned on simultaneously based on the first light-emitting signal and the second light-emitting signal, and the pulse rise times of the first light-emitting signal and the second light-emitting signal are the same; the first light-emitting transistor and the second light-emitting transistor are turned on sequentially based on the first light-emitting signal and the second light-emitting signal, and the pulse rise time of the first light-emitting signal is earlier than the pulse rise time of the second light-emitting signal.

[0014] In some possible implementations of the first aspect described above, the second terminal of the third reset transistor is used to receive the first reset voltage, or the second terminal of the third reset transistor is used to receive the third reset voltage, wherein the third reset voltage, the second reset voltage and the first reset voltage are different from each other.

[0015] It is understood that, in the embodiments of this application, the voltage connected to the second terminal of the third reset transistor can be selected in multiple ways. Among them, the third reset transistor (e.g., Figure 4 The second terminal of transistor T14 can be used to receive the reset voltage Vinit1. Then, the voltage of node N6 during the write phase is not affected by the voltage drop of the reset voltage Vinit2, but is only related to the value of Vinit1.

[0016] In some possible implementations of the first aspect described above, the control terminal of the third reset transistor is used to receive the first scan signal, the control terminal of the fourth reset transistor is used to receive the second scan signal, the control terminal of the first reset transistor is used to receive the third scan signal, and the control terminal of the second reset transistor is used to receive the fourth scan signal. The third reset transistor, the fourth reset transistor, the first reset transistor, and the second reset transistor are simultaneously turned on based on the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal, and the third reset transistor and the fourth reset transistor are simultaneously turned off based on the first scan signal and the second scan signal, or the fourth reset transistor and the first reset transistor are simultaneously turned off based on the second scan signal and the third scan signal, or the fourth reset transistor and the second reset transistor are simultaneously turned off based on the second scan signal and the fourth scan signal.

[0017] It is understood that this application does not specifically limit the scan signals received by the control terminals of each reset transistor. Some scan signals may be the same, so that the corresponding reset transistors can be turned on / off simultaneously. The same scan signals can be connected to the same external circuit, thereby simplifying the circuit structure of the display panel where the pixel circuit is located.

[0018] In some possible implementations of the first aspect above, the change in data voltage is the first voltage, the change in gate-source voltage of the first driving transistor is the second voltage, and the ratio between the second voltage and the first voltage is related to the capacitance values ​​of the first capacitor and the second capacitor.

[0019] In some possible implementations of the first aspect described above, the first driving transistor is an N-type transistor.

[0020] It is understandable that, compared to P-type driving transistors, N-type driving transistors are more helpful in improving the display effect of the picture and reducing the occurrence of black spots and uneven color display on the screen.

[0021] Secondly, embodiments of this application provide another pixel circuit, including a third light-emitting transistor, a second driving transistor, a second writing transistor, a fourth capacitor, a fifth capacitor, and a light-emitting device; a first terminal of the second driving transistor is connected to one terminal of the third light-emitting transistor, the other terminal of the third light-emitting transistor is connected to a first power supply, and a second terminal of the second driving transistor is connected to the light-emitting device; a first terminal of the second writing transistor is used to receive a data voltage, and a second terminal of the second writing transistor is connected to one terminal of the fourth capacitor; the other terminal of the fourth capacitor is connected to one terminal of the fifth capacitor and also connected to the control terminal of the second driving transistor, and the other terminal of the fifth capacitor is connected to the second terminal of the second driving transistor; wherein, the first terminal is the source and the second terminal is the drain; or, the first terminal is the drain and the second terminal is the source.

[0022] Based on the above scheme, the data voltage written via the second write transistor can be divided by the fourth and fifth capacitors connected in series. The voltage divided by the fourth capacitor can be written to the gate of the second drive transistor, thereby changing the current flowing through the light-emitting device to adjust the brightness. Thus, when adjusting the brightness of the light-emitting device, for example, reducing the brightness, the data voltage needs to be reduced. The pixel circuit can gradually reduce the brightness of the light-emitting device based on a voltage change smaller than the data voltage change, enabling the pixel circuit to achieve more precise brightness control of the display.

[0023] It is understandable that the difference between the pixel circuit in the second aspect and the pixel circuit in the first aspect lies in the different data writing methods, that is, the different connection methods between the writing transistor and the driving transistor. For example, the first writing transistor is connected to the source or drain of the first driving transistor. In this case, the larger the data voltage, the smaller the current. The second writing transistor is connected to the gate of the second driving transistor. In this case, the larger the data voltage, the larger the current.

[0024] Among some possible implementations of the second aspect above, the following are also included: a fifth reset transistor, the first terminal of which is used to receive a first reset voltage, and the second terminal of which is connected to one end of a fourth capacitor; a sixth reset transistor, the first terminal of which is used to receive the first reset voltage, and the second terminal of which is connected to the other end of the fourth capacitor; and a seventh reset transistor, the first terminal of which is used to receive a second reset voltage, and the second terminal of which is connected to a light-emitting device.

[0025] Among some possible implementations of the second aspect described above, a sixth capacitor is also included, one end of which is connected to the second end of the second driving transistor, and the other end of which is connected to the first power supply or the second power supply; or, the other end of the sixth capacitor is used to receive the first reset voltage or the second reset voltage.

[0026] In some possible implementations of the second aspect above, the control terminal of the fifth reset transistor is used to receive the first scan signal, the control terminal of the sixth reset transistor is used to receive the third scan signal, and the control terminal of the seventh reset transistor is used to receive the fourth scan signal. The fifth, sixth, and seventh reset transistors are simultaneously turned on based on the first, third, and fourth scan signals, and the sixth and seventh reset transistors are simultaneously turned off based on the third and fourth scan signals, or the sixth and fifth reset transistors are simultaneously turned off based on the third and first scan signals, or the fifth and seventh reset transistors are simultaneously turned off based on the first and fourth scan signals.

[0027] In this embodiment of the application, the sixth reset transistor (e.g.) Figure 10 The control terminal of transistor T17 (shown) is used to receive the third scan signal (e.g., Figure 11B / Figure 11C As shown in Scan3), and the third scan signal remains high during the compensation phase, causing the sixth reset transistor to remain on, which enables the second drive transistor (such as...) to... Figure 10 The gate voltage of transistor T22 is stabilized at Vinit1, which ensures good uniformity of the pixel circuit.

[0028] In some possible implementations of the second aspect above, the change in data voltage corresponds to the third voltage, the change in the gate-source voltage of the second driving transistor corresponds to the fourth voltage, and the ratio between the fourth voltage and the third voltage is related to the capacitance values ​​of the fourth capacitor and the fifth capacitor.

[0029] In some possible implementations of the second aspect described above, the second driving transistor is an N-type transistor.

[0030] Thirdly, embodiments of this application provide a display panel including the pixel circuit described in the first or second aspect above.

[0031] Fourthly, embodiments of this application provide an electronic device, including a display panel, the display panel including the pixel circuit described in the first or second aspect above.

[0032] The technical effects of the third and fourth aspects mentioned above can be referred to the relevant description of the first aspect, and will not be repeated here. Attached Figure Description

[0033] Figure 1 A schematic diagram of an application scenario is shown according to some embodiments of this application;

[0034] Figure 2 According to some embodiments of this application, a schematic diagram of the structure of the display panel 10 is shown;

[0035] Figure 3 A schematic diagram of a pixel circuit 1011 is shown according to some embodiments of this application;

[0036] Figure 4 A schematic diagram of a pixel circuit 1011a is shown according to some embodiments of this application;

[0037] Figure 5 According to some embodiments of this application, a waveform diagram of a signal in a pixel circuit 1011a is shown;

[0038] Figure 6 According to some embodiments of this application, a waveform simulation diagram of the gate-source voltage of transistor T11 under different data voltages Vdata is shown;

[0039] Figure 7 According to some embodiments of this application, a waveform simulation diagram of the current on the light-emitting device L under different data voltages Vdata is shown;

[0040] Figure 8 A schematic diagram of a pixel circuit 1011b is shown according to some embodiments of this application;

[0041] Figure 9According to some embodiments of this application, a waveform diagram of a signal in a pixel circuit 1011b is shown;

[0042] Figure 10 A schematic diagram of a pixel circuit 1011c is shown according to some embodiments of this application;

[0043] Figure 11A According to some embodiments of this application, a waveform diagram of a signal in a pixel circuit 1011c is shown;

[0044] Figure 11B According to some embodiments of this application, waveform diagrams of signals in another pixel circuit 1011c are shown;

[0045] Figure 11C According to some embodiments of this application, waveform diagrams of signals in another pixel circuit 1011c are shown;

[0046] Figure 12A A schematic diagram of a pixel circuit 1011d is shown according to some embodiments of this application;

[0047] Figure 12B A schematic diagram of a pixel circuit 1011e is shown according to some embodiments of this application. Detailed Implementation

[0048] The illustrative embodiments of this application include, but are not limited to, a pixel circuit, a display panel, and an electronic device.

[0049] Figure 1 A schematic diagram of an application scenario is shown. Electronic device 1 includes a display panel 10, through which electronic device 1 can display various content, such as text, images, or videos.

[0050] Figure 2 A schematic diagram of the display panel 10 is shown. The display panel 10 includes a pixel array 101, a display driver chip (DDIC) 102, and a gate driver on array (GOA) circuit 103. The pixel array 101 includes multiple pixel circuits 1011 arranged in a matrix. The DDIC 102 outputs data voltages to the pixel circuits 1011, and these data voltages are used to control the brightness of the light-emitting devices in the pixel circuits 101.

[0051] It is understood that each pixel circuit 1011 may include at least one thin film transistor (TFT) and at least one capacitor. This application does not limit the specific structure of the pixel circuit. Figure 3A schematic diagram of a pixel circuit 1011 is shown. The pixel circuit 1011 may include thin-film transistors T1 to T8, capacitor C1, and light-emitting element L.

[0052] In this configuration, the gate of transistor T1 receives the reset signal Reset1, one of its source and drain receives the reset voltage Vinit1, and the other is connected to one end of capacitor C1. The other end of capacitor C1 is connected to the power supply VDD. The gate of transistor T2 receives the scan signal Gate, one of its source and drain is connected to node N1, which is the connection point between transistor T1 and capacitor C1, and the other is connected to node N3, which is the connection point between transistor T3 (the driving transistor) and transistor T6. The gate of transistor T3 is connected to node N1. The gates of transistors T5 and T6 both receive the light emission signal EM. One of the source and drain of transistor T5 is connected to the power supply VDD, and the other is connected to one of the source and drain of transistor T3. The other of the source and drain of transistor T3 is connected to one of the source and drain of transistor T6. The other of the source and drain of transistor T6 is connected to the anode of the light-emitting element L, and the cathode of the light-emitting element L is connected to the power supply VSS. Transistor T4's gate receives the scan signal Gate, one of its source and drain receives the data voltage Vdata, and the other is connected to node N2, which is the connection point between transistors T5 and T3. Transistor T7's gate receives the reset signal Reset2, one of its source and drain receives the reset voltage Vinit2, and the other is connected to node N4, which is the connection point between the light-emitting element L and transistor T6. Transistor T8's gate receives the reset signal Reset2, one of its source and drain receives the reset voltage Vinit3, and the other is connected to node N2.

[0053] It can be understood that during the writing phase of pixel circuit 1011, the scan signal Gate controls transistor T4 to turn on, and the data voltage Vdata is written to node N2 via transistor T4. During the light-emitting phase of pixel circuit 1011, the light-emitting signal EM controls transistors T5 and T6 to turn on, causing transistor T3 to drive the light-emitting device L to emit light under the data voltage at node N2. Thus, by controlling the magnitude of the data voltage Vdata, the brightness of the light-emitting device L can be adjusted. For example, increasing the data voltage results in a larger voltage at node N2, leading to a larger current in the light-emitting device L, and consequently, a brighter light-emitting device L.

[0054] However, the step interval of the data voltage output by DDIC to the pixel circuit 1011 is fixed. The pixel circuit cannot display the brightness corresponding to the value between two adjacent values. That is, as mentioned above, the current pixel circuit 1011 can only adjust the brightness of the light-emitting device according to the fixed change range of the data voltage, making the light-emitting device prone to brightness jumps. For example, if the data voltage increases from 2V to 3V, the light-emitting device L can only jump from the brightness corresponding to 2V to the brightness corresponding to 3V, and cannot display the brightness corresponding to the voltage between 2V and 3V.

[0055] Based on this, embodiments of this application provide a pixel circuit, which includes a writing module and a driving transistor. The writing module includes at least two capacitors connected in series. The gate, source, and drain of the driving transistor are connected to the series connection point between the two capacitors. The writing module also receives a data voltage. By adding two capacitors in series to the writing module, the received data voltage can be divided, and the divided data voltage is written to the gate, source, and drain of the driving transistor, controlling the driving transistor to drive the light-emitting device to emit light. Thus, when adjusting the brightness of the light-emitting device, for example, by increasing or decreasing the data voltage according to a fixed change range, the brightness of the light-emitting device can be adjusted according to a value smaller than that change range, enabling the pixel circuit to achieve more precise brightness control.

[0056] Figure 4A schematic diagram of a pixel circuit 1011a according to an embodiment of this application is shown. The pixel circuit 1011a includes transistors T9 to T16, capacitors C2 to C4, and a light-emitting device L. The first terminal of transistor T9 (an example of a first reset transistor in this application) receives a reset voltage Vinit1 (first reset voltage), and its second terminal is connected to one end of capacitor C2 (an example of a second capacitor in this application). The other end of capacitor C2 is node 10, connected to the first terminal of transistor T10 (an example of a second reset transistor in this application). The second terminal of transistor T10 receives the reset voltage Vinit1. The control terminal of transistor T9 receives a scan signal Scan3 (third scan signal), and the control terminal of transistor T10 receives a scan signal Scan4 (fourth scan signal). The control terminal of transistor T11 (an example of a first driving transistor in this application) is node N5, which is the connection point between transistor T9 and capacitor C2. The first terminal of transistor T11 is at node N7 and is connected to the first terminal of transistor T12. The second terminal of transistor T11 is at node N6 and is connected to the first terminal of transistor T13 (an example of a second light-emitting transistor in this application). The second terminal of transistor T12 (an example of a first light-emitting transistor in this application) is connected to power supply VDD (first power supply), and its control terminal is used to receive light emission signal EM1 (first light emission signal). The second terminal of transistor T13 is at node N8 and is connected to the anode of light-emitting device L. Its control terminal is used to receive light emission signal EM2 (second light emission signal). The cathode of light-emitting device L is connected to power supply VSS. Capacitor C3 (an example of a first capacitor in this application) and capacitor C4 (an example of a second capacitor in this application) are connected in series at node N6. The other terminal of capacitor C4 is connected to the other terminal of capacitor C2, and the other terminal of capacitor C3 is at node N9. Node N9 is also connected to the second terminal of transistor T14 (an example of a third reset transistor in this application) and the first terminal of transistor T15 (an example of a first write transistor in this application). The second terminal of transistor T14 is used to receive the reset voltage Vinit2 (second reset voltage), and the control terminal is used to receive the scan signal Scan1 (first scan signal). The first terminal of transistor T15 is used to receive the data voltage Vdata, and the control terminal is used to receive the scan signal Scan5. The first terminal of transistor T16 (an example of the fourth reset transistor of this application) is used to receive the reset voltage Vinit2, the second terminal is connected to the anode of the light-emitting device L, and the control terminal is used to receive the scan signal Scan2 (second scan signal).

[0057] It should be noted that in the embodiments of this application, the control terminal of the transistor refers to the gate, and the first and second terminals of the transistor refer to the source and drain, respectively. The distinction between the source and drain is not made and can be adjusted according to the transistor type (P-type or N-type) and the connection between the transistor and other devices. Furthermore, the back gate electrode of the aforementioned transistor T11 can be electrically connected to the second terminal (e.g., the source) of transistor T11. This connection method can improve the hysteresis performance of the driving transistor T11 and reduce the threshold voltage offset. In other embodiments, the back gate of transistor T11 may not be connected to the second terminal.

[0058] In this circuit, T9, T10, T14, and T16 are reset transistors, T12 and T13 are light-emitting transistors, T11 is a drive transistor, and T15 is a write transistor. The write module may include transistor T15, capacitor C3, and capacitor C4.

[0059] It is understandable that during the writing phase, the data voltage Vdata can be written to node N9 via transistor T15. Due to the coupling effect of capacitor C3, the voltage change of node N9 causes a voltage change of node N6. Since capacitors C3 and C4 are connected in series, node N6 performs a voltage divider on connection point N9, with the voltage divider coefficient being C3 / (C3+C4). Therefore, by adjusting the values ​​of capacitors C3 and C4, the voltage divider on capacitor C3 can be changed, so that the voltage change of node N6 can be less than the voltage change corresponding to the data voltage Vdata, thereby allowing for more precise adjustment of the intensity of light emitted by the light-emitting device L.

[0060] In some embodiments, the light-emitting device L can be an organic light-emitting diode (OLED), and the driving transistor used to drive the light-emitting device L, i.e., transistor T11, can be an N-type transistor made of indium gallium zinc oxide (IGZO) material. Since the manufacturing process of IGZO material is relatively mature and has good uniformity, compared to P-type transistors, it helps to improve the display effect and reduce black spots and uneven color rendering on the screen. Furthermore, it should be noted that this application uses N-type transistors T9 to T16 as an example for illustration, and does not constitute a limitation on the transistor type. That is, in other embodiments of this application, transistors T9 to T16 can also be P-type transistors.

[0061] The following is combined with Figure 5 The waveform diagram illustrates the control timing of the pixel circuit 1011a.

[0062] During the initialization phase t0-t1, the scan signal Scan1 is high, transistor T14 is turned on, and the voltage at node N9 is reset to Vinit2. The scan signal Scan2 is high, transistor T16 is turned on, and the voltage at node N8 is reset to Vinit2. Simultaneously, the light emission signal EM2 is high, transistor T13 is turned on, and the voltage at node N6 is reset to Vinit2. The scan signal Scan3 is high, transistor T9 is turned on, and the voltage at node N5 is reset to Vinit1. The scan signal Scan4 is high, transistor T10 is turned on, and the voltage at node N10 is reset to Vinit1.

[0063] During the compensation phase t1-t2, scan signals Scan1, Scan3, and Scan4 are at high levels. Therefore, transistors T9, T10, and T14 remain on. By controlling the voltage difference between nodes N5 and N6, i.e., the gate-source voltage (Vgs) of transistor T11, the threshold voltage (Vth) is reached, achieving threshold compensation for transistor T11. Specifically, the voltage at node N5 is continuously controlled by transistor T9 at Vinit1. The high level of the light-emitting signal EM1 turns on transistor T12, and transistor T11 is turned on under the voltage difference between nodes N5 and N6 until it turns off when the voltage difference between nodes N5 and N6 reaches Vth. At this time, the voltage at node N6 is Vinit1 - Vth.

[0064] During the write phase t2-t3, the scan signal Scan5 is high, transistor T15 is turned on, and the voltage at node N9 changes from Vinit2 to Vdata. The voltage change is Vdata - Vinit2. As mentioned earlier, since capacitors C3 and C4 are connected in series, node N6 will divide the voltage at node N9. Therefore, the voltage change at node N6 is (Vdata - Vinit2) * C3 / (C3 + C4). That is, the voltage at node N6 changes from Vinit1 - Vth to Vinit1 - Vth + (Vdata - Vinit2) * C3 / (C3 + C4).

[0065] Compared to the above Figure 3 In the pixel circuit 1011 shown, with the voltage of the write node N2 being Vdata during the write phase, the voltage of the write node N6 during the write phase can be adjusted more precisely by adjusting the values ​​of capacitors C3 and C4: Vdata*C3 / (C3+C4), thereby adjusting the intensity of the light emitted by the light-emitting device L more precisely, that is, adjusting the brightness of the pixel circuit display more precisely.

[0066] The period from t3 to t4 is the waiting phase for light emission. During this phase, the light emission signal EM2 is low, so transistor T13 is off, and the light-emitting device L does not emit light. From time t4 onwards, the light emission phase begins. Both light emission signals EM1 and EM2 are high. At this time, transistors T12 and T13 are both on, thus creating a path between power supply VDD and power supply VSS. Transistor T11 drives the light-emitting device L to emit light based on the voltage at node N6, and the current through the light-emitting device L is affected by the voltage difference between nodes N5 and N6.

[0067] In the above embodiment, light-emitting transistors T12 and T13 use different light-emitting signals EM1 / EM2, and they are turned on sequentially. For example, by controlling the pulse rise time of the light-emitting signal EM1 (e.g., Figure 5 The high-level rise time of the signal EM2 precedes the pulse rise time of the EM2 signal. Figure 5 At time t4, transistor T12 is turned on before transistor T13, thus preventing a path from forming between node N6 and power supply VSS if transistor T13 turns on first, which would interfere with the normal light emission of the light-emitting device L. It is understood that this application does not restrict the order in which light-emitting transistors T12 and T13 are turned on, that is, it does not restrict the order of the pulse rise times of light-emitting signals EM2 and EM1. In other embodiments, light-emitting transistors T12 and T13 can be turned on simultaneously, meaning the pulse rise times of light-emitting signals EM2 and EM1 are the same. Alternatively, after writing, transistor T13 can be turned on first via light-emitting signal EM2, and then transistor T12 can be turned on via light-emitting signal EM1, meaning the pulse rise time of light-emitting signal EM2 precedes the pulse rise time of light-emitting signal EM1.

[0068] In the above embodiment, the second terminal of transistor T14 is used to receive the reset voltage Vinit2.

[0069] In other embodiments of this application, the second terminal of transistor T14 can also be used to receive the reset voltage Vinit1. Wherein, if the second terminal of transistor T14 receives the reset voltage Vinit1, the voltage of node N6 during the write phase becomes: Vinit1 - Vth + (Vdata - Vinit1) * C3 / (C3 + C4). Thus, the voltage of node N6 is unaffected by the voltage drop of the reset voltage Vinit2, and is only related to the value of Vinit1.

[0070] In other embodiments of this application, the second terminal of transistor T14 can also be used to receive other reset voltages different from the reset voltages Vinit1 and Vinit2. The smaller the other reset voltage, the smaller the data voltage Vdata; the larger the other reset voltage, the larger the data voltage Vdata. In this way, the range of the data voltage Vdata can be flexibly set, and the data voltage Vdata can be reduced by using a smaller reset voltage to achieve a reduction in the overall power consumption of the pixel circuit 1011a.

[0071] In the above embodiment, the waveform of scan signal Scan2 differs from that of other scan signals. In other embodiments of this application, the waveform of scan signal Scan2 can be the same as that of any one of scan signals Scan4, Scan3, and Scan1. It is only necessary to ensure that transistor T16 is turned on during the initialization phase. At other times, since transistor T13 is turned off under the control of the light-emitting signal EM2, changes in scan signal Scan2 will not affect the normal operation of the circuit. For example, if the waveforms of scan signal Scan2 and Scan signal Scan3 are the same, they can be turned on during the t2-t3 write phase without affecting the normal writing of the data voltage Vdata. It should be noted that the same waveforms here include the same pulse rise / fall time and the same pulse width, i.e., the same pulse duration.

[0072] Figure 6 The figure shows a waveform simulation of the gate-source voltage of transistor T11 under different data voltages Vdata. As can be seen from the figure, the gate-source voltage of transistor T11 in pixel circuit 1011a changes with the data voltage Vdata, and for every 1V change in data voltage Vdata, the gate-source voltage of transistor T11 changes by approximately 0.5V. That is, a 1V change in data voltage results in a 0.5V change in gate-source voltage. In other words, by connecting capacitors C3 and C4 in series, voltage division of the data voltage can be achieved, enabling more precise voltage control.

[0073] Figure 7 The waveform simulation diagram of the current on the light-emitting device L under different data voltages Vdata is shown. As can be seen from the figure, the current on the light-emitting device L in the pixel circuit 1011a changes with the data voltage Vdata, and the larger the data voltage Vdata, the smaller the current. The pixel circuit 1011a can normally perform light emission and brightness adjustment.

[0074] Figure 8 A circuit diagram of a pixel circuit 1011b according to an embodiment of this application is shown. Pixel circuit 1011b and... Figure 4The only difference between pixel circuit 1011a and pixel circuit 1011b is that pixel circuit 1011b does not include transistor T13; that is, pixel circuit 1011b only has one light-emitting transistor. The rest of the circuit structure of pixel circuit 1011b and pixel circuit 1011a is the same, so please refer to the description above, and it will not be repeated here.

[0075] The following is combined Figure 9 The waveform diagram illustrates the control timing of the pixel circuit 1011b.

[0076] During the initialization phase t0-t1, the scan signal Scan1 is high, transistor T14 is turned on, and the voltage at node N9 is reset to Vinit2. The scan signal Scan2 is high, transistor T16 is turned on, and the voltage at node N6 is reset to Vinit2. The scan signal Scan3 is high, transistor T9 is turned on, and the voltage at node N5 is reset to Vinit1. The scan signal Scan4 is high, transistor T10 is turned on, and the voltage at node N10 is reset to Vinit1.

[0077] During the compensation phase t1-t2, scan signals Scan1, Scan3, and Scan4 are at high levels. Therefore, transistors T9, T10, and T14 remain on. By controlling the voltage difference between nodes N5 and N6, i.e., the gate-source voltage (Vgs) of transistor T11, the threshold voltage (Vth) is reached, thus achieving threshold compensation for transistor T11.

[0078] During the write phase t2-t3, the scan signal Scan5 is high, transistor T15 is turned on, and the voltage of node N9 changes from Vinit2 to Vdata. The voltage change is: Vdata-Vinit2. As mentioned before, due to capacitors C3 and C4, node N6 will divide the voltage of node N9, so the voltage change of node N6 is: (Vdata-Vinit2)*C3 / (C3+C4).

[0079] Compared to the above Figure 3 In the pixel circuit 1011 shown, with the voltage of the write node N2 being Vdata during the write phase, the voltage of the write node N6 during the write phase can be adjusted more precisely by adjusting the values ​​of capacitors C3 and C4: Vdata*C3 / (C3+C4), thereby adjusting the intensity of the light emitted by the light-emitting device L more precisely, that is, adjusting the brightness of the pixel circuit display more precisely.

[0080] The period from t3 to t4 is the waiting phase for light emission. During this phase, the light emission signal EM1 is low, so transistor T12 is off, and the light-emitting device L does not emit light. From time t4 onwards, the light emission phase begins. The light emission signal EM1 is high, and transistor T12 is turned on, thus creating a path between power supplies VDD and VSS. Transistor T11 drives the light-emitting device L to emit light based on the voltage at node N6, and the current through the light-emitting device L is affected by the voltage difference between nodes N5 and N6.

[0081] It is understood that in this embodiment, the scan signal Scan2 can only be turned on during the initialization phase. Unlike the pixel circuit 1011a in the previous embodiment, since there is no transistor T13 controlled by the light emission signal EM2, the scan signal Scan2 needs to be turned off during both the compensation and writing phases; otherwise, the voltage of node N6 will be written incorrectly.

[0082] It is understood that the pixel circuit 1011a in the above embodiment includes a transistor T13. By controlling the transistor T13 to turn off through the light-emitting signal EM2, all coupling current pulses in the non-light-emitting phase of the pixel circuit 1011a do not affect the light-emitting device L, thus reducing the interference of coupling on brightness. The pixel circuit 1011b in the above embodiment does not include a transistor T13, which reduces the area occupied by the pixel circuit 1011b, increases the pixel density (pixels per inch, PPI) of the display panel, and improves the sharpness of the displayed image.

[0083] Figure 10A schematic diagram of a pixel circuit 1011c according to an embodiment of this application is shown. The pixel circuit 1011c includes transistors T17-T23, capacitors C5 and C6, and a light-emitting device L. Specifically, transistor T17 (an example of the sixth reset transistor of this application) has its first terminal for receiving a reset voltage Vinit1 (first reset voltage), its second terminal at node N11 connected to one end of capacitor C5 (an example of the fourth capacitor of this application), and its control terminal for receiving a scan signal Scan3 (third scan signal). Transistor T18 (an example of the second write transistor of this application) has its first terminal for receiving a data voltage Vdata, its second terminal at node N14 connected to the other end of capacitor C5, and its control terminal for receiving a scan signal Scan2 (second scan signal). Transistor T20 (an example of the fifth reset transistor of this application) has its first terminal for receiving the reset voltage Vinit1, its second terminal connected to node N14, and its control terminal for receiving a scan signal Scan1 (first scan signal). The control terminal of transistor T21 (an example of a third light-emitting transistor in this application) is used to receive the light-emitting signal EM1, the first terminal is used to receive the power supply VDD (first power supply), and the second terminal is node N13, connected to the first terminal of transistor T22 (an example of a second driving transistor in this application). The control terminal of transistor T22 is connected to node N11, the second terminal is node N12, and it is connected to the second terminal of transistor T23 (an example of a seventh reset transistor in this application), one end of capacitor C6 (an example of a fifth capacitor in this application), and the anode of the light-emitting device L. The other end of capacitor C6 is connected to node N11. The cathode of the light-emitting device L is connected to the power supply VSS (second power supply). The control terminal of transistor T23 is used to receive the scan signal Scan4 (fourth scan signal), and the first terminal is used to receive the reset voltage Vinit2 (second reset voltage).

[0084] It should be noted that in the embodiments of this application, the control terminal of the transistor refers to the gate, and the first terminal and the second terminal of the transistor refer to the source and drain, respectively. The source and drain are not distinguished and can be adjusted according to the type of transistor (P-type or N-type) and the connection between the transistor and other devices. Furthermore, the back gate electrode of the aforementioned transistor T22 can be electrically connected to the second terminal (e.g., the source) of transistor T22. This connection method can improve the hysteresis performance of the driving transistor T22 and reduce the threshold voltage offset. In other embodiments, the back gate of transistor T22 may not be connected to the second terminal.

[0085] In this design, T20, T17, and T23 are reset transistors, T21 is a light-emitting transistor, T22 is a driving transistor, and T18 is a write transistor. The write module may include transistor T18, capacitor C5, and capacitor C6.

[0086] It is understandable that during the writing phase, the data voltage Vdata can be written to node N14 via transistor T18. Due to the coupling effect of capacitor C5, the voltage change of node N14 causes a voltage change of node N11. Since capacitors C5 and C6 are connected in series, node N11 performs a voltage divider on connection point N14, with the voltage divider coefficient being C5 / (C5+C6). Therefore, by adjusting the values ​​of capacitors C5 and C6, the voltage divider on capacitor C5 can be changed, so that the voltage change of node N11 can be less than the voltage change corresponding to the data voltage Vdata, thereby allowing for more precise adjustment of the intensity of light emitted by the light-emitting device L.

[0087] It is understandable that, compared to some solutions, such as the one where the data voltage Vdata is directly written to node N11 (i.e., the control terminal of transistor T22) via transistor T18, the capacitance of transistor T22 itself will divide the data voltage Vdata, resulting in poor uniformity of the pixel circuit. In this embodiment, the data voltage Vdata is written to node N11 via transistor T18 and capacitor C5. That is, the voltage of node N11 is coupled and written through capacitor C5, which can reduce the influence of the capacitance of transistor T22 and improve the uniformity of the pixel circuit.

[0088] In some embodiments, the light-emitting device L can be an organic light-emitting diode (OLED), and the driving transistor used to drive the light-emitting device L, that is, the transistor T22, can be an N-type transistor made of indium gallium zinc oxide (IGZO) material. Since the production process of IGZO material is relatively mature and has good uniformity, it helps to improve the display effect of the picture and reduce the occurrence of black spots and uneven color display on the screen compared with P-type transistors.

[0089] Furthermore, it should be noted that this application uses transistor T21 as a P-type transistor and the rest of T17 to T23 as N-type transistors for illustration, and does not constitute a limitation on the transistor type. Since the internal resistance of a P-type transistor is lower than that of an N-type transistor, the power consumption of a P-type transistor when it is turned on is lower than that of an N-type transistor when it is turned on. When the light-emitting device L emits light, transistor T21 is turned on, which can reduce the circuit power consumption when the light-emitting device L emits light.

[0090] The following is combined Figure 11A The waveform diagram illustrates a control timing of the pixel circuit 1011c.

[0091] During the initialization phase t0-t1, the scan signal Scan1 is high, transistor T20 is turned on, and the voltage at node N14 is reset to Vinit1. The scan signal Scan2 is low, and transistor T18 is turned off. The scan signal Scan3 is high, transistor T17 is turned on, and the voltage at node N11 is reset to Vinit1. The scan signal Scan4 is high, transistor T23 is turned on, and the voltage at node N12 is reset to Vinit2.

[0092] During the compensation phase t1-t2, the scan signal Scan1 is high, and T20 remains on. The threshold voltage (Vth) is reached by controlling the voltage difference between nodes N11 and N12, i.e., the gate-source voltage (Vgs) of transistor T22, thus achieving threshold compensation for transistor T22. At this time, the voltage at node N11 is Vinit1, and the voltage at node N12 becomes Vinit1 - Vth.

[0093] During the write phase t2-t3, the scan signal Scan2 is high, transistor T18 is on, and the data voltage Vdata is written to node N14 through transistor T18. The voltage of node N14 changes from Vinit1 to Vdata, and the voltage change of node N14 is Vdata - Vinit1. Due to the coupling effect of capacitor C5, the voltage change of node N14 causes a voltage change of node N11. Since capacitors C5 and C6 are connected in series, node N11 divides the voltage of node N14. Therefore, the voltage change of node N11 is (Vdata - Vinit1) * C5 / (C5 + C6), and the voltage of node N11 changes from Vinit1 to Vinit1 + (Vdata - Vinit1) * C5 / (C5 + C6). Due to the coupling effect of capacitor C6, node N12 also rises, with the voltage change being (Vdata-Vinit1)*C6 / (C5+C6+Coled), where Coled is the capacitance of the light-emitting device L. The voltage at node N12 changes from Vinit1-Vth to (Vinit1-Vth)+(Vdata-Vinit1)*C6 / (C5+C6+Coled).

[0094] During the light-emitting phase after t4, the light-emitting signal EM1 is at a low level, transistor T21 is turned on, the light-emitting device L is turned on, and the voltage at node N12 changes from (Vinit1-Vth)+(Vdata-Vinit1)*C6 / (C5+C6+Coled) to Voled+VSS, where Voled is the on-state voltage drop of the light-emitting device L, and the voltage change at node N12 is Voled+VSS-[(Vinit1-Vth)+(Vdata-Vinit1)*C6 / (C5+C6+Coled)]. Due to the coupling effect of capacitor C6, the voltage at node N11 changes from Vinit1+(Vdata-Vinit1)*C5 / (C5+C6) to Vinit1+(Vdata-Vinit1)*C5 / (C5+C6)+Voled+VSS-[(Vinit1-Vth)+(Vdata-Vinit1)*C6 / (C5+C6+Coled)]=(Vdata-Vinit1)*C5 / (C5+C6)-(Vdata-Vinit1)*C6 / (C5+C6+Coled)+Voled+VSS+Vth. The gate-source voltage Vgs of transistor T22 is equal to the difference between the voltage at node N11 and the voltage at node N12, Voled + VSS, i.e., Vgs = (Vdata - Vinit1) * C5 / (C5 + C6) - (Vdata - Vinit1) * C6 / (C5 + C6 + Coled) + Vth.

[0095] The luminous intensity of the light-emitting device L is determined by its driving current, which in turn (i.e., the drain-source current of transistor T22) is related to the voltage of node N11 during the write phase. Specifically, the driving current of the light-emitting device L satisfies:

[0096] Ids=1 / 2*k*(Vgs-Vth)^2=1 / 2*k*[(Vdata-Vinit1)*C2 / (C1+C2)-(Vdata-Vinit1)*C1 / (C1+C2+Coled)]^2

[0097] Where, k = μ n C ox W / L, μ n For electron mobility, C oxHere, W represents the gate oxide capacitance per unit area, W is the channel width, and L is the channel length. The driving current of the light-emitting device L is independent of the threshold voltage Vth of transistor T22, therefore, the brightness of the light-emitting device L is independent of the threshold voltage Vth of transistor T22. Furthermore, the driving current of the light-emitting device L varies with the data voltage Vdata; as the data voltage Vdata increases, the driving current of the light-emitting device L also increases, and as the data voltage Vdata decreases, the driving current of the light-emitting device L also decreases.

[0098] As can be seen, compared to the above... Figure 3 In the pixel circuit 1011 shown, with the voltage Vdata at the write node N2 during the write phase, the pixel circuit 1011c of this embodiment can more precisely adjust the voltage Vdata*C5 / (C5+C6)-Vdata*C6 / (C5+C6+Coled) at the write node N11 during the write phase by adjusting the values ​​of capacitors C5 and C6. The ratio is C5 / (C5+C6)-C6 / (C5+C6+Coled). This allows for more precise adjustment of the intensity of the light emitted by the light-emitting device L, i.e., more precise adjustment of the grayscale displayed by the pixel circuit.

[0099] Figure 11B Another waveform diagram of some signals in pixel circuit 1011c is shown. Figure 11B and Figure 11A The only difference is that, Figure 11A The waveforms of the scanning signals Scan3 and Scan4 are the same, while Figure 11B The waveforms of scan signals Scan3 and Scan4 are different, but the same as those of scan signal Scan1. Correspondingly, during the compensation phase t1-t2, scan signal Scan3 is at a high level, and T17 is turned on, which stabilizes the voltage of node N11 at Vinit1, preventing the voltage of node N11 from floating and ensuring good uniformity of the pixel circuit. Figure 11B Changes in the Scan3 signal do not affect the normal operation of the circuit; the remaining stages can be referred to the above. Figure 11A The relevant descriptions will not be repeated here.

[0100] Figure 11C Another waveform diagram of some signals in pixel circuit 1011c is shown. Figure 11C and Figure 11B The only difference is that, Figure 11B The scan signals Scan1 and Scan3 are the same, while Figure 11CThe scanning signal Scan1 is different from Scan3, but the same as Scan4. Correspondingly, during the compensation phase t1-t2, Scan3 is at a high level, transistor T17 is turned on, and the voltage of node N11 remains at Vinit1, stabilizing the voltage of node N11 at Vinit1 and preventing the voltage of node N11 from floating, thus ensuring good uniformity of the pixel circuit. Figure 11C Changes in the Scan1 signal do not affect the normal operation of the circuit; the remaining stages can be referred to the above. Figure 11A The relevant descriptions will not be repeated here.

[0101] It should be noted that the scanning signals Scan1, Scan3 and Scan4 described in the embodiments of this application may have various different timing variations, all of which can ensure that the voltage of node N11 is Vinit1 during the compensation stage of t1-t2, and are not limited to those shown above.

[0102] Figure 12A A schematic diagram of a pixel circuit 1011d according to an embodiment of this application is shown. Pixel circuit 1011d is based on pixel circuit 1011c described above, with the addition of capacitor C7 (an example of the sixth capacitor in this application). One end of capacitor C7 is connected to power supply VDD, and the other end is connected to node N12. The remaining circuit structure of pixel circuit 1011d is the same as that of pixel circuit 1011c, and therefore can be referred to the description above, and will not be repeated here.

[0103] Figure 12B A schematic diagram of a pixel circuit 1011e according to an embodiment of this application is shown. The only difference between pixel circuit 1011e and pixel circuit 1011d is that one end of capacitor C7 is not connected to the power supply VDD, but is connected to any one of the reset voltage Vinit1, reset voltage Vinit2, and power supply VSS. The remaining circuit structure of pixel circuit 1011e can be referred to the description of pixel circuit 1011c above, and will not be repeated here.

[0104] It can be understood that in pixel circuit 1011d or pixel circuit 1011e, the writing module includes transistor T18, capacitor C5, capacitor C6, and capacitor C7. Thus, during the writing phase, the data voltage Vdata can be written to node N14 via transistor T18. Due to the coupling effect of capacitor C5, the voltage change at node N14 causes a voltage change at node N11. Since capacitors C5, C6, and C7 are connected in series, node N11 performs a voltage divider on connection point N14, with a voltage divider coefficient of C5 / (C5+C6+C7). Therefore, by adjusting the values ​​of capacitors C5, C6, and C7, the voltage divider on capacitor C5 can be changed, allowing the voltage change at node N11 to be less than the voltage change corresponding to the data voltage Vdata. This enables more precise adjustment of the intensity of the light emitted by the light-emitting device L.

[0105] It should be noted that pixel circuits 1011d and 1011e can both refer to [the relevant technology / mechanism]. Figures 11A to 11C The control timing completes the reset, compensation, writing, and light emission stages, which will not be elaborated further.

[0106] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0107] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0108] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0109] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0110] The embodiments of this application are illustrated above, and those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Although the description of this application is presented in conjunction with some embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of describing the application in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of this application. This application may also be implemented without using these details. In addition, in order to avoid confusion or obscuring the focus of this application, some specific details have been omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0111] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A pixel circuit, characterized in that, It includes a first light-emitting transistor, a first driving transistor, a first writing transistor, a first capacitor, a second capacitor, and a light-emitting device; The first terminal of the first driving transistor is connected to one terminal of the first light-emitting transistor, the other terminal of the first light-emitting transistor is connected to the first power supply, and the second terminal of the first driving transistor is connected to the light-emitting device. The first terminal of the first write transistor is used to receive data voltage, and the second terminal of the first write transistor is connected to one end of the first capacitor. The other end of the first capacitor is connected in series with the second capacitor, and the other end of the first capacitor is also connected to the second end of the first driving transistor; Wherein, the first terminal is the source and the second terminal is the drain; or, the first terminal is the drain and the second terminal is the source.

2. The pixel circuit according to claim 1, characterized in that, It also includes a second light-emitting transistor; The second terminal of the first driving transistor is connected to the light-emitting device through the second light-emitting transistor.

3. The pixel circuit according to claim 1 or 2, characterized in that, Also includes: A first reset transistor, wherein a first terminal of the first reset transistor is used to receive a first reset voltage, and a second terminal of the first reset transistor is connected to the control terminal of the first drive transistor; A third capacitor and a second reset transistor are connected in series. One end of the third capacitor is connected to the control terminal of the first driving transistor, and the other end of the third capacitor is connected to the second capacitor. The third capacitor, the second capacitor, and the first capacitor are connected in series. The first terminal of the second reset transistor is connected to the other terminal of the third capacitor, and the second terminal of the second reset transistor is used to receive the first reset voltage. A third reset transistor, wherein the first terminal of the third reset transistor is connected to one terminal of the first capacitor, and the second terminal of the third reset transistor is used to receive a second reset voltage; A fourth reset transistor, wherein the first terminal of the fourth reset transistor is used to receive the second reset voltage, and the second terminal of the fourth reset transistor is connected to the light-emitting device.

4. The pixel circuit according to claim 2, characterized in that, The control terminal of the first light-emitting transistor is used to receive the first light-emitting signal. The control terminal of the second light-emitting transistor is used to receive the second light-emitting signal. The first light-emitting transistor and the second light-emitting transistor are turned on simultaneously or sequentially based on the first light-emitting signal and the second light-emitting signal.

5. The pixel circuit according to claim 4, characterized in that, The first light-emitting transistor and the second light-emitting transistor are turned on simultaneously based on the first light-emitting signal and the second light-emitting signal, and the pulse rise time of the first light-emitting signal and the second light-emitting signal is the same; The first light-emitting transistor and the second light-emitting transistor are turned on sequentially based on the first light-emitting signal and the second light-emitting signal, respectively, with the rise time of the pulse of the first light-emitting signal preceding the rise time of the pulse of the second light-emitting signal.

6. The pixel circuit according to claim 3, characterized in that, The second terminal of the third reset transistor is used to receive the first reset voltage, or the second terminal of the third reset transistor is used to receive the third reset voltage. The third reset voltage, the second reset voltage, and the first reset voltage are all different from each other.

7. The pixel circuit according to claim 3, characterized in that, The control terminal of the third reset transistor is used to receive the first scan signal. The control terminal of the fourth reset transistor is used to receive the second scan signal. The control terminal of the first reset transistor is used to receive the third scan signal. The control terminal of the second reset transistor is used to receive the fourth scan signal. The third reset transistor, the fourth reset transistor, the first reset transistor, and the second reset transistor are simultaneously turned on based on the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal, and The third reset transistor and the fourth reset transistor are simultaneously turned off based on the first scan signal and the second scan signal, or the fourth reset transistor and the first reset transistor are simultaneously turned off based on the second scan signal and the third scan signal, or the fourth reset transistor and the second reset transistor are simultaneously turned off based on the second scan signal and the fourth scan signal.

8. The pixel circuit according to any one of claims 2, 4-7, characterized in that, The first voltage corresponds to the change in the data voltage, the second voltage corresponds to the change in the gate-source voltage of the first driving transistor, and the ratio between the second voltage and the first voltage is related to the capacitance values ​​of the first capacitor and the second capacitor.

9. The pixel circuit according to any one of claims 2, 4-7, characterized in that, The first driving transistor is an N-type transistor.

10. A pixel circuit, characterized in that, It includes a third light-emitting transistor, a second driving transistor, a second writing transistor, a fourth capacitor, a fifth capacitor, and a light-emitting device; The first end of the second driving transistor is connected to one end of the third light-emitting transistor, the other end of the third light-emitting transistor is connected to the first power supply, and the second end of the second driving transistor is connected to the light-emitting device. The first terminal of the second write transistor is used to receive data voltage, and the second terminal of the second write transistor is connected to one end of the fourth capacitor; The other end of the fourth capacitor is connected to one end of the fifth capacitor and also to the control terminal of the second driving transistor; the other end of the fifth capacitor is connected to the second terminal of the second driving transistor. Wherein, the first terminal is the source and the second terminal is the drain; or, the first terminal is the drain and the second terminal is the source.

11. The pixel circuit according to claim 10, characterized in that, Also includes: A fifth reset transistor, wherein the first terminal of the fifth reset transistor is used to receive a first reset voltage, and the second terminal of the fifth reset transistor is connected to one terminal of the fourth capacitor; A sixth reset transistor, the first terminal of which is used to receive the first reset voltage, and the second terminal of the fifth reset transistor is connected to the other terminal of the fourth capacitor; A seventh reset transistor, the first terminal of which is used to receive a second reset voltage, and the second terminal of which is connected to the light-emitting device.

12. The pixel circuit according to claim 11, characterized in that, Also includes: A sixth capacitor, one end of which is connected to the second terminal of the second driving transistor, and the other end of which is connected to the first power supply or the second power supply; or, the other end of which is used to receive the first reset voltage or the second reset voltage.

13. The pixel circuit according to claim 11 or 12, characterized in that, The control terminal of the fifth reset transistor is used to receive the first scan signal. The control terminal of the sixth reset transistor is used to receive the third scan signal. The control terminal of the seventh reset transistor is used to receive the fourth scan signal. The fifth reset transistor, the sixth reset transistor, and the seventh reset transistor are simultaneously turned on based on the first scan signal, the third scan signal, and the fourth scan signal, and The sixth reset transistor and the seventh reset transistor are simultaneously turned off based on the third scan signal and the fourth scan signal, or the sixth reset transistor and the fifth reset transistor are simultaneously turned off based on the third scan signal and the first scan signal, or the fifth reset transistor and the seventh reset transistor are simultaneously turned off based on the first scan signal and the fourth scan signal.

14. The pixel circuit according to any one of claims 10-12, characterized in that, The change in the data voltage corresponds to the third voltage, and the change in the gate-source voltage of the second driving transistor is the fourth voltage. The ratio between the fourth voltage and the third voltage is related to the capacitance values ​​of the fourth capacitor and the fifth capacitor.

15. The pixel circuit according to any one of claims 10-12, characterized in that, The second driving transistor is an N-type transistor.

16. A display panel, characterized in that, It includes a plurality of pixel circuits as described in any one of claims 1-15.

17. An electronic device, characterized in that, It includes a display panel, the display panel comprising a plurality of pixel circuits as claimed in any one of claims 1-15.

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