Asynchronous signal processing circuit and storage device
By using the state determination circuit and signal acquisition circuit in the asynchronous signal processing circuit, the problem of signal acquisition distortion during asynchronous signal updates is solved, and the steady-state signal can be accurately acquired before and after the signal update, thus improving the accuracy of signal acquisition.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN XINCUN SEMICONDUCTOR CO LTD
- Filing Date
- 2025-11-17
- Publication Date
- 2026-04-21
AI Technical Summary
In existing technologies, the mismatch between the setup time and acquisition timing of asynchronous signals during updates leads to signal acquisition distortion and reduces the accuracy of signal acquisition.
An asynchronous signal processing circuit is adopted, including a state determination circuit and a signal acquisition circuit. By acquiring the target input signal at different state times of the asynchronous signal, it is ensured that the signal in a stable state is acquired before and after the signal update. By using the combination of the state determination circuit and the signal acquisition circuit, an accurate target output signal is output.
It improves the accuracy of signal acquisition, reduces the possibility of signal distortion, and ensures that the latest stable state signal is output under any circumstances.
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Figure CN121905231A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal detection technology, and in particular to asynchronous signal processing circuits and storage devices. Background Technology
[0002] In the prior art, when acquiring asynchronous signals in a system, D flip-flops or other types of flip-flops are usually used to acquire and output the acquired asynchronous signals.
[0003] The drawback of the existing technology is that, due to the influence of the establishment time of the asynchronous signal in the trigger after the update and / or the timing of the trigger receiving the acquisition indication signal, there is a high probability that the signal to be acquired may fail to be established or may be acquired before it is fully established during the update process, resulting in distortion of the acquired signal and low accuracy of signal acquisition. Summary of the Invention
[0004] The main technical problem addressed in this application is how to improve the accuracy of signal acquisition.
[0005] To address the aforementioned technical problems, the first technical solution adopted in this application is: an asynchronous signal processing circuit, comprising: a state determination circuit, configured to determine the current state of a state indication signal in response to receiving a collection indication signal; wherein the state indication signal switches from a second state to a first state at a first moment, and switches from the first state to the second state at a second moment, the first moment being before the target input signal is updated, and the second moment being after the target input signal is updated; and a signal acquisition circuit, configured to output a target output signal based on the target input signal acquired at the first moment in response to receiving the collection indication signal and the current state of the state indication signal being the first state, and / or, output a target output signal based on the target input signal acquired at the second moment in response to receiving the collection indication signal and the current state of the state indication signal being the second state.
[0006] The signal acquisition circuit includes: a first acquisition circuit, used to update its output first acquisition signal based on the target input signal acquired at each first moment; a second acquisition circuit, used to update its output second acquisition signal based on the target input signal acquired at each second moment; and a third acquisition circuit, used to output a target output signal based on the first acquisition signal in response to receiving an acquisition indication signal and the current state of the state indication signal being a first state, and / or, in response to receiving an acquisition indication signal and the current state of the state indication signal being a second state, output a target output signal based on the second acquisition signal.
[0007] The third acquisition circuit includes: a switching circuit, which is connected to the first acquisition circuit and the second acquisition circuit respectively; and an output circuit, which is connected to the switching circuit. The switching circuit is used to send a first acquisition signal to the output circuit in response to the current state of the status indication signal being the first state, and to send a second acquisition signal to the output circuit in response to the current state of the status indication signal being the second state. The output circuit is used to output a target output signal based on the received first acquisition signal or second acquisition signal in response to receiving the acquisition indication signal.
[0008] The first acquisition circuit includes: a first flip-flop, the input of which is used to receive a target input signal, the clock terminal of which is used to receive a status indication signal, and the output of which is used to update its output of a first acquisition signal based on the received target input signal when the status indication signal switches from a second state to a first state; and / or, the second acquisition circuit includes: a second flip-flop, the input of which is used to receive a target input signal, the clock terminal of which is used to receive a status indication signal, and the output of which is used to update its output of a second acquisition signal based on the received target input signal when the status indication signal switches from a first state to a second state.
[0009] The state determination circuit is used to sample the state indication signal according to the acquisition indication signal, and output the current state signal of the first state in response to the current state of the state indication signal being a first state; and to sample the state indication signal according to the acquisition indication signal, and output the current state signal of the second state in response to the current state of the state indication signal being a second state; the switching circuit includes a data selector, used to send a first acquisition signal to the output circuit in response to receiving the current state signal of the first state, and to send a second acquisition signal to the output circuit in response to receiving the current state signal of the second state.
[0010] The output circuit includes a third flip-flop, the input of which is used to receive a first acquisition signal or a second acquisition signal, the clock terminal of which is used to receive an acquisition indication signal through a first delay, and the output of which, upon receiving the delayed acquisition indication signal, updates its target output signal based on the received first acquisition signal or second acquisition signal.
[0011] The delay duration of the first delay unit is less than the duration between the first and second moments corresponding to a single update.
[0012] The delay duration of the first delay unit is greater than the setup time of the current state signal generated by the state determination circuit to characterize the state indication signal.
[0013] The state determination circuit includes: a fourth flip-flop, the input of which is used to receive a state indication signal, and the clock terminal of which is used to receive a data acquisition indication signal; and a fifth flip-flop, the input of which is used to receive the signal output by the output terminal of the fourth flip-flop, the clock terminal of which is used to receive the data acquisition indication signal delayed by the second delay unit, and the output terminal of which is used to output a current state signal to characterize the current state of the state indication signal.
[0014] The first moment is before the signal establishment period when the target input signal is updated, and the second moment is after the signal establishment period when the target input signal is updated.
[0015] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: a storage device, including the above-mentioned asynchronous signal processing circuit.
[0016] The storage device also includes a mode register; the target output signal is used as an output in response to a mode register set read instruction and is saved to the mode register.
[0017] The beneficial effects of this application are as follows: Unlike the prior art, the asynchronous signal processing circuit in this application includes a state determination circuit and a signal acquisition circuit. The state determination circuit determines the current state of the state indication signal in response to receiving an acquisition indication signal. The state indication signal switches from a second state to a first state at a first moment and from the first state to the second state at a second moment. The first moment occurs before the target input signal is updated, and the second moment occurs after the target input signal is updated. The signal acquisition circuit outputs a target output signal based on the target input signal acquired at the first moment, in response to receiving the acquisition indication signal and the current state of the state indication signal being the first state. And / or, in response to receiving the acquisition indication signal and the current state of the state indication signal being the second state, it outputs a target output signal based on the target input signal acquired at the second moment. Based on the above method, relatively accurate target input signals in a stable state can be acquired at two time points, before and after the target input signal is updated. When the state indicator signal is in the first state, it is determined that the target input signal may be in the update period, and the target input signal acquired at the first time point can be used as the target output signal. When the state indicator signal is in the second state, it is determined that the target input signal is not in the update period, and the target input signal acquired at the second time point can be used as the target output signal. Thus, under any circumstances, the latest acquired relatively accurate target input signal in a stable state can be used as the target output signal, thereby reducing the possibility of signal distortion and improving the accuracy of signal acquisition. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram of one embodiment of the asynchronous signal processing circuit of this application.
[0020] Figure 2 This is a waveform diagram of one embodiment of the signal waveform of this application.
[0021] Figure 3 This is a second schematic diagram of an embodiment of the asynchronous signal processing circuit of this application.
[0022] Figure 4 This is the third schematic diagram of an embodiment of the asynchronous signal processing circuit of this application.
[0023] Figure 5 This is the fourth schematic diagram of an embodiment of the asynchronous signal processing circuit of this application.
[0024] Figure 6 This is a schematic diagram of the structure of an embodiment of the storage device of this application.
[0025] Reference numerals in the attached figures: 1. State determination circuit; 11. Fourth flip-flop; 12. Fifth flip-flop; 2. Signal acquisition circuit; 21. First acquisition circuit; 211. First flip-flop; 22. Second acquisition circuit; 221. Second flip-flop; 23. Third acquisition circuit; 231. Data selector; 232. Third flip-flop; 3. First delay unit; 4. Second delay unit; 50. Storage device; 51. Asynchronous signal processing circuit. Detailed Implementation
[0026] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.
[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "setting," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or a connection through an intermediate medium. Those skilled in the art will understand the specific meanings of the above terms within the context of this application.
[0029] In the prior art, when acquiring asynchronous signals in a system, D flip-flops or other types of flip-flops are usually used to acquire and output the acquired asynchronous signals.
[0030] The drawback of the existing technology is that, due to the influence of the establishment time of the asynchronous signal in the trigger after the update and / or the timing of the trigger receiving the acquisition indication signal, there is a high probability that the signal to be acquired may fail to be established or may be acquired before it is fully established during the update process, resulting in distortion of the acquired signal and low accuracy of signal acquisition.
[0031] For example, in traditional technology, two cascaded D flip-flops are typically used to acquire the target input signal. A corresponding acquisition indicator signal serves as a clock signal to control the acquisition of the target input signal by the two D flip-flops, thereby outputting the corresponding target output signal. However, due to the timing of the acquisition indicator signal, the target input signal may be updated before the first-stage D flip-flop has established its output signal based on the target input signal. That is, if the first-stage D flip-flop acquires the target input signal precisely when it is in a metastable state, the output signal of the first-stage D flip-flop is prone to unpredictable changes (it may be 0 or 1). This can easily lead to distortion of the target output signal output by the second-stage D flip-flop based on the signal output by the first-stage D flip-flop. Therefore, the signal acquisition accuracy in traditional technology is relatively poor.
[0032] In one example, the target input signal may specifically refer to the update rate signal. The update rate signal is used to instruct the storage cells in the storage device to update at a preset rate. The corresponding update rate is usually determined based on the temperature of the chip in the storage device. The lower the temperature, the better the maintenance performance of the storage cells, and the lower the required update rate. Conversely, the higher the temperature, the worse the maintenance performance of the storage cells, and the higher the required update rate, in order to ensure the normal operation of the storage device. If the acquired signal is distorted when reading the update rate signal, it may easily lead to storage performance failure of the storage device and affect normal storage operations.
[0033] In other examples, the target input signal can also be any signal that is asynchronous with the clock signal in the corresponding electronic device, such as temperature acquisition signal, humidity acquisition signal, electromagnetic interference acquisition signal, etc., without limitation here.
[0034] Specifically, the storage device can be LPDDR4 (Low Power Double Data Rate 4) or other types of memory devices. The target output signal can be a signal that needs to be read from the MR register of the MRS instruction (Model) in LPDDR4. The target output signal can be obtained by sampling the target input signal by the asynchronous signal processing circuit under the instruction of the MRS instruction. The MRS instruction can be a read instruction or a write instruction. For example, the target input signal can be the update rate signal mentioned above, which can be used to indicate the update rate of the corresponding memory device.
[0035] This application proposes an asynchronous signal processing circuit, see [link to relevant documentation] Figure 1 , Figure 1 This is a schematic diagram of one embodiment of the asynchronous signal processing circuit of this application, as shown below. Figure 1 As shown, the asynchronous signal processing circuit includes a state determination circuit 1 and a signal acquisition circuit 2.
[0036] The state determination circuit 1 is used to determine the current state of the state indication signal in response to receiving the acquisition indication signal.
[0037] Specifically, the state indication signal switches from the second state to the first state at a first moment, and then switches from the first state to the second state at a second moment. The first moment occurs before the target input signal is updated, and the second moment occurs after the target input signal is updated.
[0038] See Figure 2 , Figure 2 This is a waveform diagram of one embodiment of the signal waveform of this application, as shown below. Figure 2As shown, UPD is a status indicator signal. In this example, the first state is a high level state and the second state is a low level state. SAMPLE_CK is a acquisition indicator signal, and UPD_ENB is a signal used to characterize the current state of the status indicator signal UPD. After detecting the pulse signal of the acquisition indicator signal SAMPLE_CK, if the current state of the status indicator signal UPD is a high level state, UPD_ENB can be controlled to switch to the first state signal (i.e., a high level signal). If the current state of the status indicator signal UPD is a low level state, UPD_ENB can be controlled to switch to the second state signal (i.e., a low level signal) to characterize the current state of the status indicator signal UPD.
[0039] The signal acquisition circuit 2 is used to respond to receiving an acquisition instruction signal and the current state of the status instruction signal is a first state, and output a target output signal based on the target input signal acquired at the first time moment, and / or, respond to receiving an acquisition instruction signal and the current state of the status instruction signal is a second state, and output a target output signal based on the target input signal acquired at the second time moment.
[0040] Specifically, the target input signal can be a signal that updates its own data once at a preset interval, such as an update rate signal or a temperature acquisition signal.
[0041] like Figure 2 As shown, DATA is the target input signal, and DATA_VALID is the target output signal. Specifically, the target input signal DATA can be the signal that the asynchronous signal processing circuit needs to sample, while the target output signal DATA_VALID can be the signal obtained by the asynchronous signal processing circuit sampling the target input signal DATA.
[0042] When the target input signal DATA switches from a low level to a high level (rising edge), the target input signal DATA has not yet been updated. The signal acquisition circuit 2 can acquire the target input signal DATA to obtain a stable and accurate signal before the target input signal DATA is updated. When the target input signal DATA switches from a high level to a low level (falling edge), the target input signal DATA has been updated. The signal acquisition circuit 2 can acquire the target input signal DATA to obtain a stable and accurate signal after the target input signal DATA is updated.
[0043] The signal acquisition circuit 2 can receive the signal mentioned above used to characterize the current state of the state indicator signal UPD. If the received signal is a first state signal, it can be determined that the current state of the state indicator signal UPD is the first state. When the state indicator signal UPD is in the first state, the target input signal DATA may be in the process of updating. Therefore, at this time, the stable and accurate signal of the latest acquired target input signal DATA before the update can be output as the target output signal DATA_VALID. Furthermore, if the received signal is a second state signal, it can be determined that the current state of the state indicator signal UPD is the second state. When the state indicator signal UPD is in the second state, the target input signal DATA has been updated. Therefore, at this time, the stable and accurate signal of the latest acquired target input signal DATA after the update can be output as the target output signal DATA_VALID.
[0044] Based on the above approach, since the signals that may be output as the target output signal DATA_VALID are all signals acquired from the target input signal DATA before or after the target input signal DATA is updated, the possibility of insufficient signal establishment time or other faults in the corresponding devices due to the conflict between the timing of the target input signal DATA update and the timing of the acquisition indication signal SAMPLE_CK can be reduced. This reduces the possibility of errors in the acquired target output signal DATA_VALID due to insufficient signal establishment time or other faults in the corresponding devices.
[0045] In summary, this reduces the possibility of signal distortion and improves the accuracy of signal acquisition.
[0046] Unlike existing technologies, the asynchronous signal processing circuit in this application includes a state determination circuit and a signal acquisition circuit. The state determination circuit determines the current state of the state indication signal in response to receiving an acquisition indication signal. The state indication signal switches from a second state to a first state at a first moment and from the first state to the second state at a second moment. The first moment occurs before the target input signal is updated, and the second moment occurs after the target input signal is updated. The signal acquisition circuit outputs a target output signal based on the target input signal acquired at the first moment, in response to receiving the acquisition indication signal and the current state of the state indication signal being the first state. And / or, in response to receiving the acquisition indication signal and the current state of the state indication signal being the second state, it outputs a target output signal based on the target input signal acquired at the second moment. Based on the above method, relatively accurate target input signals in a stable state can be acquired at two time points, before and after the target input signal is updated. When the state indicator signal is in the first state, it is determined that the target input signal may be in the update period, and the target input signal acquired at the first time point can be used as the target output signal. When the state indicator signal is in the second state, it is determined that the target input signal is not in the update period, and the target input signal acquired at the second time point can be used as the target output signal. Thus, under any circumstances, the latest acquired relatively accurate target input signal in a stable state can be used as the target output signal, thereby reducing the possibility of signal distortion and improving the accuracy of signal acquisition.
[0047] In one embodiment, see Figure 3 , Figure 3 This is a second schematic diagram of an embodiment of the asynchronous signal processing circuit of this application, as shown below. Figure 3 As shown, the signal acquisition circuit 2 includes a first acquisition circuit 21, a second acquisition circuit 22, and a third acquisition circuit 23.
[0048] The first acquisition circuit 21 is used to update its output first acquisition signal based on the target input signal acquired at each first moment.
[0049] The second acquisition circuit 22 is used to update its output second acquisition signal based on the target input signal acquired at each second time moment.
[0050] The third acquisition circuit 23 is used to output a target output signal based on the first acquisition signal in response to receiving an acquisition indication signal and the current state of the status indication signal being a first state, and / or to output a target output signal based on the second acquisition signal in response to receiving an acquisition indication signal and the current state of the status indication signal being a second state.
[0051] Specifically, the first acquisition circuit 21 can acquire the target input signal DATA when the rising edge of the status indication signal UPD is detected, and output the first acquisition signal DATA_PRE before the target input signal DATA is updated.
[0052] Specifically, the second acquisition circuit 22 can acquire the target input signal DATA when the falling edge of the status indication signal UPD is detected, and output the second acquisition signal DATA_POST after the target input signal DATA is updated.
[0053] The third acquisition circuit 23 can respond to receiving the acquisition indication signal SAMPLE_CK and the current state signal UPD_ENB used to characterize the state indication signal UPD being a first state signal, by outputting the first acquisition signal DATA_PRE before the target input signal DATA is updated as the target output signal DATA_VALID. Furthermore, in response to receiving the acquisition indication signal SAMPLE_CK and the current state signal UPD_ENB used to characterize the state indication signal UPD being a second state signal, by outputting the second acquisition signal DATA_POST after the target input signal DATA is updated as the target output signal DATA_VALID.
[0054] Based on the above method, it is possible to output the latest, stable, and relatively accurate target input signal as the target output signal under any circumstances, thereby reducing the possibility of signal distortion and improving the accuracy of signal acquisition.
[0055] Optionally, see Figure 4 , Figure 4 This is a third schematic diagram of an embodiment of the asynchronous signal processing circuit of this application, as shown below. Figure 4 As shown, the first acquisition circuit 21 includes a first flip-flop 211 and a second flip-flop 221.
[0056] The input terminal of the first flip-flop 211 is used to receive the target input signal, the clock terminal of the first flip-flop 211 is used to receive the status indication signal, and the output terminal of the first flip-flop 211 is used to update its output first acquisition signal based on the received target input signal when the status indication signal switches from the second state to the first state.
[0057] And / or, The second acquisition circuit 22 includes: The input terminal of the second flip-flop 221 is used to receive the target input signal, the clock terminal of the second flip-flop 221 is used to receive the status indication signal, and the output terminal of the second flip-flop 221 is used to update its output second acquisition signal based on the received target input signal when the status indication signal switches from the first state to the second state.
[0058] Specifically, assuming the first state is a high-level state and the second state is a low-level state, the first flip-flop 211 can be a rising-edge triggered D flip-flop, and the second flip-flop 221 can be a falling-edge triggered D flip-flop.
[0059] Based on the above method, it is possible to output the latest, stable, and relatively accurate target input signal as the target output signal under any circumstances, thereby reducing the possibility of signal distortion and improving the accuracy of signal acquisition.
[0060] Optionally, the third acquisition circuit 23 includes a switching circuit and an output circuit.
[0061] The switching circuit is connected to the first acquisition circuit 21 and the second acquisition circuit 22 respectively.
[0062] The output circuit is connected to the switching circuit. The switching circuit is used to send a first acquisition signal to the output circuit in response to the current state of the status indication signal being a first state, and to send a second acquisition signal to the output circuit in response to the current state of the status indication signal being a second state. The output circuit is used to output a target output signal based on the received first acquisition signal or second acquisition signal in response to receiving the acquisition indication signal.
[0063] Specifically, in one example, such as Figure 4 As shown, the state determination circuit 1 is used to sample the state indication signal UPD according to the acquisition indication signal SAMPLE_CK, and output the current state signal UPD_ENB of the first state in response to the current state of the state indication signal UPD being the first state, and to sample the state indication signal UPD according to the acquisition indication signal SAMPLE_CK, and output the current state signal UPD_ENB of the second state in response to the current state of the state indication signal UPD being the second state.
[0064] The switching circuit includes a data selector 231, which is used to send a first acquisition signal to the output circuit in response to receiving a current status signal UPD_ENB of a first state, and to send a second acquisition signal to the output circuit in response to receiving a current status signal UPD_ENB of a second state.
[0065] Assuming the first state is a high level state, i.e. "1", and the second state is a low level state, i.e. "0", then when the driver terminal of the data selector 231 receives "1", it selects to output the output signal of the first flip-flop 211, and when the driver terminal of the data selector 231 receives "0", it selects to output the output signal of the second flip-flop 221.
[0066] In another example, such as Figure 4 As shown, the output circuit includes a third flip-flop 232. The input terminal of the third flip-flop 232 is used to receive a first acquisition signal or a second acquisition signal. The clock terminal of the third flip-flop 232 is used to receive an acquisition indication signal through a first delay unit 3. The output terminal of the third flip-flop 232 is used to update its target output signal based on the received first acquisition signal or second acquisition signal when it receives the acquisition indication signal delayed by the first delay unit 3.
[0067] By utilizing the first delay timer 3, it is ensured that the state determination circuit 1 outputs a corresponding current state signal UPD_ENB to characterize the state indication signal UPD based on the acquisition indication signal SAMPLE_CK. This allows the data selector 231 to select one of the output signals of the first flip-flop 211 and the second flip-flop 221 as its selected output signal DATA_IN after receiving the current state signal UPD_ENB and determining the current state of the state indication signal UPD. Consequently, the third flip-flop 232, after receiving the selected output signal DATA_IN generated according to the acquisition indication signal SAMPLE_CK, outputs the target output signal DATA_VALID based on the selected output signal DATA_IN. This reduces the possibility that the third flip-flop 232 might prematurely output the incorrect target output signal DATA_VALID before receiving the selected output signal DATA_IN generated according to the current acquisition indication signal SAMPLE_CK, further improving the accuracy of signal acquisition.
[0068] Based on the above method, it is possible to output the latest, stable, and relatively accurate target input signal as the target output signal under any circumstances, thereby reducing the possibility of signal distortion and improving the accuracy of signal acquisition.
[0069] Furthermore, the delay duration of the first delayer 3 is less than the duration between the first and second moments corresponding to a single update.
[0070] Specifically, such as Figure 2As shown, during the second high-level state of the status indicator signal UPD, since the timing of the acquisition indicator signal SAMPLE_CK is very close to the rising edge of the status indicator signal UPD, if the current status signal UPD_ENB used to characterize the status indicator signal UPD does not accurately acquire the status indicator signal UPD (e.g., ... Figure 2 If the current status signal UPD_ENB shown is not switched to a high level, then the selected output signal DATA_IN will be selected based on the current status signal UPD_ENB representing "0". The data selector 231 will output the selected output signal DATA_IN based on the second acquisition signal DATA_POST. Therefore, by making the delay duration of the first delay unit 3 less than the duration between the first and second moments corresponding to a single update, the selected output signal DATA_IN can be accurately output based on the signal DATA_POST before the falling edge of the status indicator signal UPD causes the signal DATA_POST to be updated. That is, the target input signal DATA corresponding to the acquisition indicator signal SAMPLE_CK at that moment is accurately output before the update. In the above special case, the target output signal DATA_VALID can also be accurately output, further improving the accuracy of signal acquisition.
[0071] It can also be understood that, based on the above method, even if the state determination circuit 1 fails to accurately acquire the current state of the state indication signal UPD, it can still output the accurate target output signal DATA_VALID by reasonably setting the delay duration of the first delay unit 3 and cooperating with other circuits or devices, thus avoiding the defects in traditional technologies and further improving the accuracy of signal acquisition.
[0072] Furthermore, the delay duration of the first delay unit 3 is greater than the setup duration of the current state signal generated by the state determination circuit 1 to characterize the state indication signal.
[0073] Specifically, LATCH_CK is the signal obtained after the first delay unit 3 has delayed.
[0074] By making the delay duration of the first delay unit 3 greater than the setup duration of the current state signal UPD_ENB generated by the state determination circuit 1 to characterize the state indication signal, the possibility of the third trigger 232 prematurely outputting the erroneous target output signal DATA_VALID before receiving the selection output signal DATA_IN generated according to the current acquisition indication signal SAMPLE_CK can be reduced, thereby further improving the accuracy of signal acquisition.
[0075] In one embodiment, see Figure 5 , Figure 5This is a fourth schematic diagram of an embodiment of the asynchronous signal processing circuit of this application, as shown below. Figure 5 As shown, the state determination circuit 1 includes a fourth flip-flop 11 and a fifth flip-flop 12.
[0076] The input of the fourth flip-flop 11 is used to receive the status indication signal, and the clock terminal of the fourth flip-flop 11 is used to receive the acquisition indication signal.
[0077] The input terminal of the fifth flip-flop 12 is used to receive the signal output from the output terminal of the fourth flip-flop 11. The clock terminal of the fifth flip-flop 12 is used to receive the acquisition indication signal delayed by the second delayer 4. The output terminal of the fifth flip-flop 12 is used to output the current state signal to characterize the current state of the state indication signal.
[0078] Specifically, in Figure 4 In this configuration, the second flip-flop 221 can be a falling-edge triggered D flip-flop, while the other flip-flops are rising-edge triggered D flip-flops. Furthermore, the fourth flip-flop 11 and the fifth flip-flop 12 require devices with relatively fast response speeds, while the other flip-flops can be equipped with devices with relatively slow response speeds and lower costs. This achieves the technical solution of this application, reducing device costs and overall power consumption.
[0079] By reasonably setting the delay duration of the second delay unit 4, after the fourth trigger 11 generates the corresponding output signal based on the status indication signal UPD in response to the acquisition indication signal SAMPLE_CK, the fifth trigger 12 outputs the corresponding current status signal UPD_ENB based on the output signal of the fourth trigger 11, thereby triggering the signal acquisition circuit 2 to output the target output signal DATA_VALID, thus improving the accuracy of signal acquisition.
[0080] In one embodiment, the first moment is before the signal establishment period when the target input signal is updated, and the second moment is after the signal establishment period when the target input signal is updated.
[0081] Specifically, if the target input signal is a signal that requires a signal establishment period before it can be updated, then based on the above method, it can be ensured that the signals acquired by the signal acquisition circuit 2 at the first and second moments are relatively stable and accurate signals, thereby improving the accuracy of signal acquisition.
[0082] This application also proposes a storage device, see [link to relevant documentation] Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the storage device of this application, as shown below. Figure 6 As shown, the storage device 50 includes the asynchronous signal processing circuit 51 described in any of the preceding embodiments, which will not be repeated here.
[0083] In one embodiment, the storage device further includes a model register (MR).
[0084] The target output signal is used as the output in response to the mode register set read instruction and is saved to the mode register.
[0085] Specifically, the storage device can be LPDDR4 (Low Power Double Data Rate 4) or other types of memory devices. The target output signal DATA_VALID can be a signal that needs to be read by the MRS (Model Register Set) instruction in LPDDR4. The target output signal DATA_VALID, which is sampled by the asynchronous signal processing circuit, responds to the MRS instruction output and is sent to the host (not shown in the figure), and is stored in the MR register at the same time.
[0086] The target output signal DATA_VALID can be obtained by sampling the target input signal DATA through an asynchronous signal processing circuit under the instruction of MRS. The MRS instruction can be either a read instruction or a write instruction. For example, the target input signal DATA can be the update rate signal mentioned above, which can be used to indicate the update rate of the corresponding memory device. The target input signal DATA can also be the signal that needs to be sampled in other types of memory, which is not limited here.
[0087] The mode register setting read instruction specifically refers to the MRS Read instruction, which can be used to instruct the asynchronous signal processing circuit to sample the target input signal DATA to output the corresponding target output signal DATA_VALID and simultaneously store it in the MR register, so as to realize the reading of the operating parameters of the storage device, and control and drive the normal operation of the storage device.
[0088] Unlike existing technologies, the asynchronous signal processing circuit in this application includes a state determination circuit and a signal acquisition circuit. The state determination circuit determines the current state of the state indication signal in response to receiving an acquisition indication signal. The state indication signal switches from a second state to a first state at a first moment and from the first state to the second state at a second moment. The first moment occurs before the target input signal is updated, and the second moment occurs after the target input signal is updated. The signal acquisition circuit outputs a target output signal based on the target input signal acquired at the first moment, in response to receiving the acquisition indication signal and the current state of the state indication signal being the first state. And / or, in response to receiving the acquisition indication signal and the current state of the state indication signal being the second state, it outputs a target output signal based on the target input signal acquired at the second moment. Based on the above method, relatively accurate target input signals in a stable state can be acquired at two time points, before and after the target input signal is updated. When the state indicator signal is in the first state, it is determined that the target input signal may be in the update period, and the target input signal acquired at the first time point can be used as the target output signal. When the state indicator signal is in the second state, it is determined that the target input signal is not in the update period, and the target input signal acquired at the second time point can be used as the target output signal. Thus, under any circumstances, the latest acquired relatively accurate target input signal in a stable state can be used as the target output signal, thereby reducing the possibility of signal distortion and improving the accuracy of signal acquisition.
[0089] In the description of this application, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0091] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.
[0092] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (which may be a personal computer, server, network device, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.
[0093] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. An asynchronous signal processing circuit, characterized in that, include: A state determination circuit is used to determine the current state of a state indication signal in response to receiving a data acquisition indication signal; wherein the state indication signal switches from a second state to a first state at a first moment, and switches from the first state to the second state at a second moment, the first moment being before the target input signal is updated, and the second moment being after the target input signal is updated; A signal acquisition circuit is configured to, in response to receiving the acquisition indication signal and the current state of the state indication signal being a first state, output a target output signal based on the target input signal acquired at the first time moment, and / or, in response to receiving the acquisition indication signal and the current state of the state indication signal being a second state, output the target output signal based on the target input signal acquired at the second time moment.
2. The asynchronous signal processing circuit according to claim 1, characterized in that, The signal acquisition circuit includes: The first acquisition circuit is used to update its output first acquisition signal based on the target input signal acquired at each of the first moments; The second acquisition circuit is used to update its output second acquisition signal based on the target input signal acquired at each of the second times. The third acquisition circuit is configured to, in response to receiving the acquisition indication signal and the current state of the status indication signal being a first state, output the target output signal based on the first acquisition signal, and / or, in response to receiving the acquisition indication signal and the current state of the status indication signal being a second state, output the target output signal based on the second acquisition signal.
3. The asynchronous signal processing circuit according to claim 2, characterized in that, The third acquisition circuit includes: A switching circuit, wherein the switching circuit is connected to the first acquisition circuit and the second acquisition circuit respectively; An output circuit is connected to the switching circuit. The switching circuit is configured to send the first acquisition signal to the output circuit in response to the current state of the state indication signal being a first state, and to send the second acquisition signal to the output circuit in response to the current state of the state indication signal being a second state. The output circuit is configured to output the target output signal based on the received first acquisition signal or the second acquisition signal in response to receiving the acquisition indication signal.
4. The asynchronous signal processing circuit according to claim 2 or 3, characterized in that, The first acquisition circuit includes: A first trigger, wherein the input terminal of the first trigger is used to receive the target input signal, the clock terminal of the first trigger is used to receive the state indication signal, and the output terminal of the first trigger is used to update its output of the first acquisition signal based on the received target input signal when the state indication signal switches from the second state to the first state; And / or, The second acquisition circuit includes: The second flip-flop has an input terminal for receiving the target input signal, a clock terminal for receiving the status indication signal, and an output terminal for updating its output of the second acquisition signal based on the received target input signal when the status indication signal switches from the first state to the second state.
5. The asynchronous signal processing circuit according to claim 3, characterized in that, The state determination circuit is configured to sample the state indication signal according to the acquisition indication signal, and output the current state signal of the first state in response to the current state of the state indication signal being the first state, and to sample the state indication signal according to the acquisition indication signal, and output the current state signal of the second state in response to the current state of the state indication signal being the second state. The switching circuit includes: A data selector is configured to send the first acquisition signal to the output circuit in response to receiving the current state signal of the first state, and to send the second acquisition signal to the output circuit in response to receiving the current state signal of the second state.
6. The asynchronous signal processing circuit according to claim 3, characterized in that, The output circuit includes: The third flip-flop has an input terminal for receiving the first acquisition signal or the second acquisition signal, a clock terminal for receiving the acquisition indication signal through a first delay, and an output terminal for updating the target output signal based on the received first acquisition signal or the second acquisition signal when the delayed acquisition indication signal is received.
7. The asynchronous signal processing circuit according to claim 6, characterized in that, The delay duration of the first delay device is less than the duration between the first time point and the second time point corresponding to a single update.
8. The asynchronous signal processing circuit according to claim 6, characterized in that, The delay duration of the first delay unit is greater than the establishment time of the current state signal generated by the state determination circuit to characterize the state indication signal.
9. The asynchronous signal processing circuit according to any one of claims 1 to 3, characterized in that, The state determination circuit includes: The fourth flip-flop, wherein the input terminal of the fourth flip-flop is used to receive the status indication signal, and the clock terminal of the fourth flip-flop is used to receive the acquisition indication signal; The fifth flip-flop has an input terminal for receiving the signal output by the output terminal of the fourth flip-flop, a clock terminal for receiving the acquisition indication signal delayed by the second delay unit, and an output terminal for outputting a current state signal to characterize the current state of the state indication signal.
10. The asynchronous signal processing circuit according to any one of claims 1 to 3, characterized in that, The first time point is before the signal establishment period when the target input signal is updated, and the second time point is after the signal establishment period when the target input signal is updated.
11. A storage device, characterized in that, Includes the asynchronous signal processing circuit as described in any one of claims 1 to 10.
12. The storage device according to claim 11, characterized in that, The storage device further includes a mode register; The target output signal is used as an output in response to a mode register set read instruction and is stored in the mode register.