Compensation of dead time in PWM controlled switching arms

Abstract

Examples include systems and methods for compensating for dead time in pulse width modulation control applied to a switching arm connected between two supply lines, such as a switching arm of an inverter.

Description

Background Technology

[0001] This disclosure relates to a method and system for compensating for dead time in PWM (pulse width modulation) control of a switching arm, such as a variable speed drive (VSD), also known as a voltage source inverter (VSi).

[0002] It is known that inverters, typically used in variable speed drives, have several switching arms, each connected to an electrical load to be controlled. The switching arms are connected in parallel between two power lines connected to a voltage source. Each arm includes at least two switches connected in series between the two power lines and a midpoint located between the first and second switches, which is connected to the electrical load. Each switch specifically includes a transistor associated with a diode, such as an IGBT-type transistor.

[0003] In the inverter's switching arms, two switches are controlled by complementary PWM signals, meaning that when one switch is closed, the other is open, and vice versa. Additionally, to prevent both switches from closing simultaneously, a dead time is inserted between their switching times. During this dead time, both switches are open. This prevents a short circuit between the two power lines when both switches are closed, and avoids current spikes caused by such a short circuit.

[0004] During the dead time, the output voltage applied to the electrical load can be determined by the sign of the current flowing through the switching arm. For example, a positive current (flowing to the load) generates a negative output voltage, and a negative current (flowing from the load to the switch) generates a positive output voltage. This leads to a significant uncertainty regarding the actual output voltage applied during the dead time, which should be determined and considered in the PWM signal to improve the control of the electrical load.

[0005] To manage this situation, document EP2403119 A1 proposes integrating the output voltage applied to the electrical load during a time window that includes the dead time, and applying a compensation time to the PWM signal based on the integrated voltage.

[0006] This disclosure improves upon the solution proposed in document EP2403119 A1. Attached Figure Description

[0007] Figure 1 An example of a PWM sequence for controlling two switches of a switching arm and an integral time window of the output voltage, according to document EP2403119A1, is illustrated schematically.

[0008] Figure 2 An example of an inverter according to this disclosure is schematically illustrated.

[0009] Figure 3An example of a PWM sequence for controlling two switches of a switching arm according to the present disclosure and the effect of the sequence on the output voltage are illustrated schematically.

[0010] Figure 4 An example of a system for compensating for dead time in PWM control applied to a switching arm, according to the present disclosure, is illustrated schematically.

[0011] Figure 5a An example of the electronic circuitry of a system according to this disclosure is shown schematically.

[0012] Figure 5b Another example of the electronic circuitry of a system according to this disclosure is illustrated schematically.

[0013] Figure 6 Examples of different phases of an electronic circuit according to this disclosure are schematically shown.

[0014] Figure 7a Another example of the electronic circuitry of the system according to this disclosure is illustrated schematically.

[0015] Figure 7b Another example of the electronic circuitry of the system according to this disclosure is illustrated schematically.

[0016] Figure 8 An example of a method for compensating for dead time in PWM control applied to a switching arm, according to the present disclosure, is illustrated schematically. Detailed Implementation

[0017] The inventors have noted that in the solution proposed in document EP2403119A1, the time window for integrating the output voltage during its duration is larger than the effective duration of the dead time, thus adding error to the integrated output voltage used to apply compensation time in the PWM signal. This document specifically states that the duration of the integration time window, Wint, is set to be slightly longer than the dead time duration to account for the time propagation of the switching sequence and the time used for commutation.

[0018] In this application Figure 1 The text indicates the overlap of the integral time window Wint in the on-time of the switching arm after the dead time in document EP2403119A1, and corresponds to t' d The duration between t'1 and t'1, where t' d This marks the effective end of the dead time, and t'1 marks the effective end of the integration time window Wint. In this figure, CT1 represents the PWM signal of the first switch T11, and CT2 represents the PWM signal of the second switch T21. As shown in the figure, t' dThe duration between t'1 and t'1—which is part of the integration window Wint—corresponds to the on-time of the second switch T21. Therefore, it should be noted that at t' d The voltage integrated during the time period between t'1 and t'1 does not correspond to the output voltage applied to the electrical load during the dead time DT, even though it is taken into account for the correction of the PWM signal.

[0019] To mitigate or even suppress this overlap of the integration time window Wint in the next conduction cycle, the inventors ingeniously proposed simulating the integration of the output voltage with the dead time. Therefore, the integrated output voltage obtained during the dead time does not include any component belonging to the switching conduction time.

[0020] refer to Figure 2 An example of an inverter INV is now presented, which can be used in a variable speed drive, and in which the solutions proposed in this disclosure can be applied.

[0021] Inverters refer to all conventional two-level or multi-level inverters, including those with a DC bus, as well as so-called flying capacitor inverters and matrix converter type inverters. In the following description, we focus on conventional two-level inverters; however, it should be understood that the solutions disclosed herein can be applied to all the aforementioned inverters, and more generally to every device including switching arms.

[0022] The inverter INV comprises two power lines, a positive power line and a negative power line, with a bus capacitor Cbus and several switch arms 1, 2, and 3 connected between these two power lines. Typically, each switch arm 1, 2, or 3 includes at least two switches (T11, T21, T12, T22, T13, T23) connected between the two power lines. In each arm 1, 2, or 3, the midpoint of the connection between two switches is connected to the electrical load M.

[0023] The scheme disclosed herein can be applied independently to each switching arm of an inverter. In the following description, we will focus on a single switching arm 1, which may include, for example, switches T11 and T21.

[0024] refer to Figure 3 The PWM control sequences for switches T11 and T21 used to control switch arm 1, in chronological order, include:

[0025] 1) Keep switch T11 closed for a specific duration (curve CT1),

[0026] 2) Command to disconnect switch T11 (curve CT1),

[0027] 3) Dead time DT: During the dead time DT, switches T11 and T21 are both open.

[0028] 4) The command to close switch T21 (curve CT2),

[0029] 5) Maintain switch T21 closed for a specific duration (curve CT2).

[0030] 6) Command to disconnect switch T21 (curve CT2),

[0031] 7) New Dead Time (DT)

[0032] 8) Command to close switch T11 (curve CT1).

[0033] The switching duration of the switches is determined based on the desired output voltage Vph applied to the electrical load M. Outside the dead time DT, the output voltage Vph is controlled because one of the switches is always closed. However, during the dead time DT necessary to prevent a short circuit in the DC bus, the evolution of the output voltage Vph applied to the electrical load M depends on the current flowing through the electrical load M. Figure 2 The middle is denoted as i s The sign and value of ). Figure 3 This aspect is illustrated. In the figure, it can be seen that the actual output voltage Vph obtained from the switching arm exhibits different profiles depending on whether the current is positive (Vph_is>0), negative (Vph_is<0), or close to zero (Vph_is~0). The figure also shows the desired ideal voltage Vph_id.

[0034] refer to Figure 4 An example of a system 10 is now presented for compensating for the dead time DT in the PWM control applied to the switching arm in order to apply the output voltage Vph to the first electrical load M.

[0035] Examples of system 10 include electronic circuitry 11 and data processing equipment 12.

[0036] Data processing device 12 may include, for example, a processor PROC and a memory MEM. The processor PROC may implement PWM control based on a control law of a first electrical load M. The control law executed by the processor PROC makes it possible to determine the output voltage Vph to be applied to the output phase of the electrical load M to be controlled. The processor PROC may be configured to operate at least a portion of any example of the method 100 described herein.

[0037] The memory MEM can correspond to a non-transitory machine-readable or computer-readable storage medium. The memory MEM may be encoded with instructions executable by a controller, such as a controller PROC. The memory MEM may include instructions that operate the controller PROC to perform at least a portion of the example of method 100 described herein. The memory MEM according to this disclosure can be any electronic, magnetic, optical, or other physical storage device storing executable instructions. The memory MEM can be, for example, random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a storage drive, an optical disk, etc. Therefore, the controller PROC can access information stored in the memory MEM.

[0038] Electronic circuit 11 is configured to integrate the output voltage Vph during a time window Wint that is synchronized with the dead time DT analog, in order to determine the compensation duration of the PWM control pulse.

[0039] By simulating a time window Wint with the dead time DT, this disclosure means that the time window Wint is synchronized with the electrical signal of the switching sequence of switches T11 and T21, such that the time window Wint begins with the opening sequence of one of switches T11 and T21 and ends with the closing sequence of the other switch.

[0040] By measuring the integral of the output voltage Vph over the duration of the time window Wint, which is synchronized with the dead time DT, system 10 allows for precise determination of the output voltage Vph applied to the first electrical load M during the most uncertain duration (dead time DT). This is because the integration time window Wint is always defined as slightly larger than the dead time DT (see [reference]). Figure 1 This method determines the output voltage Vph applied to the first electrical load M with higher accuracy compared to the solution proposed in document EP2403119 A1, in which the determined applied output voltage includes a component outside the dead time DT.

[0041] The data processing device 12 is configured to determine the pulse width for PWM control based on the compensation duration; and to apply the pulse. The pulse may preferably be the next pulse after the dead time DT, that is, the pulse after the integration time window Wint, during which the output voltage has been integrated.

[0042] Because the output voltage Vph is integrated during the time window Wint, which is synchronized with the dead time DT simulation, the obtained integrated output voltage does not include any components belonging to the switching on time. Therefore, the compensation duration determined based on the integrated voltage is more accurate than the compensation duration determined in document EP2403119A1, enabling improved control of the electrical load.

[0043] Reference Figure 5a , 5b Figures 7a and 7b present examples of electronic circuitry 11 configured to integrate the output voltage Vph during a time window Wint synchronized with the dead-time DT simulation. These figures represent possible examples of electronic circuitry 11 that allow integration of the output voltage Vph during a time window Wint synchronized with the dead-time DT simulation, but other examples may be implemented.

[0044] In some examples, electronic circuit 11 may include an H-topology circuit and an output circuit.

[0045] The output circuit can be understood as an electronic circuit that delivers a voltage signal with a width proportional to the integral output voltage, as described below.

[0046] The H-topology circuit includes a first arm h1, a second arm h2, and an intermediate arm hm connecting the first arm h1 and the second arm h2. The intermediate arm hm is connected to the corresponding midpoint of the connection between the first arm h1 and the second arm h2. Arms h1, h2, and hm thus form the H-topology circuit.

[0047] The intermediate arm hm includes capacitor C. Capacitor C will be used to integrate the output voltage Vph during the time window Wint, which is synchronized with the dead-time DT simulation.

[0048] exist Figure 5a and 5b In some examples illustrated in the diagram, the first arm h1 includes a switching circuit F1, a first current source F2, and a first connection midpoint disposed between the switching circuit F1 and the current source F2. The first connection midpoint connects the first arm h1 to the intermediate arm hm. Specifically, the first connection midpoint connects the first arm h1 to the first terminal of the capacitor C.

[0049] The first terminal of the switching circuit F1 can be connected to the voltage line Vcc. The second terminal of the switching circuit F1 can be connected to the first connection midpoint. The first terminal of the first current source F2 can be connected to the first connection midpoint of the first arm h1. The second terminal of the first current source F2 can be connected to ground of the voltage line Vcc, such as... Figure 5a and 5b As shown. The first current source F2 generates a current that depends on the output voltage Vph, as... Figure 5a and 5b As shown. In other words, the first current source F2 corresponds to the voltage-controlled current source.

[0050] exist Figure 5a and 5bIn some of the examples shown, the switching circuit F1 is controlled based on electrical signals (labeled CT1 and CT2) that control the first switch T11 and the second switch T21, respectively. In other words, the switching circuit F1 is controlled based on a PWM signal. The switching circuit F1 is specifically controlled to be off during the dead time DT and to be on when one of the switches (T11, T21) is turned on. The switching circuit F1 can also be off only during the dead time DT and can be turned on only when one of the switches (T11, T21) is turned on.

[0051] exist Figure 5a and 5b In some of the examples shown, the second arm h2 includes a diode circuit F3, a second current source F4, and a second connection midpoint arranged between the diode circuit F3 and the second current source F4.

[0052] As described below, the second current source F4 will be used to discharge capacitor C after capacitor C has integrated the output voltage Vph during the dead time DT. Then, based on the discharge time of capacitor C, the compensation duration will be determined. Therefore, the second current source F4 can be:

[0053] Constant, meaning it is limited by the characteristics of the components used, such as Figure 5a As shown.

[0054] In this case, during capacitor discharge, the actual volt-seconds are recovered, which must then be normalized by the DC bus voltage to correct the pulse width used for compensation.

[0055] Compliant, that is, proportional to the DC bus voltage at the inverter input, such as Figure 5b As shown, the DC bus voltage is referenced as Vbus.

[0056] In this case, the measured integral has been normalized by the DC bus voltage Vbus and corresponds directly to the time that can be used for compensation.

[0057] The second connection midpoint connects the second arm h2 to the middle arm hm. Specifically, the second arm h2 is connected to the second terminal of capacitor C. Diode circuit F3 can be arranged in the second arm to prevent current from flowing from the midpoint of the second arm h2 to the voltage line Vcc, as... Figure 5a and Figure 5b As shown in the image.

[0058] The first terminal (anode) of diode circuit F3 can be connected to the voltage line Vcc. The second terminal (cathode) of diode circuit F3 can be connected to the midpoint of the second connection of the second arm h2. The first terminal of the second current source F4 can be connected to the midpoint of the second connection. The second terminal of the second current source F4 can be connected to ground of the voltage line Vcc.

[0059] exist Figure 5a and 5b In some of the examples shown, the output circuit includes a transistor function Tf, i.e., an electronic component that can be controlled like a transistor. Here, the transistor function TF can be controlled so that it turns on when the diode circuit F3 is on and turns off when the diode circuit F3 is off. That is, the emitter / base of the transistor function Tf can be connected in parallel to the diode circuit F3.

[0060] Figure 5a and Figure 5b The functional principle of electronic architecture:

[0061] As explained earlier, Figure 5a and Figure 5b The electronic architecture allows the output voltage Vph to be integrated during the dead time DT by charging the capacitor C. This architecture also allows for the triggering of pulses with a width proportional to the integrated output voltage, which can therefore be processed, for example, by the data processing device 12 to determine the compensated duration of the pulses for PWM control.

[0062] Based on the different stages representing electronic circuit 11 Figure 6 To explain the functional principles of electronic architecture.

[0063] In phase 1 (P1), until time t0 (which corresponds to the opening sequence of switch T11), switch T11 is turned on (CT1=1), and the voltage across capacitor C is constant and equal to V. C0 The dormant voltage. That is, no current flows through capacitor C.

[0064] At time t0, switch T11 is open (CT1=0), and the integration time window Wint begins. The electronic circuit is in phase 2 (P2). In fact, since both switches on the switching arm are open (CT1+CT2=0), the dead time DT begins. Furthermore, for the same reason (i.e., CT1+CT2=0), switching circuit F1 is open. Because switching circuit F1 is open, the current flowing through diode circuit F3 and attracted by the first current source F2 is charging the second terminal of capacitor C. It should be noted that the current i(t) drawn by the first current source F2 and charging the second terminal of capacitor C is related to the output voltage V. ph Proportional. The current charging capacitor C (especially its second terminal) therefore corresponds to i(t) ≈ K1V. ph (t), where V ph(t) corresponds to the output voltage, and K1 is a constant coefficient. It should also be noted that since diode circuit F3 is conducting, transistor function Tf is also conducting (the emitter-base terminals of transistor function Tf are connected in parallel with the terminals of diode circuit F3), so that the voltage corresponding to voltage line Vcc can be measured between the collector of transistor function Tf and the ground of voltage line Vcc—which can be the ground of electronic circuit 11.

[0065] At time t1, the dead time DT ends with the closing of switch T21 (CT2=1). The voltage VC(t1) across the capacitor is given by the following equation:

[0066]

[0067] We enter phase P3, from t1 to t2. Switch F1 is closed (CT1 + CT2 = 1, since CT2 = 1), connecting the first terminal of capacitor C to the voltage line Vcc. However, the second terminal of capacitor C, having been charged during phase P2, presents a voltage greater than the voltage line Vcc. Therefore, at this point, capacitor C discharges using the second current source F4 until it reaches its sleep voltage V at t2. C0 The evolution of the voltage across capacitor C during discharge depends on the fact that the second current source F4 is constant. Figure 5a The example shown) is still compliant ( Figure 5b (The example shown below) is described in detail below.

[0068] When the second current source F4 is constant, the evolution of the voltage VC(t) across the capacitor C follows the relationship i(t) = -K2, where K2 is a constant:

[0069]

[0070] Therefore, since VC(t2) = V at time t2 C0 We can obtain the following relation from (1):

[0071]

[0072] When the second current source F4 depends on the relationship i(t) = -K3V bus When the DC bus voltage is [value], where K3 is a constant, and V [value] is [value]. bus Corresponding to the DC bus voltage, the current voltage V across capacitor C is... C The evolution of (t) is given by the following relationship:

[0073]

[0074] If we consider the DC bus voltage V during t1 and t2 bus If the voltage is constant, then we can obtain the voltage V across capacitor C. C The following equation for (t):

[0075]

[0076] Then we can obtain:

[0077]

[0078] Time t2 can then be used to calculate the compensation duration to be applied in the PWM control in order to determine the pulse width of the PWM signal for the switch, as explained in EP2403119A1.

[0079] It should be noted that during phase P3, since the potential of the second terminal (cathode) of diode circuit F3 is equal to the potential of the second terminal of capacitor C, which is greater than the potential of the first terminal (anode) of diode circuit F3 corresponding to the potential of voltage line Vcc, current cannot flow through diode circuit F3 (diode circuit F3 is open). We understand that during this time period, transistor function Tf is open because the emitter-base terminals of transistor function Tf are connected in parallel with diode circuit F3.

[0080] Then, when the second terminal of capacitor C is fully discharged by the second current source F4 (at t2), the diode circuit F3 turns on again (and the transistor function Tf turns on again), so that there is no more current charging or discharging the second terminal of capacitor C (stage P4) until the next dead time DT is reached.

[0081] We understand that since diode circuit F3 is off during phase P3 (from t1 to t2), the voltage measured between the collector of transistor function Tf and ground of voltage line Vcc of electronic circuit 11 is equal to 0 during this phase. Therefore, by monitoring this voltage, and in particular by monitoring the transition of the voltage from 0 to Vcc, the end of the discharge of capacitor C can be simulatedly determined, and thus time t2 can be determined, which can then be used to calculate the compensation duration. Time t1 can be obtained based on the PWM signal. In some examples, the compensation duration can be determined based on the duration during which transistor function Tf is off, which therefore corresponds to the discharge time of capacitor C.

[0082] In some examples, the output circuit may also include a second resistor R2 (the first resistor R1 will be described below). The first terminal of the second resistor R2 may be connected to the collector of the transistor function Tf. The second terminal of the second resistor R2 may be connected to ground of the voltage line Vcc (which may correspond to the ground of electronic circuit 11). The compensation duration may be determined based on the voltage across the second resistor R2.

[0083] In some examples, the switching circuit F1 may include or correspond to a metal-oxide-semiconductor field-effect transistor (MOSFET), and in particular to a P-channel MOSFET.

[0084] The source of the MOSFET can be connected to the voltage line Vcc. The source of the MOSFET can thus be connected to the diode circuit F3 (specifically to its anode), and via the voltage line Vcc to the transistor function Tf (specifically to its emitter).

[0085] The gate of the MOSFET can be controlled based on electrical signals (CT1, CT2) that trigger the first switch T11 and the second switch T21.

[0086] The drain of the MOSFET can be connected to the first terminal of the capacitor C and to the first current source F2.

[0087] In some examples, the first current source F2 may correspond to the first current mirror MC1.

[0088] The first transistor T1 of the first current mirror MC1 MC1 The collector of the resistor can be connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 can be connected to the output voltage Vph.

[0089] The second transistor T2 of the first current mirror MC1 MC1 The collector can be connected to the first terminal of capacitor C and switching circuit F1, especially when switching circuit F1 includes MOSFET, it is connected to the drain of MOSFET.

[0090] The first transistor T1 of the first current mirror MC1 MC1 The emitter and the second transistor T2 MC1 The emitter can be connected to ground on the voltage line Vcc.

[0091] In some examples, the second current source F4 can correspond to the second current mirror MC2.

[0092] The first transistor T1 of the second current mirror MC2 MC2 The collector can be connected to the second terminal of capacitor C and diode circuit F3 (especially its cathode).

[0093] The second transistor T2 of the second current mirror MC2 MC1 The collector of the resistor can be connected to the first terminal of the third resistor R3. In some examples where the second current source F4 is a constant current source, the second terminal of the third resistor R3 can be connected to the voltage line Vcc (e.g., ...). Figure 7a (As shown in the diagram). The second current source F4 depends on the DC bus voltage V. bus In some examples of current sources, the second terminal of the third resistor R3 can be connected to the DC bus voltage V. bus (like Figure 7b (As shown).

[0094] The first transistor T1 of the second current mirror MC2 MC2 The emitter and the second transistor T2 MC2 The emitter can be connected to ground on the voltage line Vcc.

[0095] In some examples, the diode circuit F3 and the transistor function Tf are formed by the third current mirror MC3.

[0096] The first transistor T1 of the third current mirror MC3 MC3 The emitter and the second transistor T2 MC3 The emitter can be connected to the switching circuit F1 via the voltage line Vcc.

[0097] The first transistor T1 of the third current mirror MC3 MC3 The collector can be connected to the second terminal of capacitor C and the second current source F2.

[0098] The second transistor T2 of the third current mirror MC3 MC3 The collector of the resistor can be connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 can be connected to ground of the voltage line Vcc.

[0099] In some examples, the freewheeling diode fD can be connected in parallel to the second transistor T2 of the third current mirror MC3. MC3 This is used to protect the latter transistor from voltage spikes. Therefore, the cathode of the freewheeling diode fD can be connected to the switching circuit F1 (especially to the source of the MOSFET when F1 includes one), and connected to the first transistor T1 of the third current mirror MC3 via the voltage line Vcc. MC3 Second transistor T2 MC3 The emitter of the freewheeling diode fD. The anode of the freewheeling diode fD can be connected to the first terminal of the second resistor R2 and the second transistor T2 of the third current mirror MC3. MC3 The collector. These examples are, for instance, in... Figure 7a and 7b As shown in the image.

[0100] exist Figure 7a and 7b In some examples of the electronic circuit 11 shown, the output circuit includes a second resistor R2. A first current source F2 corresponds to a first current mirror MC1. A second current source F4 corresponds to a second current mirror MC2. A diode circuit F3 and a transistor function Tf are formed by a third current mirror MC3. A switching circuit F1 corresponds to a MOSFET.

[0101] exist Figure 7a and 7b In some examples of the electronic circuit 11 shown in the figure, the first transistor T1 of the first current mirror MC1 MC1 The collector of the first transistor is connected to the first terminal of the first resistor R1. The second terminal of the first resistor R1 is connected to the output voltage Vph. The second transistor T2 is a mirror of the first current MC1. MC1 The collector of the first transistor is connected to the first terminal of capacitor C and to the drain of the MOSFET. The first current mirror MC1 is connected to the first transistor T1. MC1 The emitter and the second transistor T2 MC1 The emitter is connected to the ground of the voltage line Vcc, which can again correspond to the ground of electronic circuit 11.

[0102] exist Figure 7a and 7b In some examples of the electronic circuit 11 shown, the first transistor T1 of the second current mirror MC2 MC2 The collector of the first transistor T1 is connected to the second terminal of capacitor C and the third current mirror MC3. MC3 The collector. The second current mirror MC2 and the second transistor T2. MC2 The collector of the resistor is connected to the first terminal of the third resistor R3. In some examples where the second current source F4 is a constant current source, the second terminal of the third resistor R3 is connected to the voltage line Vcc. Figure 7a In this context, the second current source F4 depends on the DC bus voltage V. bus In some examples of current sources, the second terminal of the third resistor R3 is connected to the DC bus voltage V. bus (like Figure 7b (As shown).

[0103] The first transistor T1 of the second current mirror MC2 MC2 Second transistor T2 MC2 The emitter of the transistor and the second terminal of the second resistor R2 are connected to ground of the voltage line Vcc. Therefore, the emitter of the transistor of the first current mirror MC1 and the second current mirror MC2 and the second terminal of the resistor R2 are connected to ground of the voltage line Vcc.

[0104] exist Figure 7a and7b In some examples of the electronic circuit 11 shown in the diagram, the first transistor T1 of the third current mirror MC3 MC3 The emitter and the second transistor T2 MC3 The emitter is connected to the source of the MOSFET via the voltage line Vcc. The first transistor T1 of the third current mirror MC3... MC3 The emitter and the second transistor T2 MC3 The emitter can also be connected to the cathode of the freewheeling diode fD.

[0105] The first transistor T1 of the third current mirror MC3 MC3 The collector of the first transistor T1 is connected to the second terminal of the capacitor C and to the second current mirror MC2. MC2 The collector. The second transistor T2 of the third current mirror MC3. MC3 The collector of the transistor is connected to the first terminal of the second resistor R2. The second transistor T2 of the third current mirror MC3... MC3 The collector can also be connected to the anode of the freewheeling diode fD.

[0106] exist Figure 7a and 7b In some examples of the electronic circuit 11 shown, the source of the MOSFET is connected to the first transistor T1 of the third current mirror MC3 via the voltage line Vcc. MC3 The emitter and the second transistor T2 MC3 The emitter of the MOSFET. The source of the MOSFET can also be connected to the cathode of the freewheeling diode fD. The gate of the MOSFET is controlled based on the electrical signal that triggers the first switch T11 and the second switch T21. The drain of the MOSFET is connected to the first terminal of the capacitor C and to the second transistor T2 connected to the first current mirror MC1. MC1 The collector.

[0107] exist Figure 7a and 7b In some examples of the electronic circuit 11 shown, the compensation duration is determined based on the voltage across the second resistor R2.

[0108] exist Figure 7a and Figure 7b In the example of electronic circuit 11 shown, electronic circuit 11 can be implemented as an application-specific integrated circuit (ASIC). Implementing electronic circuit 11 as an ASIC offers significant advantages, including a compact design and cost efficiency for mass production, making it well-suited for integration into existing inverters.

[0109] Reference Figure 8 An example of a method 100 for compensating for the dead time DT in PWM control applied to a switching arm is presented.

[0110] As shown in box 110, method 100 includes integrating the output voltage Vph during a time window Wint that is synchronized with the dead time DT simulation to determine the compensation duration of the PWM control pulse. The compensation duration of the PWM control pulse can be determined based on the discharge time of the capacitor C as explained above, for example, based on times t1 and t2.

[0111] As shown in box 120, method 100 includes determining the width of the PWM control pulse based on the compensation duration. The pulse may preferably be the next pulse after the dead time DT, i.e., the pulse after the integration time window Wint, during which the output voltage has been integrated, as described above.

[0112] As shown in box 130, method 100 includes applying a pulse defined in box 120.

[0113] In some examples, the integration of the output voltage Vph during the time window Wint, which is synchronized with the dead time DT simulation of block 110, is performed by any of the examples of electronic circuit 11 presented in this invention.

[0114] This disclosure also proposes a computer-readable storage medium including instructions that, when executed by at least one controller, cause the controller to perform any of the methods proposed herein.

[0115] This disclosure also describes a computer program product including instructions that, when executed by a computer, cause the computer to perform any of the methods described herein.

[0116] The terminology used herein is for the purpose of describing specific examples only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising,” “including,” “including,” and / or “having” as used herein specify the presence of stated features, integers, steps, operations, blocks, constituent elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, blocks, constituent elements, components, and / or combinations thereof.

[0117] The various examples described above can be combined to provide further examples. Based on the detailed description above, these and other changes can be made to the examples. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific examples disclosed in the specification, but should be interpreted to include all possible examples and the full scope of the equivalents conferred by these claims.

Claims

1. A system (10) for compensating for the dead time (DT) in pulse width modulation (PWM) control applied to a switching arm (1) to apply an output voltage (Vph) to a first electrical load (M); The switch arm includes a first switch (T11), a second switch (T21), and a connection midpoint arranged between the first switch and the second switch and connected to the electrical load (M); The system (10) includes: Electronic circuit (11) is configured to integrate the output voltage (Vph) during a time window (Wint) synchronized with the dead time (DT) analog to determine the compensation duration of the pulse of the PWM control; The data processing device (12) is configured as follows: The width of the PWM control pulse is determined based on the compensation duration; and Apply a pulse.

2. The system according to the preceding claim, wherein, The electronic circuit (11) includes an H-topology circuit and an output circuit; The H-topology circuit includes a first arm (h1), a second arm (h2), and an intermediate arm (hm) connected between the first arm (h1) and the second arm (h2) to form the H-topology. The intermediate arm (hm) includes a capacitor (C); The first arm includes a switching circuit (F1), a first current source (F2), and a connection midpoint disposed between the switching circuit (F1) and the current source (F2) and connected to the intermediate arm (hm); The second arm includes a diode circuit (F3), a second current source (F4), and a connection midpoint disposed between the diode circuit (F3) and the current source (F4) and connected to the intermediate arm (hm); The output circuit includes a transistor function (Tf) arranged such that the transistor function (Tf) is turned on when the diode circuit (F3) is turned on, and the transistor function (Tf) is turned off when the diode circuit (F3) is turned off. The switching circuit (F1) is controlled based on the electrical signals controlling the first switch (T11) and the second switch (T21), such that the switching circuit (F1) is open during the dead time (DT) and is turned on when one of the switches (T11, T21) is turned on. The first current source (F2) is arranged to charge the capacitor (C) with a current proportional to the output voltage (Vph) when the switching circuit (F1) is off and when the diode circuit (F3) is on; and The second current source (F4) is arranged to discharge the capacitor (C) when the switching circuit (F1) is turned on and when the diode circuit (F3) is turned off.

3. The system according to claim 2, wherein, The compensation duration is determined based on the time during which the transistor function (Tf) is off.

4. The system according to any one of claims 2 or 3, wherein, The switching circuit (F1) includes a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET); In this circuit, the source of the MOSFET is connected to the diode circuit (F3) and the transistor function (Tf) via a voltage line (Vcc); The gate of the MOSFET is controlled based on the electrical signal that controls the first switch (T11) and the second switch (T21); Furthermore, the drain of the MOSFET is connected to the first terminal of the capacitor (C) and to the first current source (F2).

5. The system according to any one of claims 2 to 4, wherein, The first current source (F2) corresponds to the first current mirror (MC1).

6. The system according to claim 5, wherein, The first transistor (T1) of the first current mirror (MC1) MC1 The collector of the resistor is connected to the first terminal of the first resistor (R1), and the second terminal of the first resistor (R1) is connected to the output voltage (Vph). Among them, the second transistor (T2) of the first current mirror (MC1) MC1 The collector of the capacitor (C) is connected to the first terminal of the capacitor (C) and the switching circuit (F1); and Among them, the first transistor (T1) of the first current mirror (MC1) MC1 The emitter of the second transistor (T2) MC1 The emitter of the ) is connected to the ground of the voltage line (Vcc).

7. The system according to any one of claims 2 to 6, wherein, The second current source (F4) corresponds to the second current mirror (MC2).

8. The system according to claim 7, wherein, The first transistor (T1) of the second current mirror (MC2) MC2 The collector of the diode is connected to the second terminal of the capacitor (C) and the diode circuit (F3); Among them, the second transistor (T2) of the second current mirror (MC2) MC2 The collector of the resistor is connected to the first terminal of the third resistor (R3), and the second terminal of the third resistor (R3) is connected to the voltage line (Vcc) or the DC bus voltage (V). bus );and Among them, the first transistor (T1) of the second current mirror (MC2) MC2 The emitter of the second transistor (T2) MC2 The emitter of the voltage line (Vcc) is connected to ground.

9. The system according to any one of claims 2 to 8, wherein, The diode circuit (F3) and the transistor function (Tf) are formed by a third current mirror (MC3).

10. The system according to claim 9, wherein, The first transistor (T1) of the third current mirror (MC3) MC3 The emitter of the second transistor (T2) MC3 The emitter of the circuit is connected to the switching circuit (F1) via a voltage line (Vcc); Among them, the first transistor (T1) of the third current mirror (MC3) MC3 The collector of the capacitor (C) is connected to the second terminal of the capacitor (C) and the second current source (F2); Among them, the second transistor (T2) of the third current mirror (MC3) MC3 The collector of the first resistor (R2) is connected to the first terminal of the second resistor (R2); and The second terminal of the second resistor (R2) is connected to the ground of the voltage line (Vcc).

11. The system according to any one of claims 1 to 10, wherein, The output circuit includes a second resistor (R2); The first terminal of the second resistor (R2) is connected to the collector of the transistor function (Tf); The second terminal of the second resistor (R2) is connected to ground of the voltage line (Vcc); and The compensation duration is determined based on the voltage across the second resistor (R2).

12. The system according to any one of claims 2 to 11, wherein, The output circuit includes a second resistor (R2), the first current source (F2) corresponds to a first current mirror (MC1), the second current source (F4) corresponds to a second current mirror (MC2), the diode circuit (F3) and the transistor function (Tf) are formed by a third current mirror (MC3), and the switching circuit (F1) corresponds to a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Among them, the first transistor (T1) of the first current mirror (MC1) MC1 The collector of the first current mirror (MC1) is connected to the first terminal of the first resistor (R1), and the second terminal of the first resistor (R1) is connected to the output voltage (Vph); the second transistor (T2) of the first current mirror (MC1) MC1 The collector of the first current mirror (MC1) is connected to the first terminal of the capacitor (C) and the drain of the MOSFET; the first transistor (T1) of the first current mirror (MC1) MC1 The emitter of ) and the second transistor (T2) MC1 The emitter of the ) is connected to ground on the voltage line (Vcc); Among them, the first transistor (T1) of the second current mirror (MC2) MC2 The collector of the capacitor (C) is connected to the second terminal of the capacitor (C) and the first transistor (T1) of the third current mirror (MC3). MC3 The collector of the second current mirror (MC2); the second transistor (T2) of the second current mirror (MC2) MC2 The collector of the resistor is connected to the first terminal of the third resistor (R3), and the second terminal of the third resistor (R3) is connected to the voltage line (Vcc) or the DC bus voltage (V). bus ); the first transistor (T1) of the second current mirror (MC2) MC2 The emitter of the second transistor (T2) MC2 The emitter of the second resistor (R2) and the second terminal of the second resistor (R2) are connected to the ground of the voltage line (Vcc); Among them, the first transistor (T1) of the third current mirror (MC3) MC3 The emitter of the second transistor (T2) MC3 The emitter of the third current mirror (MC3) is connected to the source of the MOSFET via the voltage line (Vcc); the second transistor (T2) of the third current mirror (MC3) MC3 The collector of the resistor is connected to the first terminal of the second resistor (R2); The gate of the MOSFET is controlled based on electrical signals that control the first switch (T11) and the second switch (T21); and The compensation duration is determined based on the voltage across the second resistor (R2).

13. A method (100) for compensating dead time (DT) in pulse width modulation (PWM) control applied to a switch arm (1), the switch arm (1) being connected between two power supply lines, the switch arm including a first switch (T11), a second switch (T21), and a connection midpoint located between the first switch (T11) and the second switch (T21) and connected to an electrical load (M), The PWM control executes the switching of the first switch (T11) and the second switch (T21), and inserts a dead time (DT) between the switching of the first switch (T11) and the switching of the second switch (T21) to apply an output voltage (Vph) to the electrical load (M). in, The method includes: The output voltage (Vph) is integrated (110) during a time window (Wint) synchronized with the dead time (DT) simulation to determine the compensation duration of the pulse of the PWM control; The width of the PWM control pulse is determined (120) based on the compensation duration; and Apply the pulse described in (130).

14. The method according to the preceding claim, wherein, Integrating the output voltage (Vph) during a defined time window (Wint) synchronized with the dead time (DT) is implemented by the electronic circuitry of the system according to any one of claims 1 to 12.

15. A computer-readable storage medium comprising instructions that, when executed by at least one controller, cause the at least one controller to perform at least a portion of the method described in any of the preceding method claims.

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