Pulse circuit
By using capacitors and diodes in the pulse circuit for voltage boosting, and combining them with components such as signal amplification circuits and NMOS transistors, the problem of insufficient output voltage of the main control chip is solved, realizing low-cost high-voltage signal output, which is suitable for communication and power supply fields.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG NASITER INT LIGHTNING CO LTD
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-21
AI Technical Summary
Traditional pulse circuits require the addition of boost chips and peripheral circuits to output higher voltage pulse signals due to the low output voltage of the main control chip, which increases circuit cost and makes maintenance difficult.
The first power supply is boosted by capacitors and diodes, and the boosted power supply is used as an enable signal to control the pull-up switch to output a higher voltage pulse signal. The boost chip is omitted, and components such as NMOS transistors and NPN transistors are used to achieve signal amplification and control.
It enables the output of high-voltage pulse signals at low cost, simplifies the circuit structure, reduces maintenance costs, and is suitable for fields such as communication and power supply.
Smart Images
Figure CN121907191A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic technology, and more particularly to a pulse circuit. Background Technology
[0002] In traditional pulse circuits, when a main control chip controls a transistor to output a higher voltage pulse signal, the main control chip itself can only output a relatively low voltage, so it cannot directly control the transistor to output a higher voltage pulse signal. Therefore, a boost chip and its peripheral circuits need to be added between the main control chip and the transistor to enable the main control chip to control the transistor to output a higher voltage pulse signal.
[0003] However, adding a boost chip and its peripheral circuits will increase the circuit cost accordingly. Furthermore, if the boost chip fails internally, the entire chip needs to be replaced and repaired, which will also increase the cost of pulse circuit maintenance. Summary of the Invention
[0004] The purpose of this invention is to provide a pulse circuit that first boosts a first power supply through a capacitor and a diode, and then uses the boosted first power supply as an enable through a signal amplification circuit to output to a pull-up switch, thereby controlling the pull-up switch to output a higher voltage pulse signal, in order to solve the technical problems existing in the prior art.
[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: One aspect of this invention provides a pulse circuit, comprising: a boost circuit, the boost circuit including a boost control circuit, a first diode, and a first capacitor, a first terminal of the boost control circuit being connected to one terminal of the first capacitor, the other terminal of the first capacitor being connected to the cathode of the first diode, and the anode of the first diode being connected to a first power supply; a signal amplification circuit, the first terminal of the signal amplification circuit being connected to the cathode of the first diode and the other terminal of the first capacitor; a pull-up switch and a pull-down switch, the second terminal of the signal amplification circuit being connected to control the on / off state of the pull-up switch, the first terminal of the pull-up switch being connected to a second power supply, the first terminal of the pull-down switch being grounded, and the second terminals of the pull-up switch and the pull-down switch being connected to cooperate in outputting a pulse signal; and a main control chip, the main control chip being connected to control the boost control circuit, the signal amplification circuit, and the pull-down switch respectively.
[0006] In some embodiments, the pull-up switch includes an NMOS transistor and a first resistor, and the pull-down switch includes a first NPN transistor, a second resistor, and a third resistor. The drain of the NMOS transistor is connected to a second power supply, the gate of the NMOS transistor is connected to the second terminal of the signal amplification circuit and one end of the first resistor, the base of the first NPN transistor is connected to the main control chip through the second resistor, the emitter of the first NPN transistor is grounded through the third resistor, and the source of the NMOS transistor is connected to the collector of the first NPN transistor and the other end of the first resistor. The NMOS transistor and the first NPN transistor cooperate to output a pulse signal.
[0007] In some embodiments, the boost circuit further includes a second diode and a second capacitor. The anode of the second diode is connected to the cathode of the first diode and the other end of the first capacitor. The cathode of the second diode is connected to one end of the second capacitor and the first terminal of the signal amplification circuit. The other end of the second capacitor is connected to the source of the NMOS transistor and the collector of the first NPN transistor.
[0008] In some embodiments, the boost control circuit includes a second NPN transistor, a fourth resistor, and a charging switch. The base of the second NPN transistor is connected to the main control chip through the fourth resistor. The charging switch is connected to the main control chip. The emitter of the second NPN transistor is grounded. The collector of the second NPN transistor and the charging switch are connected to one end of the first capacitor. The charging switch and the second NPN transistor charge and discharge one end of the first capacitor in sequence.
[0009] In some embodiments, the charging switch includes a third NPN transistor, a fourth NPN transistor, a fifth resistor, and a sixth resistor. The collector of the third NPN transistor and one end of the fifth resistor are connected to the source of the NMOS transistor and the collector of the first NPN transistor. The emitter of the third NPN transistor is connected to one end of the first capacitor. The base of the third NPN transistor is connected to the other end of the fifth resistor and the collector of the fourth NPN transistor. The base of the fourth NPN transistor is connected to the main control chip. The emitter of the fourth NPN transistor is grounded.
[0010] In some embodiments, the signal amplification circuit includes a fifth NPN transistor, a seventh resistor, and an eighth resistor. The collector of the fifth NPN transistor and one end of the eighth resistor are connected to the cathode of the second diode and one end of the second capacitor. The other end of the eighth resistor is connected to the base of the fifth NPN transistor and the main control chip. The emitter of the fifth NPN transistor is connected to the gate of the NMOS transistor through the seventh resistor.
[0011] In some embodiments, the signal amplification circuit further includes a PNP transistor, a ninth resistor, and a tenth resistor. The emitter of the PNP transistor is connected to the gate of the NMOS transistor through the tenth resistor. The base of the PNP transistor is connected to one end of the ninth resistor. The other end of the ninth resistor is connected to the base of the fifth NPN transistor and the main control chip. The collector of the PNP transistor is connected to the source of the NMOS transistor and the collector of the first NPN transistor.
[0012] In some embodiments, the signal amplification circuit further includes a sixth NPN transistor and an eleventh resistor. The collector of the sixth NPN transistor is connected to the other end of the ninth resistor and the base of the fifth NPN transistor. The base of the sixth NPN transistor is connected to the main control chip through the eleventh resistor. The emitter of the sixth NPN transistor is grounded.
[0013] In some embodiments, the signal amplification circuit further includes a third capacitor connected in parallel with the eleventh resistor.
[0014] According to an embodiment of the present invention, a pulse circuit has at least the following advantages: The present application includes a first diode and a first capacitor for a first voltage boost, and a second diode and a second capacitor for a second voltage boost. The first power supply after the second voltage boost is used to control the NMOS transistor to output a higher voltage pulse signal. A first NPN transistor is used to pull down the pulse signal. The main control chip performs a first signal amplification control through a sixth NPN transistor, and a second signal amplification control through a fifth NPN transistor and a PNP transistor, so that the control chip can control the first power supply after the second voltage boost to start the NMOS transistor to output a pulse signal through the sixth and fifth NPN transistors. The pulse circuit of the present application has low manufacturing cost, can output a higher voltage pulse signal, and can be used for communication and power supply applications, thus having strong practicality.
[0015] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of a pulse circuit according to an embodiment. Detailed Implementation
[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0019] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0020] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0021] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0022] The technical solutions of the embodiments of this application are briefly described below: According to some embodiments, this application provides a pulse circuit, the pulse circuit comprising: The boost circuit includes a boost control circuit, a first diode D1, and a first capacitor C1. The first terminal of the boost control circuit is connected to one terminal of the first capacitor C1, the other terminal of the first capacitor C1 is connected to the negative terminal of the first diode D1, and the positive terminal of the first diode D1 is connected to the first power supply V1. The signal amplification circuit has its first terminal connected to the cathode of the first diode D1 and the other terminal of the first capacitor C1. The second terminal of the signal amplification circuit is connected to control the on / off state of the pull-up switch and the first terminal of the pull-up switch is connected to the second power supply V2. The first terminal of the pull-down switch is grounded. The second terminals of the pull-up switch and the second terminal of the pull-down switch are connected to cooperate with the output pulse signal VOUT. The main control chip is connected to the boost control circuit, the signal amplification circuit, and the pull-down switch.
[0023] The working principle based on the above embodiment is as follows: the main control chip controls the first diode D1 and the first capacitor C1 to perform boost operation through the boost control circuit to boost the first power supply V1. Then, the boosted first power supply V1 is sent to the pull-up switch as an enable signal through the signal amplification circuit to control the pull-up switch to output a higher voltage pulse signal VOUT.
[0024] Specifically, such as Figure 1 As shown, the pull-up switch includes an NMOS transistor MN and a first resistor R1, and the pull-down switch includes a first NPN transistor QN1, a second resistor R2, and a third resistor R3. The drain of the NMOS transistor MN is connected to the second power supply V2, and the gate of the NMOS transistor MN is connected to the second terminal of the signal amplifier circuit and one end of the first resistor R1. The base of the first NPN transistor QN1 is connected to the main control chip through the second resistor R2, and the emitter of the first NPN transistor QN1 is grounded through the third resistor R3. The source of the NMOS transistor MN is connected to the collector of the first NPN transistor QN1 and the other end of the first resistor R1. The NMOS transistor MN and the first NPN transistor QN1 work together to output a pulse signal VOUT.
[0025] In other embodiments, the first NPN transistor QN1 can be replaced with an NMOS transistor or other transistors with switching functions. This application does not limit the application. The pull-up switch in this application preferably uses an NMOS transistor MN, which has a higher output power than an NPN transistor, and also offers better cost-effectiveness than a PMOS transistor.
[0026] Furthermore, such as Figure 1 As shown, the boost circuit also includes a second diode D2 and a second capacitor C2. The positive terminal of the second diode D2 is connected to the negative terminal of the first diode D1 and the other end of the first capacitor C1. The negative terminal of the second diode D2 is connected to one end of the second capacitor C2 and the first terminal of the signal amplification circuit. The other end of the second capacitor C2 is connected to the source of the NMOS transistor MN and the collector of the first NPN transistor QN1.
[0027] Furthermore, such as Figure 1As shown, the boost control circuit includes a second NPN transistor QN2, a fourth resistor R4, and a charging switch. The base of the second NPN transistor QN2 is connected to the main control chip through the fourth resistor R4. The charging switch is connected to the main control chip. The emitter of the second NPN transistor QN2 is grounded. The collector of the second NPN transistor QN2 and the charging switch are connected to one end of the first capacitor C1. The charging switch and the second NPN transistor QN2 charge and discharge one end of the first capacitor C1 in sequence.
[0028] Furthermore, such as Figure 1 As shown, the charging switch includes a third NPN transistor QN3, a fourth NPN transistor QN4, a fifth resistor R5, and a sixth resistor R6. The collector of the third NPN transistor QN3 and one end of the fifth resistor R5 are connected to the source of the NMOS transistor MN and the collector of the first NPN transistor QN1. The emitter of the third NPN transistor QN3 is connected to one end of the first capacitor C1. The base of the third NPN transistor QN3 is connected to the other end of the fifth resistor R5 and the collector of the fourth NPN transistor QN4. The base of the fourth NPN transistor QN4 is connected to the main control chip, and the emitter of the fourth NPN transistor QN4 is grounded.
[0029] According to some embodiments, such as Figure 1 As shown, the signal amplification circuit includes a fifth NPN transistor QN5, a seventh resistor R7, and an eighth resistor R8. The collector of the fifth NPN transistor QN5 and one end of the eighth resistor R8 are connected to the cathode of the second diode D2 and one end of the second capacitor C2. The other end of the eighth resistor R8 is connected to the base of the fifth NPN transistor QN5 and the main control chip. The emitter of the fifth NPN transistor QN5 is connected to the gate of the NMOS transistor MN through the seventh resistor R7.
[0030] Furthermore, such as Figure 1 As shown, the signal amplification circuit also includes a PNP transistor QP, a ninth resistor R9, and a tenth resistor R10. The emitter of the PNP transistor QP is connected to the gate of the NMOS transistor MN through the tenth resistor R10. The base of the PNP transistor QP is connected to one end of the ninth resistor R9. The other end of the ninth resistor R9 is connected to the base of the fifth NPN transistor QN5 and the main control chip. The collector of the PNP transistor QP is connected to the source of the NMOS transistor MN and the collector of the first NPN transistor QN1.
[0031] Furthermore, such as Figure 1 As shown, the signal amplification circuit also includes a sixth NPN transistor QN6 and an eleventh resistor R11. The collector of the sixth NPN transistor QN6 is connected to the other end of the ninth resistor R9 and the base of the fifth NPN transistor QN5. The base of the sixth NPN transistor QN6 is connected to the main control chip through the eleventh resistor R11. The emitter of the sixth NPN transistor QN6 is grounded.
[0032] Furthermore, such as Figure 1 As shown, the signal amplification circuit also includes a third capacitor C3, which is connected in parallel with the eleventh resistor R11.
[0033] The working principle of this application is as follows: the main control chip outputs a PWM signal to the base of the second NPN transistor QN2 and the base of the fourth NPN transistor QN4 to control the first power supply V1 to perform a first voltage boost operation using the first diode D1 and the first capacitor C1, and then to perform a second voltage boost operation using the second diode D2 and the second capacitor C2. After the first power supply V1 has been boosted twice, the main control chip outputs a low-level L_CTL_H signal to the base of the sixth NPN transistor QN6, turning off the sixth NPN transistor QN6 and turning on the fifth NPN transistor QN5. At the same time, the main control chip also outputs a low-level L_CTL_L signal to the base of the first NPN transistor QN1, turning off the first NPN transistor QN1. The fifth NPN transistor QN5 outputs the first power supply V1 after the two boosts to the gate of the NMOS transistor MN, enabling the NMOS transistor MN to conduct, and the pulse signal VOUT outputs a high-level signal. If the first voltage is not boosted and the first power supply V1 is directly output to the gate of the NMOS transistor MN, the NMOS transistor MN cannot be turned on. Then, the main control chip outputs a high-level L_CTL_H signal to the base of the sixth NPN transistor QN6 and a high-level L_CTL_L signal to the base of the first NPN transistor QN1. The sixth NPN transistor QN6 turns on, the fifth NPN transistor QN5 turns off, the PNP transistor QP turns on, the NMOS transistor MN turns off, the first NPN transistor QN1 turns on, and the pulse signal VOUT outputs a low-level signal.
[0034] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0035] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or substance of this application, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.
Claims
1. A pulse circuit, characterized in that, The pulse circuit includes: A boost circuit, comprising a boost control circuit, a first diode and a first capacitor, wherein a first terminal of the boost control circuit is connected to one terminal of the first capacitor, the other terminal of the first capacitor is connected to the cathode of the first diode, and the anode of the first diode is connected to a first power supply. A signal amplification circuit, wherein the first terminal of the signal amplification circuit is connected to the negative terminal of the first diode and the other terminal of the first capacitor; The signal amplification circuit includes a pull-up switch and a pull-down switch. The second terminal of the signal amplification circuit is connected to control the on / off state of the pull-up switch. The first terminal of the pull-up switch is connected to a second power supply. The first terminal of the pull-down switch is grounded. The second terminals of the pull-up switch and the pull-down switch are connected to cooperate in outputting a pulse signal. The main control chip is connected to and controls the boost control circuit, the signal amplification circuit, and the pull-down switch.
2. The pulse circuit according to claim 1, characterized in that, The pull-up switch includes an NMOS transistor and a first resistor, and the pull-down switch includes a first NPN transistor, a second resistor, and a third resistor. The drain of the NMOS transistor is connected to a second power supply, and the gate of the NMOS transistor is connected to the second terminal of the signal amplification circuit and one end of the first resistor. The base of the first NPN transistor is connected to the main control chip through the second resistor, and the emitter of the first NPN transistor is grounded through the third resistor. The source of the NMOS transistor is connected to the collector of the first NPN transistor and the other end of the first resistor. The NMOS transistor and the first NPN transistor cooperate to output a pulse signal.
3. The pulse circuit according to claim 2, characterized in that, The boost circuit further includes a second diode and a second capacitor. The anode of the second diode is connected to the cathode of the first diode and the other end of the first capacitor. The cathode of the second diode is connected to one end of the second capacitor and the first terminal of the signal amplification circuit. The other end of the second capacitor is connected to the source of the NMOS transistor and the collector of the first NPN transistor.
4. The pulse circuit according to claim 3, characterized in that, The boost control circuit includes a second NPN transistor, a fourth resistor, and a charging switch. The base of the second NPN transistor is connected to the main control chip through the fourth resistor. The charging switch is connected to the main control chip. The emitter of the second NPN transistor is grounded. The collector of the second NPN transistor and the charging switch are connected to one end of the first capacitor. The charging switch and the second NPN transistor charge and discharge one end of the first capacitor in sequence.
5. The pulse circuit according to claim 4, characterized in that, The charging switch includes a third NPN transistor, a fourth NPN transistor, a fifth resistor, and a sixth resistor. The collector of the third NPN transistor and one end of the fifth resistor are connected to the source of the NMOS transistor and the collector of the first NPN transistor. The emitter of the third NPN transistor is connected to one end of the first capacitor. The base of the third NPN transistor is connected to the other end of the fifth resistor and the collector of the fourth NPN transistor. The base of the fourth NPN transistor is connected to the main control chip. The emitter of the fourth NPN transistor is grounded.
6. The pulse circuit according to claim 3, characterized in that, The signal amplification circuit includes a fifth NPN transistor, a seventh resistor, and an eighth resistor. The collector of the fifth NPN transistor and one end of the eighth resistor are connected to the cathode of the second diode and one end of the second capacitor. The other end of the eighth resistor is connected to the base of the fifth NPN transistor and the main control chip. The emitter of the fifth NPN transistor is connected to the gate of the NMOS transistor through the seventh resistor.
7. The pulse circuit according to claim 6, characterized in that, The signal amplification circuit further includes a PNP transistor, a ninth resistor, and a tenth resistor. The emitter of the PNP transistor is connected to the gate of the NMOS transistor through the tenth resistor. The base of the PNP transistor is connected to one end of the ninth resistor. The other end of the ninth resistor is connected to the base of the fifth NPN transistor and the main control chip. The collector of the PNP transistor is connected to the source of the NMOS transistor and the collector of the first NPN transistor.
8. The pulse circuit according to claim 7, characterized in that, The signal amplification circuit also includes a sixth NPN transistor and an eleventh resistor. The collector of the sixth NPN transistor is connected to the other end of the ninth resistor and the base of the fifth NPN transistor. The base of the sixth NPN transistor is connected to the main control chip through the eleventh resistor. The emitter of the sixth NPN transistor is grounded.
9. The pulse circuit according to claim 8, characterized in that, The signal amplification circuit also includes a third capacitor, which is connected in parallel with the eleventh resistor.