Pulse wave width modulation signal generation method and circuit
By combining a controller, counter, comparator, lookup table, and delay circuit, and utilizing delay values and lookup table techniques, the problem of increasing the clock signal frequency is solved in the prior art for improving the resolution of pulse width modulation signals, thus realizing the generation of high-resolution pulse width modulation signals.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHROMA ATE (SUZHOU) CO LTD
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-21
AI Technical Summary
Existing technologies require increasing the frequency of the clock signal to improve the resolution of pulse width modulation signals, which leads to increased cost and complexity.
By combining a controller, counter, comparator, lookup table, output double data rate buffer, and output delay circuit, a high-resolution pulse width modulation signal can be generated without increasing the clock signal frequency using delay values and lookup table techniques.
Without increasing the clock signal frequency, the resolution of the pulse width modulation signal is significantly improved from 9.96 bits to 14.96 bits, enabling the generation of more than 13,000 working cycle states and achieving high-resolution pulse width modulation.
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Figure CN121907207A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a digital signal generation method, and more particularly to a pulse width modulation signal generation method. Background Technology
[0002] See Figure 1 This is a basic method for generating pulse width modulation (PWM) signals. It mainly involves a comparator (not shown) comparing a target value with the level of a carrier S generated by a counter (not shown). When the level of the carrier S is less than the target value, the comparator sets the output digital signal D to a high level until the level of the carrier S reaches (equals) the target value. Then, the comparator sets the digital signal D to a low level, thereby generating a PWM signal with a target duty cycle.
[0003] And such as Figure 2 As shown, comparison Figure 2 As shown in the right and left figures, when the PWM signal frequency is 200kHz, to generate more duty cycles within one cycle (5μs) of the PWM signal (compare...), Figure 2 To improve the resolution of the PWM signal (as shown in the right and left figures), the frequency of the clock signal that generates the carrier S needs to be increased. For example, if the clock signal is 200MHz, the carrier S can generate 1000 level changes within one cycle (5μs) of the PWM signal, allowing the PWM signal to generate 1000 states in its working cycle, which is approximately 9.96 bits of resolution. Therefore, when the PWM signal needs to generate 13000 states in its working cycle, i.e., have 13.66 bits of resolution, the frequency of the clock signal needs to be as high as 2.6GHz, i.e., 5μs / (1 / 2.6G) = 13000. Summary of the Invention
[0004] The purpose of this invention is to provide a pulse width modulation signal generation method and circuit that can generate a high-resolution pulse width modulation signal without increasing the frequency of the clock signal.
[0005] Therefore, the present invention provides a pulse width modulation (PWM) signal generation method comprising: a controller determining a working period based on a clock signal, converting the working period into a default value and a delay value, and inputting the default value into a comparator and the delay value into a lookup table; the controller controlling a counter to count according to the clock signal and inputting a count value into the comparator; the controller controlling the comparator to output a first digital signal at a first level to the lookup table, until the comparator determines that the count value has reached the default value, the comparator outputs the first digital signal at a second level to the lookup table; the controller instructing the lookup table to determine that the first digital signal changes from the first level to the second level. During positioning, based on a trigger delay data obtained from a table using the delay value, the first digital signal is converted into two second digital signals and output to an output double data rate buffer. Simultaneously, a delay number is calculated based on the delay value and output to an output delay circuit. The controller instructs the output double data rate buffer to generate and output a third digital signal to the output delay circuit based on the two second digital signals. The third digital signal has double the data rate compared to the first digital signal and is either not delayed or delayed by half a clock cycle of the clock signal. The controller instructs the output delay circuit to delay the third digital signal by a default time based on the delay number to generate and output a pulse width modulation signal with the working cycle.
[0006] Furthermore, a pulse width modulation signal generation circuit for implementing the above method according to the present invention includes a controller, a counter electrically connected to the controller, a comparator electrically connected to the controller and the counter, a lookup table electrically connected to the controller and the comparator, an output double data rate buffer electrically connected to the controller and the lookup table, and an output delay circuit electrically connected to the controller, the lookup table, and the output double data rate buffer; wherein, the controller determines a working period based on a clock signal, converts the working period into a default value and a delay value, and inputs the default value into the comparator and the delay value into the lookup table; the counter is controlled by the controller to count according to the clock signal and inputs a count value into the comparator; the comparator is controlled by the controller to output a first digital signal at a first level to the lookup table until the comparator determines that the count value has reached the first level. At the default value, the comparator outputs the first digital signal at the second level to the lookup table; the lookup table, controlled by the controller, determines when the first digital signal changes from the first level to the second level, and according to the delay value, obtains a trigger delay data from the lookup table, converts the first digital signal into two second digital signals and outputs them to the output double data rate buffer, and simultaneously calculates a delay number according to the delay value and outputs it to the output delay circuit; the output double data rate buffer, controlled by the controller, generates and outputs a third digital signal to the output delay circuit based on the two second digital signals, the third digital signal having double the data rate compared to the first digital signal and not delayed or delayed by half a clock cycle of the clock signal; the output delay circuit, controlled by the controller, delays the third digital signal by a default time according to the delay number to generate and output a pulse width modulation signal with the working cycle.
[0007] In some embodiments of the present invention, the controller controls the counter to count up or down the clock cycle of the clock signal according to the clock signal, and the counter also inputs a directional value representing the counting direction to the comparator to notify the comparator that the counter is currently counting up or down; when the controller controls the counter to count up, the default value is M clock cycles (M is an integer) and the delay value is N clock cycles (N is a value less than 1); when the controller controls the counter to count down, the default value is (M+1) clock cycles and the delay value is (1-N) clock cycles.
[0008] In some embodiments of the present invention, when the counter counts up, the first level is a high level, the second level is a low level, and the two second digital signals cause the trailing edge of the third digital signal generated by the output double data rate buffer to be either not delayed or delayed by half a clock cycle of the clock signal; when the counter counts down, the first level is a low level, the second level is a high level, and the two second digital signals cause the leading edge of the third digital signal generated by the output double data rate buffer to be either not delayed or delayed by half a clock cycle of the clock signal.
[0009] In some embodiments of the present invention, the output delay circuit includes a plurality of delay components connected in series and a multiplexer electrically connected to the output terminal of the delay components. The multiplexer causes the third digital signal to pass through the delay components in a number equal to the number of delays before outputting the pulse width modulation signal, wherein each of the delay components can delay by 78 picoseconds.
[0010] The beneficial effects of this invention are as follows: when the clock signal is 200MHz and the pulse width modulation signal is 200KHz, by means of the lookup table, the output double data rate buffer, and the output delay circuit, without increasing the frequency of the clock signal, when the output delay circuit has 32 delay components, the resolution of the generated pulse width modulation signal can be increased by 5 bits from the original 9.96 bits to a resolution of 14.96 bits, meeting the requirements of high resolution, and capable of making a tiny pulse width modulation of 78ps. Attached Figure Description
[0011] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:
[0012] Figure 1 This is a schematic diagram illustrating the basic method for generating pulse width modulation signals.
[0013] Figure 2 A schematic diagram illustrating how to improve the resolution of a pulse width modulation signal.
[0014] Figure 3 These are the main process steps of an embodiment of the pulse width modulation signal generation method of the present invention.
[0015] Figure 4 This is a circuit block diagram of an embodiment of the pulse width modulation signal generation circuit of the present invention.
[0016] Figure 5 This is a detailed circuit block diagram of the output delay circuit in this embodiment.
[0017] Figure 6This embodiment describes the process of generating a pulse width modulation signal with a working period of 480.625 clock cycles based on the carrier number.
[0018] Figure 7 The output double data rate buffer in this embodiment generates a digital signal with double data rate and trailing edge delay of half a clock cycle based on the two input digital signals.
[0019] Figure 8 This embodiment describes an output double data rate buffer that generates a digital signal with double data rate and no trailing edge delay based on two input digital signals.
[0020] Figure 9 This embodiment describes the process of generating a pulse width modulation signal with a working period of 480.625 clock cycles based on the carrier number.
[0021] Figure 10 The output double data rate buffer in this embodiment generates a digital signal with double data rate and no leading edge delay based on the two input digital signals.
[0022] Figure 11 The output double data rate buffer in this embodiment generates a digital signal with double data rate and a leading edge delay of half a clock cycle based on the two input digital signals.
[0023] Figure 12 This embodiment describes the process of generating a pulse width modulation signal with a working period of 499.9 clock cycles based on the number of carrier ups and downs. Detailed Implementation
[0024] Before the invention is described in detail, it should be noted that similar components are represented by the same numbers in the following description.
[0025] See Figure 3 The diagram illustrates the flow steps of an embodiment of the pulse width modulation signal generation method of the present invention, and it is composed of... Figure 4 The circuit shown is an implementation of the pulse width modulation (PWM) signal generation circuit of the present invention. Figure 4As shown, the PWM generation circuit 100 in this embodiment mainly includes a controller 1, a counter 2, a comparator 3, a lookuptable 4, an output double data rate (ODDR) buffer 5, and an output delay circuit 6. The controller 1 provides a clock signal CLK to the counter 2, the lookuptable 4, the ODDR buffer 5, and the output delay circuit 6 to drive their operation. The aforementioned components can be, but are not limited to, the IP (silicon intellectual property) built into the Kintex-7 FPGA (Field Programmable Gate Array) published by Xilinx.
[0026] In this embodiment, the clock signal CLK is taken as an example with a frequency of 200MHz, that is, one clock cycle is 5ns (nanoseconds). And as... Figure 5 As shown, the output delay circuit 6 basically consists of several series-connected delay components (tap) 61 and a multiplexer 62 electrically connected to the output terminals of the delay components 61. Under the control of the multiplexer 62, a signal can be input from the first delay component 61, pass through a default number of delay components 61, and then be output by the multiplexer 62, thus achieving the purpose of delaying the signal for a certain period of time. In this embodiment, the number of delay components 61 is, for example, but not limited to, 31, and each delay component 61 can delay for, for example, but not limited to, 78 picoseconds (ps). Therefore, the output delay circuit 6 is equivalent to providing 5-bit resolution.
[0027] Furthermore, this embodiment uses a PWM signal with a frequency of 200kHz as an example for explanation. Therefore, as... Figure 3 In step S1, when a PWM signal is to be generated, the controller 1 in this embodiment first determines a duty cycle of the PWM signal to be generated based on the clock signal CLK, for example, the clock cycle of 480.625 clock signals CLK, that is, a duty cycle of 480.625 x 5 ns (nanoseconds) is generated within one cycle (5μs) of the PWM signal, and the duty cycle is converted into a default value and a delay value. For example, when the counter 2 is set to count from 0, the integer (480) of 480.625 is used as the default value, the decimal (0.625) of 480.625 is used as the delay value, and the default value (480) is input to the comparator 3, and the delay value (0.625) is input to the lookup table 4.
[0028] Next, as Figure 3In step S2, the controller 1 controls the counter 2 to perform counting based on the clock signal CLK and inputs the generated count value into the comparator 3. Specifically, the counter 2 generates a count value based on the clock signal CLK. Figure 6 The comparator 3 outputs a continuously counting (sawtooth wave) carrier signal f1 and a direction value dir representing the counting direction to the comparator 3. The count value is the current level of the carrier signal f1. The direction value dir is 0 for counting up and 1 for counting down, but is not limited to this.
[0029] Then, as Figure 3 In step S3, the controller 1 controls the comparator 3 to output a first digital signal D11 located at a first level (e.g., a high level) to the lookup table 4 according to the direction value dir (e.g., 0). Figure 6 As shown, compare whether the count value (level) of the carrier signal f1 reaches (equals or is greater than) the default value. If so, as... Figure 6 As shown, the comparator 3 changes the first digital signal D11 from the first level (high level) to the second level (low level) and outputs the first digital signal D11 to the lookup table 4.
[0030] Next, in Figure 3 In step S4, the controller 1 instructs the lookup table 4 to determine when the first digital signal D11 changes from the first level to the second level. Based on the delay value (0.625), the controller 1 looks up a trigger delay data in the table and converts the first digital signal D11 into two second digital signals D21 and D22 based on the trigger delay data. The controller then outputs the two second digital signals D21 and D22 to the output double data rate buffer 5. At the same time, the lookup table 4 also calculates a delay number TN based on the delay value and outputs the delay number TN to the output delay circuit 6.
[0031] Specifically, the lookup table process of the lookup table 4 is as follows: when the first digital signal D11 changes from a high level to a low level (i.e., the counter 2 is counting up), and the lookup table 4 determines that the delay value (0.625) is greater than or equal to 0.5, then the first data in the trigger delay data is set to 1 and the second data is set to 0; conversely, if the lookup table 4 determines that the delay value is less than 0.5, then the first data in the trigger delay data is set to 0 and the second data is set to 0. Therefore, in this embodiment, the first data in the trigger delay data is 1 and the second data is 0. Next, the lookup table 4 converts the first digital signal D11 into the second digital signal D21 according to the first data (1) in the trigger delay data, such as... Figure 7 As shown, the first data (1) causes the trailing edge of the second digital signal D21 to be delayed by one clock cycle compared to the first digital signal D11, while the second data (0) causes the trailing edge of the second digital signal D22 to remain unchanged and the same as the first digital signal D11. Therefore, when the counter 2 counts, the trigger delay data is used to determine whether the trailing edges of the second digital signals D21 and D22 should be delayed by one clock cycle compared to the first digital signal D11.
[0032] Specifically, the lookup table 4 determines the delay value based on the delay value. If the delay value is greater than or equal to 0.5, it calculates the delay number TN based on the value obtained by subtracting 0.5 from the delay value. The delay number TN refers to the number of delay components 61 connected in series in the output delay circuit 6. Therefore, in this embodiment, the lookup table 4 calculates the delay number TN based on 0.125 (0.625-0.5). Thus, one clock cycle (1 / 200MHz) is 5 nanoseconds (ns), 0.125 clock cycles is 0.625 nanoseconds (ns), or 625 picoseconds (ps). Since one delay component is 78 picoseconds, 625 picoseconds is equivalent to using 8 (625 / 78) delay components 21. Therefore, the delay number TN is 8. Furthermore, as... Figure 4 As shown, the lookup table 4 also transmits a trigger signal TD to notify the output delay circuit 6 to load the delay number TN.
[0033] Next, proceed Figure 3 In step S5, the controller 1 instructs the output double data rate buffer 5 to generate and output a third digital signal D31 to the output delay circuit 6 based on the two input second digital signals D21 and D22, and as follows... Figure 7 As shown, the third digital signal D31 has twice the data rate of the first digital signal D11, and its trailing edge is delayed by half a clock cycle. This is because the trailing edge of the second digital signal D21 is at a high level (1), while the trailing edge of the second digital signal D22 is at a low level (0), causing the trailing edge of the third digital signal D31 to be delayed by half a clock cycle compared to the first digital signal D11. Conversely, in another case, such as Figure 8 As shown, if the trailing edges of the two second digital signals D21 and D22 are both low level (0), the trailing edge of the generated third digital signal D31' will be the same as that of the first digital signal D11 without delay.
[0034] Next, as Figure 3In step S6, the controller 1 instructs the multiplexer 62 of the output delay circuit 6 to delay the input third digital signal D31 by a default time (i.e., 8 x 78 = 624 picoseconds, close to the aforementioned 625 picoseconds) through eight cascaded delay components 61 according to the delay number (8) before outputting a PWM signal D41 with a working period of 480.625 clock cycles. Figure 6 As shown.
[0035] Furthermore, when a PWM signal with a working cycle of 480.625 clock cycles is also to be generated, but the controller 1 sets the counter 2 to start counting down from the maximum value (e.g., 500), since time cannot be reversed, in the above step S1, (480+1) will be used as the default value and (1-0.625) will be used as the delay value. That is, 480.625 clock cycles are obtained by subtracting (delay) 0.375 clock cycles from the 481st clock cycle. Therefore, the default value (481) is input to the comparator 3 and the delay value (0.375) is input to the lookup table 4.
[0036] Therefore, in step S2, the counter 2 starts counting from the maximum value (e.g., 500) and generates and outputs the following: Figure 9 The carrier signal f2 and the direction value (1) representing the counting direction are sent to the comparator 3. Then, in step S3, the comparator 3 outputs a first digital signal D12 located at a first level (e.g., a low level) to the lookup table 4 according to the direction value (1), as shown. Figure 9 As shown, compare whether the count value (level) of the carrier signal f2 reaches the default value (481). If so, as Figure 9 As shown, the comparator 3 changes the first digital signal D12 from the first level (low level) to the second level (high level) and outputs the first digital signal D12 to the lookup table 4.
[0037] Next, in Figure 3 In step S4, the controller 1 instructs the lookup table 4 to determine when the first digital signal D12 changes from the first level to the second level, and obtains a trigger delay data by looking up the table according to the delay value (0.375). That is, the lookup table 4 determines that the delay value (0.375) is less than 0.5, and makes the first data in the generated trigger delay data 1 and the second data 1, and so on. Figure 10As shown, the lookup table 4 converts the first digital signal D12 into two second digital signals D23 and D24 according to the trigger delay data and outputs the two second digital signals D23 and D24 to the output double data rate buffer 5. The first data (1) ensures that the leading edge of the second digital signal D23 is not delayed compared to the first digital signal D12 and remains the same as the first digital signal D12. Similarly, the second data (1) also ensures that the leading edge of the second digital signal D24 is not delayed and remains the same as the first digital signal D12. Conversely, as... Figure 11 As shown, if the delay value is greater than 0.5, the first data in the trigger delay data will be 0 and the second data will be 1, causing the leading edge of the second digital signal D23 to be delayed by one clock cycle compared to the first digital signal D12, while the leading edge of the second digital signal D24 remains unchanged and the same as the first digital signal D12. Therefore, when counter 2 counts down, the trigger delay data is used to determine whether the leading edges of the second digital signals D23 and D24 should be delayed by one clock cycle compared to the first digital signal D12.
[0038] Meanwhile, the lookup table 4 also calculates a delay number based on the delay value (0.375) and outputs the delay number to the output delay circuit 6. In this example, the delay number is 24, which is 1875 picoseconds (0.375 clock cycles) / 78 picoseconds.
[0039] Then, in Figure 3 In step S5, the controller 1 instructs the output double data rate buffer 5 to generate and output a third digital signal D32 to the output delay circuit 6 based on the two input second digital signals D23 and D24, and as follows Figure 10 As shown, the third digital signal D32 has twice the data rate of the first digital signal D12 and its leading edge is not delayed because the leading edges of the two second digital signals D23 and D24 are both at high levels (1), which makes the leading edge of the third digital signal D32 not delayed compared to the first digital signal D12. Conversely, as Figure 11 As shown, if the leading edge of the second digital signal D23 is at a low level (0) and the leading edge of the second digital signal D24 is at a high level (1), the leading edge of the generated third digital signal D32' will be delayed by half a clock cycle compared to the first digital signal D12.
[0040] Next, in Figure 3In step S6, the controller 1 instructs the multiplexer 62 of the output delay circuit 6 to delay the input third digital signal D32 by a default time (i.e., 78 x 24 = 1872 picoseconds, close to the aforementioned 1875 picoseconds) via 24 cascaded delay components 61 according to the delay number (24), thereby generating and outputting a PWM signal D42 with the working cycle (480.625 clock cycles). Figure 9 As shown.
[0041] In addition, such as Figure 12 As shown, when the working period of the PWM signal to be generated is an extreme value, such as 499.9 clock cycles, and the carrier wave generated by the up and down counting of the counter 2, i.e., the triangular wave f3 shown in the figure, is used to generate the PWM signal, the controller 1 will set the default value to 499 and the delay value to 0.9 for the up counting case of the counter 2. Figure 12 As shown, after the comparator 3 outputs a first digital signal D13 with a working cycle of 499 clock cycles, the first digital signal D13 is delayed by half (0.5) clock cycles via the lookup table 4 and the output double data rate buffer 5 to generate and output a third digital signal D33 to the output delay circuit 6. The output delay circuit 6 then outputs a PWM signal D43 with a working cycle of 499.9 clock cycles after being delayed by approximately 0.4 clock cycles based on the delay number calculated by the lookup table 4 based on the delay value (0.9) - 0.5 (0.4).
[0042] When the counter 2 counts down, the controller 1 sets the default value to (499+1) and the delay value to (1-0.9), thereby... Figure 12 As shown, the comparator 3 initially outputs a first digital signal D14 with a working cycle of 500 working cycles. Then, the first digital signal D14 passes through the lookup table 4 and the output double data rate buffer 5 without delay (because the delay value (0.1) is less than 0.5) to generate and output a third digital signal D34 to the output delay circuit 6. Then, the output delay circuit 6 delays the third digital signal D34 by 0.1 clock cycles according to the delay number calculated by the lookup table 4 based on the delay value (0.1) to generate and output a PWM signal D44 with a working cycle of 499.9.
[0043] It is worth mentioning that although this embodiment takes the frequency of the clock signal CLK as 1000 times that of the PWM signal as an example, it is not limited to this. For example, the frequency of the clock signal CLK is about 64 times or more of the frequency of the PWM signal and can be applied to this embodiment.
[0044] In summary, the above embodiments, through the lookup table 4, the output double data rate buffer 5, and the output delay circuit 6, can increase the resolution of the generated PWM signal's working cycle from the original 9.96 bits to 14.96 bits without increasing the frequency of the clock signal. When the output delay circuit 6 has 32 delay components, it can provide more than 13,000 working cycle states, meeting the requirements of high resolution, and can make tiny pulse width modulation of 78 ps, thus truly achieving the effects and objectives of the present invention.
Claims
1. A method for generating a pulse width modulation signal, characterized in that: The pulse width modulation signal generation method includes: A controller determines a working cycle based on a clock signal, converts the working cycle into a default value and a delay value, and inputs the default value into a comparator and the delay value into a lookup table. The controller controls a counter to count according to the clock signal and inputs a count value into the comparator; The controller controls the comparator to output a first digital signal at a first level to the lookup table until the comparator determines that the count value has reached the default value, at which point the comparator outputs the first digital signal at a second level to the lookup table. When the controller instructs the lookup table to determine that the first digital signal changes from the first level to the second level, it uses a trigger delay data obtained by looking up the table based on the delay value to convert the first digital signal into two second digital signals and output them to an output double data rate buffer. At the same time, it calculates a delay number based on the delay value and outputs it to an output delay circuit. The controller instructs the output double data rate buffer to generate and output a third digital signal to the output delay circuit based on the two second digital signals. The third digital signal has double the data rate compared to the first digital signal and is either not delayed or delayed by half a clock cycle of the clock signal. The controller instructs the output delay circuit to delay the third digital signal by a default time according to the delay number to generate and output a pulse width modulation signal having the duty cycle.
2. The pulse width modulation signal generation method according to claim 1, characterized in that: The controller controls the counter to count up or down the clock cycle of the clock signal according to the clock signal, and the counter also inputs a directional value representing the counting direction to the comparator to notify the comparator that the counter is currently counting up or down; when the controller controls the counter to count up, the default value is M clock cycles (M is an integer) and the delay value is N clock cycles (N is a value less than 1); when the controller controls the counter to count down, the default value is (M+1) clock cycles and the delay value is (1-N) clock cycles.
3. The pulse width modulation signal generation method according to claim 2, characterized in that: When the counter counts up, the first level is a high level, the second level is a low level, and the two second digital signals cause the trailing edge of the third digital signal generated by the output double data rate buffer to be either not delayed or delayed by half a clock cycle of the clock signal; when the counter counts down, the first level is a low level, the second level is a high level, and the two second digital signals cause the leading edge of the third digital signal generated by the output double data rate buffer to be either not delayed or delayed by half a clock cycle of the clock signal.
4. The pulse width modulation signal generation method according to any one of claims 1 to 3, characterized in that: The output delay circuit includes several series-connected delay components and a multiplexer electrically connected to the output terminals of the delay components. The multiplexer causes the third digital signal to pass through the delay components in a number equal to the number of delays before outputting the pulse width modulation signal, wherein each delay component can delay by 78 picoseconds.
5. A pulse width modulation signal generation circuit, characterized in that: The pulse width modulation signal generation circuit includes: One controller; A counter, which is electrically connected to the controller; A comparator, which is electrically connected to the controller and the counter; A lookup table device, which is electrically connected to the controller and the comparator; A double data rate output buffer, electrically connected to the controller and the lookup table; and An output delay circuit is electrically connected to the controller, the lookup table, and the output double data rate buffer; wherein The controller determines a working cycle based on a clock signal, converts the working cycle into a default value and a delay value, and inputs the default value into the comparator and the delay value into the lookup table. The counter is controlled by the controller to count according to the clock signal and inputs a count value into the comparator; The comparator is controlled by the controller to output a first digital signal at a first level to the lookup table until the comparator determines that the count value has reached the default value, at which point the comparator outputs the first digital signal at a second level to the lookup table. When the lookup table device, controlled by the controller, determines that the first digital signal changes from the first level to the second level, it retrieves a trigger delay data from the lookup table based on the delay value, converts the first digital signal into two second digital signals, and outputs them to the output double data rate buffer. Simultaneously, a delay number is calculated based on the delay value and output to the output delay circuit; The output double data rate buffer is controlled by the controller to generate and output a third digital signal to the output delay circuit based on the two second digital signals. The third digital signal has double the data rate compared to the first digital signal and does not delay or delays the clock signal by half a clock cycle. The output delay circuit, controlled by the controller, delays the third digital signal by a default time according to the delay number to generate and output a pulse width modulation signal having the duty cycle.
6. The pulse width modulation signal generation circuit according to claim 5, characterized in that: The controller controls the counter to count up or down the clock cycle of the clock signal according to the clock signal, and the counter also inputs a directional value representing the counting direction to the comparator to notify the comparator that the counter is currently counting up or down; when the controller controls the counter to count up, the default value is M clock cycles (M is an integer) and the delay value is N clock cycles (N is a value less than 1); when the controller controls the counter to count down, the default value is (M+1) clock cycles and the delay value is (1-N) clock cycles.
7. The pulse width modulation signal generation circuit according to claim 6, characterized in that: When the counter counts up, the first level is a high level, the second level is a low level, and the two second digital signals cause the trailing edge of the third digital signal generated by the output double data rate buffer to be either not delayed or delayed by half a clock cycle of the clock signal; when the counter counts down, the first level is a low level, the second level is a high level, and the two second digital signals cause the leading edge of the third digital signal generated by the output double data rate buffer to be either not delayed or delayed by half a clock cycle of the clock signal.
8. The pulse width modulation signal generation circuit according to any one of claims 5 to 7, characterized in that: The output delay circuit includes several series-connected delay components and a multiplexer electrically connected to the output terminals of the delay components. The multiplexer causes the third digital signal to pass through the delay components in a number equal to the number of delays before outputting the pulse width modulation signal, wherein each delay component can delay by 78 picoseconds.