Multiplexer for connecting any one of plurality of input signals to output path

Abstract

A multiplexer for connecting any one of a plurality of input signals to an output path for connecting any one of a plurality of input signals to an output path includes a plurality of transistors, a set of switches, and a control unit. Each transistor has a control terminal and a pair of current terminals. The pair of terminals is connected to a fixed reference potential and an output node at one end of the output path, respectively. When an input signal is sent to a control terminal, each transistor can provide a corresponding forwarding signal at an output node; and when the control terminal is connected to the fixed reference potential, the output node enters three states. The control unit controls the group of switches according to a received control value, couples a corresponding input signal to the control terminal of only one transistor, and simultaneously connects the control terminals of the other transistors to a fixed reference potential.

Description

[0001] Priority Statement

[0002] This invention relates to and claims priority to the following Indian provisional patent application: Application No. 202541005303, filed January 22, 2025. This invention relates to and claims priority to the following U.S. patent applications: Application No. 19 / 361,037, filed October 17, 2025; and Application No. 19 / 361,039, filed October 17, 2025. The entire contents of these applications are incorporated herein by reference only, without prejudice to this specification. Technical Field

[0003] Embodiments of the present invention generally relate to signal transmission in wired media, and more specifically, to a multiplexer for connecting any one of a plurality of input signals to an output path. Background Technology

[0004] A multiplexer (MUX) is a circuit with multiple input nodes and one output node. It can control the selection of one of multiple input signals received from the respective input nodes and transmit (forward) the selected input signal to the output node. The multiplexer receives a "select" signal, indicating which input signal should be transmitted at the output node.

[0005] Various aspects of the present invention relate to a multiplexer. Summary of the Invention

[0006] This invention provides a multiplexer for connecting any one of a plurality of input signals to an output path, characterized in that it comprises: a plurality of transistors, each transistor having a control terminal and a pair of current terminals, wherein one end of the pair of current terminals is connected to a constant reference potential, and the other end is connected to an output node at one end of the output path, wherein the transistor is operable to provide a forwarding signal corresponding to a transistor control signal at the output node, causing the output node to be tri-state if the transistor control signal is received at the control terminal and if the control terminal is coupled to the constant reference potential; a set of switches; and a control unit for receiving a value indicating that a specific transistor among the plurality of transistors should provide a corresponding input signal to the output path, the control unit controlling the switch group of the specific transistor to couple the corresponding input signal as a transistor control signal to the control terminal of the specific transistor; the control unit controlling the switch groups of the remaining transistors among the plurality of transistors to provide the constant reference potential to the control terminals of the remaining transistors.

[0007] In some embodiments, the multiplexer includes a plurality of drivers, each driver receiving a corresponding input signal, and only one of the plurality of drivers provides a corresponding forwarding signal to the output path. Each of the plurality of drivers includes: a first pair of transistors, coupled in series at a first contact and disposed between a first constant reference potential and a second constant reference potential, wherein the constant reference potential is one of the first constant reference potential and the second constant reference potential, and the first contact is the output node, wherein each of the plurality of transistors corresponds to a transistor in the first pair of transistors; and a first pair of switches included in the set of switches, which, when closed, couple a corresponding control terminal of each of the first pair of transistors to the corresponding input signal, and when open, couple a corresponding control terminal of each of the first pair of transistors to the corresponding input signal. The corresponding control terminal is decoupled from the corresponding input signal; and a second pair of switches included in the group of switches, when closed, couples the corresponding control terminal of the first pair of transistors to a corresponding potential of the first constant reference potential and the second constant reference potential, and when open, decouples the corresponding control terminal of the first pair of transistors from a corresponding potential of the first constant reference potential and the second constant reference potential. In order to ensure that only the driver containing the specific transistor forwards the corresponding input signal to the output path and makes the output nodes of the remaining multiple drivers tri-state, the control signal performs the following operations: closes the first pair of switches of the specific driver and opens each of the first pair of switches in the remaining multiple drivers; and opens the second pair of switches of the specific driver and closes each of the second pair of switches in the remaining multiple drivers.

[0008] In some embodiments, each of the plurality of input signals is a single-ended signal, and the output path includes the output node and one or both of the first constant reference potential and the second constant reference potential.

[0009] In some embodiments, each of the plurality of input signals is a differential signal, comprising a first complementary signal and a second complementary signal, wherein the first complementary signal is provided as a transistor control signal for each of the plurality of transistors, wherein the output path is a differential path, and wherein each of the plurality of drivers further comprises: a second pair of transistors, which are coupled in series at a second contact and disposed between the first constant reference potential and the second constant reference potential, wherein the second contact is coupled to the output path at a second output node of the driver, wherein the output node and the second output node together provide an output signal differentially on the output path; and a third pair of switches, which, when closed, couple the second complementary signal corresponding to the input signal to the control terminal of each of the second pair of transistors, and when open, couple the second complementary signal of the second pair of transistors to the control terminal of each of the second pair of transistors. Each control terminal is decoupled from the second complementary signal of the corresponding input signal; and a fourth pair of switches, when closed, couples the corresponding control terminal of the second pair of transistors to a corresponding potential of the first constant reference potential and the second constant reference potential, and when open, decouples the corresponding control terminal of the second pair of transistors from a corresponding potential of the first constant reference potential and the second constant reference potential. In order to ensure that only a specific driver containing the specific transistor forwards the corresponding second complementary signal to the output path and makes the output nodes of the remaining multiple drivers tri-state, the control signal also performs the following operations: closes the third set of switches of the specific driver and opens each of the third set of switches of the remaining multiple drivers; and opens the fourth set of switches of the specific driver and closes each of the fourth set of switches of the remaining multiple drivers.

[0010] In some embodiments, each of the plurality of drivers is a source-series-terminated (SST) differential inverter.

[0011] In some embodiments, each of the plurality of drivers further includes: a first impedance coupled between the first transistor of the first pair of transistors and the first contact; a second impedance coupled between the second transistor of the first pair of transistors and the first contact; a third impedance coupled between the first transistor of the second pair of transistors and the second contact; and a fourth impedance coupled between the second transistor of the second pair of transistors and the second contact.

[0012] In some embodiments, the impedance values ​​of the first impedance, the second impedance, the third impedance, and the fourth impedance are all equal.

[0013] In some embodiments, the differential output impedance of the driver is less than the characteristic impedance of the output path.

[0014] The present invention further provides a signal distributor comprising a first plurality of input ports and a second plurality of output ports. The signal distributor is operable to couple each input port of the first plurality of input ports to any output port of the second plurality of output ports. The signal distributor further comprises: a third plurality of multiplexers, wherein the number of multiplexers in the third plurality of multiplexers is equal to the number of ports in the second plurality of output ports; wherein each multiplexer in the third plurality of multiplexers has a fourth plurality of input nodes, each input node being coupled to a corresponding input port of the first plurality of input ports; wherein each multiplexer in the third plurality of multiplexers has an output node coupled to a corresponding output port of the second plurality of output ports; wherein each multiplexer includes: a plurality of transistors, each transistor having a control terminal and a pair of current terminals, wherein one end of the pair of current terminals is coupled to... The transistor is connected to a fixed reference potential at one end and to an output node at one end of the output path at the other end; wherein the transistor is operable to provide a forwarding signal corresponding to a transistor control signal at the output node, causing the output node to be tri-state if the transistor control signal is received at the control terminal and if the control terminal is coupled to the constant reference potential; a set of switches; and a control unit for receiving a value indicating which of the plurality of transistors should provide its corresponding input signal to the output path; the control unit controls a set of switches of the particular transistor, such that the corresponding input signal is coupled to the control terminal of the particular transistor as a transistor control signal; the control unit controls a set of switches of the remaining transistors in the plurality of transistors, such that the fixed reference potential is provided to the control terminals of each of the remaining transistors.

[0015] In some embodiments, each multiplexer includes multiple drivers, each driver receiving a corresponding input signal, and only one driver provides its corresponding forward output signal to the output path. Each driver includes: a first pair of transistors connected in series at a first contact and positioned between a first fixed reference potential and a second fixed reference potential, wherein the fixed reference potential is one of the first fixed reference potential and the second fixed reference potential, and the first contact is the output node, wherein each of the multiple transistors corresponds to one transistor in the first pair of transistors; and a first pair of switches, belonging to the set of switches, for coupling the control terminal of each transistor in the first pair of transistors to the corresponding input signal when closed. When disconnected, the control terminal is decoupled from the corresponding input signal; a second pair of switches, also belonging to the group of switches, is used to couple the control terminals of each of the first pair of transistors to one of the first fixed reference potential and the second fixed reference potential when closed, and to decouple each control terminal from its corresponding first or second fixed reference potential when disconnected; wherein, in order to enable the driver containing only the specific transistor to output its corresponding input signal forward to the output path, and to enable the output nodes of the remaining drivers to be tri-state, the control signal operates as follows: to close the first pair of switches of the specific driver and to open the first pair of switches of the remaining drivers; and to open the second pair of switches of the specific driver and to close the second pair of switches of the remaining drivers.

[0016] In some embodiments, the plurality of input signals are all single-ended signals, and the output path includes the output node, as well as one or both of the first fixed reference potential and the second fixed reference potential.

[0017] In some embodiments, the plurality of input signals are all differential signals, and the output path is a differential path. Each of the plurality of drivers further includes: a second pair of transistors connected in series at a second contact and disposed between the first fixed reference potential and the second fixed reference potential, wherein the second contact is coupled to a second output node of the driver on the output path; a third pair of switches for coupling the control terminals of each of the second pair of transistors to the corresponding input signal when closed, and decoupling each control terminal from the corresponding input signal when open; and a fourth pair of switches for coupling the control terminals of each of the second pair of transistors to the corresponding power supply or fixed reference potential when closed, and decoupling each control terminal from its corresponding power supply or fixed reference potential when open. To enable a specific driver containing only the specific transistors to output its corresponding second compensation signal forward to the output path, and to make the output nodes of the remaining drivers tri-state, the control signal also operates as follows: closing the third pair of switches of the specific driver and opening all third pairs of switches of the remaining drivers; and opening the fourth pair of switches of the specific driver and closing all fourth pairs of switches of the remaining drivers.

[0018] In some embodiments, each of the plurality of drivers is a source-terminated series-terminated (SST) differential inverter.

[0019] In some embodiments, each of the plurality of drivers further includes: a first impedance coupled between the first transistor of the first pair of transistors and the first contact; a second impedance coupled between the second transistor of the first pair of transistors and the first contact; a third impedance coupled between the first transistor of the second pair of transistors and the second contact; and a fourth impedance coupled between the second transistor of the second pair of transistors and the second contact.

[0020] In some embodiments, the impedance values ​​of the first impedance, the second impedance, the third impedance, and the fourth impedance are all equal.

[0021] In some embodiments, the differential output impedance of the driver is less than the characteristic impedance of the output path.

[0022] In some embodiments, the number of input ports in the first group of ports is equal to the number of output ports in the second group of ports.

[0023] In some embodiments, the number of input ports in the first group of ports is different from the number of output ports in the second group of ports. Attached Figure Description

[0024] Embodiments of the present invention will be described with reference to the accompanying drawings, which are briefly described below.

[0025] Figure 1 This is a block diagram of an example device that can implement several aspects of this disclosure.

[0026] Figure 2 This is a diagram illustrating how a multiplexer is implemented in one embodiment of various aspects of the present invention.

[0027] Figure 3 This is a diagram illustrating the implementation details of one half of the differential driver portion for a multiplexer in one embodiment of the present invention.

[0028] Figure 4 This is a diagram illustrating, in one embodiment, the implementation of a signal allocation channel using a multiplexer designed according to various aspects of the present invention.

[0029] In the accompanying drawings, the same reference numerals generally denote identical, functionally similar, and / or structurally similar components. The first appearance of a component in the accompanying drawing is indicated by the leftmost digit of the corresponding reference numeral. Detailed Implementation

[0030] 1. Overview

[0031] A multiplexer connects any one of multiple input signals to an output path. It comprises multiple transistors, a set of switches, and a control unit. Each transistor has a control terminal and a pair of current terminals, connected to a constant reference potential and an output node at one end of the output path, respectively. When the control terminal receives an input signal, each transistor provides the corresponding forwarding signal to the output node; when the control terminal is connected to the constant reference potential, the transistor puts the output node into a tri-state. Based on the received control value, the control unit controls the set of switches to couple the corresponding input signal to the control terminal of only one transistor, while connecting the control terminals of the remaining transistors to the constant reference potential.

[0032] In one embodiment, the multiplexer has multiple drivers, each receiving a corresponding input signal. Only one driver provides a forwarded signal of the corresponding input signal to the output node. Each driver is implemented as a source-series-terminated (SST) differential inverter.

[0033] A signal distributor can be constructed using multiple multiplexers, so that any one of the multiple received input signals can be provided to any one of the output ports of the signal distributor.

[0034] Several aspects of this specification are illustrated exemplarily below. However, it will be understood by those skilled in the art that this disclosure may be practiced without using one or more specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not shown in detail to avoid obscuring the features of this disclosure. Furthermore, the described features / aspects may be implemented in various combinations, although only some combinations are described in this specification for the sake of brevity.

[0035] 2. Exemplary device

[0036] Figure 1 A block diagram of an example apparatus that can be implemented for several aspects of this disclosure. Figure 1 The diagram shows relevant portions of an integrated circuit (IC) 100 (which may be a system-on-chip, SOC), including signal generators 110A to 110N, a signal distributor 120, receivers (Rx) 125A to 125N, output drivers (O / P DRV) 130A to 130N, and package pins 140A to 140N.

[0037] As used in this specification, signal generators 110A to 110N may be collectively referred to or individually by reference numeral 110, depending on the context. The same convention applies to other similar components. For clarity and conciseness, Figure 1 Other components of IC 100, such as the power supply and oscillator, are not shown. Furthermore, Figure 1 The specific modules shown are merely examples. Various aspects of the invention can also be implemented in other devices and environments.

[0038] exist Figure 1 In the example, signal generators 110A through 110N are all phase-locked loops (PLLs) used to generate clock signals. The clock signal frequency range described in this specification can be from several hertz (Hz) to several gigahertz (GHz). The clock signal can have waveforms such as square waves (or generally non-sine waves), sine waves, etc., although the description in this specification assumes a square wave.

[0039] While the following description is provided for square wave clock signals (digital signals), it should be understood that the features of this disclosure are equally applicable to other types of signals, such as analog signals, information-carrying (modulated) signals, such as video signals, modulated radio frequency (RF) signals used in wireless devices, etc. Generally, the features of this disclosure are particularly useful when the characteristics of a signal (especially its frequency content and / or rise / fall times) necessitate that the length of the signal transmission path (electrical trace) be considered as a transmission line. However, it should be noted here that the features of this disclosure can also be applied to non-transmission line environments, where a specific relationship is not required between the source impedance and load impedance of the driver and receiver and the characteristic impedance (Zo) of the corresponding transmission line used.

[0040] As is well known in the relevant art, a conductor or conductive path whose length is much greater than (e.g., more than 10 times the period of the highest frequency component in the signal) (for a square wave signal, the rise or fall time of the signal edge) should be considered a transmission line. The transmitters and receivers at both ends of the conductor, as well as the conductor itself, need to have matched controlled impedances, which is also well known in the relevant art. In IC 100, the electrical path from the PLL 110 output to output pin 140 (or the corresponding signal pad on the chip) is subject to length constraints imposed by the various circuits and modules within IC 100 (including...). Figure 1 The layout of the parts not shown in the image, as well as the wiring required for traces, signal pads, and package pins between them, are therefore considered as transmission lines.

[0041] As described in this specification, the path from the output of signal generator 110 to each pin of IC 100 is a differential path for transmitting differential signals. However, these paths and signals can also be single-ended signals, requiring only corresponding modifications to the circuits and modules described in this specification, a point that will be understood by those skilled in the art upon reading this disclosure.

[0042] In the examples provided in this specification, signal generators 110A to 110N are all phase-locked loops (PLLs) and generate clock signals at their output nodes. In one embodiment, the modules within each PLL (such as phase detectors, low-pass filters, etc.) are single-ended circuits, and the generated clock signal is a single-ended clock. However, in another embodiment, IC 100 uses a fully differential PLL to generate differential clock signals. When the PLL circuit generates a single-ended clock signal, a single-ended to differential converter (not shown) is used in the PLL to convert the single-ended clock signal into differential form.

[0043] In the embodiments described in this specification, the signal distributor 120, receiver 125, and output driver 130 employ differential circuitry and operate on differential signals, with each pin 140 being a pair of pins. However, in another embodiment, Figure 1 All components and modules are single-ended circuits, and each pin 140 is a single pin. The output of PLL 110 is connected to the corresponding input port of signal distributor 120. Therefore, the clock signal generated by PLL 110A is provided to the input port In1 of signal distributor 120 through path 112A.

[0044] Each of the receivers (Rx) 125A through 125N is connected to a corresponding output port of signal distributor 120. For example, Rx 125A is connected to output port O1 via path 122A. Receiver 125 receives a corresponding clock signal from the output port of signal distributor 120 and amplifies the clock signal to the desired level. For example, when the clock is a square wave signal with binary logic levels, receiver 125 can be designed to amplify the received clock signal to a rail-to-rail level. The received clock signal may have a low signal swing (low amplitude), which may be because the signal itself is generated as a low-swing signal and / or is distorted due to noise and / or signal reflection. Receiver 125 forwards its amplified signal (after internal buffering) to the corresponding driver in output driver 130. For example, Rx 125A is connected to output driver 130A of driver 130.

[0045] Output driver (DRV) 130 includes multiple drivers 130A to 130N, each receiving its own amplified and buffered clock signal and transmitting the amplified and buffered clock signal to the corresponding output pin 140 of IC 100 with the required drive strength.

[0046] In the exemplary embodiments described in this specification, the number of signal generators 110 is equal to the number of output pins 140. However, in some alternative embodiments, the number of signal generators may be fewer or more than the number of output pins 140. Although the endpoint of the clock signal is referred to herein as IC pin 140 (or at least as the receiver 125 connected to that pin via output driver 130), in other embodiments, the endpoint may be a node (or port) within IC 100. These internal nodes may be, for example, nodes where other circuitry / devices (such as processors or simpler logic modules) receive clock inputs.

[0047] Signal distributor 120 has multiple input ports (In1 to InN) and multiple output ports (O1 to ON). Although the number of input ports and output ports indicated herein is equal (N), in general, their numbers may not be equal. Therefore, the number of input ports may be less than, equal to, or more than the number of output ports. Correspondingly, the number of signal generators 110 may also generally be less than, equal to, or more than the number of endpoints (here, pins 140 of IC 100). The techniques disclosed herein, including the design of multiplexers, are applicable to any number of input and output ports.

[0048] Signal distributor 120 receives a corresponding clock signal as input at each of its input ports. Signal distributor 120 is designed to selectively connect an input port to any output port. This selection is achieved by generating respective control signals. Figure 1 These control signals are not shown, but they can be generated from signals that are external inputs to IC 100, from non-volatile memory cells storing configuration data internally in IC 100, or through other known techniques. Each input port can be connected to any output port.

[0049] Signal distributor 120 can achieve the connection between its input and output ports using specific techniques designed to minimize congestion between connection paths / signal traces / clock signals within the path, thereby reducing crosstalk. Some exemplary implementations of signal distributor 120 include cross-point switch matrices and analog multiplexers. The connection traces from the input port to the output port of signal distributor 120, and the traces from the output port to receiver 125, are designed to have controlled impedance. These connection traces (generally referring to paths) can be implemented in known ways, such as as striplines.

[0050] The signal distributor 120 is implemented through a set of multiplexers, each of which is implemented as described below.

[0051] 3. Multiplexer

[0052] Figure 2The illustrations illustrate embodiments of the multiplexer in several aspects of this disclosure. A 4:1 multiplexer 290 is shown, comprising drivers 115A-1, 115B-1, 115C-1, and 115D-1, and a control unit 270. The multiplexer (MUX) 290 receives four input signals and operates to forward a selected one of the four input signals as an output signal. The control unit 270 of the MUX 290 generates a "select" signal on path 275 to select a specific one of the four input signals as the output signal for forwarding. Figure 2 The specific details are provided for illustrative purposes only. Generally, the multiplexer implemented as described in this specification can be an N:1 multiplexer, where N is any integer greater than 1.

[0053] For illustrative purposes only and in accordance with Figure 1 The continuity Figure 2 It was also shown in the middle. Figure 1 The receiver is 125A, the output driver is 130A, and the pins are 140+ / 140-. However, it must be understood that the multiplexer implemented according to one or more aspects of this disclosure can also be used in other systems and environments and can be combined with other components and circuits.

[0054] As described above, in the example provided in this specification, the input signal of the MUX 290 is a square wave clock signal. However, in general, the input signal can also be an analog signal or a digital signal. In the example provided in this specification, the frequency content and / or rise / fall time of the input signal make the signal from the output node of the MUX 290 to the endpoint (e.g., a receiver, such as...)... Figure 1 The signal transmission path (electrical trace) shown needs to be treated as a transmission line, and the design of the multiplexer must take into account the transmission line effect. In addition, it is generally desirable to minimize the size / area required to implement the multiplexer.

[0055] Reference Figure 2 The MUX 290 display consists of four drivers: 115A-1, 115B-1, 115C-1, and 115D-1. The input nodes of these drivers (which are also the input nodes of the MUX 290) receive the input signals required for multiplexing. The output nodes of the four drivers are interconnected and connected to the output nodes of the MUX.

[0056] exist Figure 2In this diagram, nodes 111A-1P / 111A-1M, 111B-1P / 111B-1M, 111C-1P / 111C-1M, and 111D-1P / 111D-1M are the input nodes of drivers 115A-1, 115B-1, 115C-1, and 115D-1, respectively. Each input node of driver 115A-1, 115B-1, 115C-1, and 115D-1 is connected to the corresponding PLL 110 output. Therefore, assuming... Figure 1 If N is 4, then there will be four PLLs 110. In this example, the input nodes of drivers 115A-1, 115B-1, 115C-1 and 115D-1 are connected to the outputs of PLLs 110A, 110B, 110C and 110D respectively, and receive the corresponding clock signals from the PLLs.

[0057] Node pair 211P / 211M represents the output node of driver 115A-1. For clarity, the output nodes of the remaining drivers are not numbered. All output nodes (or node pairs) are connected to the MUX output nodes 122A+ / 122A- (outp / outm). Output nodes 122A+ / 122A- are connected to receiver RX 125A, which is then connected to output driver 130A, and finally to pins 140A+ / 140-.

[0058] Driver 115A-1 is shown as a differential inverter consisting of a pair of single-ended inverters 250P and 250M. Single-ended inverter 250P is also shown... Figure 3 The inverter includes a PMOS (P-type metal-oxide-semiconductor field-effect transistor) 217P, an NMOS (N-type MOS) 217M, resistors 212P and 212M, and switches 213P, 214P, 213M, and 214M. The inverter is powered by a voltage Vc (201). Terminal 299 (GND) represents the ground terminal. In one embodiment, switches 213P, 214P, 214M, and 213M are all implemented as MOS transistors.

[0059] When switches 214P and 214M are closed, and switches 213P and 213M are open, the input signal 111A-1P is applied as a transistor control signal to the gate terminals of transistors 217P and 217M. Therefore, inverter 250P operates to generate a signal at output node 122A- that is logically inverted from the input signal 111A-1P. The signal at output node 122A- is treated as a forwarded signal, representing the input signal 111A-1P (albeit in inverted form). When switches 214P and 214M are open, and switches 213P and 213M are closed, both PMOS 217P and NMOS 217M are turned off, and node 122A- is in a high-impedance state (tri-state).

[0060] Figure 3 The control unit 270 is also shown. The control unit 270 receives one or more inputs on path 279, which indicate which input signal of the MUX 290 should be selected and forwarded to the output node of the MUX 290. Input 279 may come from a unit external to IC 100 (e.g., a user-operated unit) or from another module within IC 100 (or internal to the control unit 270 itself), such as configuration memory storing configuration bits, to indicate the selection to be made in the MUX 290. Other methods of providing such inputs may also be used, as will be apparent to those skilled in the art. Based on the received inputs or local configuration data, the control unit 270 generates signals on paths 271, 272, 273, and 274 to turn switches 213P, 214P, 214M, and 213M on or off, respectively. Paths 271-274 are contained within... Figure 2 In path 275.

[0061] 250M single-ended inverter Figure 2 Similar to inverter 250P, it includes PMOS 215P, NMOS 215M, resistors 216P and 216M, and switches 210P, 218P, 210M, and 218M. Inverter 250M operates similarly to inverter 250P as described above. Inverter 250M also receives corresponding switch control signals from control unit 270 to control the opening or closing of the corresponding switches, although these signals are not shown in the figure.

[0062] The implementation and operation of drives 115B-1, 115C-1, and 115D-1 are similar to those of drive 115A-1, and in... Figure 2 The components are shown but not numbered. Although not shown, each driver 115B-1, 115C-1 and 115D-1 also receives a corresponding switch control signal from the control unit 270 to control the opening or closing of the corresponding switch inside it.

[0063] Understandably, the MUX 290 can also handle small-amplitude analog signals under appropriate bias. For example, differential signals with a common-mode value of half the voltage 201 (i.e., 0.5 × Vc) and a relatively small voltage swing near the common-mode level can be multitasked using the MUX 290.

[0064] Now refer to Figure 2The switching positions of the drivers in MUX 290 are configured such that driver 115A-1 can drive the clock signal (input 111A-1P / 111A-1M) received from PLL 110A to output path 122A+ / 122A-, while simultaneously setting the outputs of drivers 115B-1, 115C-1, and 115D-1 to a tri-state. Thus, by operating the appropriate switches of the multiplexer drivers, the required input signal can be forwarded to the multiplexer output. An N:1 multiplexer can be implemented by configuring an appropriate number of drivers for each MUX and connecting the outputs (clock signals) of each PLL 110 to the corresponding drivers of the MUX. Other multiplexers required to implement signal distributor 120 are implemented in a similar manner, as described below.

[0065] It is noted here that when the MUX 290 processes single-ended signals, that is, when both the input and output signals of the MUX 290 are single-ended signals, or when the input signal is a differential signal but the output signal is a single-ended signal, the output of the MUX 290 will be provided between 122A+(outp) or 122A-(outm) and ground (GND, 299) or Vc (201). This type of output is usually referred to as a "three-wire output". In addition, when the input signal is a single-ended signal, ground (GND, 299) or Vc (201) needs to be connected to the source of the input signal. For example, the MUX 290 may receive four single-ended input signals at terminals 111A-1P, 111B-1P, 111C-1P, and 111D-1P, and forward one of these four input signals to the output path. This output path includes either node pair 122A-(outm) and ground (GND, 299) or node pair 122A-(outm) and Vc (201), depending on the resistance values ​​within the MUX 290 (typically all resistances are equal). Therefore, to support both differential and single-ended outputs, in addition to node pairs 122A+ and 122A-, ground and Vc are also connected to the corresponding receiver that will receive the MUX 290 output. Thus, generally speaking, the "output path" of the MUX 290 includes GND (299) and Vc (201) in addition to nodes 122A+ and 122A-. In the corresponding embodiment, GND (299) and Vc (201) are also provided as outputs of MUX 290 and are presented on the output pins of IC 100, as shown below. Figure 2 As shown.

[0066] When in Figure 1In exemplary environments, particularly in signal distributor 120, each driver of the MUX 290 is designed to have an output impedance (source-end termination) whose value is selected relative to the characteristic impedance of the wire / electrical path from that driver through the multiplexer to the corresponding receiver. This "impedance matching" is well known in the art and aims to minimize signal distortion caused by reflections on the transmission line, as well as crosstalk that may be caused by the distortion of one or more wires carrying clock signals (or other types of signals) when they are close together.

[0067] exist Figure 2 In the diagram, each driver is implemented as a source-side series-terminated (SST) differential inverter. The differential output impedance of the driver is 2R ohms, where R is the resistance of the four resistors in the driver (e.g., 212P, 212M, 216P, and 216M of driver 115A-1). In one embodiment, the differential output impedance (2R) of the driver is designed to be less than the impedance from the driver to the corresponding receiver (…). Figure 2 The characteristic impedance (Zo) of the transmission path / channel of the RX 125A is specified. The source impedance is intentionally designed to be lower than the channel impedance to minimize crosstalk. In one embodiment, the output impedance of the MUX driver can be selected from several values. In one embodiment, the differential output impedance is equal to Zo / 2. All multiplexers used to implement the signal distributor 120 are composed of drivers similarly implemented as SST differential inverters.

[0068] The multiplexer implemented as described above has several advantages over some existing multiplexer implementations. For example, conventional multiplexers commonly used for signal multitasking include additional switches in the signal path from the MUX to the receiver (i.e., the output path of the MUX). Referring to Figure 3, in a conventional multiplexer, one additional switch is connected in series between PMOS 217P and resistor 212P, and another switch is connected in series between NMOS 217M and resistor 212M. Switches 213P and 213M are not implemented; the nodes that should be connected when closed are permanently open / disconnected. Switches 214P and 214M are also not used; the nodes that should be connected when closed are permanently connected / closed. Therefore, signal 111A-1P can always be used as the input to the inverter. When the input signal needs to be forwarded to output 122A- (as a logic inversion), the two additional switches are in the on (closed) state, thus providing the logic inverted signal of the input at the output. When the output needs to be in a tri-state, the additional switch switches to the off (open) state. Traditional multiplexers consist of multiple drivers, but each driver uses the switch described above in the signal (or output) path.

[0069] One drawback of traditional multiplexers is that the additional switches located in the signal path need to withstand the power / current of the signal, which is typically high for the driver. Therefore, the additional switches need to be implemented as relatively large switches (e.g., MOS transistors), and the required additional area is itself a disadvantage. Another drawback is that each additional switch introduces associated parasitic capacitance in the output (signal) path. Even when the corresponding switch is off, these parasitic capacitances still affect the MUX's output signal. Therefore, it is generally more difficult to provide a controllable output impedance for the driver. Furthermore, the more drivers each MUX has (i.e., the larger the N value in an N:1 MUX), the larger the total parasitic capacitance of the driver output path, making impedance control of the driver output impedance and impedance matching with the characteristic impedance of the output path even more difficult.

[0070] On the other hand, multiplexers implemented according to various aspects of this disclosure (e.g.) Figure 2 The MUX 290 has no additional switches in its output path. Instead, each driver in the MUX contains eight switches in its differential input path. Because these switches are located at the input, they do not need to handle large currents, resulting in a relatively small size. Furthermore, since the additional switches are not located in the output path, no additional parasitic capacitance is introduced into the output path, and the output impedance of the SST driver can be precisely controlled and is easier to implement.

[0071] As mentioned above, regarding Figure 2 and Figure 3 The multiplexer implemented in this manner is used to implement the signal distributor 120, as described below.

[0072] 4. Signal distributor

[0073] Figure 4 This is a schematic diagram detailing the implementation of a signal distributor 120 in one embodiment of the present disclosure. The signal distributor 120 shows drivers 115-A1 to 115-N1, 115-A2 to 115-N2, and up to 115-AN to 115-NN. In driver groups 115-A1 to 115-N1, the output of each driver is permanently connected to path 122A (consisting of 122A+ and 122A-). Similarly, the outputs of other driver groups are also hard-connected to their corresponding output paths (122B to 122N). Paths 122A to 122N terminate at output ports O1 to ON, respectively. Figure 4 As shown. Figure 4 Receiver 125, output driver 130 and pin 140 are also shown for clarity.

[0074] Each input port is connected to a driver for each output path. For example, input port In1 (receives...) Figure 1The clock signal generated by PLL 110A is connected to driver 115-A1 on path 410-A1, driver 115-A2 on path 410-A2, and so on, up to driver 115-AN on path 410-An. Input port In2 (receiver) Figure 1 The clock signal generated by PLL 110B is connected to driver 115-B1 on path 410-B1, driver 115-B2 on path 410-B2, and so on, up to driver 115-BN on path 410-BN. Input port InN shows the connection to driver 115-N1 on path 410-N1. For clarity and simplicity, other connections are not shown in the diagram.

[0075] Each transmission channel 122 includes an N:1 multiplexer consisting of N drivers. For example, channel 122A includes an N:1 multiplexer consisting of drivers 115-A1 to 115-N1. This is achieved by appropriately configuring the switches of the multiplexer drivers in the signal distributor 120 (e.g., ...). Figure 2 As illustrated in the example, any clock signal generated by PLLs 110 can be provided to any output port of signal distributor 120, and then to the corresponding output pin 140. This configuration can be accomplished by applying the desired value to the control unit (e.g., control unit 270 described above) in each multiplexer. In one embodiment, drivers connected to the same PLL output (e.g., drivers 115-A1 to 115-AN, all connected to the output of PLL 110A via port In1) are physically placed close to the corresponding PLLs and to each other, and connected to their respective output channel traces (122). Crosstalk between output traces 122 (i.e., traces 122A – 122N) can be reduced through standard practices such as shielding and / or careful frequency planning (e.g., multiplexers can be configured so that output traces relatively close to each other do not carry harmonic-independent clock / signals).

[0076] In another embodiment, the multiplexer does not have its own built-in control unit (e.g., control unit 270). Instead, a master control unit is implemented within the signal distributor 120, which is designed to receive control signals or control values ​​from external devices and generate control signals to configure each multiplexer, forwarding the required inputs to its outputs. The implementation details of such a master control unit will be well known to those skilled in the art upon reading this disclosure.

[0077] It should be noted that although the number of PLLs 110 is indicated as equal to the number of output pins 140 in the example presented herein, in general, their numbers do not need to be equal. The number of PLLs can be less than, equal to, or greater than the number of output pins, as described above for the input and output ports of signal distributor 120. When the numbers are unequal, the implementation of signal distributor 120 can be modified accordingly. For example, if the number of PLLs 110 is one less than the number of output pins 140, and it is necessary to selectively provide the clock signal of each PLL to any output pin, an additional channel needs to be implemented to connect to the additional output pin. This channel will connect to the output of an additional multiplexer, which will contain another set of drivers, each of whose inputs is connected to the output of the corresponding PLL.

[0078] It should be noted that although each driver is described above as an SST inverter (differential or single-ended) with additional switches at the input to enable its use in a multiplexer, in other environments, the drivers can be implemented differently from SST inverters, as long as switches are provided at the input to enable their use in a multiplexer as described above. Such implementations will be readily apparent to those skilled in the art upon reading this disclosure.

[0079] 5. Conclusion

[0080] References to "one embodiment," "an embodiment," or similar language in this specification indicate that a particular feature, structure, or property associated with that embodiment is included at least in one embodiment disclosed herein. Therefore, "in one embodiment," "in an embodiment," and similar language appearing in this specification may refer to the same embodiment, but not necessarily.

[0081] Although Figures 1 to 4 In the diagram, terminals / nodes are shown as being directly connected to various other terminals (i.e., "connected to"), but it should be understood that in a real environment, there may be other components in the path (depending on the specific situation), so these connections can be considered as "electrically coupled" to the same terminals.

[0082] It should be understood that the specific transistor types described above (e.g., NMOS, PMOS, etc.) are for illustrative purposes only. However, it will be apparent to those skilled in the art upon reading this disclosure that other embodiments may use different configurations and transistors (e.g., bipolar junction transistors, BJTs). For example, NMOS transistors may be interchanged with PMOS (P-channel MOS) transistors, while also swapping connections to power and ground.

[0083] Therefore, in this application, the power supply terminal and the ground terminal are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of the transistor (which provide a current path when the transistor is turned on and an open circuit when the transistor is turned off) are referred to as current terminals, and the gate (base) terminal is referred to as control terminals.

[0084] Several aspects of the present invention will be described below with reference to examples. However, those skilled in the art will understand that the present invention can be practiced without one or more specific details, or other methods, components, materials, etc. may be used. In other cases, well-known structures, materials, or operations will not be described in detail to avoid obscuring the focus of the invention. Furthermore, the described features / aspects can be implemented in various combinations, but for the sake of brevity, only some combinations are described herein.

Claims

1. A multiplexer for connecting any one of a plurality of input signals to an output path, characterized in that, include: Multiple transistors, each transistor having a control terminal and a pair of current terminals, wherein one end of the pair of current terminals is connected to a constant reference potential, and the other end is connected to an output node at one end of the output path. The transistor is operable to provide a forwarding signal corresponding to a transistor control signal at the output node, which, if the transistor control signal is received at the control terminal and if the control terminal is coupled to the constant reference potential, causes the output node to be in a tri-state. A set of switches; and A control unit is configured to receive a value indicating that a specific transistor among the plurality of transistors should provide a corresponding input signal to the output path, the control unit controlling the switching group of the specific transistor so that the corresponding input signal is coupled to the control terminal of the specific transistor as a transistor control signal; The control unit controls the switching groups of the remaining transistors among the plurality of transistors, so that the constant reference potential is provided to each control terminal of the remaining transistors.

2. The multiplexer according to claim 1, characterized in that, The multiplexer comprises multiple drivers, each receiving a corresponding input signal, and of these drivers, only one provides a corresponding forwarding signal to the output path, wherein each of the multiple drivers includes: A first pair of transistors is coupled in series at a first junction and disposed between a first constant reference potential and a second constant reference potential, wherein the constant reference potential is one of the first constant reference potential and the second constant reference potential, and the first junction is the output node, wherein each of the plurality of transistors corresponds to one of the transistors in the first pair of transistors. The first pair of switches included in the group of switches, when closed, couples the corresponding control terminal of each of the first pair of transistors to the corresponding input signal, and when open, decouples the corresponding control terminal of each of the first pair of transistors from the corresponding input signal; as well as The second pair of switches included in this set of switches, when closed, couples the corresponding control terminals of the first pair of transistors to a corresponding potential of the first constant reference potential and the second constant reference potential, and when open, decouples the corresponding control terminals of the first pair of transistors from a corresponding potential of the first constant reference potential and the second constant reference potential. Specifically, to ensure that only the driver containing the specific transistor forwards the corresponding input signal to the output path, and to make the output nodes of the remaining multiple drivers tri-state, the control signal performs the following operations: The first pair of switches of this particular driver is closed, and the first pair of switches of each of the remaining multiple drivers is opened; and Disconnect the second pair of switches for that particular driver and close the second pair of switches for each of the remaining multiple drivers.

3. The multiplexer according to claim 2, characterized in that, Each of the plurality of input signals is a single-ended signal, and the output path includes the output node and one or both of the first constant reference potential and the second constant reference potential.

4. The multiplexer according to claim 2, characterized in that, Each of the plurality of input signals is a differential signal, comprising a first complementary signal and a second complementary signal, wherein the first complementary signal is provided as a transistor control signal for each of the plurality of transistors, wherein the output path is a differential path, and wherein each of the plurality of drivers further comprises: The second pair of transistors, which are coupled in series at a second contact and are positioned between the first constant reference potential and the second constant reference potential, wherein the second contact is coupled to the output path at a second output node of the driver, wherein the output node and the second output node together provide an output signal in a differential form on the output path; The third pair of switches, when closed, couples the second complementary signal of the corresponding input signal to the control terminal of each of the second pair of transistors, and when open, decouples the control terminal of each of the second pair of transistors from the second complementary signal of the corresponding input signal. as well as The fourth pair of switches, when closed, couples the corresponding control terminals of the second pair of transistors to a corresponding potential among the first and second constant reference potentials; when open, it decouples the corresponding control terminals of the second pair of transistors from a corresponding potential among the first and second constant reference potentials. Specifically, in order to ensure that only the specific driver containing the particular transistor forwards the corresponding second complementary signal to the output path, and to make the output nodes of the remaining multiple drivers tri-state, the control signal also performs the following operations: To close the third set of switches for that particular driver, and to open the third set of switches for each of the remaining plurality of drivers; and Disconnect the fourth group switch of that particular driver and close the fourth group switch of each of the remaining plurality of drivers.

5. The multiplexer according to claim 4, characterized in that, Each of the plurality of drivers is a source-series-terminated (SST) differential inverter.

6. The multiplexer according to claim 5, characterized in that, Each of the plurality of drives further comprises: A first impedance is coupled between the first transistor in the first pair of transistors and the first junction; A second impedance is coupled between the second transistor in the first pair of transistors and the first junction; A third impedance is coupled between the first transistor in the second pair of transistors and the second junction; as well as A fourth impedance is coupled between the second transistor in the second pair of transistors and the second junction.

7. The multiplexer according to claim 6, characterized in that, The impedance values ​​of the first impedance, the second impedance, the third impedance, and the fourth impedance are all equal.

8. The multiplexer according to claim 7, characterized in that, The differential output impedance of the driver is less than the characteristic impedance of the output path.

9. A signal distributor comprising a first plurality of input ports and a second plurality of output ports, the signal distributor being operable to couple each of the first plurality of input ports to any one of the second plurality of output ports, the signal distributor comprising: A third multiplexer, wherein the number of multiplexers in the third multiplexer is equal to the number of ports in the second multiple output port; Each of the third multiplexers has a fourth multiple input node, and each input node is coupled to a corresponding input port in the first multiple input ports. Each of the third multiplexers has an output node coupled to a corresponding output port in the second multiple output ports; Each multiplexer includes: Multiple transistors, each transistor having a control terminal and a pair of current terminals, wherein one end of the pair of current terminals is coupled to a fixed reference potential and the other end is coupled to an output node at one end of the output path; The transistor is operable to provide a forwarding signal corresponding to a transistor control signal at the output node, which, if the transistor control signal is received at the control terminal and if the control terminal is coupled to the constant reference potential, causes the output node to be in a tri-state. A set of switches; and A control unit is configured to receive a value indicating which of the plurality of transistors should provide its corresponding input signal to the output path; the control unit controls a set of switches of the particular transistor such that the corresponding input signal is coupled to the control terminal of the particular transistor as a transistor control signal. The control unit controls a set of switches of the remaining transistors in the plurality of transistors, so that a fixed reference potential is provided to the control terminal of each of the remaining transistors.

10. The signal distributor according to claim 9, characterized in that, Each multiplexer includes multiple drivers, each driver receiving a corresponding input signal, and only one driver provides its corresponding forward output signal to the output path, wherein each driver includes: A first pair of transistors is connected in series at a first contact and positioned between a first fixed reference potential and a second fixed reference potential, wherein the fixed reference potential is one of the first fixed reference potential and the second fixed reference potential, and the first contact is the output node, wherein each of the plurality of transistors corresponds to one of the transistors in the first pair of transistors. A first pair of switches, belonging to the group of switches, is used to couple the control terminal of each transistor in the first pair of transistors to the corresponding input signal when closed, and to decouple the control terminal from the corresponding input signal when open; A second pair of switches, also belonging to the set of switches, is used to couple the control terminals of each of the first pair of transistors to one of the first fixed reference potential and the second fixed reference potential when closed, and to decouple each control terminal from its corresponding first or second fixed reference potential when open. Specifically, to ensure that the driver containing only the specific transistor outputs its corresponding input signal forward to the output path, and to make the output nodes of the other drivers tri-state, the control signal operates as follows: The first pair of switches of the specific driver is closed, and the first pair of switches of the remaining drivers are all open; and Disconnect the second pair of switches of the specific driver and close the second pair of switches of the remaining drivers.

11. The signal distributor according to claim 10, characterized in that, All of the input signals are single-ended signals, and the output path includes the output node, as well as one or both of the first fixed reference potential and the second fixed reference potential.

12. The signal distributor according to claim 10, characterized in that, All of the input signals are differential signals, and the output path is a differential path. Each of the plurality of drives further includes: A second pair of transistors, connected in series at a second contact and positioned between the first fixed reference potential and the second fixed reference potential, wherein the second contact is coupled to a second output node of the driver on the output path; A third pair of switches is used to couple the control terminals of each of the second pair of transistors to the corresponding input signal when closed, and to decouple each control terminal from the corresponding input signal when open; A fourth pair of switches is used to couple the control terminals of each of the second pair of transistors to the corresponding power supply or fixed reference potential when closed, and to decouple each control terminal from its corresponding power supply or fixed reference potential when open. Specifically, to ensure that a specific driver containing only the specific transistor outputs its corresponding second compensation signal forward to the output path, and to make the output nodes of the remaining drivers in the plurality of drivers tri-state, the control signal also operates as follows: Close the third pair of switches of the specific driver, and open the third pair of switches of all other drivers; and Disconnect the fourth pair of switches of the specific driver and close the fourth pair of switches of the remaining drivers.

13. The signal distributor according to claim 12, characterized in that, Each of the plurality of drivers is a source-terminated series-terminated (SST) differential inverter.

14. The signal distributor according to claim 13, characterized in that, Each of the plurality of drivers further includes: A first impedance is coupled between the first transistor in the first pair of transistors and the first junction; A second impedance is coupled between the second transistor in the first pair of transistors and the first junction; A third impedance is coupled between the first transistor in the second pair of transistors and the second junction; and A fourth impedance is coupled between the second transistor in the second pair of transistors and the second junction.

15. The signal distributor according to claim 14, characterized in that, The impedance values ​​of the first impedance, the second impedance, the third impedance, and the fourth impedance are all equal.

16. The signal distributor according to claim 15, characterized in that, The differential output impedance of the driver is less than the characteristic impedance of the output path.

17. The signal distributor according to claim 16, characterized in that, The number of input ports in the first group of ports is equal to the number of output ports in the second group of ports.

18. The signal distributor according to claim 16, characterized in that, The number of input ports in the first group of ports is different from the number of output ports in the second group of ports.

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